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authorDavid S. Miller <davem@redhat.com>2011-09-27 04:30:32 +0000
committerDavid S. Miller <davem@redhat.com>2011-09-27 04:30:32 +0000
commit92a7795b59d61413c7df90cf615ec9c9d2977411 (patch)
treeb051438cdca59852d776b4fb66c8ebae845ef1f5
parent79df06c40d5e4c0182d25075d463e861d7e8c930 (diff)
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opcodes/
* sparc-opc.c (sparc_opcodes): Fix random instruction to write to a float instead of an integer register. gas/testsuite/ * gas/sparc/hpcvis3.s: Update to use float reg for random insn. * gas/sparc/hpcvis3.d: Likewise.
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/sparc/hpcvis3.d2
-rw-r--r--gas/testsuite/gas/sparc/hpcvis3.s2
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/sparc-opc.c2
5 files changed, 13 insertions, 3 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5def8f5..9df84ae 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-09-27 David S. Miller <davem@davemloft.net>
+
+ * gas/sparc/hpcvis3.s: Update to use float reg for random insn.
+ * gas/sparc/hpcvis3.d: Likewise.
+
2011-09-26 David S. Miller <davem@davemloft.net>
* gas/sparc/ima.d: New test.
diff --git a/gas/testsuite/gas/sparc/hpcvis3.d b/gas/testsuite/gas/sparc/hpcvis3.d
index faa3137..f4606ac 100644
--- a/gas/testsuite/gas/sparc/hpcvis3.d
+++ b/gas/testsuite/gas/sparc/hpcvis3.d
@@ -41,7 +41,7 @@ Disassembly of section .text:
7c: 95 f9 11 c6 fnumaddd %f4, %f6, %f8, %f10
80: 8f b1 42 26 addxc %g5, %g6, %g7
84: 97 b2 42 6a addxccc %o1, %o2, %o3
- 88: 99 b0 02 a0 random %o4
+ 88: 8d b0 02 a0 random %f6
8c: 9f b3 42 ce umulxhi %o5, %sp, %o7
90: b5 b0 02 f9 lzd %i1, %i2
94: 81 b0 03 7b cmask8 %i3
diff --git a/gas/testsuite/gas/sparc/hpcvis3.s b/gas/testsuite/gas/sparc/hpcvis3.s
index 8da08f4..9f3ac36 100644
--- a/gas/testsuite/gas/sparc/hpcvis3.s
+++ b/gas/testsuite/gas/sparc/hpcvis3.s
@@ -34,7 +34,7 @@
fnumaddd %f4, %f6, %f8, %f10
addxc %g5, %g6, %g7
addxccc %o1, %o2, %o3
- random %o4
+ random %f6
umulxhi %o5, %o6, %o7
lzd %i1, %i2
cmask8 %i3
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 67bfbdf..051f52a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2011-09-27 David S. Miller <davem@davemloft.net>
+
+ * sparc-opc.c (sparc_opcodes): Fix random instruction to write
+ to a float instead of an integer register.
+
2011-09-26 David S. Miller <davem@davemloft.net>
* sparc-opc.c (sparc_opcodes): Add integer multiply-add
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 6fbe025..a2096c5 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1869,7 +1869,7 @@ SLCBCC("cbnefr", 15),
{ "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT|F_FJFMAU, v9b },
{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", F_VIS3, v9b },
{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", F_VIS3, v9b },
-{ "random", F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "d", F_RANDOM, v9b },
+{ "random", F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT|F_RANDOM, v9b },
{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", F_VIS3, v9b },
{ "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_VIS3, v9b },
{ "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", F_VIS3, v9b },