PR binutils/15068

	* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
	* gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add
	and xor.
	* gas/tic6x/insns16-lsd-unit.d: Update expected output.

5 files changed, 43 insertions, 31 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 8206282..7bd46f6 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR binutils/15068
+	* gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add
+	and xor.
+	* gas/tic6x/insns16-lsd-unit.d: Update expected output.
+
 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/addr32.s: Add an SIB test.
diff --git a/gas/testsuite/gas/tic6x/insns16-lsd-unit.d b/gas/testsuite/gas/tic6x/insns16-lsd-unit.d
index 07b20e4..4538876 100644
--- a/gas/testsuite/gas/tic6x/insns16-lsd-unit.d
+++ b/gas/testsuite/gas/tic6x/insns16-lsd-unit.d
@@ -55,16 +55,16 @@ Disassembly of section .text:
 [0-9a-f]+[02468ace] <[^>]*> 1866[ \t]+mvk \.L1 0,a0
 [0-9a-f]+[02468ace] <[^>]*> 1867[ \t]+mvk \.L2 0,b0
 [0-9a-f]+[02468ace] <[^>]*> 1866[ \t]+mvk \.L1 0,a0
-[0-9a-f]+[02468ace] <[^>]*> 1867[ \t]+mvk \.L2 0,b0
-[0-9a-f]+[02468ace] <[^>]*> 1866[ \t]+mvk \.L1 0,a0
-[0-9a-f]+[02468ace] <[^>]*> 1867[ \t]+mvk \.L2 0,b0
-[0-9a-f]+[02468ace] <[^>]*> 1866[ \t]+mvk \.L1 0,a0
-[0-9a-f]+[02468ace] <[^>]*> 1867[ \t]+mvk \.L2 0,b0
-[0-9a-f]+[02468ace] <[^>]*> 1866[ \t]+mvk \.L1 0,a0
-[0-9a-f]+[02468ace] <[^>]*> 1867[ \t]+mvk \.L2 0,b0
-[0-9a-f]+[02468ace] <[^>]*> 1866[ \t]+mvk \.L1 0,a0
-[0-9a-f]+[02468ace] <[^>]*> 1867[ \t]+mvk \.L2 0,b0
-[0-9a-f]+[02468ace] <[^>]*> 1866[ \t]+mvk \.L1 0,a0
-[0-9a-f]+[02468ace] <[^>]*> 1867[ \t]+mvk \.L2 0,b0
+[0-9a-f]+[02468ace] <[^>]*> 3867[ \t]+mvk \.L2 1,b0
+[0-9a-f]+[02468ace] <[^>]*> 3866[ \t]+mvk \.L1 1,a0
+[0-9a-f]+[02468ace] <[^>]*> 3877[ \t]+mvk \.D2 1,b0
+[0-9a-f]+[02468ace] <[^>]*> 3876[ \t]+mvk \.D1 1,a0
+[0-9a-f]+[02468ace] <[^>]*> b877[ \t]+add \.D2 b0,1,b0
+[0-9a-f]+[02468ace] <[^>]*> b876[ \t]+add \.D1 a0,1,a0
+[0-9a-f]+[02468ace] <[^>]*> b86f[ \t]+add \.S2 b0,1,b0
+[0-9a-f]+[02468ace] <[^>]*> f86e[ \t]+xor \.S1 a0,1,a0
+[0-9a-f]+[02468ace] <[^>]*> f86f[ \t]+xor \.S2 b0,1,b0
+[0-9a-f]+[02468ace] <[^>]*> f86e[ \t]+xor \.S1 a0,1,a0
+[0-9a-f]+[02468ace] <[^>]*> f86f[ \t]+xor \.S2 b0,1,b0
 [0-9a-f]+[02468ace] <[^>]*> efe00000[ \t]+<fetch packet header 0xefe00000>
 [ \t]*\.\.\.
diff --git a/gas/testsuite/gas/tic6x/insns16-lsd-unit.s b/gas/testsuite/gas/tic6x/insns16-lsd-unit.s
index 8e93d04..6491288 100644
--- a/gas/testsuite/gas/tic6x/insns16-lsd-unit.s
+++ b/gas/testsuite/gas/tic6x/insns16-lsd-unit.s
@@ -56,16 +56,16 @@ lsdx1:
         .short 0x1866
         .short 0x1867
         .short 0x1866
-        .short 0x1867
-        .short 0x1866
-        .short 0x1867
-        .short 0x1866
-        .short 0x1867
-        .short 0x1866
-        .short 0x1867
-        .short 0x1866
-        .short 0x1867
-        .short 0x1866
-        .short 0x1867
+        .short 0x3867
+        .short 0x3866
+        .short 0x3877
+        .short 0x3876
+        .short 0xb877
+        .short 0xb876
+        .short 0xb86f
+        .short 0xf86e
+        .short 0xf86f
+        .short 0xf86e
+        .short 0xf86f
         .word  0xefe00000 | 0x0000
 
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 9f7f157..5813878 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,6 +1,11 @@
 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 
 	PR binutils/15068
+	* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
+
+2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR binutils/15068
 	* tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 	Add 16-bit opcodes.
 	* tic6xc-opcode-table.h: Add 16-bit insns.
diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h
index 3b7ee14..d876c56 100644
--- a/include/opcode/tic6x-opcode-table.h
+++ b/include/opcode/tic6x-opcode-table.h
@@ -251,15 +251,15 @@ INSN(add, d, dx2op, 1cycle, C64XP, 0,
      ENC5(ENC(s, fu, 0), ENC(x, xpath, 1), ENC(srcdst, reg, 0),
           ENC(src2, reg, 1), ENC(srcdst, reg, 2)))
 INSNU(add, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
-     FIX2(FIX(op, 0x7), FIX(unit, 0x0)),
+     FIX2(FIX(op, 0x5), FIX(unit, 0x0)),
      OP3(ORREG1, OHWCST1, OWREG1),
      ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
 INSNU(add, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
-     FIX2(FIX(op, 0x7), FIX(unit, 0x1)),
+     FIX2(FIX(op, 0x5), FIX(unit, 0x1)),
      OP3(ORREG1, OHWCST1, OWREG1),
      ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
 INSNU(add, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
-     FIX2(FIX(op, 0x7), FIX(unit, 0x2)),
+     FIX2(FIX(op, 0x5), FIX(unit, 0x2)),
      OP3(ORREG1, OHWCST1, OWREG1),
      ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
 /**/
@@ -1320,7 +1320,7 @@ INSN(lddw, d, load_store, load, C64X_AND_C67X,
 
 /* 16 bits insn */
 INSN(lddw, d, dpp, load, C64XP,
-     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS,
      FIX2(FIX(op, 1), FIX(dw, 1)),
      OP2(ORMEMSD, OWDREGD5),
      ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
@@ -1477,8 +1477,8 @@ INSN(ldnw, d, load_store, load, C64X,
 	  ENC(srcdst, reg, 1)))
 
 /* 16 bits insn */
-INSN(ldnw, d, doff4_dsz_110, store, C64XP,
-     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+INSN(ldnw, d, doff4_dsz_110, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
      FIX2(FIX(op, 1), FIX(sz, 1)),
      OP2(ORMEMSW, OWTREG5),
      ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
@@ -3519,15 +3519,15 @@ INSN(xor, l, l2c, 1cycle, C64XP, 0,
            ENC(src2, reg, 1), ENC(dst, reg, 2)))
 INSNU(xor, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
      FIX2(FIX(op, 0x7), FIX(unit, 0x0)),
-     OP3(ORREG1, OHWCST0, OWREG1),
+     OP3(ORREG1, OHWCST1, OWREG1),
      ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
 INSNU(xor, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
      FIX2(FIX(op, 0x7), FIX(unit, 0x1)),
-     OP3(ORREG1, OHWCST0, OWREG1),
+     OP3(ORREG1, OHWCST1, OWREG1),
      ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
 INSNU(xor, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
      FIX2(FIX(op, 0x7), FIX(unit, 0x2)),
-     OP3(ORREG1, OHWCST0, OWREG1),
+     OP3(ORREG1, OHWCST1, OWREG1),
      ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
 /**/