2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

	* s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
	* s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.

2008-08-15  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* gas/s390/esa-g5.d: lxr operands are floating point.
	* gas/s390/esa-g5.s: Likewise.
	* gas/testsuite/gas/s390/zarch-z9-ec.d: rrdtr, rrxtr third
	operands is gpr.
	* gas/testsuite/gas/s390/zarch-z9-ec.s: Likewise.

8 files changed, 24 insertions, 9 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index ed31fcc..3c95264 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2008-08-15  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* gas/s390/esa-g5.d: lxr operands are floating point.
+	* gas/s390/esa-g5.s: Likewise.
+	* gas/testsuite/gas/s390/zarch-z9-ec.d: rrdtr, rrxtr third
+	operands is gpr.
+	* gas/testsuite/gas/s390/zarch-z9-ec.s: Likewise.
+
 2008-08-12  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/amd.s: Add syscall and sysret.  Remove padding.
diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d
index 7d75142..dd2defe 100644
--- a/gas/testsuite/gas/s390/esa-g5.d
+++ b/gas/testsuite/gas/s390/esa-g5.d
@@ -268,7 +268,7 @@ Disassembly of section .text:
 .*:	ed 65 af ff 00 06 [	 ]*lxeb	%f6,4095\(%r5,%r10\)
 .*:	b3 06 00 69 [	 ]*lxebr	%f6,%f9
 .*:	b3 26 00 69 [	 ]*lxer	%f6,%f9
-.*:	b3 65 00 69 [	 ]*lxr	%r6,%r9
+.*:	b3 65 00 69 [	 ]*lxr	%f6,%f9
 .*:	b3 75 00 60 [	 ]*lzdr	%f6
 .*:	b3 74 00 60 [	 ]*lzer	%f6
 .*:	b3 76 00 60 [	 ]*lzxr	%f6
diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s
index 8150be7..b3be827 100644
--- a/gas/testsuite/gas/s390/esa-g5.s
+++ b/gas/testsuite/gas/s390/esa-g5.s
@@ -262,7 +262,7 @@ foo:
 	lxeb	%f6,4095(%r5,%r10)
 	lxebr	%f6,%f9
 	lxer	%f6,%f9
-	lxr	%r6,%r9
+	lxr	%f6,%f9
 	lzdr	%f6
 	lzer	%f6
 	lzxr	%f6
diff --git a/gas/testsuite/gas/s390/zarch-z9-ec.d b/gas/testsuite/gas/s390/zarch-z9-ec.d
index bf766a3..691d1e2 100644
--- a/gas/testsuite/gas/s390/zarch-z9-ec.d
+++ b/gas/testsuite/gas/s390/zarch-z9-ec.d
@@ -53,8 +53,8 @@ Disassembly of section .text:
 .*:	b3 d8 40 62 [	 ]*mxtr	%f6,%f2,%f4
 .*:	b3 f5 21 64 [	 ]*qadtr	%f6,%f2,%f4,1
 .*:	b3 fd 21 64 [	 ]*qaxtr	%f6,%f2,%f4,1
-.*:	b3 f7 21 64 [	 ]*rrdtr	%f6,%f2,%f4,1
-.*:	b3 ff 21 64 [	 ]*rrxtr	%f6,%f2,%f4,1
+.*:	b3 f7 21 64 [	 ]*rrdtr	%f6,%f2,%r4,1
+.*:	b3 ff 21 64 [	 ]*rrxtr	%f6,%f2,%r4,1
 .*:	b2 b9 10 03 [	 ]*srnmt	3\(%r1\)
 .*:	b3 85 00 20 [	 ]*sfasr	%r2
 .*:	ed 21 40 03 60 40 [	 ]*sldt	%f6,%f2,3\(%r1,%r4\)
diff --git a/gas/testsuite/gas/s390/zarch-z9-ec.s b/gas/testsuite/gas/s390/zarch-z9-ec.s
index b1ecb60..bf3dcaf 100644
--- a/gas/testsuite/gas/s390/zarch-z9-ec.s
+++ b/gas/testsuite/gas/s390/zarch-z9-ec.s
@@ -47,8 +47,8 @@ foo:
 	mxtr	%f6,%f2,%f4
 	qadtr	%f6,%f2,%f4,1
 	qaxtr	%f6,%f2,%f4,1
-	rrdtr	%f6,%f2,%f4,1
-	rrxtr	%f6,%f2,%f4,1
+	rrdtr	%f6,%f2,%r4,1
+	rrxtr	%f6,%f2,%r4,1
 	srnmt	3(%r1)
 	sfasr	%r2
 	sldt	%f6,%f2,3(%r1,%r4)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0a553af..8fa3342 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2008-08-15  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
+	* s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
+
 2008-08-15  Alan Modra  <amodra@bigpond.net.au>
 
 	PR 6526
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index d7a114b..d31ca1e 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -274,6 +274,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 }      /* e.g. fidtr */
 #define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 }          /* e.g. ldetr */
 #define INSTR_RRF_FFFU   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. qadtr */
+#define INSTR_RRF_FFRU   4, { F_24,F_16,R_28,U4_20,0,0 }       /* e.g. rrdtr */
 #define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 }           /* e.g. sske  */
 #define INSTR_RRF_U0RR   4, { R_24,R_28,U4_16,0,0,0 }          /* e.g. clrt  */
 #define INSTR_RRF_00RR   4, { R_24,R_28,0,0,0,0 }              /* e.g. clrtne */
@@ -378,6 +379,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRF_UUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_0UFF    { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
 #define MASK_RRF_FFFU    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FFRU    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_M0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_00RR    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 7f6aee2..6e0f3ad 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -577,7 +577,7 @@ b336 sqxr RRE_FF "square root extended hfp" g5 esa,zarch
 ed0000000034 sqe RXE_FRRD "square root short hfp" g5 esa,zarch
 b263 cmpsc RRE_RR "compression call" g5 esa,zarch
 eb00000000c0 tp RSL_R0RD "test decimal" g5 esa,zarch
-b365 lxr RRE_RR "load extended hfp" g5 esa,zarch
+b365 lxr RRE_FF "load extended fp" g5 esa,zarch
 b22e pgin RRE_RR "page in" g5 esa,zarch
 b22f pgout RRE_RR "page out" g5 esa,zarch
 b276 xsch S_00 "cancel subchannel" g5 esa,zarch
@@ -833,8 +833,8 @@ b3d0 mdtr RRR_F0FF "multiply long dfp" z9-ec zarch
 b3d8 mxtr RRR_F0FF "multiply extended dfp" z9-ec zarch
 b3f5 qadtr RRF_FFFU "Quantize long dfp" z9-ec zarch
 b3fd qaxtr RRF_FFFU "Quantize extended dfp" z9-ec zarch
-b3f7 rrdtr RRF_FFFU "Reround long dfp" z9-ec zarch
-b3ff rrxtr RRF_FFFU "Reround extended dfp" z9-ec zarch
+b3f7 rrdtr RRF_FFRU "Reround long dfp" z9-ec zarch
+b3ff rrxtr RRF_FFRU "Reround extended dfp" z9-ec zarch
 b2b9 srnmt S_RD "set rounding mode dfp" z9-ec zarch
 b385 sfasr RRE_R0 "set fpc and signal" z9-ec zarch
 ed0000000040 sldt RXF_FRRDF "shift coefficient left long dfp" z9-ec zarch