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authorMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2012-08-24 08:01:18 +0000
committerMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2012-08-24 08:01:18 +0000
commit53c4b28b4f873fd41d158eb9f23b2d07e2780b98 (patch)
treeee108b7763d5cb1be914bf911564fc8416b4ab34
parente797f7e0b2bedc9328d4a9a0ebc63ca7a2dbbebc (diff)
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* gas/config/tc-arm.c (T16_32_TAB): Add _sevl.
(insns): Add SEVL. * gas/testsuite/gas/arm/armv8-a.s: New testcase. * gas/testsuite/gas/arm/armv8-a.d: Likewise. * opcodes/arm-dis.c (arm_opcodes): Add SEVL. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise.
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-arm.c13
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/arm/armv8-a.d10
-rw-r--r--gas/testsuite/gas/arm/armv8-a.s14
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/arm-dis.c9
7 files changed, 61 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index da59383..785bf08 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * config/tc-arm.c (T16_32_TAB): Add _sevl.
+ (insns): Add SEVL.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* config/tc-arm.c (asm_barrier_opt): Add arch field.
(mark_feature_used): New function.
(parse_barrier): Check specified option is valid for the
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d3838ab..cfcdecb 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -9549,7 +9549,8 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_yield, bf10, f3af8001), \
X(_wfe, bf20, f3af8002), \
X(_wfi, bf30, f3af8003), \
- X(_sev, bf40, f3af8004),
+ X(_sev, bf40, f3af8004), \
+ X(_sevl, bf50, f3af8005)
/* To catch errors in encoding functions, the codes are all offset by
0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
@@ -17966,8 +17967,18 @@ static const struct asm_opcode insns[] =
TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
+ /* AArchv8 instructions. */
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_v8
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8
+
+ tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
+
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT NULL
cCE("wfs", e200110, 1, (RR), rd),
cCE("rfs", e300110, 1, (RR), rd),
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d70a2c6..a890b80 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,10 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * gas/arm/armv8-a.s: New testcase.
+ * gas/arm/armv8-a.d: Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* gas/arm/armv8-a-barrier.s: New testcase.
* gas/arm/armv8-a-barrier-arm.d: Likewise.
* gas/arm/armv8-a-barrier-thumb.d: Likewise.
diff --git a/gas/testsuite/gas/arm/armv8-a.d b/gas/testsuite/gas/arm/armv8-a.d
new file mode 100644
index 0000000..f558910
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a.d
@@ -0,0 +1,10 @@
+#name: Valid v8-a
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> e320f005 sevl
+0[0-9a-f]+ <[^>]+> bf50 sevl
+0[0-9a-f]+ <[^>]+> bf50 sevl
+0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w
diff --git a/gas/testsuite/gas/arm/armv8-a.s b/gas/testsuite/gas/arm/armv8-a.s
new file mode 100644
index 0000000..000a5a7
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .arch armv8-a
+
+ .arm
+foo:
+ sevl
+
+ .thumb
+ .thumb_func
+bar:
+ sevl
+ sevl.n
+ sevl.w
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2b60eb5..b60b6af 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * arm-dis.c (arm_opcodes): Add SEVL.
+ (thumb_opcodes): Likewise.
+ (thumb32_opcodes): Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* arm-dis.c (data_barrier_option): New function.
(print_insn_arm): Use data_barrier_option.
(print_insn_thumb32): Use data_barrier_option.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ccbb6b3..5a450d7 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -849,6 +849,9 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
+ /* V8 instructions. */
+ {ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"},
+
/* Virtualization Extension instructions. */
{ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
{ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
@@ -1244,6 +1247,9 @@ static const struct opcode16 thumb_opcodes[] =
{
/* Thumb instructions. */
+ /* ARM V8 instructions. */
+ {ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"},
+
/* ARM V6K no-argument instructions. */
{ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
{ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
@@ -1413,6 +1419,9 @@ static const struct opcode16 thumb_opcodes[] =
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
+ /* V8 instructions. */
+ {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
+
/* V7 instructions. */
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
{ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},