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authorMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2012-08-24 08:13:24 +0000
committerMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2012-08-24 08:13:24 +0000
commit4f51b4bdbbae0b751bb093ebcf568e5808fc87c2 (patch)
tree83703bfd05b806e174fab6c53af65045f2a7893c
parent91ff78946d8fd0c1eb13a65225b72eea3f8b8c17 (diff)
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* gas/config/tc-arm.c (neon_type_mask): Add P64 type.
(type_chk_of_el_type): Handle P64 type. (el_type_of_type_chk): Likewise. (do_neon_vmull): Handle VMULL.P64. * gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise. * opcodes/arm-dis.c (neon_opcodes): Handle VMULL.P64.
-rw-r--r--gas/ChangeLog7
-rw-r--r--gas/config/tc-arm.c27
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/arm/armv8-a+crypto.d4
-rw-r--r--gas/testsuite/gas/arm/armv8-a+crypto.s4
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/arm-dis.c1
7 files changed, 46 insertions, 6 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b756b45..ff6ce6b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * config/tc-arm.c (neon_type_mask): Add P64 type.
+ (type_chk_of_el_type): Handle P64 type.
+ (el_type_of_type_chk): Likewise.
+ (do_neon_vmull): Handle VMULL.P64.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* config/tc-arm.c (NEON_ENC_TAB): Add aes entry.
(neon_type_mask): Add N_UNT.
(neon_check_type): Don't always decay typed to untyped sizes.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 0214d77..627274c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12570,6 +12570,7 @@ enum neon_type_mask
N_F16 = 0x0040000,
N_F32 = 0x0080000,
N_F64 = 0x0100000,
+ N_P64 = 0x0200000,
N_KEY = 0x1000000, /* Key element (main type specifier). */
N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
@@ -12582,7 +12583,7 @@ enum neon_type_mask
N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
N_UTYP = 0,
- N_MAX_NONSPECIAL = N_F64
+ N_MAX_NONSPECIAL = N_P64
};
#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
@@ -12790,6 +12791,7 @@ type_chk_of_el_type (enum neon_el_type type, unsigned size)
{
case 8: return N_P8;
case 16: return N_P16;
+ case 64: return N_P64;
default: ;
}
break;
@@ -12838,7 +12840,7 @@ el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
*size = 16;
else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
*size = 32;
- else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
+ else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
*size = 64;
else
return FAIL;
@@ -12851,7 +12853,7 @@ el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
*type = NT_integer;
else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
*type = NT_untyped;
- else if ((mask & (N_P8 | N_P16)) != 0)
+ else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
*type = NT_poly;
else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
*type = NT_float;
@@ -15120,13 +15122,26 @@ do_neon_vmull (void)
else
{
struct neon_type_el et = neon_check_type (3, NS_QDD,
- N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
+ N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
+
if (et.type == NT_poly)
NEON_ENCODE (POLY, inst);
else
NEON_ENCODE (INTEGER, inst);
- /* For polynomial encoding, size field must be 0b00 and the U bit must be
- zero. Should be OK as-is. */
+
+ /* For polynomial encoding the U bit must be zero, and the size must
+ be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
+ obviously, as 0b10). */
+ if (et.size == 64)
+ {
+ /* Check we're on the correct architecture. */
+ if (!mark_feature_used (&fpu_crypto_ext_armv8))
+ inst.error =
+ _("Instruction form not available on this architecture.");
+
+ et.size = 32;
+ }
+
neon_mixed_length (et, et.size);
}
}
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d64dbf9..3543cd7 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,10 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * gas/arm/armv8-a+crypto.d: Update testcase.
+ * gas/arm/armv8-a+crypto.s: Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* gas/arm/armv8-a+crypto.d: New testcase.
* gas/arm/armv8-a+crypto.s: Likewise.
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d
index 238f9b6..bfff964 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.d
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.d
@@ -4,6 +4,8 @@
.*: +file format .*arm.*
Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f2a00e00 vmull.p64 q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2efeeaf vmull.p64 q15, d31, d31
0[0-9a-f]+ <[^>]+> f3b00300 aese.8 q0, q0
0[0-9a-f]+ <[^>]+> f3b0e30e aese.8 q7, q7
0[0-9a-f]+ <[^>]+> f3f00320 aese.8 q8, q8
@@ -20,6 +22,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3b0e3ce aesimc.8 q7, q7
0[0-9a-f]+ <[^>]+> f3f003e0 aesimc.8 q8, q8
0[0-9a-f]+ <[^>]+> f3f0e3ee aesimc.8 q15, q15
+0[0-9a-f]+ <[^>]+> efa0 0e00 vmull.p64 q0, d0, d0
+0[0-9a-f]+ <[^>]+> efef eeaf vmull.p64 q15, d31, d31
0[0-9a-f]+ <[^>]+> ffb0 0300 aese.8 q0, q0
0[0-9a-f]+ <[^>]+> ffb0 e30e aese.8 q7, q7
0[0-9a-f]+ <[^>]+> fff0 0320 aese.8 q8, q8
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.s b/gas/testsuite/gas/arm/armv8-a+crypto.s
index 4f01b79..03b5c41 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.s
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.s
@@ -3,6 +3,8 @@
.arch_extension crypto
.arm
+ vmull.p64 q0, d0, d0
+ vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
@@ -21,6 +23,8 @@
aesimc.8 q15, q15
.thumb
+ vmull.p64 q0, d0, d0
+ vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5f04b9d..c879cb3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * arm-dis.c (neon_opcodes): Handle VMULL.P64.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* arm-dis.c (neon_opcodes): Add support for AES instructions.
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ef5c752..c0a6479 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -757,6 +757,7 @@ static const struct opcode32 neon_opcodes[] =
{FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
/* Three registers of different lengths. */
+ {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},