Implement missing powerpc extended mnemonics

gas/
	* testsuite/gas/ppc/power8.d,
	* testsuite/gas/ppc/power8.s: Add miso.
	* testsuite/gas/ppc/power9.d,
	* testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru.
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
	Enable icbt for power5, miso for power8.

7 files changed, 35 insertions, 7 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index e918b52..a511ec4 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
 2020-08-10  Alan Modra  <amodra@gmail.com>
 
+	* testsuite/gas/ppc/power8.d,
+	* testsuite/gas/ppc/power8.s: Add miso.
+	* testsuite/gas/ppc/power9.d,
+	* testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru.
+
+2020-08-10  Alan Modra  <amodra@gmail.com>
+
 	* testsuite/gas/ppc/power8.d: Update.
 	* testsuite/gas/ppc/vsx2.d: Update.
 
diff --git a/gas/testsuite/gas/ppc/power8.d b/gas/testsuite/gas/ppc/power8.d
index 1439496..df3f5d4 100644
--- a/gas/testsuite/gas/ppc/power8.d
+++ b/gas/testsuite/gas/ppc/power8.d
@@ -310,4 +310,6 @@ Disassembly of section \.text:
 .*:	(4d 89 04 61|61 04 89 4d) 	bgttarl cr2
 .*:	(4d 89 04 61|61 04 89 4d) 	bgttarl cr2
 .*:	(4d 89 1c 61|61 1c 89 4d) 	bctarl  12,4\*cr2\+gt,3
+.*:	(7f 5a d3 78|78 d3 5a 7f) 	miso
+.*:	(7f 5a d3 78|78 d3 5a 7f) 	miso
 #pass
diff --git a/gas/testsuite/gas/ppc/power8.s b/gas/testsuite/gas/ppc/power8.s
index beb1c5e..52a3e8e 100644
--- a/gas/testsuite/gas/ppc/power8.s
+++ b/gas/testsuite/gas/ppc/power8.s
@@ -302,3 +302,5 @@ power8:
 	bctarl       0b01100,4*cr2+gt
 	bctarl       0b01100,4*cr2+gt,0
 	bctarl       0b01100,4*cr2+gt,3
+	or	     26,26,26
+	miso
diff --git a/gas/testsuite/gas/ppc/power9.d b/gas/testsuite/gas/ppc/power9.d
index 4e7156d..45a8f49 100644
--- a/gas/testsuite/gas/ppc/power9.d
+++ b/gas/testsuite/gas/ppc/power9.d
@@ -399,4 +399,8 @@ Disassembly of section \.text:
 .*:	(7c 20 20 ac|ac 20 20 7c) 	dcbfl   0,r4
 .*:	(7c 60 28 ac|ac 28 60 7c) 	dcbflp  0,r5
 .*:	(7c 60 28 ac|ac 28 60 7c) 	dcbflp  0,r5
+.*:	(63 ff 00 00|00 00 ff 63) 	exser
+.*:	(63 ff 00 00|00 00 ff 63) 	exser
+.*:	(7c 00 18 9c|9c 18 00 7c) 	msgsndu r3
+.*:	(7c 00 d8 dc|dc d8 00 7c) 	msgclru r27
 #pass
diff --git a/gas/testsuite/gas/ppc/power9.s b/gas/testsuite/gas/ppc/power9.s
index 6905381..2d412b9 100644
--- a/gas/testsuite/gas/ppc/power9.s
+++ b/gas/testsuite/gas/ppc/power9.s
@@ -390,3 +390,7 @@ power9:
 	dcbf	    0,4,1
 	dcbflp	    0,5
 	dcbf	    0,5,3
+	ori	    31,31,0
+	exser
+	msgsndu     3
+	msgclru     27
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f745e56..94b5d77 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2020-08-10  Alan Modra  <amodra@gmail.com>
 
+	* ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
+	Enable icbt for power5, miso for power8.
+
+2020-08-10  Alan Modra  <amodra@gmail.com>
+
 	* ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
 	mtvsrd, and similarly for mfvsrd.
 
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 83579ea..8294c76 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -6114,6 +6114,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"rlnm.",	M(23,1),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
 
 {"nop",		OP(24),		0xffffffff,  PPCCOM,	PPCVLE,		{0}},
+{"exser",	0x63ff0000,	0xffffffff,  POWER9,	PPCVLE,		{0}},
 {"ori",		OP(24),		OP_MASK,     PPCCOM,	PPCVLE,		{RA, RS, UI}},
 {"oril",	OP(24),		OP_MASK,     PWRCOM,	PPCVLE,		{RA, RS, UI}},
 
@@ -6236,7 +6237,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"ldx",		X(31,21),	X_MASK,	     PPC64,	0,		{RT, RA0, RB}},
 
-{"icbt",	X(31,22),  X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0,	{CT, RA0, RB}},
+{"icbt",	X(31,22), X_MASK, POWER5|BOOKE|PPCE300, 0,		{CT, RA0, RB}},
 
 {"lwzx",	X(31,23),	X_MASK,	     PPCCOM,	0,		{RT, RA0, RB}},
 {"lx",		X(31,23),	X_MASK,	     PWRCOM,	0,		{RT, RA, RB}},
@@ -6354,6 +6355,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mulhw",	XO(31,75,0,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
 {"mulhw.",	XO(31,75,0,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
 
+{"msgsndu",	XRTRA(31,78,0,0), XRTRA_MASK, POWER9,	0,		{RB}},
 {"dlmzb",	XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0,	{RA, RS, RB}},
 {"dlmzb.",	XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0,	{RA, RS, RB}},
 
@@ -6387,6 +6389,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxvrdx",	X(31,109),	XX1_MASK,    POWER10,	0,		{XT6, RA0, RB}},
 
+{"msgclru",	XRTRA(31,110,0,0), XRTRA_MASK, POWER9,	0,		{RB}},
 {"mvidsplt",	X(31,110),	X_MASK,	     E6500,	0,		{VD, RA, RB}},
 
 {"mtsrdin",	X(31,114),	XRA_MASK,    PPC64,	0,		{RS, RB}},
@@ -7051,14 +7054,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"sthux",	X(31,439),	X_MASK,	     COM,	0,		{RS, RAS, RB}},
 
-{"mdors",	0x7f9ce378,	0xffffffff,  E500MC,	0,		{0}},
-
-{"miso",	0x7f5ad378,	0xffffffff,  E6500,	0,		{0}},
-
-/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
-   "or rX,rX,rX", with rX being r27, r29 and r30 respectively.	*/
+/* or 26,26,26 */
+{"miso",	0x7f5ad378,   0xffffffff, POWER8|E6500,	0,		{0}},
+/* or 27,27,27 */
 {"yield",	0x7f7bdb78,	0xffffffff,  POWER7,	0,		{0}},
+/* or 28,28,28 */
+{"mdors",	0x7f9ce378,	0xffffffff,  E500MC,	0,		{0}},
+/* or 29,29,29 */
 {"mdoio",	0x7fbdeb78,	0xffffffff,  POWER7,	0,		{0}},
+/* or 30,30,30 */
 {"mdoom",	0x7fdef378,	0xffffffff,  POWER7,	0,		{0}},
 {"mr",		XRC(31,444,0),	X_MASK,	     COM,	0,		{RA, RSB}},
 {"or",		XRC(31,444,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},