Formatting changes for RISC-V

This is a mixed bag of format changes:

 * Replacing constants with macros (0xffffffff with MINUS_ONE, for
   example).  There's one technically functional change in here (some
   MINUS_ONEs are changed to 0), but it only changes the behavior of an
   otherwise-unused field.
 * Using 0 instead of 0x0 in the relocation table.
 * There were some missing spaces before parens, the spaces have been
   added.
 * A handful of comments are now more descriptive.
 * A bunch of whitespace-only changes, mostly alignment and brace
   newlines.

bfd/
	* elfnn-riscv.c: Formatting and comment fixes throughout.
	* elfxx-riscv.c: Likewise.
	(howto_table): Change the src_mask field from MINUS_ONE to 0 for
	R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32,
	R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64.
opcodes/
	* riscv-opc.c: Formatting fixes.
gas/
	* config/tc-riscv.c: Formatting and comment fixes throughout.

7 files changed, 68 insertions, 59 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 8e0269c..500003d 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,11 @@
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+	* elfnn-riscv.c: Formatting and comment fixes throughout.
+	* elfxx-riscv.c: Likewise.
+	(howto_table): Change the src_mask field from MINUS_ONE to 0 for
+	R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32,
+	R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64.
+
 2016-12-20  Palmer Dabbelt  <palmer@dabbelt.com>
 
 	* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Improve
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 1ab97b9..f9b3e2c 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -220,7 +220,7 @@ riscv_make_plt_entry (bfd_vma got, bfd_vma addr, uint32_t *entry)
      nop */
 
   entry[0] = RISCV_UTYPE (AUIPC, X_T3, RISCV_PCREL_HIGH_PART (got, addr));
-  entry[1] = RISCV_ITYPE (LREG,  X_T3, X_T3, RISCV_PCREL_LOW_PART(got, addr));
+  entry[1] = RISCV_ITYPE (LREG,  X_T3, X_T3, RISCV_PCREL_LOW_PART (got, addr));
   entry[2] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
   entry[3] = RISCV_NOP;
 }
@@ -2329,7 +2329,7 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
     }
 
   if (h->got.offset != (bfd_vma) -1
-      && !(riscv_elf_hash_entry(h)->tls_type & (GOT_TLS_GD | GOT_TLS_IE)))
+      && !(riscv_elf_hash_entry (h)->tls_type & (GOT_TLS_GD | GOT_TLS_IE)))
     {
       asection *sgot;
       asection *srela;
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c1f28f7..0fb250d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -63,7 +63,7 @@ static reloc_howto_type howto_table[] =
 	 "R_RISCV_32",			/* name */
 	 FALSE,				/* partial_inplace */
 	 0,				/* src_mask */
-	 0xffffffff,			/* dst_mask */
+	 MINUS_ONE,			/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
   /* 64 bit relocation.  */
@@ -93,7 +93,7 @@ static reloc_howto_type howto_table[] =
 	 "R_RISCV_RELATIVE",		/* name */
 	 FALSE,				/* partial_inplace */
 	 0,				/* src_mask */
-	 0xffffffff,			/* dst_mask */
+	 MINUS_ONE,			/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
   HOWTO (R_RISCV_COPY,			/* type */
@@ -106,8 +106,8 @@ static reloc_howto_type howto_table[] =
 	 bfd_elf_generic_reloc,		/* special_function */
 	 "R_RISCV_COPY",		/* name */
 	 FALSE,				/* partial_inplace */
-	 0x0,         			/* src_mask */
-	 0x0,		        	/* dst_mask */
+	 0,         			/* src_mask */
+	 0,		        	/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
   HOWTO (R_RISCV_JUMP_SLOT,		/* type */
@@ -120,8 +120,8 @@ static reloc_howto_type howto_table[] =
 	 bfd_elf_generic_reloc,		/* special_function */
 	 "R_RISCV_JUMP_SLOT",		/* name */
 	 FALSE,				/* partial_inplace */
-	 0x0,         			/* src_mask */
-	 0x0,		        	/* dst_mask */
+	 0,         			/* src_mask */
+	 0,		        	/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
   /* Dynamic TLS relocations.  */
@@ -135,7 +135,7 @@ static reloc_howto_type howto_table[] =
 	 bfd_elf_generic_reloc, 	/* special_function */
 	 "R_RISCV_TLS_DTPMOD32",	/* name */
 	 FALSE,				/* partial_inplace */
-	 MINUS_ONE,			/* src_mask */
+	 0,				/* src_mask */
 	 MINUS_ONE,			/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
@@ -149,7 +149,7 @@ static reloc_howto_type howto_table[] =
 	 bfd_elf_generic_reloc, 	/* special_function */
 	 "R_RISCV_TLS_DTPMOD64",	/* name */
 	 FALSE,				/* partial_inplace */
-	 MINUS_ONE,			/* src_mask */
+	 0,				/* src_mask */
 	 MINUS_ONE,			/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
@@ -163,7 +163,7 @@ static reloc_howto_type howto_table[] =
 	 bfd_elf_generic_reloc, 	/* special_function */
 	 "R_RISCV_TLS_DTPREL32",	/* name */
 	 TRUE,				/* partial_inplace */
-	 MINUS_ONE,			/* src_mask */
+	 0,				/* src_mask */
 	 MINUS_ONE,			/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
@@ -177,7 +177,7 @@ static reloc_howto_type howto_table[] =
 	 bfd_elf_generic_reloc, 	/* special_function */
 	 "R_RISCV_TLS_DTPREL64",	/* name */
 	 TRUE,				/* partial_inplace */
-	 MINUS_ONE,			/* src_mask */
+	 0,				/* src_mask */
 	 MINUS_ONE,			/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
@@ -191,7 +191,7 @@ static reloc_howto_type howto_table[] =
 	 bfd_elf_generic_reloc, 	/* special_function */
 	 "R_RISCV_TLS_TPREL32",		/* name */
 	 FALSE,				/* partial_inplace */
-	 MINUS_ONE,			/* src_mask */
+	 0,				/* src_mask */
 	 MINUS_ONE,			/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
@@ -205,7 +205,7 @@ static reloc_howto_type howto_table[] =
 	 bfd_elf_generic_reloc, 	/* special_function */
 	 "R_RISCV_TLS_TPREL64",		/* name */
 	 FALSE,				/* partial_inplace */
-	 MINUS_ONE,			/* src_mask */
+	 0,				/* src_mask */
 	 MINUS_ONE,			/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
@@ -238,9 +238,6 @@ static reloc_howto_type howto_table[] =
 	 TRUE,				/* pc_relative */
 	 0,				/* bitpos */
 	 complain_overflow_dont,	/* complain_on_overflow */
-					/* This needs complex overflow
-					   detection, because the upper 36
-					   bits must match the PC + 4.  */
 	 bfd_elf_generic_reloc,		/* special_function */
 	 "R_RISCV_JAL",			/* name */
 	 FALSE,				/* partial_inplace */
@@ -264,7 +261,7 @@ static reloc_howto_type howto_table[] =
 					/* dst_mask */
 	 TRUE),				/* pcrel_offset */
 
-  /* 32-bit PC-relative function call (AUIPC/JALR).  */
+  /* Like R_RISCV_CALL, but not locally binding.  */
   HOWTO (R_RISCV_CALL_PLT,		/* type */
 	 0,				/* rightshift */
 	 2,				/* size */
@@ -460,7 +457,7 @@ static reloc_howto_type howto_table[] =
 	 ENCODE_STYPE_IMM (-1U),	/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
-  /* TLS LE thread pointer usage.  */
+  /* TLS LE thread pointer usage.  May be relaxed.  */
   HOWTO (R_RISCV_TPREL_ADD,		/* type */
 	 0,				/* rightshift */
 	 2,				/* size */
@@ -665,9 +662,6 @@ static reloc_howto_type howto_table[] =
 	 TRUE,				/* pc_relative */
 	 0,				/* bitpos */
 	 complain_overflow_dont,	/* complain_on_overflow */
-					/* This needs complex overflow
-					   detection, because the upper 36
-					   bits must match the PC + 4.  */
 	 bfd_elf_generic_reloc,		/* special_function */
 	 "R_RISCV_RVC_JUMP",		/* name */
 	 FALSE,				/* partial_inplace */
@@ -690,7 +684,7 @@ static reloc_howto_type howto_table[] =
 	 ENCODE_RVC_IMM (-1U),		/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
-  /* High 12 bits of 32-bit load or add.  */
+  /* GP-relative load.  */
   HOWTO (R_RISCV_GPREL_I,		/* type */
 	 0,				/* rightshift */
 	 2,				/* size */
@@ -705,7 +699,7 @@ static reloc_howto_type howto_table[] =
 	 ENCODE_ITYPE_IMM (-1U),	/* dst_mask */
 	 FALSE),			/* pcrel_offset */
 
-  /* High 12 bits of 32-bit store.  */
+  /* GP-relative store.  */
   HOWTO (R_RISCV_GPREL_S,		/* type */
 	 0,				/* rightshift */
 	 2,				/* size */
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8a41fc7..36f1c2f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+	* config/tc-riscv.c: Formatting and comment fixes throughout.
+
 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 
 	* config/tc-mips.c (md_convert_frag): Report an error instead of
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index b363867..d8a627d 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -28,6 +28,7 @@
 #include "itbl-ops.h"
 #include "dwarf2dbg.h"
 #include "dw2gencfi.h"
+#include "struc-symbol.h"
 
 #include "elf/riscv.h"
 #include "opcode/riscv.h"
@@ -511,29 +512,29 @@ validate_riscv_insn (const struct riscv_opcode *opc)
       case 'C': /* RVC */
 	switch (c = *p++)
 	  {
-	  case 'a': used_bits |= ENCODE_RVC_J_IMM(-1U); break;
+	  case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
 	  case 'c': break; /* RS1, constrained to equal sp */
 	  case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
-	  case 'j': used_bits |= ENCODE_RVC_IMM(-1U); break;
-	  case 'k': used_bits |= ENCODE_RVC_LW_IMM(-1U); break;
-	  case 'l': used_bits |= ENCODE_RVC_LD_IMM(-1U); break;
-	  case 'm': used_bits |= ENCODE_RVC_LWSP_IMM(-1U); break;
-	  case 'n': used_bits |= ENCODE_RVC_LDSP_IMM(-1U); break;
-	  case 'p': used_bits |= ENCODE_RVC_B_IMM(-1U); break;
+	  case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
+	  case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
+	  case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
+	  case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
+	  case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
+	  case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
 	  case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
 	  case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
-	  case 'u': used_bits |= ENCODE_RVC_IMM(-1U); break;
-	  case 'v': used_bits |= ENCODE_RVC_IMM(-1U); break;
+	  case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
+	  case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
 	  case 'w': break; /* RS1S, constrained to equal RD */
 	  case 'x': break; /* RS2S, constrained to equal RD */
-	  case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM(-1U); break;
-	  case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM(-1U); break;
-	  case 'M': used_bits |= ENCODE_RVC_SWSP_IMM(-1U); break;
-	  case 'N': used_bits |= ENCODE_RVC_SDSP_IMM(-1U); break;
+	  case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
+	  case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
+	  case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
+	  case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
 	  case 'U': break; /* RS1, constrained to equal RD */
 	  case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
-	  case '<': used_bits |= ENCODE_RVC_IMM(-1U); break;
-	  case '>': used_bits |= ENCODE_RVC_IMM(-1U); break;
+	  case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
+	  case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
 	  case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
 	  case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
 	  default:
@@ -563,11 +564,11 @@ validate_riscv_insn (const struct riscv_opcode *opc)
       case 'P':	USE_BITS (OP_MASK_PRED,		OP_SH_PRED); break;
       case 'Q':	USE_BITS (OP_MASK_SUCC,		OP_SH_SUCC); break;
       case 'o':
-      case 'j': used_bits |= ENCODE_ITYPE_IMM(-1U); break;
-      case 'a':	used_bits |= ENCODE_UJTYPE_IMM(-1U); break;
-      case 'p':	used_bits |= ENCODE_SBTYPE_IMM(-1U); break;
-      case 'q':	used_bits |= ENCODE_STYPE_IMM(-1U); break;
-      case 'u':	used_bits |= ENCODE_UTYPE_IMM(-1U); break;
+      case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
+      case 'a':	used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
+      case 'p':	used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
+      case 'q':	used_bits |= ENCODE_STYPE_IMM (-1U); break;
+      case 'u':	used_bits |= ENCODE_UTYPE_IMM (-1U); break;
       case '[': break;
       case ']': break;
       case '0': break;
@@ -661,7 +662,7 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
     {
       reloc_howto_type *howto;
 
-      gas_assert(address_expr);
+      gas_assert (address_expr);
       if (reloc_type == BFD_RELOC_12_PCREL
 	  || reloc_type == BFD_RELOC_RISCV_JMP)
 	{
@@ -814,7 +815,7 @@ static symbolS *
 make_internal_label (void)
 {
   return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg,
-					(valueT) frag_now_fix(), frag_now);
+					(valueT) frag_now_fix (), frag_now);
 }
 
 /* Load an entry from the GOT.  */
@@ -874,14 +875,14 @@ load_const (int reg, expressionS *ep)
       return;
     }
 
-  if (xlen > 32 && !IS_SEXT_32BIT_NUM(ep->X_add_number))
+  if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
     {
       /* Reduce to a signed 32-bit constant using SLLI and ADDI.  */
       while (((upper.X_add_number >> shift) & 1) == 0)
 	shift++;
 
       upper.X_add_number = (int64_t) upper.X_add_number >> shift;
-      load_const(reg, &upper);
+      load_const (reg, &upper);
 
       macro_build (NULL, "slli", "d,s,>", reg, reg, shift);
       if (lower.X_add_number != 0)
@@ -1469,8 +1470,8 @@ rvc_lui:
 		  my_getExpression (imm_expr, s);
 		  check_absolute_expr (ip, imm_expr);
 		  if ((unsigned long) imm_expr->X_add_number > 0xfff)
-		    as_warn(_("Improper CSR address (%lu)"),
-			    (unsigned long) imm_expr->X_add_number);
+		    as_warn (_("Improper CSR address (%lu)"),
+			     (unsigned long) imm_expr->X_add_number);
 		  INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
 		  imm_expr->X_op = O_absent;
 		  s = expr_end;
@@ -2242,7 +2243,7 @@ md_convert_frag_branch (fragS *fragp)
 	    goto done;
 
 	  default:
-	    abort();
+	    abort ();
 	}
     }
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 430b1f4..df466ef 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+	* riscv-opc.c: Formatting fixes.
+
 2016-12-20  Alan Modra  <amodra@gmail.com>
 
 	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1d8d579..256e089 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -34,8 +34,7 @@ const char * const riscv_gpr_names_numeric[NGPR] =
   "x24",  "x25",  "x26",  "x27",  "x28",  "x29",  "x30",  "x31"
 };
 
-const char * const riscv_gpr_names_abi[NGPR] =
-{
+const char * const riscv_gpr_names_abi[NGPR] = {
   "zero", "ra", "sp",  "gp",  "tp", "t0",  "t1",  "t2",
   "s0",   "s1", "a0",  "a1",  "a2", "a3",  "a4",  "a5",
   "a6",   "a7", "s2",  "s3",  "s4", "s5",  "s6",  "s7",
@@ -50,8 +49,7 @@ const char * const riscv_fpr_names_numeric[NFPR] =
   "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31"
 };
 
-const char * const riscv_fpr_names_abi[NFPR] =
-{
+const char * const riscv_fpr_names_abi[NFPR] = {
   "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
   "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
   "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
@@ -72,9 +70,9 @@ const char * const riscv_fpr_names_abi[NFPR] =
 #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
 #define MASK_RD (OP_MASK_RD << OP_SH_RD)
 #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
-#define MASK_IMM ENCODE_ITYPE_IMM(-1U)
-#define MASK_RVC_IMM ENCODE_RVC_IMM(-1U)
-#define MASK_UIMM ENCODE_UTYPE_IMM(-1U)
+#define MASK_IMM ENCODE_ITYPE_IMM (-1U)
+#define MASK_RVC_IMM ENCODE_RVC_IMM (-1U)
+#define MASK_UIMM ENCODE_UTYPE_IMM (-1U)
 #define MASK_RM (OP_MASK_RM << OP_SH_RM)
 #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
 #define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC)
@@ -240,7 +238,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"or",        "I",   "d,s,t",  MATCH_OR, MASK_OR, match_opcode, 0 },
 {"or",        "I",   "d,s,j",  MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
 {"auipc",     "I",   "d,u",  MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
-{"seqz",      "I",   "d,s",  MATCH_SLTIU | ENCODE_ITYPE_IMM(1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
+{"seqz",      "I",   "d,s",  MATCH_SLTIU | ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
 {"snez",      "I",   "d,t",  MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
 {"sltz",      "I",   "d,s",  MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
 {"sgtz",      "I",   "d,t",  MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },