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| author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 00:22:28 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 19:26:33 -0500 |
| commit | a2f8e947a8457341d2d82b555ff739839cb8de1f (patch) | |
| tree | f17e4e1e4dcd46368d7ad00d57b9b15dc40e4dfc | |
| parent | 0c7f5bd08c61ac3607f54cf1c5fe08f88b989175 (diff) | |
| download | gdb-a2f8e947a8457341d2d82b555ff739839cb8de1f.zip gdb-a2f8e947a8457341d2d82b555ff739839cb8de1f.tar.gz gdb-a2f8e947a8457341d2d82b555ff739839cb8de1f.tar.bz2 | |
sim: h8300: fix test mach markers
These tests all fail to assemble when targeting the h8300 or h8300h
cpu variants with errors like:
rotl.s:242: Warning: Opcode `rotl.b' with these operand types not available in H8/300H mode
rotl.s:242: Error: invalid operands
It's been this way for years and no one seems to care, so disable
them for those targets since the assembler thinks it's impossible.
| -rw-r--r-- | sim/testsuite/sim/h8300/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/rotl.s | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/rotr.s | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/rotxl.s | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/rotxr.s | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/shal.s | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/shar.s | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/shll.s | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/shlr.s | 2 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/tas.s | 2 |
10 files changed, 15 insertions, 9 deletions
diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog index a4e7532..82128cc 100644 --- a/sim/testsuite/sim/h8300/ChangeLog +++ b/sim/testsuite/sim/h8300/ChangeLog @@ -1,5 +1,11 @@ 2021-01-05 Mike Frysinger <vapier@gentoo.org> + * rotl.s (mach): Set to "h8300s h8sx". + * rotr.s, rotxl.s, rotxr.s, shal.s, shar.s, shll.s, shlr.s, tas.s: + Likewise. + +2021-01-05 Mike Frysinger <vapier@gentoo.org> + * allinsn.exp: Rewrite file to use globs. 2004-06-28 Alexandre Oliva <aoliva@redhat.com> diff --git a/sim/testsuite/sim/h8300/rotl.s b/sim/testsuite/sim/h8300/rotl.s index 088345d..1978c2d 100644 --- a/sim/testsuite/sim/h8300/rotl.s +++ b/sim/testsuite/sim/h8300/rotl.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotl' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s index 2a964c1..658ef82 100644 --- a/sim/testsuite/sim/h8300/rotr.s +++ b/sim/testsuite/sim/h8300/rotr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotxl.s b/sim/testsuite/sim/h8300/rotxl.s index 3ae703e..d0ff4a3 100644 --- a/sim/testsuite/sim/h8300/rotxl.s +++ b/sim/testsuite/sim/h8300/rotxl.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotxl' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s index 96ec8a1..31a351f 100644 --- a/sim/testsuite/sim/h8300/rotxr.s +++ b/sim/testsuite/sim/h8300/rotxr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotxr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shal.s b/sim/testsuite/sim/h8300/shal.s index ccea907..5d930d9 100644 --- a/sim/testsuite/sim/h8300/shal.s +++ b/sim/testsuite/sim/h8300/shal.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shal' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s index 9c9166b..6b182aa 100644 --- a/sim/testsuite/sim/h8300/shar.s +++ b/sim/testsuite/sim/h8300/shar.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shar' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shll.s b/sim/testsuite/sim/h8300/shll.s index 7fbf14d..f21a60b 100644 --- a/sim/testsuite/sim/h8300/shll.s +++ b/sim/testsuite/sim/h8300/shll.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shll' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s index 4223313..c9f6a08 100644 --- a/sim/testsuite/sim/h8300/shlr.s +++ b/sim/testsuite/sim/h8300/shlr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shlr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/tas.s b/sim/testsuite/sim/h8300/tas.s index b8aebd8..60bea92 100644 --- a/sim/testsuite/sim/h8300/tas.s +++ b/sim/testsuite/sim/h8300/tas.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'tas' -# mach(): h8300h h8300s h8sx +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 |