diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:48:41 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:48:41 +0100 |
| commit | 10d76650106ac50cd690536014244a0a03778a8e (patch) | |
| tree | 43ccc81ed587925867a6fc58cd35ef6e3b874930 | |
| parent | 53021dd1a03ecde87239c999d70c5591a91f1385 (diff) | |
| download | gdb-10d76650106ac50cd690536014244a0a03778a8e.zip gdb-10d76650106ac50cd690536014244a0a03778a8e.tar.gz gdb-10d76650106ac50cd690536014244a0a03778a8e.tar.bz2 | |
[AArch64][SVE 06/32] Generalise parse_neon_reg_list
Rename parse_neon_reg_list to parse_vector_reg_list and take
in the required register type as an argument. Later patches
will reuse the function for SVE registers.
gas/
* config/tc-aarch64.c (parse_neon_reg_list): Rename to...
(parse_vector_reg_list): ...this and take a register type
as input.
(parse_operands): Update accordingly.
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/config/tc-aarch64.c | 13 |
2 files changed, 15 insertions, 5 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 4780bf4..1af84be 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,12 @@ 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * config/tc-aarch64.c (parse_neon_reg_list): Rename to... + (parse_vector_reg_list): ...this and take a register type + as input. + (parse_operands): Update accordingly. + +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * config/tc-aarch64.c (parse_neon_type_for_operand): Rename to... (parse_vector_type_for_operand): ...this. (parse_typed_reg): Update accordingly. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index c425418..e65cc7a 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -982,8 +982,9 @@ eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2) && e1.width == e2.width && e1.index == e2.index; } -/* This function parses the NEON register list. On success, it returns - the parsed register list information in the following encoded format: +/* This function parses a list of vector registers of type TYPE. + On success, it returns the parsed register list information in the + following encoded format: bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg @@ -1003,7 +1004,8 @@ eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2) (by reg_list_valid_p). */ static int -parse_neon_reg_list (char **ccp, struct vector_type_el *vectype) +parse_vector_reg_list (char **ccp, aarch64_reg_type type, + struct vector_type_el *vectype) { char *str = *ccp; int nb_regs; @@ -1038,7 +1040,7 @@ parse_neon_reg_list (char **ccp, struct vector_type_el *vectype) str++; /* skip over '-' */ val_range = val; } - val = parse_typed_reg (&str, REG_TYPE_VN, NULL, &typeinfo, + val = parse_typed_reg (&str, type, NULL, &typeinfo, /*in_reg_list= */ TRUE); if (val == PARSE_FAIL) { @@ -5135,7 +5137,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_LVt: case AARCH64_OPND_LVt_AL: case AARCH64_OPND_LEt: - if ((val = parse_neon_reg_list (&str, &vectype)) == PARSE_FAIL) + if ((val = parse_vector_reg_list (&str, REG_TYPE_VN, + &vectype)) == PARSE_FAIL) goto failure; if (! reg_list_valid_p (val, /* accept_alternate */ 0)) { |