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authorTamar Christina <tamar.christina@arm.com>2017-08-04 09:39:35 -0300
committerAdhemerval Zanella <adhemerval.zanella@linaro.org>2017-08-04 09:39:35 -0300
commite0f59b0a7b5a2d879b0afc665ca0f28fb5b3d54e (patch)
treed612ef0ed6f215b82bf4197fbda50c9044a36558
parenteab9b00a3ab359d0a611ae33271ea337ade6f70f (diff)
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[AArch64] Add dot product support for AArch64 to binutils
gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B. (aarch64_features): Added dotprod. * doc/c-aarch64.texi: Added dotprod. * testsuite/gas/aarch64/dotproduct.d: New. * testsuite/gas/aarch64/dotproduct.s: New. opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. * aarch64-dis.c (aarch64_ext_reglane): Likewise. * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. (aarch64_feature_dotprod, DOT_INSN): New. (udot, sdot): New. * aarch64-dis-2.c: Regenerated. include/ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New. (aarch64_insn_class): Added dotprod. Cherry-pick of 65a55fbbd949868f7df3c65d39eb8d4455515132. Change-Id: I712657d13a2fdb43f14536aa0388dbbb2d13ee43
Diffstat
-rw-r--r--gas/ChangeLog.linaro8
-rw-r--r--gas/config/tc-aarch64.c10
-rw-r--r--gas/doc/c-aarch64.texi2
-rw-r--r--gas/testsuite/gas/aarch64/dotproduct.d548
-rw-r--r--gas/testsuite/gas/aarch64/dotproduct.s540
-rw-r--r--include/ChangeLog.linaro5
-rw-r--r--include/opcode/aarch64.h2
-rw-r--r--opcodes/ChangeLog.linaro9
-rw-r--r--opcodes/aarch64-asm.c14
-rw-r--r--opcodes/aarch64-dis-2.c382
-rw-r--r--opcodes/aarch64-dis.c15
-rw-r--r--opcodes/aarch64-tbl.h24
12 files changed, 1377 insertions, 182 deletions
diff --git a/gas/ChangeLog.linaro b/gas/ChangeLog.linaro
index 9a99365..717640e 100644
--- a/gas/ChangeLog.linaro
+++ b/gas/ChangeLog.linaro
@@ -2,6 +2,14 @@
Backport from master.
+ 2017-06-28 Tamar Christina <tamar.christina@arm.com>
+
+ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B.
+ (aarch64_features): Added dotprod.
+ * doc/c-aarch64.texi: Added dotprod.
+ * testsuite/gas/aarch64/dotproduct.d: New.
+ * testsuite/gas/aarch64/dotproduct.s: New.
+
2017-06-28 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f7b611c..3f3a5ea 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -790,7 +790,7 @@ aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
succeeds; otherwise return FALSE.
Accept only one occurrence of:
- 8b 16b 2h 4h 8h 2s 4s 1d 2d
+ 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
b h s d q */
static bfd_boolean
parse_vector_type_for_operand (aarch64_reg_type reg_type,
@@ -851,8 +851,10 @@ elt_size:
first_error (_("missing element size"));
return FALSE;
}
- if (width != 0 && width * element_size != 64 && width * element_size != 128
- && !(width == 2 && element_size == 16))
+ if (width != 0 && width * element_size != 64
+ && width * element_size != 128
+ && !(width == 2 && element_size == 16)
+ && !(width == 4 && element_size == 8))
{
first_error_fmt (_
("invalid element size %d and vector size combination %c"),
@@ -8450,6 +8452,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
| AARCH64_FEATURE_SIMD, 0)},
{"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
AARCH64_ARCH_NONE},
+ {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD, 0),
+ AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index f5be0d4..86a2e99 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -161,6 +161,8 @@ automatically cause those extensions to be disabled.
@item @code{sve} @tab ARMv8.2-A @tab No
@tab Enable the Scalable Vector Extensions. This implies @code{fp16},
@code{simd} and @code{compnum}.
+@item @code{dotprod} @tab ARMv8.2-A @tab No
+ @tab Enable the Dot Product extension. This implies @code{simd}.
@end multitable
@node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/dotproduct.d b/gas/testsuite/gas/aarch64/dotproduct.d
new file mode 100644
index 0000000..58669ff
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/dotproduct.d
@@ -0,0 +1,548 @@
+#as: -march=armv8.2-a+dotprod
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
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+[^:]+:\s+6fabe816 udot v22.4s, v0.16b, v11.b\[3\]
+[^:]+:\s+6fb6e816 udot v22.4s, v0.16b, v22.b\[3\]
+[^:]+:\s+6f80e176 udot v22.4s, v11.16b, v0.b\[0\]
+[^:]+:\s+6f8be176 udot v22.4s, v11.16b, v11.b\[0\]
+[^:]+:\s+6f96e176 udot v22.4s, v11.16b, v22.b\[0\]
+[^:]+:\s+6fa0e176 udot v22.4s, v11.16b, v0.b\[1\]
+[^:]+:\s+6fabe176 udot v22.4s, v11.16b, v11.b\[1\]
+[^:]+:\s+6fb6e176 udot v22.4s, v11.16b, v22.b\[1\]
+[^:]+:\s+6f80e976 udot v22.4s, v11.16b, v0.b\[2\]
+[^:]+:\s+6f8be976 udot v22.4s, v11.16b, v11.b\[2\]
+[^:]+:\s+6f96e976 udot v22.4s, v11.16b, v22.b\[2\]
+[^:]+:\s+6fa0e976 udot v22.4s, v11.16b, v0.b\[3\]
+[^:]+:\s+6fabe976 udot v22.4s, v11.16b, v11.b\[3\]
+[^:]+:\s+6fb6e976 udot v22.4s, v11.16b, v22.b\[3\]
+[^:]+:\s+6f80e2d6 udot v22.4s, v22.16b, v0.b\[0\]
+[^:]+:\s+6f8be2d6 udot v22.4s, v22.16b, v11.b\[0\]
+[^:]+:\s+6f96e2d6 udot v22.4s, v22.16b, v22.b\[0\]
+[^:]+:\s+6fa0e2d6 udot v22.4s, v22.16b, v0.b\[1\]
+[^:]+:\s+6fabe2d6 udot v22.4s, v22.16b, v11.b\[1\]
+[^:]+:\s+6fb6e2d6 udot v22.4s, v22.16b, v22.b\[1\]
+[^:]+:\s+6f80ead6 udot v22.4s, v22.16b, v0.b\[2\]
+[^:]+:\s+6f8bead6 udot v22.4s, v22.16b, v11.b\[2\]
+[^:]+:\s+6f96ead6 udot v22.4s, v22.16b, v22.b\[2\]
+[^:]+:\s+6fa0ead6 udot v22.4s, v22.16b, v0.b\[3\]
+[^:]+:\s+6fabead6 udot v22.4s, v22.16b, v11.b\[3\]
+[^:]+:\s+6fb6ead6 udot v22.4s, v22.16b, v22.b\[3\]
+[^:]+:\s+4f80e000 sdot v0.4s, v0.16b, v0.b\[0\]
+[^:]+:\s+4f8be000 sdot v0.4s, v0.16b, v11.b\[0\]
+[^:]+:\s+4f96e000 sdot v0.4s, v0.16b, v22.b\[0\]
+[^:]+:\s+4fa0e000 sdot v0.4s, v0.16b, v0.b\[1\]
+[^:]+:\s+4fabe000 sdot v0.4s, v0.16b, v11.b\[1\]
+[^:]+:\s+4fb6e000 sdot v0.4s, v0.16b, v22.b\[1\]
+[^:]+:\s+4f80e800 sdot v0.4s, v0.16b, v0.b\[2\]
+[^:]+:\s+4f8be800 sdot v0.4s, v0.16b, v11.b\[2\]
+[^:]+:\s+4f96e800 sdot v0.4s, v0.16b, v22.b\[2\]
+[^:]+:\s+4fa0e800 sdot v0.4s, v0.16b, v0.b\[3\]
+[^:]+:\s+4fabe800 sdot v0.4s, v0.16b, v11.b\[3\]
+[^:]+:\s+4fb6e800 sdot v0.4s, v0.16b, v22.b\[3\]
+[^:]+:\s+4f80e160 sdot v0.4s, v11.16b, v0.b\[0\]
+[^:]+:\s+4f8be160 sdot v0.4s, v11.16b, v11.b\[0\]
+[^:]+:\s+4f96e160 sdot v0.4s, v11.16b, v22.b\[0\]
+[^:]+:\s+4fa0e160 sdot v0.4s, v11.16b, v0.b\[1\]
+[^:]+:\s+4fabe160 sdot v0.4s, v11.16b, v11.b\[1\]
+[^:]+:\s+4fb6e160 sdot v0.4s, v11.16b, v22.b\[1\]
+[^:]+:\s+4f80e960 sdot v0.4s, v11.16b, v0.b\[2\]
+[^:]+:\s+4f8be960 sdot v0.4s, v11.16b, v11.b\[2\]
+[^:]+:\s+4f96e960 sdot v0.4s, v11.16b, v22.b\[2\]
+[^:]+:\s+4fa0e960 sdot v0.4s, v11.16b, v0.b\[3\]
+[^:]+:\s+4fabe960 sdot v0.4s, v11.16b, v11.b\[3\]
+[^:]+:\s+4fb6e960 sdot v0.4s, v11.16b, v22.b\[3\]
+[^:]+:\s+4f80e2c0 sdot v0.4s, v22.16b, v0.b\[0\]
+[^:]+:\s+4f8be2c0 sdot v0.4s, v22.16b, v11.b\[0\]
+[^:]+:\s+4f96e2c0 sdot v0.4s, v22.16b, v22.b\[0\]
+[^:]+:\s+4fa0e2c0 sdot v0.4s, v22.16b, v0.b\[1\]
+[^:]+:\s+4fabe2c0 sdot v0.4s, v22.16b, v11.b\[1\]
+[^:]+:\s+4fb6e2c0 sdot v0.4s, v22.16b, v22.b\[1\]
+[^:]+:\s+4f80eac0 sdot v0.4s, v22.16b, v0.b\[2\]
+[^:]+:\s+4f8beac0 sdot v0.4s, v22.16b, v11.b\[2\]
+[^:]+:\s+4f96eac0 sdot v0.4s, v22.16b, v22.b\[2\]
+[^:]+:\s+4fa0eac0 sdot v0.4s, v22.16b, v0.b\[3\]
+[^:]+:\s+4fabeac0 sdot v0.4s, v22.16b, v11.b\[3\]
+[^:]+:\s+4fb6eac0 sdot v0.4s, v22.16b, v22.b\[3\]
+[^:]+:\s+4f80e00b sdot v11.4s, v0.16b, v0.b\[0\]
+[^:]+:\s+4f8be00b sdot v11.4s, v0.16b, v11.b\[0\]
+[^:]+:\s+4f96e00b sdot v11.4s, v0.16b, v22.b\[0\]
+[^:]+:\s+4fa0e00b sdot v11.4s, v0.16b, v0.b\[1\]
+[^:]+:\s+4fabe00b sdot v11.4s, v0.16b, v11.b\[1\]
+[^:]+:\s+4fb6e00b sdot v11.4s, v0.16b, v22.b\[1\]
+[^:]+:\s+4f80e80b sdot v11.4s, v0.16b, v0.b\[2\]
+[^:]+:\s+4f8be80b sdot v11.4s, v0.16b, v11.b\[2\]
+[^:]+:\s+4f96e80b sdot v11.4s, v0.16b, v22.b\[2\]
+[^:]+:\s+4fa0e80b sdot v11.4s, v0.16b, v0.b\[3\]
+[^:]+:\s+4fabe80b sdot v11.4s, v0.16b, v11.b\[3\]
+[^:]+:\s+4fb6e80b sdot v11.4s, v0.16b, v22.b\[3\]
+[^:]+:\s+4f80e16b sdot v11.4s, v11.16b, v0.b\[0\]
+[^:]+:\s+4f8be16b sdot v11.4s, v11.16b, v11.b\[0\]
+[^:]+:\s+4f96e16b sdot v11.4s, v11.16b, v22.b\[0\]
+[^:]+:\s+4fa0e16b sdot v11.4s, v11.16b, v0.b\[1\]
+[^:]+:\s+4fabe16b sdot v11.4s, v11.16b, v11.b\[1\]
+[^:]+:\s+4fb6e16b sdot v11.4s, v11.16b, v22.b\[1\]
+[^:]+:\s+4f80e96b sdot v11.4s, v11.16b, v0.b\[2\]
+[^:]+:\s+4f8be96b sdot v11.4s, v11.16b, v11.b\[2\]
+[^:]+:\s+4f96e96b sdot v11.4s, v11.16b, v22.b\[2\]
+[^:]+:\s+4fa0e96b sdot v11.4s, v11.16b, v0.b\[3\]
+[^:]+:\s+4fabe96b sdot v11.4s, v11.16b, v11.b\[3\]
+[^:]+:\s+4fb6e96b sdot v11.4s, v11.16b, v22.b\[3\]
+[^:]+:\s+4f80e2cb sdot v11.4s, v22.16b, v0.b\[0\]
+[^:]+:\s+4f8be2cb sdot v11.4s, v22.16b, v11.b\[0\]
+[^:]+:\s+4f96e2cb sdot v11.4s, v22.16b, v22.b\[0\]
+[^:]+:\s+4fa0e2cb sdot v11.4s, v22.16b, v0.b\[1\]
+[^:]+:\s+4fabe2cb sdot v11.4s, v22.16b, v11.b\[1\]
+[^:]+:\s+4fb6e2cb sdot v11.4s, v22.16b, v22.b\[1\]
+[^:]+:\s+4f80eacb sdot v11.4s, v22.16b, v0.b\[2\]
+[^:]+:\s+4f8beacb sdot v11.4s, v22.16b, v11.b\[2\]
+[^:]+:\s+4f96eacb sdot v11.4s, v22.16b, v22.b\[2\]
+[^:]+:\s+4fa0eacb sdot v11.4s, v22.16b, v0.b\[3\]
+[^:]+:\s+4fabeacb sdot v11.4s, v22.16b, v11.b\[3\]
+[^:]+:\s+4fb6eacb sdot v11.4s, v22.16b, v22.b\[3\]
+[^:]+:\s+4f80e016 sdot v22.4s, v0.16b, v0.b\[0\]
+[^:]+:\s+4f8be016 sdot v22.4s, v0.16b, v11.b\[0\]
+[^:]+:\s+4f96e016 sdot v22.4s, v0.16b, v22.b\[0\]
+[^:]+:\s+4fa0e016 sdot v22.4s, v0.16b, v0.b\[1\]
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+[^:]+:\s+4fb6e016 sdot v22.4s, v0.16b, v22.b\[1\]
+[^:]+:\s+4f80e816 sdot v22.4s, v0.16b, v0.b\[2\]
+[^:]+:\s+4f8be816 sdot v22.4s, v0.16b, v11.b\[2\]
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+[^:]+:\s+4fabe816 sdot v22.4s, v0.16b, v11.b\[3\]
+[^:]+:\s+4fb6e816 sdot v22.4s, v0.16b, v22.b\[3\]
+[^:]+:\s+4f80e176 sdot v22.4s, v11.16b, v0.b\[0\]
+[^:]+:\s+4f8be176 sdot v22.4s, v11.16b, v11.b\[0\]
+[^:]+:\s+4f96e176 sdot v22.4s, v11.16b, v22.b\[0\]
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+[^:]+:\s+4fb6e176 sdot v22.4s, v11.16b, v22.b\[1\]
+[^:]+:\s+4f80e976 sdot v22.4s, v11.16b, v0.b\[2\]
+[^:]+:\s+4f8be976 sdot v22.4s, v11.16b, v11.b\[2\]
+[^:]+:\s+4f96e976 sdot v22.4s, v11.16b, v22.b\[2\]
+[^:]+:\s+4fa0e976 sdot v22.4s, v11.16b, v0.b\[3\]
+[^:]+:\s+4fabe976 sdot v22.4s, v11.16b, v11.b\[3\]
+[^:]+:\s+4fb6e976 sdot v22.4s, v11.16b, v22.b\[3\]
+[^:]+:\s+4f80e2d6 sdot v22.4s, v22.16b, v0.b\[0\]
+[^:]+:\s+4f8be2d6 sdot v22.4s, v22.16b, v11.b\[0\]
+[^:]+:\s+4f96e2d6 sdot v22.4s, v22.16b, v22.b\[0\]
+[^:]+:\s+4fa0e2d6 sdot v22.4s, v22.16b, v0.b\[1\]
+[^:]+:\s+4fabe2d6 sdot v22.4s, v22.16b, v11.b\[1\]
+[^:]+:\s+4fb6e2d6 sdot v22.4s, v22.16b, v22.b\[1\]
+[^:]+:\s+4f80ead6 sdot v22.4s, v22.16b, v0.b\[2\]
+[^:]+:\s+4f8bead6 sdot v22.4s, v22.16b, v11.b\[2\]
+[^:]+:\s+4f96ead6 sdot v22.4s, v22.16b, v22.b\[2\]
+[^:]+:\s+4fa0ead6 sdot v22.4s, v22.16b, v0.b\[3\]
+[^:]+:\s+4fabead6 sdot v22.4s, v22.16b, v11.b\[3\]
+[^:]+:\s+4fb6ead6 sdot v22.4s, v22.16b, v22.b\[3\]
diff --git a/gas/testsuite/gas/aarch64/dotproduct.s b/gas/testsuite/gas/aarch64/dotproduct.s
new file mode 100644
index 0000000..b3844e1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/dotproduct.s
@@ -0,0 +1,540 @@
+UDOT V0.2S, V0.8B, V0.8B
+UDOT V0.2S, V0.8B, V11.8B
+UDOT V0.2S, V0.8B, V22.8B
+UDOT V0.2S, V11.8B, V0.8B
+UDOT V0.2S, V11.8B, V11.8B
+UDOT V0.2S, V11.8B, V22.8B
+UDOT V0.2S, V22.8B, V0.8B
+UDOT V0.2S, V22.8B, V11.8B
+UDOT V0.2S, V22.8B, V22.8B
+UDOT V11.2S, V0.8B, V0.8B
+UDOT V11.2S, V0.8B, V11.8B
+UDOT V11.2S, V0.8B, V22.8B
+UDOT V11.2S, V11.8B, V0.8B
+UDOT V11.2S, V11.8B, V11.8B
+UDOT V11.2S, V11.8B, V22.8B
+UDOT V11.2S, V22.8B, V0.8B
+UDOT V11.2S, V22.8B, V11.8B
+UDOT V11.2S, V22.8B, V22.8B
+UDOT V22.2S, V0.8B, V0.8B
+UDOT V22.2S, V0.8B, V11.8B
+UDOT V22.2S, V0.8B, V22.8B
+UDOT V22.2S, V11.8B, V0.8B
+UDOT V22.2S, V11.8B, V11.8B
+UDOT V22.2S, V11.8B, V22.8B
+UDOT V22.2S, V22.8B, V0.8B
+UDOT V22.2S, V22.8B, V11.8B
+UDOT V22.2S, V22.8B, V22.8B
+SDOT V0.2S, V0.8B, V0.8B
+SDOT V0.2S, V0.8B, V11.8B
+SDOT V0.2S, V0.8B, V22.8B
+SDOT V0.2S, V11.8B, V0.8B
+SDOT V0.2S, V11.8B, V11.8B
+SDOT V0.2S, V11.8B, V22.8B
+SDOT V0.2S, V22.8B, V0.8B
+SDOT V0.2S, V22.8B, V11.8B
+SDOT V0.2S, V22.8B, V22.8B
+SDOT V11.2S, V0.8B, V0.8B
+SDOT V11.2S, V0.8B, V11.8B
+SDOT V11.2S, V0.8B, V22.8B
+SDOT V11.2S, V11.8B, V0.8B
+SDOT V11.2S, V11.8B, V11.8B
+SDOT V11.2S, V11.8B, V22.8B
+SDOT V11.2S, V22.8B, V0.8B
+SDOT V11.2S, V22.8B, V11.8B
+SDOT V11.2S, V22.8B, V22.8B
+SDOT V22.2S, V0.8B, V0.8B
+SDOT V22.2S, V0.8B, V11.8B
+SDOT V22.2S, V0.8B, V22.8B
+SDOT V22.2S, V11.8B, V0.8B
+SDOT V22.2S, V11.8B, V11.8B
+SDOT V22.2S, V11.8B, V22.8B
+SDOT V22.2S, V22.8B, V0.8B
+SDOT V22.2S, V22.8B, V11.8B
+SDOT V22.2S, V22.8B, V22.8B
+UDOT V0.4S, V0.16B, V0.16B
+UDOT V0.4S, V0.16B, V11.16B
+UDOT V0.4S, V0.16B, V22.16B
+UDOT V0.4S, V11.16B, V0.16B
+UDOT V0.4S, V11.16B, V11.16B
+UDOT V0.4S, V11.16B, V22.16B
+UDOT V0.4S, V22.16B, V0.16B
+UDOT V0.4S, V22.16B, V11.16B
+UDOT V0.4S, V22.16B, V22.16B
+UDOT V11.4S, V0.16B, V0.16B
+UDOT V11.4S, V0.16B, V11.16B
+UDOT V11.4S, V0.16B, V22.16B
+UDOT V11.4S, V11.16B, V0.16B
+UDOT V11.4S, V11.16B, V11.16B
+UDOT V11.4S, V11.16B, V22.16B
+UDOT V11.4S, V22.16B, V0.16B
+UDOT V11.4S, V22.16B, V11.16B
+UDOT V11.4S, V22.16B, V22.16B
+UDOT V22.4S, V0.16B, V0.16B
+UDOT V22.4S, V0.16B, V11.16B
+UDOT V22.4S, V0.16B, V22.16B
+UDOT V22.4S, V11.16B, V0.16B
+UDOT V22.4S, V11.16B, V11.16B
+UDOT V22.4S, V11.16B, V22.16B
+UDOT V22.4S, V22.16B, V0.16B
+UDOT V22.4S, V22.16B, V11.16B
+UDOT V22.4S, V22.16B, V22.16B
+SDOT V0.4S, V0.16B, V0.16B
+SDOT V0.4S, V0.16B, V11.16B
+SDOT V0.4S, V0.16B, V22.16B
+SDOT V0.4S, V11.16B, V0.16B
+SDOT V0.4S, V11.16B, V11.16B
+SDOT V0.4S, V11.16B, V22.16B
+SDOT V0.4S, V22.16B, V0.16B
+SDOT V0.4S, V22.16B, V11.16B
+SDOT V0.4S, V22.16B, V22.16B
+SDOT V11.4S, V0.16B, V0.16B
+SDOT V11.4S, V0.16B, V11.16B
+SDOT V11.4S, V0.16B, V22.16B
+SDOT V11.4S, V11.16B, V0.16B
+SDOT V11.4S, V11.16B, V11.16B
+SDOT V11.4S, V11.16B, V22.16B
+SDOT V11.4S, V22.16B, V0.16B
+SDOT V11.4S, V22.16B, V11.16B
+SDOT V11.4S, V22.16B, V22.16B
+SDOT V22.4S, V0.16B, V0.16B
+SDOT V22.4S, V0.16B, V11.16B
+SDOT V22.4S, V0.16B, V22.16B
+SDOT V22.4S, V11.16B, V0.16B
+SDOT V22.4S, V11.16B, V11.16B
+SDOT V22.4S, V11.16B, V22.16B
+SDOT V22.4S, V22.16B, V0.16B
+SDOT V22.4S, V22.16B, V11.16B
+SDOT V22.4S, V22.16B, V22.16B
+UDOT V0.2S, V0.8B, V0.4B[0]
+UDOT V0.2S, V0.8B, V11.4B[0]
+UDOT V0.2S, V0.8B, V22.4B[0]
+UDOT V0.2S, V0.8B, V0.4B[1]
+UDOT V0.2S, V0.8B, V11.4B[1]
+UDOT V0.2S, V0.8B, V22.4B[1]
+UDOT V0.2S, V0.8B, V0.4B[2]
+UDOT V0.2S, V0.8B, V11.4B[2]
+UDOT V0.2S, V0.8B, V22.4B[2]
+UDOT V0.2S, V0.8B, V0.4B[3]
+UDOT V0.2S, V0.8B, V11.4B[3]
+UDOT V0.2S, V0.8B, V22.4B[3]
+UDOT V0.2S, V11.8B, V0.4B[0]
+UDOT V0.2S, V11.8B, V11.4B[0]
+UDOT V0.2S, V11.8B, V22.4B[0]
+UDOT V0.2S, V11.8B, V0.4B[1]
+UDOT V0.2S, V11.8B, V11.4B[1]
+UDOT V0.2S, V11.8B, V22.4B[1]
+UDOT V0.2S, V11.8B, V0.4B[2]
+UDOT V0.2S, V11.8B, V11.4B[2]
+UDOT V0.2S, V11.8B, V22.4B[2]
+UDOT V0.2S, V11.8B, V0.4B[3]
+UDOT V0.2S, V11.8B, V11.4B[3]
+UDOT V0.2S, V11.8B, V22.4B[3]
+UDOT V0.2S, V22.8B, V0.4B[0]
+UDOT V0.2S, V22.8B, V11.4B[0]
+UDOT V0.2S, V22.8B, V22.4B[0]
+UDOT V0.2S, V22.8B, V0.4B[1]
+UDOT V0.2S, V22.8B, V11.4B[1]
+UDOT V0.2S, V22.8B, V22.4B[1]
+UDOT V0.2S, V22.8B, V0.4B[2]
+UDOT V0.2S, V22.8B, V11.4B[2]
+UDOT V0.2S, V22.8B, V22.4B[2]
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+SDOT V0.4S, V22.16B, V11.4B[3]
+SDOT V0.4S, V22.16B, V22.4B[3]
+SDOT V11.4S, V0.16B, V0.4B[0]
+SDOT V11.4S, V0.16B, V11.4B[0]
+SDOT V11.4S, V0.16B, V22.4B[0]
+SDOT V11.4S, V0.16B, V0.4B[1]
+SDOT V11.4S, V0.16B, V11.4B[1]
+SDOT V11.4S, V0.16B, V22.4B[1]
+SDOT V11.4S, V0.16B, V0.4B[2]
+SDOT V11.4S, V0.16B, V11.4B[2]
+SDOT V11.4S, V0.16B, V22.4B[2]
+SDOT V11.4S, V0.16B, V0.4B[3]
+SDOT V11.4S, V0.16B, V11.4B[3]
+SDOT V11.4S, V0.16B, V22.4B[3]
+SDOT V11.4S, V11.16B, V0.4B[0]
+SDOT V11.4S, V11.16B, V11.4B[0]
+SDOT V11.4S, V11.16B, V22.4B[0]
+SDOT V11.4S, V11.16B, V0.4B[1]
+SDOT V11.4S, V11.16B, V11.4B[1]
+SDOT V11.4S, V11.16B, V22.4B[1]
+SDOT V11.4S, V11.16B, V0.4B[2]
+SDOT V11.4S, V11.16B, V11.4B[2]
+SDOT V11.4S, V11.16B, V22.4B[2]
+SDOT V11.4S, V11.16B, V0.4B[3]
+SDOT V11.4S, V11.16B, V11.4B[3]
+SDOT V11.4S, V11.16B, V22.4B[3]
+SDOT V11.4S, V22.16B, V0.4B[0]
+SDOT V11.4S, V22.16B, V11.4B[0]
+SDOT V11.4S, V22.16B, V22.4B[0]
+SDOT V11.4S, V22.16B, V0.4B[1]
+SDOT V11.4S, V22.16B, V11.4B[1]
+SDOT V11.4S, V22.16B, V22.4B[1]
+SDOT V11.4S, V22.16B, V0.4B[2]
+SDOT V11.4S, V22.16B, V11.4B[2]
+SDOT V11.4S, V22.16B, V22.4B[2]
+SDOT V11.4S, V22.16B, V0.4B[3]
+SDOT V11.4S, V22.16B, V11.4B[3]
+SDOT V11.4S, V22.16B, V22.4B[3]
+SDOT V22.4S, V0.16B, V0.4B[0]
+SDOT V22.4S, V0.16B, V11.4B[0]
+SDOT V22.4S, V0.16B, V22.4B[0]
+SDOT V22.4S, V0.16B, V0.4B[1]
+SDOT V22.4S, V0.16B, V11.4B[1]
+SDOT V22.4S, V0.16B, V22.4B[1]
+SDOT V22.4S, V0.16B, V0.4B[2]
+SDOT V22.4S, V0.16B, V11.4B[2]
+SDOT V22.4S, V0.16B, V22.4B[2]
+SDOT V22.4S, V0.16B, V0.4B[3]
+SDOT V22.4S, V0.16B, V11.4B[3]
+SDOT V22.4S, V0.16B, V22.4B[3]
+SDOT V22.4S, V11.16B, V0.4B[0]
+SDOT V22.4S, V11.16B, V11.4B[0]
+SDOT V22.4S, V11.16B, V22.4B[0]
+SDOT V22.4S, V11.16B, V0.4B[1]
+SDOT V22.4S, V11.16B, V11.4B[1]
+SDOT V22.4S, V11.16B, V22.4B[1]
+SDOT V22.4S, V11.16B, V0.4B[2]
+SDOT V22.4S, V11.16B, V11.4B[2]
+SDOT V22.4S, V11.16B, V22.4B[2]
+SDOT V22.4S, V11.16B, V0.4B[3]
+SDOT V22.4S, V11.16B, V11.4B[3]
+SDOT V22.4S, V11.16B, V22.4B[3]
+SDOT V22.4S, V22.16B, V0.4B[0]
+SDOT V22.4S, V22.16B, V11.4B[0]
+SDOT V22.4S, V22.16B, V22.4B[0]
+SDOT V22.4S, V22.16B, V0.4B[1]
+SDOT V22.4S, V22.16B, V11.4B[1]
+SDOT V22.4S, V22.16B, V22.4B[1]
+SDOT V22.4S, V22.16B, V0.4B[2]
+SDOT V22.4S, V22.16B, V11.4B[2]
+SDOT V22.4S, V22.16B, V22.4B[2]
+SDOT V22.4S, V22.16B, V0.4B[3]
+SDOT V22.4S, V22.16B, V11.4B[3]
+SDOT V22.4S, V22.16B, V22.4B[3]
diff --git a/include/ChangeLog.linaro b/include/ChangeLog.linaro
index d952a16..23d01ac 100644
--- a/include/ChangeLog.linaro
+++ b/include/ChangeLog.linaro
@@ -2,6 +2,11 @@
Backport from master.
+ 2017-06-28 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New.
+ (aarch64_insn_class): Added dotprod.
+
2017-06-28 Jiong Wang <jiong.wang@arm.com>
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 37e2486..c5788e2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -55,6 +55,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
+#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -508,6 +509,7 @@ enum aarch64_insn_class
sve_size_hsd,
sve_size_sd,
testbranch,
+ dotproduct,
};
/* Opcode enumerators. */
diff --git a/opcodes/ChangeLog.linaro b/opcodes/ChangeLog.linaro
index 1a076e7..f3d7e4a 100644
--- a/opcodes/ChangeLog.linaro
+++ b/opcodes/ChangeLog.linaro
@@ -2,6 +2,15 @@
Backport from master.
+ 2017-06-28 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
+ * aarch64-dis.c (aarch64_ext_reglane): Likewise.
+ * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
+ (aarch64_feature_dotprod, DOT_INSN): New.
+ (udot, sdot): New.
+ * aarch64-dis-2.c: Regenerated.
+
2017-06-28 Jiong Wang <jiong.wang@arm.com>
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 91e40cb..a8173b3 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -121,6 +121,20 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
insert_field (FLD_imm5, code, value, 0);
}
}
+ else if (inst->opcode->iclass == dotproduct)
+ {
+ unsigned reglane_index = info->reglane.index;
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_S_B:
+ /* L:H */
+ assert (reglane_index < 4);
+ insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
+ break;
+ default:
+ assert (0);
+ }
+ }
else
{
/* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index fe71ebc..bbe0669 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -12771,11 +12771,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx10x001xxxxx0xx01110xxx
- sqrdmlah. */
- return 364;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx100001xxxxx0xx01110xxx
+ sqrdmlah. */
+ return 364;
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101001xxxxx0xx011100xx
+ sdot. */
+ return 1987;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx101001xxxxx0xx011101xx
+ udot. */
+ return 1986;
+ }
+ }
}
else
{
@@ -17931,13 +17953,13 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 28) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
- if (((word >> 13) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 13) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -17947,60 +17969,49 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx0x0011xxxxxxxx11110xxx
- sqdmulh. */
- return 109;
- }
- }
- else
- {
- if (((word >> 29) & 0x1) == 0)
- {
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx0x01x1xxxxxxxx1111000x
- smull. */
- return 105;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx0x01x1xxxxxxxx1111001x
- smull2. */
- return 106;
- }
- }
- else
- {
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx0x01x1xxxxxxxx1111010x
- umull. */
- return 123;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0101xxxxxxxx1111000x
+ smull. */
+ return 105;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0101xxxxxxxx1111001x
+ smull2. */
+ return 106;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx0x01x1xxxxxxxx1111011x
- umull2. */
- return 124;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0101xxxxxxxx1111010x
+ umull. */
+ return 123;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0101xxxxxxxx1111011x
+ umull2. */
+ return 124;
+ }
}
}
}
- }
- else
- {
- if (((word >> 13) & 0x1) == 0)
+ else
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 13) & 0x1) == 0)
{
if (((word >> 23) & 0x1) == 0)
{
@@ -18043,28 +18054,6 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 29) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx0x1011xxxxxxxx111100xx
- sqrdmulh. */
- return 110;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx0x1011xxxxxxxx111101xx
- sqrdmlah. */
- return 127;
- }
- }
- }
- else
- {
- if (((word >> 14) & 0x1) == 0)
- {
if (((word >> 30) & 0x1) == 0)
{
/* 33222222222211111111110000000000
@@ -18082,22 +18071,11 @@ aarch64_opcode_lookup_1 (uint32_t word)
return 108;
}
}
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx0x1111xxxxxxxx11110xxx
- sqrdmlsh. */
- return 128;
- }
}
}
- }
- else
- {
- if (((word >> 11) & 0x1) == 0)
+ else
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
if (((word >> 12) & 0x1) == 0)
{
@@ -18140,173 +18118,217 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 13) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
if (((word >> 29) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx10x011xxxxxxxx111100xx
- movi. */
- return 135;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110x01xxxxxxxx1111000x
+ rshrn. */
+ return 376;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110x01xxxxxxxx1111001x
+ rshrn2. */
+ return 377;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx10x011xxxxxxxx111101xx
- mvni. */
- return 143;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110x01xxxxxxxx1111010x
+ sqrshrun. */
+ return 400;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx110x01xxxxxxxx1111011x
+ sqrshrun2. */
+ return 401;
+ }
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 30) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx100111xxxxxxxx111100xx
- movi. */
- return 136;
+ xxxxxxxxxx111x01xxxxxxxx1111000x
+ sqrshrn. */
+ return 380;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx100111xxxxxxxx111101xx
- movi. */
- return 144;
+ xxxxxxxxxx111x01xxxxxxxx1111001x
+ sqrshrn2. */
+ return 381;
}
}
else
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 30) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx101111xxxxxxxx111100xx
- fmov. */
- return 137;
+ xxxxxxxxxx111x01xxxxxxxx1111010x
+ uqrshrn. */
+ return 404;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx101111xxxxxxxx111101xx
- fmov. */
- return 146;
+ xxxxxxxxxx111x01xxxxxxxx1111011x
+ uqrshrn2. */
+ return 405;
}
}
}
}
}
- else
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx110xx1xxxxxxxx1111000x
- rshrn. */
- return 376;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx110xx1xxxxxxxx1111001x
- rshrn2. */
- return 377;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x0011xxxxxxxx11110xxx
+ sqdmulh. */
+ return 109;
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx110xx1xxxxxxxx1111010x
- sqrshrun. */
- return 400;
+ xxxxxxxxxx0x1011xxxxxxxx111100xx
+ sqrdmulh. */
+ return 110;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx110xx1xxxxxxxx1111011x
- sqrshrun2. */
- return 401;
+ xxxxxxxxxx0x1011xxxxxxxx111101xx
+ sqrdmlah. */
+ return 127;
}
}
}
else
{
- if (((word >> 13) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xx011xxxxxxxx111100xx
+ movi. */
+ return 135;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx1xx011xxxxxxxx111101xx
+ mvni. */
+ return 143;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx0111xxxxxxxx111100xx
+ movi. */
+ return 136;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxx0111xxxxxxxx111101xx
+ movi. */
+ return 144;
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx0x1111xxxxxxxx11110xxx
+ sqrdmlsh. */
+ return 128;
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx1110x1xxxxxxxx1111000x
- sqrshrn. */
- return 380;
+ xxxxxxxxxx101111xxxxxxxx111100xx
+ fmov. */
+ return 137;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx1110x1xxxxxxxx1111001x
- sqrshrn2. */
- return 381;
+ xxxxxxxxxx101111xxxxxxxx111101xx
+ fmov. */
+ return 146;
}
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx1110x1xxxxxxxx1111010x
- uqrshrn. */
- return 404;
+ xxxxxxxxxx111111xxxxxxxx111100xx
+ fmov. */
+ return 138;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx1110x1xxxxxxxx1111011x
- uqrshrn2. */
- return 405;
+ xxxxxxxxxx111111xxxxxxxx111101xx
+ fcvtzu. */
+ return 412;
}
}
}
- else
- {
- if (((word >> 29) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx1111x1xxxxxxxx111100xx
- fmov. */
- return 138;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx1111x1xxxxxxxx111101xx
- fcvtzu. */
- return 412;
- }
- }
}
}
}
@@ -18743,11 +18765,13 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
case 403: return NULL; /* uqshrn2 --> NULL. */
case 136: value = 386; break; /* movi --> scvtf. */
case 386: value = 387; break; /* scvtf --> scvtf. */
- case 387: return NULL; /* scvtf --> NULL. */
+ case 387: value = 1989; break; /* scvtf --> sdot. */
+ case 1989: return NULL; /* sdot --> NULL. */
case 144: value = 145; break; /* movi --> movi. */
case 145: value = 410; break; /* movi --> ucvtf. */
case 410: value = 411; break; /* ucvtf --> ucvtf. */
- case 411: return NULL; /* ucvtf --> NULL. */
+ case 411: value = 1988; break; /* ucvtf --> udot. */
+ case 1988: return NULL; /* udot --> NULL. */
case 138: value = 388; break; /* fmov --> fcvtzs. */
case 388: value = 389; break; /* fcvtzs --> fcvtzs. */
case 389: return NULL; /* fcvtzs --> NULL. */
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index b528af6..7d771f9 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -325,6 +325,21 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
info->reglane.index = (unsigned) (value >> 1);
}
}
+ else if (inst->opcode->iclass == dotproduct)
+ {
+ /* Need information in other operand(s) to help decoding. */
+ info->qualifier = get_expected_qualifier (inst, info->idx);
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_S_B:
+ /* L:H */
+ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
+ info->reglane.regno &= 0x1f;
+ break;
+ default:
+ return 0;
+ }
+ }
else
{
/* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 72b9952..5a2ec43 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1982,6 +1982,19 @@
{ \
QLF3(X,X,NIL), \
}
+/* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.8B. */
+#define QL_V3DOT \
+{ \
+ QLF3(V_2S, V_8B, V_8B), \
+ QLF3(V_4S, V_16B, V_16B),\
+}
+
+/* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.4B[<index>]. */
+#define QL_V2DOT \
+{ \
+ QLF3(V_2S, V_8B, S_B),\
+ QLF3(V_4S, V_16B, S_B),\
+}
/* Opcode table. */
@@ -2021,6 +2034,8 @@ static const aarch64_feature_set aarch64_feature_compnum =
AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0);
static const aarch64_feature_set aarch64_feature_rcpc =
AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0);
+static const aarch64_feature_set aarch64_feature_dotprod =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_DOTPROD, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2040,6 +2055,7 @@ static const aarch64_feature_set aarch64_feature_rcpc =
#define FP_V8_3 &aarch64_feature_fp_v8_3
#define COMPNUM &aarch64_feature_compnum
#define RCPC &aarch64_feature_rcpc
+#define DOTPROD &aarch64_feature_dotprod
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL }
@@ -2072,6 +2088,8 @@ static const aarch64_feature_set aarch64_feature_rcpc =
{ NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, NULL }
#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, NULL }
+#define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{
@@ -4137,6 +4155,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("fmov", 0x05104000, 0xff30ffe0, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_HSD, F_ALIAS | F_PSEUDO, 0),
_SVE_INSN ("orn", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, 1),
+ /* SIMD Dot Product (optional in v8.2-A). */
+ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
+ DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
+ DOT_INSN ("udot", 0x2f00e000, 0xbf00f000, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
+ DOT_INSN ("sdot", 0xf00e000, 0xbf00f000, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, NULL},
};
generated by cgit v1.1 at 2024-11-21 15:21:07 +0000