diff options
| author | Paul Brook <paul@codesourcery.com> | 2005-09-02 13:12:45 +0000 |
|---|---|---|
| committer | Paul Brook <paul@codesourcery.com> | 2005-09-02 13:12:45 +0000 |
| commit | 8f06b2d82f0fa8d84dc92db3747ca44462e969b0 (patch) | |
| tree | 7213d9518c0888f1718b05afa4136a3aa03b2c66 | |
| parent | c4188bc96a6dacd4ba8d2e72ad2571cf0389eb5c (diff) | |
| download | gdb-8f06b2d82f0fa8d84dc92db3747ca44462e969b0.zip gdb-8f06b2d82f0fa8d84dc92db3747ca44462e969b0.tar.gz gdb-8f06b2d82f0fa8d84dc92db3747ca44462e969b0.tar.bz2 | |
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
| -rw-r--r-- | bfd/ChangeLog | 7 | ||||
| -rw-r--r-- | bfd/bfd-in2.h | 2 | ||||
| -rw-r--r-- | bfd/libbfd.h | 2 | ||||
| -rw-r--r-- | bfd/reloc.c | 4 | ||||
| -rw-r--r-- | gas/ChangeLog | 16 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 1582 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp-bad_t2.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp-bad_t2.l | 9 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp-bad_t2.s | 14 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp1_t2.d | 205 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp1_t2.s | 298 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp1xD_t2.d | 258 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp1xD_t2.s | 359 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp2_t2.d | 17 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/vfp2_t2.s | 21 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 1273 |
18 files changed, 2782 insertions, 1303 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 820d55c..43668d5 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,10 @@ +2005-09-02 Paul Brook <paul@codesourcery.com> + + * libbdf.h: Regenerate. + * bfd-in2.h: Regenerate. + * reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and + BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. + 2005-09-01 Dmitry Diky <diwil@spec.ru> * elf32-msp430.c (msp430_elf_relax_delete_bytes): Do not adjust diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 9359cd4..07ca098 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2881,6 +2881,8 @@ pc-relative or some form of GOT-indirect relocation. */ BFD_RELOC_ARM_MULTI, BFD_RELOC_ARM_CP_OFF_IMM, BFD_RELOC_ARM_CP_OFF_IMM_S2, + BFD_RELOC_ARM_T32_CP_OFF_IMM, + BFD_RELOC_ARM_T32_CP_OFF_IMM_S2, BFD_RELOC_ARM_ADR_IMM, BFD_RELOC_ARM_LDR_IMM, BFD_RELOC_ARM_LITERAL, diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 527b776..fc27a3e 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1219,6 +1219,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_ARM_MULTI", "BFD_RELOC_ARM_CP_OFF_IMM", "BFD_RELOC_ARM_CP_OFF_IMM_S2", + "BFD_RELOC_ARM_T32_CP_OFF_IMM", + "BFD_RELOC_ARM_T32_CP_OFF_IMM_S2", "BFD_RELOC_ARM_ADR_IMM", "BFD_RELOC_ARM_LDR_IMM", "BFD_RELOC_ARM_LITERAL", diff --git a/bfd/reloc.c b/bfd/reloc.c index f128033..3bd0d7c 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -2754,6 +2754,10 @@ ENUMX ENUMX BFD_RELOC_ARM_CP_OFF_IMM_S2 ENUMX + BFD_RELOC_ARM_T32_CP_OFF_IMM +ENUMX + BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 +ENUMX BFD_RELOC_ARM_ADR_IMM ENUMX BFD_RELOC_ARM_LDR_IMM diff --git a/gas/ChangeLog b/gas/ChangeLog index ec5219e..e50ef06 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,21 @@ 2005-09-02 Paul Brook <paul@codesourcery.com> + * config/tc-arm.c (encode_arm_cp_address): Use + BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode. + (do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb + mode. + (md_assemble): Only allow coprocessor instructions when Thumb-2 is + available. + (cCE, cC3): Define. + (insns): Use them for coprocessor instructions. + (md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM. + (get_thumb32_insn): New function. + (put_thumb32_insn): New function. + (md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and + BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. + +2005-09-02 Paul Brook <paul@codesourcery.com> + * config/tc-arm.c (opcode_lookup): Look for infix opcode when incorrect suffix matches. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index f52716d..16f1db7 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -4218,6 +4218,8 @@ encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) if (reloc_override) inst.reloc.type = reloc_override; + else if (thumb_mode) + inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; else inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; return SUCCESS; @@ -5495,9 +5497,14 @@ do_iwmmxt_wmov (void) static void do_iwmmxt_wldstbh (void) { + int reloc; inst.instruction |= inst.operands[0].reg << 12; inst.reloc.exp.X_add_number *= 4; - encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2); + if (thumb_mode) + reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; + else + reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; + encode_arm_cp_address (1, TRUE, FALSE, reloc); } static void @@ -7759,8 +7766,14 @@ md_assemble (char *str) if (thumb_mode) { + unsigned long variant; + + variant = cpu_variant; + /* Only allow coprocessor instructions on Thumb-2 capable devices. */ + if ((variant & ARM_EXT_V6T2) == 0) + variant &= ARM_ANY; /* Check that this instruction is supported for this CPU. */ - if (thumb_mode == 1 && (opcode->tvariant & cpu_variant) == 0) + if (thumb_mode == 1 && (opcode->tvariant & variant) == 0) { as_bad (_("selected processor does not support `%s'"), str); return; @@ -8247,6 +8260,13 @@ static const struct asm_cond conds[] = #define C3(mnem, op, nops, ops, ae) \ { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } +/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ +#define cCE(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } + +#define cC3(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } + #define xCM_(m1, m2, m3, op, nops, ops, ae) \ { #m1 #m2 #m3, OPS##nops ops, \ sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ @@ -8696,815 +8716,815 @@ static const struct asm_opcode insns[] = #undef ARM_VARIANT #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */ - CE(wfs, e200110, 1, (RR), rd), - CE(rfs, e300110, 1, (RR), rd), - CE(wfc, e400110, 1, (RR), rd), - CE(rfc, e500110, 1, (RR), rd), - - C3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr), - C3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr), - C3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr), - C3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr), - - C3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr), - C3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr), - C3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr), - C3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr), - - C3(mvfs, e008100, 2, (RF, RF_IF), rd_rm), - C3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), - C3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), - C3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), - C3(mvfd, e008180, 2, (RF, RF_IF), rd_rm), - C3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), - C3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), - C3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), - C3(mvfe, e088100, 2, (RF, RF_IF), rd_rm), - C3(mvfep, e088120, 2, (RF, RF_IF), rd_rm), - C3(mvfem, e088140, 2, (RF, RF_IF), rd_rm), - C3(mvfez, e088160, 2, (RF, RF_IF), rd_rm), - - C3(mnfs, e108100, 2, (RF, RF_IF), rd_rm), - C3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), - C3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), - C3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), - C3(mnfd, e108180, 2, (RF, RF_IF), rd_rm), - C3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), - C3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), - C3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), - C3(mnfe, e188100, 2, (RF, RF_IF), rd_rm), - C3(mnfep, e188120, 2, (RF, RF_IF), rd_rm), - C3(mnfem, e188140, 2, (RF, RF_IF), rd_rm), - C3(mnfez, e188160, 2, (RF, RF_IF), rd_rm), - - C3(abss, e208100, 2, (RF, RF_IF), rd_rm), - C3(abssp, e208120, 2, (RF, RF_IF), rd_rm), - C3(abssm, e208140, 2, (RF, RF_IF), rd_rm), - C3(abssz, e208160, 2, (RF, RF_IF), rd_rm), - C3(absd, e208180, 2, (RF, RF_IF), rd_rm), - C3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), - C3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), - C3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), - C3(abse, e288100, 2, (RF, RF_IF), rd_rm), - C3(absep, e288120, 2, (RF, RF_IF), rd_rm), - C3(absem, e288140, 2, (RF, RF_IF), rd_rm), - C3(absez, e288160, 2, (RF, RF_IF), rd_rm), - - C3(rnds, e308100, 2, (RF, RF_IF), rd_rm), - C3(rndsp, e308120, 2, (RF, RF_IF), rd_rm), - C3(rndsm, e308140, 2, (RF, RF_IF), rd_rm), - C3(rndsz, e308160, 2, (RF, RF_IF), rd_rm), - C3(rndd, e308180, 2, (RF, RF_IF), rd_rm), - C3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), - C3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), - C3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), - C3(rnde, e388100, 2, (RF, RF_IF), rd_rm), - C3(rndep, e388120, 2, (RF, RF_IF), rd_rm), - C3(rndem, e388140, 2, (RF, RF_IF), rd_rm), - C3(rndez, e388160, 2, (RF, RF_IF), rd_rm), - - C3(sqts, e408100, 2, (RF, RF_IF), rd_rm), - C3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), - C3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), - C3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), - C3(sqtd, e408180, 2, (RF, RF_IF), rd_rm), - C3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), - C3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), - C3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), - C3(sqte, e488100, 2, (RF, RF_IF), rd_rm), - C3(sqtep, e488120, 2, (RF, RF_IF), rd_rm), - C3(sqtem, e488140, 2, (RF, RF_IF), rd_rm), - C3(sqtez, e488160, 2, (RF, RF_IF), rd_rm), - - C3(logs, e508100, 2, (RF, RF_IF), rd_rm), - C3(logsp, e508120, 2, (RF, RF_IF), rd_rm), - C3(logsm, e508140, 2, (RF, RF_IF), rd_rm), - C3(logsz, e508160, 2, (RF, RF_IF), rd_rm), - C3(logd, e508180, 2, (RF, RF_IF), rd_rm), - C3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), - C3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), - C3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), - C3(loge, e588100, 2, (RF, RF_IF), rd_rm), - C3(logep, e588120, 2, (RF, RF_IF), rd_rm), - C3(logem, e588140, 2, (RF, RF_IF), rd_rm), - C3(logez, e588160, 2, (RF, RF_IF), rd_rm), - - C3(lgns, e608100, 2, (RF, RF_IF), rd_rm), - C3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), - C3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), - C3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), - C3(lgnd, e608180, 2, (RF, RF_IF), rd_rm), - C3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), - C3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), - C3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), - C3(lgne, e688100, 2, (RF, RF_IF), rd_rm), - C3(lgnep, e688120, 2, (RF, RF_IF), rd_rm), - C3(lgnem, e688140, 2, (RF, RF_IF), rd_rm), - C3(lgnez, e688160, 2, (RF, RF_IF), rd_rm), - - C3(exps, e708100, 2, (RF, RF_IF), rd_rm), - C3(expsp, e708120, 2, (RF, RF_IF), rd_rm), - C3(expsm, e708140, 2, (RF, RF_IF), rd_rm), - C3(expsz, e708160, 2, (RF, RF_IF), rd_rm), - C3(expd, e708180, 2, (RF, RF_IF), rd_rm), - C3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), - C3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), - C3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), - C3(expe, e788100, 2, (RF, RF_IF), rd_rm), - C3(expep, e788120, 2, (RF, RF_IF), rd_rm), - C3(expem, e788140, 2, (RF, RF_IF), rd_rm), - C3(expdz, e788160, 2, (RF, RF_IF), rd_rm), - - C3(sins, e808100, 2, (RF, RF_IF), rd_rm), - C3(sinsp, e808120, 2, (RF, RF_IF), rd_rm), - C3(sinsm, e808140, 2, (RF, RF_IF), rd_rm), - C3(sinsz, e808160, 2, (RF, RF_IF), rd_rm), - C3(sind, e808180, 2, (RF, RF_IF), rd_rm), - C3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), - C3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), - C3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), - C3(sine, e888100, 2, (RF, RF_IF), rd_rm), - C3(sinep, e888120, 2, (RF, RF_IF), rd_rm), - C3(sinem, e888140, 2, (RF, RF_IF), rd_rm), - C3(sinez, e888160, 2, (RF, RF_IF), rd_rm), - - C3(coss, e908100, 2, (RF, RF_IF), rd_rm), - C3(cossp, e908120, 2, (RF, RF_IF), rd_rm), - C3(cossm, e908140, 2, (RF, RF_IF), rd_rm), - C3(cossz, e908160, 2, (RF, RF_IF), rd_rm), - C3(cosd, e908180, 2, (RF, RF_IF), rd_rm), - C3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), - C3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), - C3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), - C3(cose, e988100, 2, (RF, RF_IF), rd_rm), - C3(cosep, e988120, 2, (RF, RF_IF), rd_rm), - C3(cosem, e988140, 2, (RF, RF_IF), rd_rm), - C3(cosez, e988160, 2, (RF, RF_IF), rd_rm), - - C3(tans, ea08100, 2, (RF, RF_IF), rd_rm), - C3(tansp, ea08120, 2, (RF, RF_IF), rd_rm), - C3(tansm, ea08140, 2, (RF, RF_IF), rd_rm), - C3(tansz, ea08160, 2, (RF, RF_IF), rd_rm), - C3(tand, ea08180, 2, (RF, RF_IF), rd_rm), - C3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), - C3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), - C3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), - C3(tane, ea88100, 2, (RF, RF_IF), rd_rm), - C3(tanep, ea88120, 2, (RF, RF_IF), rd_rm), - C3(tanem, ea88140, 2, (RF, RF_IF), rd_rm), - C3(tanez, ea88160, 2, (RF, RF_IF), rd_rm), - - C3(asns, eb08100, 2, (RF, RF_IF), rd_rm), - C3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), - C3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), - C3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), - C3(asnd, eb08180, 2, (RF, RF_IF), rd_rm), - C3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), - C3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), - C3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), - C3(asne, eb88100, 2, (RF, RF_IF), rd_rm), - C3(asnep, eb88120, 2, (RF, RF_IF), rd_rm), - C3(asnem, eb88140, 2, (RF, RF_IF), rd_rm), - C3(asnez, eb88160, 2, (RF, RF_IF), rd_rm), - - C3(acss, ec08100, 2, (RF, RF_IF), rd_rm), - C3(acssp, ec08120, 2, (RF, RF_IF), rd_rm), - C3(acssm, ec08140, 2, (RF, RF_IF), rd_rm), - C3(acssz, ec08160, 2, (RF, RF_IF), rd_rm), - C3(acsd, ec08180, 2, (RF, RF_IF), rd_rm), - C3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), - C3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), - C3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), - C3(acse, ec88100, 2, (RF, RF_IF), rd_rm), - C3(acsep, ec88120, 2, (RF, RF_IF), rd_rm), - C3(acsem, ec88140, 2, (RF, RF_IF), rd_rm), - C3(acsez, ec88160, 2, (RF, RF_IF), rd_rm), - - C3(atns, ed08100, 2, (RF, RF_IF), rd_rm), - C3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), - C3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), - C3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), - C3(atnd, ed08180, 2, (RF, RF_IF), rd_rm), - C3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), - C3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), - C3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), - C3(atne, ed88100, 2, (RF, RF_IF), rd_rm), - C3(atnep, ed88120, 2, (RF, RF_IF), rd_rm), - C3(atnem, ed88140, 2, (RF, RF_IF), rd_rm), - C3(atnez, ed88160, 2, (RF, RF_IF), rd_rm), - - C3(urds, ee08100, 2, (RF, RF_IF), rd_rm), - C3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), - C3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), - C3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), - C3(urdd, ee08180, 2, (RF, RF_IF), rd_rm), - C3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), - C3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), - C3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), - C3(urde, ee88100, 2, (RF, RF_IF), rd_rm), - C3(urdep, ee88120, 2, (RF, RF_IF), rd_rm), - C3(urdem, ee88140, 2, (RF, RF_IF), rd_rm), - C3(urdez, ee88160, 2, (RF, RF_IF), rd_rm), - - C3(nrms, ef08100, 2, (RF, RF_IF), rd_rm), - C3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), - C3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), - C3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), - C3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), - C3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), - C3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), - C3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), - C3(nrme, ef88100, 2, (RF, RF_IF), rd_rm), - C3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), - C3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), - C3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), - - C3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), - - C3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), - C3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), - - CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), + cCE(wfs, e200110, 1, (RR), rd), + cCE(rfs, e300110, 1, (RR), rd), + cCE(wfc, e400110, 1, (RR), rd), + cCE(rfc, e500110, 1, (RR), rd), + + cC3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr), + cC3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr), + cC3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr), + cC3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr), + + cC3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr), + cC3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr), + cC3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr), + cC3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr), + + cC3(mvfs, e008100, 2, (RF, RF_IF), rd_rm), + cC3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), + cC3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), + cC3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), + cC3(mvfd, e008180, 2, (RF, RF_IF), rd_rm), + cC3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), + cC3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), + cC3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), + cC3(mvfe, e088100, 2, (RF, RF_IF), rd_rm), + cC3(mvfep, e088120, 2, (RF, RF_IF), rd_rm), + cC3(mvfem, e088140, 2, (RF, RF_IF), rd_rm), + cC3(mvfez, e088160, 2, (RF, RF_IF), rd_rm), + + cC3(mnfs, e108100, 2, (RF, RF_IF), rd_rm), + cC3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), + cC3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), + cC3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), + cC3(mnfd, e108180, 2, (RF, RF_IF), rd_rm), + cC3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), + cC3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), + cC3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), + cC3(mnfe, e188100, 2, (RF, RF_IF), rd_rm), + cC3(mnfep, e188120, 2, (RF, RF_IF), rd_rm), + cC3(mnfem, e188140, 2, (RF, RF_IF), rd_rm), + cC3(mnfez, e188160, 2, (RF, RF_IF), rd_rm), + + cC3(abss, e208100, 2, (RF, RF_IF), rd_rm), + cC3(abssp, e208120, 2, (RF, RF_IF), rd_rm), + cC3(abssm, e208140, 2, (RF, RF_IF), rd_rm), + cC3(abssz, e208160, 2, (RF, RF_IF), rd_rm), + cC3(absd, e208180, 2, (RF, RF_IF), rd_rm), + cC3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), + cC3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), + cC3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), + cC3(abse, e288100, 2, (RF, RF_IF), rd_rm), + cC3(absep, e288120, 2, (RF, RF_IF), rd_rm), + cC3(absem, e288140, 2, (RF, RF_IF), rd_rm), + cC3(absez, e288160, 2, (RF, RF_IF), rd_rm), + + cC3(rnds, e308100, 2, (RF, RF_IF), rd_rm), + cC3(rndsp, e308120, 2, (RF, RF_IF), rd_rm), + cC3(rndsm, e308140, 2, (RF, RF_IF), rd_rm), + cC3(rndsz, e308160, 2, (RF, RF_IF), rd_rm), + cC3(rndd, e308180, 2, (RF, RF_IF), rd_rm), + cC3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), + cC3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), + cC3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), + cC3(rnde, e388100, 2, (RF, RF_IF), rd_rm), + cC3(rndep, e388120, 2, (RF, RF_IF), rd_rm), + cC3(rndem, e388140, 2, (RF, RF_IF), rd_rm), + cC3(rndez, e388160, 2, (RF, RF_IF), rd_rm), + + cC3(sqts, e408100, 2, (RF, RF_IF), rd_rm), + cC3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), + cC3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), + cC3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), + cC3(sqtd, e408180, 2, (RF, RF_IF), rd_rm), + cC3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), + cC3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), + cC3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), + cC3(sqte, e488100, 2, (RF, RF_IF), rd_rm), + cC3(sqtep, e488120, 2, (RF, RF_IF), rd_rm), + cC3(sqtem, e488140, 2, (RF, RF_IF), rd_rm), + cC3(sqtez, e488160, 2, (RF, RF_IF), rd_rm), + + cC3(logs, e508100, 2, (RF, RF_IF), rd_rm), + cC3(logsp, e508120, 2, (RF, RF_IF), rd_rm), + cC3(logsm, e508140, 2, (RF, RF_IF), rd_rm), + cC3(logsz, e508160, 2, (RF, RF_IF), rd_rm), + cC3(logd, e508180, 2, (RF, RF_IF), rd_rm), + cC3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), + cC3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), + cC3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), + cC3(loge, e588100, 2, (RF, RF_IF), rd_rm), + cC3(logep, e588120, 2, (RF, RF_IF), rd_rm), + cC3(logem, e588140, 2, (RF, RF_IF), rd_rm), + cC3(logez, e588160, 2, (RF, RF_IF), rd_rm), + + cC3(lgns, e608100, 2, (RF, RF_IF), rd_rm), + cC3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), + cC3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), + cC3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), + cC3(lgnd, e608180, 2, (RF, RF_IF), rd_rm), + cC3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), + cC3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), + cC3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), + cC3(lgne, e688100, 2, (RF, RF_IF), rd_rm), + cC3(lgnep, e688120, 2, (RF, RF_IF), rd_rm), + cC3(lgnem, e688140, 2, (RF, RF_IF), rd_rm), + cC3(lgnez, e688160, 2, (RF, RF_IF), rd_rm), + + cC3(exps, e708100, 2, (RF, RF_IF), rd_rm), + cC3(expsp, e708120, 2, (RF, RF_IF), rd_rm), + cC3(expsm, e708140, 2, (RF, RF_IF), rd_rm), + cC3(expsz, e708160, 2, (RF, RF_IF), rd_rm), + cC3(expd, e708180, 2, (RF, RF_IF), rd_rm), + cC3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), + cC3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), + cC3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), + cC3(expe, e788100, 2, (RF, RF_IF), rd_rm), + cC3(expep, e788120, 2, (RF, RF_IF), rd_rm), + cC3(expem, e788140, 2, (RF, RF_IF), rd_rm), + cC3(expdz, e788160, 2, (RF, RF_IF), rd_rm), + + cC3(sins, e808100, 2, (RF, RF_IF), rd_rm), + cC3(sinsp, e808120, 2, (RF, RF_IF), rd_rm), + cC3(sinsm, e808140, 2, (RF, RF_IF), rd_rm), + cC3(sinsz, e808160, 2, (RF, RF_IF), rd_rm), + cC3(sind, e808180, 2, (RF, RF_IF), rd_rm), + cC3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), + cC3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), + cC3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), + cC3(sine, e888100, 2, (RF, RF_IF), rd_rm), + cC3(sinep, e888120, 2, (RF, RF_IF), rd_rm), + cC3(sinem, e888140, 2, (RF, RF_IF), rd_rm), + cC3(sinez, e888160, 2, (RF, RF_IF), rd_rm), + + cC3(coss, e908100, 2, (RF, RF_IF), rd_rm), + cC3(cossp, e908120, 2, (RF, RF_IF), rd_rm), + cC3(cossm, e908140, 2, (RF, RF_IF), rd_rm), + cC3(cossz, e908160, 2, (RF, RF_IF), rd_rm), + cC3(cosd, e908180, 2, (RF, RF_IF), rd_rm), + cC3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), + cC3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), + cC3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), + cC3(cose, e988100, 2, (RF, RF_IF), rd_rm), + cC3(cosep, e988120, 2, (RF, RF_IF), rd_rm), + cC3(cosem, e988140, 2, (RF, RF_IF), rd_rm), + cC3(cosez, e988160, 2, (RF, RF_IF), rd_rm), + + cC3(tans, ea08100, 2, (RF, RF_IF), rd_rm), + cC3(tansp, ea08120, 2, (RF, RF_IF), rd_rm), + cC3(tansm, ea08140, 2, (RF, RF_IF), rd_rm), + cC3(tansz, ea08160, 2, (RF, RF_IF), rd_rm), + cC3(tand, ea08180, 2, (RF, RF_IF), rd_rm), + cC3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), + cC3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), + cC3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), + cC3(tane, ea88100, 2, (RF, RF_IF), rd_rm), + cC3(tanep, ea88120, 2, (RF, RF_IF), rd_rm), + cC3(tanem, ea88140, 2, (RF, RF_IF), rd_rm), + cC3(tanez, ea88160, 2, (RF, RF_IF), rd_rm), + + cC3(asns, eb08100, 2, (RF, RF_IF), rd_rm), + cC3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), + cC3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), + cC3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), + cC3(asnd, eb08180, 2, (RF, RF_IF), rd_rm), + cC3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), + cC3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), + cC3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), + cC3(asne, eb88100, 2, (RF, RF_IF), rd_rm), + cC3(asnep, eb88120, 2, (RF, RF_IF), rd_rm), + cC3(asnem, eb88140, 2, (RF, RF_IF), rd_rm), + cC3(asnez, eb88160, 2, (RF, RF_IF), rd_rm), + + cC3(acss, ec08100, 2, (RF, RF_IF), rd_rm), + cC3(acssp, ec08120, 2, (RF, RF_IF), rd_rm), + cC3(acssm, ec08140, 2, (RF, RF_IF), rd_rm), + cC3(acssz, ec08160, 2, (RF, RF_IF), rd_rm), + cC3(acsd, ec08180, 2, (RF, RF_IF), rd_rm), + cC3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), + cC3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), + cC3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), + cC3(acse, ec88100, 2, (RF, RF_IF), rd_rm), + cC3(acsep, ec88120, 2, (RF, RF_IF), rd_rm), + cC3(acsem, ec88140, 2, (RF, RF_IF), rd_rm), + cC3(acsez, ec88160, 2, (RF, RF_IF), rd_rm), + + cC3(atns, ed08100, 2, (RF, RF_IF), rd_rm), + cC3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), + cC3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), + cC3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), + cC3(atnd, ed08180, 2, (RF, RF_IF), rd_rm), + cC3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), + cC3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), + cC3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), + cC3(atne, ed88100, 2, (RF, RF_IF), rd_rm), + cC3(atnep, ed88120, 2, (RF, RF_IF), rd_rm), + cC3(atnem, ed88140, 2, (RF, RF_IF), rd_rm), + cC3(atnez, ed88160, 2, (RF, RF_IF), rd_rm), + + cC3(urds, ee08100, 2, (RF, RF_IF), rd_rm), + cC3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), + cC3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), + cC3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), + cC3(urdd, ee08180, 2, (RF, RF_IF), rd_rm), + cC3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), + cC3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), + cC3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), + cC3(urde, ee88100, 2, (RF, RF_IF), rd_rm), + cC3(urdep, ee88120, 2, (RF, RF_IF), rd_rm), + cC3(urdem, ee88140, 2, (RF, RF_IF), rd_rm), + cC3(urdez, ee88160, 2, (RF, RF_IF), rd_rm), + + cC3(nrms, ef08100, 2, (RF, RF_IF), rd_rm), + cC3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), + cC3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), + cC3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), + cC3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), + cC3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), + cC3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), + cC3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), + cC3(nrme, ef88100, 2, (RF, RF_IF), rd_rm), + cC3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), + cC3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), + cC3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), + + cC3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cC3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), + cC3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), - CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), + cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), - C3(flts, e000110, 2, (RF, RR), rn_rd), - C3(fltsp, e000130, 2, (RF, RR), rn_rd), - C3(fltsm, e000150, 2, (RF, RR), rn_rd), - C3(fltsz, e000170, 2, (RF, RR), rn_rd), - C3(fltd, e000190, 2, (RF, RR), rn_rd), - C3(fltdp, e0001b0, 2, (RF, RR), rn_rd), - C3(fltdm, e0001d0, 2, (RF, RR), rn_rd), - C3(fltdz, e0001f0, 2, (RF, RR), rn_rd), - C3(flte, e080110, 2, (RF, RR), rn_rd), - C3(fltep, e080130, 2, (RF, RR), rn_rd), - C3(fltem, e080150, 2, (RF, RR), rn_rd), - C3(fltez, e080170, 2, (RF, RR), rn_rd), + cC3(flts, e000110, 2, (RF, RR), rn_rd), + cC3(fltsp, e000130, 2, (RF, RR), rn_rd), + cC3(fltsm, e000150, 2, (RF, RR), rn_rd), + cC3(fltsz, e000170, 2, (RF, RR), rn_rd), + cC3(fltd, e000190, 2, (RF, RR), rn_rd), + cC3(fltdp, e0001b0, 2, (RF, RR), rn_rd), + cC3(fltdm, e0001d0, 2, (RF, RR), rn_rd), + cC3(fltdz, e0001f0, 2, (RF, RR), rn_rd), + cC3(flte, e080110, 2, (RF, RR), rn_rd), + cC3(fltep, e080130, 2, (RF, RR), rn_rd), + cC3(fltem, e080150, 2, (RF, RR), rn_rd), + cC3(fltez, e080170, 2, (RF, RR), rn_rd), /* The implementation of the FIX instruction is broken on some assemblers, in that it accepts a precision specifier as well as a rounding specifier, despite the fact that this is meaningless. To be more compatible, we accept it as well, though of course it does not set any bits. */ - CE(fix, e100110, 2, (RR, RF), rd_rm), - C3(fixp, e100130, 2, (RR, RF), rd_rm), - C3(fixm, e100150, 2, (RR, RF), rd_rm), - C3(fixz, e100170, 2, (RR, RF), rd_rm), - C3(fixsp, e100130, 2, (RR, RF), rd_rm), - C3(fixsm, e100150, 2, (RR, RF), rd_rm), - C3(fixsz, e100170, 2, (RR, RF), rd_rm), - C3(fixdp, e100130, 2, (RR, RF), rd_rm), - C3(fixdm, e100150, 2, (RR, RF), rd_rm), - C3(fixdz, e100170, 2, (RR, RF), rd_rm), - C3(fixep, e100130, 2, (RR, RF), rd_rm), - C3(fixem, e100150, 2, (RR, RF), rd_rm), - C3(fixez, e100170, 2, (RR, RF), rd_rm), + cCE(fix, e100110, 2, (RR, RF), rd_rm), + cC3(fixp, e100130, 2, (RR, RF), rd_rm), + cC3(fixm, e100150, 2, (RR, RF), rd_rm), + cC3(fixz, e100170, 2, (RR, RF), rd_rm), + cC3(fixsp, e100130, 2, (RR, RF), rd_rm), + cC3(fixsm, e100150, 2, (RR, RF), rd_rm), + cC3(fixsz, e100170, 2, (RR, RF), rd_rm), + cC3(fixdp, e100130, 2, (RR, RF), rd_rm), + cC3(fixdm, e100150, 2, (RR, RF), rd_rm), + cC3(fixdz, e100170, 2, (RR, RF), rd_rm), + cC3(fixep, e100130, 2, (RR, RF), rd_rm), + cC3(fixem, e100150, 2, (RR, RF), rd_rm), + cC3(fixez, e100170, 2, (RR, RF), rd_rm), /* Instructions that were new with the real FPA, call them V2. */ #undef ARM_VARIANT #define ARM_VARIANT FPU_FPA_EXT_V2 - CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), - C3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), - C3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), - CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), - C3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), - C3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cC3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cC3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cC3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cC3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), #undef ARM_VARIANT #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */ /* Moves and type conversions. */ - CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), - CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), - CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), - CE(fmstat, ef1fa10, 0, (), noargs), - CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), - CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), - CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), - CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), - CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), - CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), - CE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), - CE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), + cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), + cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), + cCE(fmstat, ef1fa10, 0, (), noargs), + cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), + cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), /* Memory operations. */ - CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst), - CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst), - CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), - CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), - CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), - CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), - CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), - CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), - CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), - CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), - CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), - CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), - CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), - CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), - CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), - CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), - CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), - CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), + cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst), + cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst), + cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), + cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), + cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), + cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), + cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), + cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), + cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), + cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), + cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), + cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), + cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), + cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), + cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), + cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), + cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), + cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), /* Monadic operations. */ - CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), - CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), - CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), /* Dyadic operations. */ - CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), - CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), - CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), - CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), - CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), - CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), - CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), - CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), - CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), /* Comparisons. */ - CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), - CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), - CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), - CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), + cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), + cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), #undef ARM_VARIANT #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */ /* Moves and type conversions. */ - CE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm), - CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), - CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), - CE(fmdhr, e200b10, 2, (RVD, RR), rn_rd), - CE(fmdlr, e000b10, 2, (RVD, RR), rn_rd), - CE(fmrdh, e300b10, 2, (RR, RVD), rd_rn), - CE(fmrdl, e100b10, 2, (RR, RVD), rd_rn), - CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), - CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), - CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), - CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), - CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), - CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm), + cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), + cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd), + cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd), + cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn), + cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn), + cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), + cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), + cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), /* Memory operations. */ - CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst), - CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst), - CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), - CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), - CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), - CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), - CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), - CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), - CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), - CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), + cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst), + cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst), + cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), + cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), + cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), + cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), + cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), + cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), + cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), + cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), /* Monadic operations. */ - CE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm), - CE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm), - CE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm), + cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm), + cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm), + cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm), /* Dyadic operations. */ - CE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm), - CE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm), - CE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm), - CE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm), - CE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm), - CE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm), - CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm), - CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm), - CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm), + cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm), /* Comparisons. */ - CE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm), - CE(fcmpzd, eb50b40, 1, (RVD), rd), - CE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm), - CE(fcmpezd, eb50bc0, 1, (RVD), rd), + cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm), + cCE(fcmpzd, eb50b40, 1, (RVD), rd), + cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm), + cCE(fcmpezd, eb50bc0, 1, (RVD), rd), #undef ARM_VARIANT #define ARM_VARIANT FPU_VFP_EXT_V2 - CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), - CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), - CE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn), - CE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm), + cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), + cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), + cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn), + cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm), #undef ARM_VARIANT #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */ - CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), - CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), - CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), - CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), - CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), - CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), - CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), - CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), + cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), + cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), #undef ARM_VARIANT #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */ - CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), - CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), - CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), - CE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), - CE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), - CE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), - CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), - CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), - CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), - CE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), - CE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), - CE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), - CE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), - CE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), - CE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), - CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), - CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), - CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), - CE(tmcr, e000110, 2, (RIWC, RR), rn_rd), - CE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), - CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), - CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), - CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), - CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), - CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), - CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), - CE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), - CE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), - CE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), - CE(tmrc, e100110, 2, (RR, RIWC), rd_rn), - CE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), - CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), - CE(torch, e53f150, 1, (RR), iwmmxt_tandorc), - CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), - CE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), - CE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), - CE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), - CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), - CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), - CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), - CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), - CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), - CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), - CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), - CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), - CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), - CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), - CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), - CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), - CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), - CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), - CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), + cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), + cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), + cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), + cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), + cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), + cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), + cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), + cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), + cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), + cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), + cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), + cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), + cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd), + cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), + cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), + cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), + cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), + cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn), + cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), + cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), + cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), + cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), + cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), + cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), + cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), + cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), + cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), + cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), + cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), + cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), + cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), + cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), + cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), + cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), + cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), + cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), + cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), #undef ARM_VARIANT #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */ - CE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr), - CE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr), - CE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr), - CE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr), - CE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr), - CE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr), - CE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr), - CE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr), - CE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), - CE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), - CE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), - CE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), - CE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), - CE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), - CE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), - CE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), - CE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), - CE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), - CE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), - CE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), - CE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), - CE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), - CE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), - CE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), - CE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), - CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), - CE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), - CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), - CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), - CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), - CE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), - CE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), - CE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), - CE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), - CE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), - CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), - CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), - CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), - CE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), - CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), - CE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), - CE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), - CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), - CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), - CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), - CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), - CE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), - CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), - CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), - CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), - CE(cfabss, e300400, 2, (RMF, RMF), rd_rn), - CE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), - CE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), - CE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), - CE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), - CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), - CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), - CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), - CE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), - CE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), - CE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), - CE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), - CE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), - CE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), - CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), - CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), - CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), - CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), - CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), - CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), - CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), - CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), - CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), - CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), - CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), - CE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), + cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr), + cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr), + cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr), + cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr), + cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr), + cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr), + cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr), + cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr), + cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), + cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), + cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), + cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), + cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), + cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), + cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), + cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), + cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), + cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), + cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), + cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), + cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), + cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), + cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), + cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), + cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), + cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), + cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), + cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), + cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), + cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), + cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), + cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), + cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), + cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), + cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), + cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), + cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), + cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), + cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), + cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), + cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), + cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), + cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), + cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), + cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), + cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), + cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), + cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), + cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), + cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), + cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), + cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), + cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), + cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), + cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), + cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), + cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), + cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), + cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), + cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), + cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), + cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), + cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), + cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), + cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), + cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), + cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), + cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), + cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), + cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), + cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), }; #undef ARM_VARIANT #undef THUMB_VARIANT @@ -9513,6 +9533,8 @@ static const struct asm_opcode insns[] = #undef TUE #undef TUF #undef TCC +#undef cCE +#undef cC3 #undef CE #undef CM #undef UE @@ -10149,6 +10171,7 @@ md_pcrel_from_section (fixS * fixP, segT seg) case BFD_RELOC_ARM_THUMB_OFFSET: case BFD_RELOC_ARM_T32_OFFSET_IMM: case BFD_RELOC_ARM_T32_ADD_PC12: + case BFD_RELOC_ARM_T32_CP_OFF_IMM: return (base + 4) & ~3; /* Thumb branches are simply offset by +4. */ @@ -10351,6 +10374,25 @@ negate_data_op (unsigned long * instruction, return value; } +/* Read a 32-bit thumb instruction from buf. */ +static unsigned long +get_thumb32_insn (char * buf) +{ + unsigned long insn; + insn = md_chars_to_number (buf, THUMB_SIZE) << 16; + insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + + return insn; +} + +/* Write a 32-bit thumb instruction to buf. */ +static void +put_thumb32_insn (char * buf, unsigned long insn) +{ + md_number_to_chars (buf, insn >> 16, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); +} + void md_apply_fix (fixS * fixP, valueT * valP, @@ -10982,6 +11024,7 @@ md_apply_fix (fixS * fixP, #endif case BFD_RELOC_ARM_CP_OFF_IMM: + case BFD_RELOC_ARM_T32_CP_OFF_IMM: if (value < -1023 || value > 1023 || (value & 3)) as_bad_where (fixP->fx_file, fixP->fx_line, _("co-processor offset out of range")); @@ -10989,14 +11032,24 @@ md_apply_fix (fixS * fixP, sign = value >= 0; if (value < 0) value = -value; - newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00; + if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM + || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) + newval = md_chars_to_number (buf, INSN_SIZE); + else + newval = get_thumb32_insn (buf); + newval &= 0xff7fff00; newval |= (value >> 2) | (sign ? INDEX_UP : 0); if (value == 0) newval &= ~WRITE_BACK; - md_number_to_chars (buf, newval, INSN_SIZE); + if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM + || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) + md_number_to_chars (buf, newval, INSN_SIZE); + else + put_thumb32_insn (buf, newval); break; case BFD_RELOC_ARM_CP_OFF_IMM_S2: + case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: if (value < -255 || value > 255) as_bad_where (fixP->fx_file, fixP->fx_line, _("co-processor offset out of range")); @@ -11314,6 +11367,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, case BFD_RELOC_ARM_SWI: type = "SWI"; break; case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; + case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index ef33b84..31b2796 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2005-09-02 Paul Brook <paul@codesourcery.com> + * gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s, + gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d, + gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files. + +2005-09-02 Paul Brook <paul@codesourcery.com> + * gas/arm/fpa-mem.d: Test "stfpls". * gas/arm/fpa-mem.s: Ditto. diff --git a/gas/testsuite/gas/arm/vfp-bad_t2.d b/gas/testsuite/gas/arm/vfp-bad_t2.d new file mode 100644 index 0000000..1ef83ba --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-bad_t2.d @@ -0,0 +1,3 @@ +#name: Thumb-2 VFP errors +#as: -mfpu=vfp +#error-output: vfp-bad_t2.l diff --git a/gas/testsuite/gas/arm/vfp-bad_t2.l b/gas/testsuite/gas/arm/vfp-bad_t2.l new file mode 100644 index 0000000..ecc0640 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-bad_t2.l @@ -0,0 +1,9 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8' +[^:]*:8: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!' +[^:]*:9: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8' +[^:]*:10: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!' +[^:]*:11: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8' +[^:]*:12: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!' +[^:]*:13: Error: instruction does not support writeback -- `flds s0,\[r0\],#8' +[^:]*:14: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!' diff --git a/gas/testsuite/gas/arm/vfp-bad_t2.s b/gas/testsuite/gas/arm/vfp-bad_t2.s new file mode 100644 index 0000000..3b904b3 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-bad_t2.s @@ -0,0 +1,14 @@ + .global entry +@ Same as vfp-bad.s, but for Thumb-2 + .syntax unified + .thumb + .text +entry: + fstd d0, [r0], #8 + fstd d0, [r0, #-8]! + fsts s0, [r0], #8 + fsts s0, [r0, #-8]! + fldd d0, [r0], #8 + fldd d0, [r0, #-8]! + flds s0, [r0], #8 + flds s0, [r0, #-8]! diff --git a/gas/testsuite/gas/arm/vfp1_t2.d b/gas/testsuite/gas/arm/vfp1_t2.d new file mode 100644 index 0000000..22c4fd6 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp1_t2.d @@ -0,0 +1,205 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Thumb-2 VFP Double-precision instructions +#as: -mfpu=vfp + +# Test the ARM VFP Double Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> eeb4 0bc0 fcmped d0, d0 +0+004 <[^>]*> eeb5 0bc0 fcmpezd d0 +0+008 <[^>]*> eeb4 0b40 fcmpd d0, d0 +0+00c <[^>]*> eeb5 0b40 fcmpzd d0 +0+010 <[^>]*> eeb0 0bc0 fabsd d0, d0 +0+014 <[^>]*> eeb0 0b40 fcpyd d0, d0 +0+018 <[^>]*> eeb1 0b40 fnegd d0, d0 +0+01c <[^>]*> eeb1 0bc0 fsqrtd d0, d0 +0+020 <[^>]*> ee30 0b00 faddd d0, d0, d0 +0+024 <[^>]*> ee80 0b00 fdivd d0, d0, d0 +0+028 <[^>]*> ee00 0b00 fmacd d0, d0, d0 +0+02c <[^>]*> ee10 0b00 fmscd d0, d0, d0 +0+030 <[^>]*> ee20 0b00 fmuld d0, d0, d0 +0+034 <[^>]*> ee00 0b40 fnmacd d0, d0, d0 +0+038 <[^>]*> ee10 0b40 fnmscd d0, d0, d0 +0+03c <[^>]*> ee20 0b40 fnmuld d0, d0, d0 +0+040 <[^>]*> ee30 0b40 fsubd d0, d0, d0 +0+044 <[^>]*> ed90 0b00 fldd d0, \[r0\] +0+048 <[^>]*> ed80 0b00 fstd d0, \[r0\] +0+04c <[^>]*> ec90 0b02 fldmiad r0, {d0} +0+050 <[^>]*> ec90 0b02 fldmiad r0, {d0} +0+054 <[^>]*> ecb0 0b02 fldmiad r0!, {d0} +0+058 <[^>]*> ecb0 0b02 fldmiad r0!, {d0} +0+05c <[^>]*> ed30 0b02 fldmdbd r0!, {d0} +0+060 <[^>]*> ed30 0b02 fldmdbd r0!, {d0} +0+064 <[^>]*> ec80 0b02 fstmiad r0, {d0} +0+068 <[^>]*> ec80 0b02 fstmiad r0, {d0} +0+06c <[^>]*> eca0 0b02 fstmiad r0!, {d0} +0+070 <[^>]*> eca0 0b02 fstmiad r0!, {d0} +0+074 <[^>]*> ed20 0b02 fstmdbd r0!, {d0} +0+078 <[^>]*> ed20 0b02 fstmdbd r0!, {d0} +0+07c <[^>]*> eeb8 0bc0 fsitod d0, s0 +0+080 <[^>]*> eeb8 0b40 fuitod d0, s0 +0+084 <[^>]*> eebd 0b40 ftosid s0, d0 +0+088 <[^>]*> eebd 0bc0 ftosizd s0, d0 +0+08c <[^>]*> eebc 0b40 ftouid s0, d0 +0+090 <[^>]*> eebc 0bc0 ftouizd s0, d0 +0+094 <[^>]*> eeb7 0ac0 fcvtds d0, s0 +0+098 <[^>]*> eeb7 0bc0 fcvtsd s0, d0 +0+09c <[^>]*> ee30 0b10 fmrdh r0, d0 +0+0a0 <[^>]*> ee10 0b10 fmrdl r0, d0 +0+0a4 <[^>]*> ee20 0b10 fmdhr d0, r0 +0+0a8 <[^>]*> ee00 0b10 fmdlr d0, r0 +0+0ac <[^>]*> eeb5 1b40 fcmpzd d1 +0+0b0 <[^>]*> eeb5 2b40 fcmpzd d2 +0+0b4 <[^>]*> eeb5 fb40 fcmpzd d15 +0+0b8 <[^>]*> eeb4 0b41 fcmpd d0, d1 +0+0bc <[^>]*> eeb4 0b42 fcmpd d0, d2 +0+0c0 <[^>]*> eeb4 0b4f fcmpd d0, d15 +0+0c4 <[^>]*> eeb4 1b40 fcmpd d1, d0 +0+0c8 <[^>]*> eeb4 2b40 fcmpd d2, d0 +0+0cc <[^>]*> eeb4 fb40 fcmpd d15, d0 +0+0d0 <[^>]*> eeb4 5b4c fcmpd d5, d12 +0+0d4 <[^>]*> eeb1 0b41 fnegd d0, d1 +0+0d8 <[^>]*> eeb1 0b42 fnegd d0, d2 +0+0dc <[^>]*> eeb1 0b4f fnegd d0, d15 +0+0e0 <[^>]*> eeb1 1b40 fnegd d1, d0 +0+0e4 <[^>]*> eeb1 2b40 fnegd d2, d0 +0+0e8 <[^>]*> eeb1 fb40 fnegd d15, d0 +0+0ec <[^>]*> eeb1 cb45 fnegd d12, d5 +0+0f0 <[^>]*> ee30 0b01 faddd d0, d0, d1 +0+0f4 <[^>]*> ee30 0b02 faddd d0, d0, d2 +0+0f8 <[^>]*> ee30 0b0f faddd d0, d0, d15 +0+0fc <[^>]*> ee31 0b00 faddd d0, d1, d0 +0+100 <[^>]*> ee32 0b00 faddd d0, d2, d0 +0+104 <[^>]*> ee3f 0b00 faddd d0, d15, d0 +0+108 <[^>]*> ee30 1b00 faddd d1, d0, d0 +0+10c <[^>]*> ee30 2b00 faddd d2, d0, d0 +0+110 <[^>]*> ee30 fb00 faddd d15, d0, d0 +0+114 <[^>]*> ee39 cb05 faddd d12, d9, d5 +0+118 <[^>]*> eeb7 0ae0 fcvtds d0, s1 +0+11c <[^>]*> eeb7 0ac1 fcvtds d0, s2 +0+120 <[^>]*> eeb7 0aef fcvtds d0, s31 +0+124 <[^>]*> eeb7 1ac0 fcvtds d1, s0 +0+128 <[^>]*> eeb7 2ac0 fcvtds d2, s0 +0+12c <[^>]*> eeb7 fac0 fcvtds d15, s0 +0+130 <[^>]*> eef7 0bc0 fcvtsd s1, d0 +0+134 <[^>]*> eeb7 1bc0 fcvtsd s2, d0 +0+138 <[^>]*> eef7 fbc0 fcvtsd s31, d0 +0+13c <[^>]*> eeb7 0bc1 fcvtsd s0, d1 +0+140 <[^>]*> eeb7 0bc2 fcvtsd s0, d2 +0+144 <[^>]*> eeb7 0bcf fcvtsd s0, d15 +0+148 <[^>]*> ee30 1b10 fmrdh r1, d0 +0+14c <[^>]*> ee30 eb10 fmrdh lr, d0 +0+150 <[^>]*> ee31 0b10 fmrdh r0, d1 +0+154 <[^>]*> ee32 0b10 fmrdh r0, d2 +0+158 <[^>]*> ee3f 0b10 fmrdh r0, d15 +0+15c <[^>]*> ee10 1b10 fmrdl r1, d0 +0+160 <[^>]*> ee10 eb10 fmrdl lr, d0 +0+164 <[^>]*> ee11 0b10 fmrdl r0, d1 +0+168 <[^>]*> ee12 0b10 fmrdl r0, d2 +0+16c <[^>]*> ee1f 0b10 fmrdl r0, d15 +0+170 <[^>]*> ee20 1b10 fmdhr d0, r1 +0+174 <[^>]*> ee20 eb10 fmdhr d0, lr +0+178 <[^>]*> ee21 0b10 fmdhr d1, r0 +0+17c <[^>]*> ee22 0b10 fmdhr d2, r0 +0+180 <[^>]*> ee2f 0b10 fmdhr d15, r0 +0+184 <[^>]*> ee00 1b10 fmdlr d0, r1 +0+188 <[^>]*> ee00 eb10 fmdlr d0, lr +0+18c <[^>]*> ee01 0b10 fmdlr d1, r0 +0+190 <[^>]*> ee02 0b10 fmdlr d2, r0 +0+194 <[^>]*> ee0f 0b10 fmdlr d15, r0 +0+198 <[^>]*> ed91 0b00 fldd d0, \[r1\] +0+19c <[^>]*> ed9e 0b00 fldd d0, \[lr\] +0+1a0 <[^>]*> ed90 0b00 fldd d0, \[r0\] +0+1a4 <[^>]*> ed90 0bff fldd d0, \[r0, #1020\] +0+1a8 <[^>]*> ed10 0bff fldd d0, \[r0, #-1020\] +0+1ac <[^>]*> ed90 1b00 fldd d1, \[r0\] +0+1b0 <[^>]*> ed90 2b00 fldd d2, \[r0\] +0+1b4 <[^>]*> ed90 fb00 fldd d15, \[r0\] +0+1b8 <[^>]*> ed8c cbc9 fstd d12, \[ip, #804\] +0+1bc <[^>]*> ec90 1b02 fldmiad r0, {d1} +0+1c0 <[^>]*> ec90 2b02 fldmiad r0, {d2} +0+1c4 <[^>]*> ec90 fb02 fldmiad r0, {d15} +0+1c8 <[^>]*> ec90 0b04 fldmiad r0, {d0-d1} +0+1cc <[^>]*> ec90 0b06 fldmiad r0, {d0-d2} +0+1d0 <[^>]*> ec90 0b20 fldmiad r0, {d0-d15} +0+1d4 <[^>]*> ec90 1b1e fldmiad r0, {d1-d15} +0+1d8 <[^>]*> ec90 2b1c fldmiad r0, {d2-d15} +0+1dc <[^>]*> ec90 eb04 fldmiad r0, {d14-d15} +0+1e0 <[^>]*> ec91 0b02 fldmiad r1, {d0} +0+1e4 <[^>]*> ec9e 0b02 fldmiad lr, {d0} +0+1e8 <[^>]*> eeb5 0b40 fcmpzd d0 +0+1ec <[^>]*> eeb5 1b40 fcmpzd d1 +0+1f0 <[^>]*> eeb5 2b40 fcmpzd d2 +0+1f4 <[^>]*> eeb5 3b40 fcmpzd d3 +0+1f8 <[^>]*> eeb5 4b40 fcmpzd d4 +0+1fc <[^>]*> eeb5 5b40 fcmpzd d5 +0+200 <[^>]*> eeb5 6b40 fcmpzd d6 +0+204 <[^>]*> eeb5 7b40 fcmpzd d7 +0+208 <[^>]*> eeb5 8b40 fcmpzd d8 +0+20c <[^>]*> eeb5 9b40 fcmpzd d9 +0+210 <[^>]*> eeb5 ab40 fcmpzd d10 +0+214 <[^>]*> eeb5 bb40 fcmpzd d11 +0+218 <[^>]*> eeb5 cb40 fcmpzd d12 +0+21c <[^>]*> eeb5 db40 fcmpzd d13 +0+220 <[^>]*> eeb5 eb40 fcmpzd d14 +0+224 <[^>]*> eeb5 fb40 fcmpzd d15 +# The "(eq|)" should be replaces by "eq" once the disassembler is fixed. +0+228 <[^>]*> bf01 itttt eq +0+22a <[^>]*> eeb4 1bcf fcmped(eq|) d1, d15 +0+22e <[^>]*> eeb5 2bc0 fcmpezd(eq|) d2 +0+232 <[^>]*> eeb4 3b4e fcmpd(eq|) d3, d14 +0+236 <[^>]*> eeb5 4b40 fcmpzd(eq|) d4 +0+23a <[^>]*> bf01 itttt eq +0+23c <[^>]*> eeb0 5bcd fabsd(eq|) d5, d13 +0+240 <[^>]*> eeb0 6b4c fcpyd(eq|) d6, d12 +0+244 <[^>]*> eeb1 7b4b fnegd(eq|) d7, d11 +0+248 <[^>]*> eeb1 8bca fsqrtd(eq|) d8, d10 +0+24c <[^>]*> bf01 itttt eq +0+24e <[^>]*> ee31 9b0f faddd(eq|) d9, d1, d15 +0+252 <[^>]*> ee83 2b0e fdivd(eq|) d2, d3, d14 +0+256 <[^>]*> ee0d 4b0c fmacd(eq|) d4, d13, d12 +0+25a <[^>]*> ee16 5b0b fmscd(eq|) d5, d6, d11 +0+25e <[^>]*> bf01 itttt eq +0+260 <[^>]*> ee2a 7b09 fmuld(eq|) d7, d10, d9 +0+264 <[^>]*> ee09 8b4a fnmacd(eq|) d8, d9, d10 +0+268 <[^>]*> ee16 7b4b fnmscd(eq|) d7, d6, d11 +0+26c <[^>]*> ee24 5b4c fnmuld(eq|) d5, d4, d12 +0+270 <[^>]*> bf02 ittt eq +0+272 <[^>]*> ee3d 3b4e fsubd(eq|) d3, d13, d14 +0+276 <[^>]*> ed95 2b00 fldd(eq|) d2, \[r5\] +0+27a <[^>]*> ed8c 1b00 fstd(eq|) d1, \[ip\] +0+27e <[^>]*> bf01 itttt eq +0+280 <[^>]*> ec91 1b02 fldmiad(eq|) r1, {d1} +0+284 <[^>]*> ec92 2b02 fldmiad(eq|) r2, {d2} +0+288 <[^>]*> ecb3 3b02 fldmiad(eq|) r3!, {d3} +0+28c <[^>]*> ecb4 4b02 fldmiad(eq|) r4!, {d4} +0+290 <[^>]*> bf01 itttt eq +0+292 <[^>]*> ed35 5b02 fldmdbd(eq|) r5!, {d5} +0+296 <[^>]*> ed36 6b02 fldmdbd(eq|) r6!, {d6} +0+29a <[^>]*> ec87 fb02 fstmiad(eq|) r7, {d15} +0+29e <[^>]*> ec88 eb02 fstmiad(eq|) r8, {d14} +0+2a2 <[^>]*> bf01 itttt eq +0+2a4 <[^>]*> eca9 db02 fstmiad(eq|) r9!, {d13} +0+2a8 <[^>]*> ecaa cb02 fstmiad(eq|) sl!, {d12} +0+2ac <[^>]*> ed2b bb02 fstmdbd(eq|) fp!, {d11} +0+2b0 <[^>]*> ed2c ab02 fstmdbd(eq|) ip!, {d10} +0+2b4 <[^>]*> bf01 itttt eq +0+2b6 <[^>]*> eeb8 fbe0 fsitod(eq|) d15, s1 +0+2ba <[^>]*> eeb8 1b6f fuitod(eq|) d1, s31 +0+2be <[^>]*> eefd 0b4f ftosid(eq|) s1, d15 +0+2c2 <[^>]*> eefd fbc2 ftosizd(eq|) s31, d2 +0+2c6 <[^>]*> bf01 itttt eq +0+2c8 <[^>]*> eefc 7b42 ftouid(eq|) s15, d2 +0+2cc <[^>]*> eefc 5bc3 ftouizd(eq|) s11, d3 +0+2d0 <[^>]*> eeb7 1ac5 fcvtds(eq|) d1, s10 +0+2d4 <[^>]*> eef7 5bc1 fcvtsd(eq|) s11, d1 +0+2d8 <[^>]*> bf01 itttt eq +0+2da <[^>]*> ee31 8b10 fmrdh(eq|) r8, d1 +0+2de <[^>]*> ee1f 7b10 fmrdl(eq|) r7, d15 +0+2e2 <[^>]*> ee21 fb10 fmdhr(eq|) d1, pc +0+2e6 <[^>]*> ee0f 1b10 fmdlr(eq|) d15, r1 +0+2ea <[^>]*> bf00 nop +0+2ec <[^>]*> bf00 nop +0+2ee <[^>]*> bf00 nop diff --git a/gas/testsuite/gas/arm/vfp1_t2.s b/gas/testsuite/gas/arm/vfp1_t2.s new file mode 100644 index 0000000..dd596cb --- /dev/null +++ b/gas/testsuite/gas/arm/vfp1_t2.s @@ -0,0 +1,298 @@ +@ VFP Instructions for D variants (Double precision) +@ Same as vfp1.s, but for Thumb-2 + .syntax unified + .thumb + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Most of these tests deliberatly use d0/r0 to avoid setting + @ any more bits than necessary. + + @ Comparison operations + + fcmped d0, d0 + fcmpezd d0 + fcmpd d0, d0 + fcmpzd d0 + + @ Monadic data operations + + fabsd d0, d0 + fcpyd d0, d0 + fnegd d0, d0 + fsqrtd d0, d0 + + @ Dyadic data operations + + faddd d0, d0, d0 + fdivd d0, d0, d0 + fmacd d0, d0, d0 + fmscd d0, d0, d0 + fmuld d0, d0, d0 + fnmacd d0, d0, d0 + fnmscd d0, d0, d0 + fnmuld d0, d0, d0 + fsubd d0, d0, d0 + + @ Load/store operations + + fldd d0, [r0] + fstd d0, [r0] + + @ Load/store multiple operations + + fldmiad r0, {d0} + fldmfdd r0, {d0} + fldmiad r0!, {d0} + fldmfdd r0!, {d0} + fldmdbd r0!, {d0} + fldmead r0!, {d0} + + fstmiad r0, {d0} + fstmead r0, {d0} + fstmiad r0!, {d0} + fstmead r0!, {d0} + fstmdbd r0!, {d0} + fstmfdd r0!, {d0} + + @ Conversion operations + + fsitod d0, s0 + fuitod d0, s0 + + ftosid s0, d0 + ftosizd s0, d0 + ftouid s0, d0 + ftouizd s0, d0 + + fcvtds d0, s0 + fcvtsd s0, d0 + + @ ARM from VFP operations + + fmrdh r0, d0 + fmrdl r0, d0 + + @ VFP From ARM operations + + fmdhr d0, r0 + fmdlr d0, r0 + + @ Now we test that the register fields are updated correctly for + @ each class of instruction. + + @ Single register operations (compare-zero): + + fcmpzd d1 + fcmpzd d2 + fcmpzd d15 + + @ Two register comparison operations: + + fcmpd d0, d1 + fcmpd d0, d2 + fcmpd d0, d15 + fcmpd d1, d0 + fcmpd d2, d0 + fcmpd d15, d0 + fcmpd d5, d12 + + @ Two register data operations (monadic) + + fnegd d0, d1 + fnegd d0, d2 + fnegd d0, d15 + fnegd d1, d0 + fnegd d2, d0 + fnegd d15, d0 + fnegd d12, d5 + + @ Three register data operations (dyadic) + + faddd d0, d0, d1 + faddd d0, d0, d2 + faddd d0, d0, d15 + faddd d0, d1, d0 + faddd d0, d2, d0 + faddd d0, d15, d0 + faddd d1, d0, d0 + faddd d2, d0, d0 + faddd d15, d0, d0 + faddd d12, d9, d5 + + @ Conversion operations + + fcvtds d0, s1 + fcvtds d0, s2 + fcvtds d0, s31 + fcvtds d1, s0 + fcvtds d2, s0 + fcvtds d15, s0 + fcvtsd s1, d0 + fcvtsd s2, d0 + fcvtsd s31, d0 + fcvtsd s0, d1 + fcvtsd s0, d2 + fcvtsd s0, d15 + + @ Move to VFP from ARM + + fmrdh r1, d0 + fmrdh r14, d0 + fmrdh r0, d1 + fmrdh r0, d2 + fmrdh r0, d15 + fmrdl r1, d0 + fmrdl r14, d0 + fmrdl r0, d1 + fmrdl r0, d2 + fmrdl r0, d15 + + @ Move to ARM from VFP + + fmdhr d0, r1 + fmdhr d0, r14 + fmdhr d1, r0 + fmdhr d2, r0 + fmdhr d15, r0 + fmdlr d0, r1 + fmdlr d0, r14 + fmdlr d1, r0 + fmdlr d2, r0 + fmdlr d15, r0 + + @ Load/store operations + + fldd d0, [r1] + fldd d0, [r14] + fldd d0, [r0, #0] + fldd d0, [r0, #1020] + fldd d0, [r0, #-1020] + fldd d1, [r0] + fldd d2, [r0] + fldd d15, [r0] + fstd d12, [r12, #804] + + @ Load/store multiple operations + + fldmiad r0, {d1} + fldmiad r0, {d2} + fldmiad r0, {d15} + fldmiad r0, {d0-d1} + fldmiad r0, {d0-d2} + fldmiad r0, {d0-d15} + fldmiad r0, {d1-d15} + fldmiad r0, {d2-d15} + fldmiad r0, {d14-d15} + fldmiad r1, {d0} + fldmiad r14, {d0} + + @ Check that we assemble all the register names correctly + + fcmpzd d0 + fcmpzd d1 + fcmpzd d2 + fcmpzd d3 + fcmpzd d4 + fcmpzd d5 + fcmpzd d6 + fcmpzd d7 + fcmpzd d8 + fcmpzd d9 + fcmpzd d10 + fcmpzd d11 + fcmpzd d12 + fcmpzd d13 + fcmpzd d14 + fcmpzd d15 + + @ Now we check the placement of the conditional execution substring. + @ On VFP this is always at the end of the instruction. + + @ Comparison operations + + itttt eq + fcmpedeq d1, d15 + fcmpezdeq d2 + fcmpdeq d3, d14 + fcmpzdeq d4 + + @ Monadic data operations + + itttt eq + fabsdeq d5, d13 + fcpydeq d6, d12 + fnegdeq d7, d11 + fsqrtdeq d8, d10 + + @ Dyadic data operations + + itttt eq + fadddeq d9, d1, d15 + fdivdeq d2, d3, d14 + fmacdeq d4, d13, d12 + fmscdeq d5, d6, d11 + itttt eq + fmuldeq d7, d10, d9 + fnmacdeq d8, d9, d10 + fnmscdeq d7, d6, d11 + fnmuldeq d5, d4, d12 + ittt eq + fsubdeq d3, d13, d14 + + @ Load/store operations + + flddeq d2, [r5] + fstdeq d1, [r12] + + @ Load/store multiple operations + + itttt eq + fldmiadeq r1, {d1} + fldmfddeq r2, {d2} + fldmiadeq r3!, {d3} + fldmfddeq r4!, {d4} + itttt eq + fldmdbdeq r5!, {d5} + fldmeadeq r6!, {d6} + + fstmiadeq r7, {d15} + fstmeadeq r8, {d14} + itttt eq + fstmiadeq r9!, {d13} + fstmeadeq r10!, {d12} + fstmdbdeq r11!, {d11} + fstmfddeq r12!, {d10} + + @ Conversion operations + + itttt eq + fsitodeq d15, s1 + fuitodeq d1, s31 + + ftosideq s1, d15 + ftosizdeq s31, d2 + itttt eq + ftouideq s15, d2 + ftouizdeq s11, d3 + + fcvtdseq d1, s10 + fcvtsdeq s11, d1 + + @ ARM from VFP operations + + itttt eq + fmrdheq r8, d1 + fmrdleq r7, d15 + + @ VFP From ARM operations + + fmdhreq d1, r15 + fmdlreq d15, r1 + + # Add three nop instructions to ensure that the + # output is 32-byte aligned as required for arm-aout. + nop + nop + nop diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d new file mode 100644 index 0000000..327383d --- /dev/null +++ b/gas/testsuite/gas/arm/vfp1xD_t2.d @@ -0,0 +1,258 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Thumb-2 VFP Single-precision instructions +#as: -mfpu=vfpxd + +# Test the ARM VFP Single Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> eef1 fa10 fmstat +0+004 <[^>]*> eeb4 0ac0 fcmpes s0, s0 +0+008 <[^>]*> eeb5 0ac0 fcmpezs s0 +0+00c <[^>]*> eeb4 0a40 fcmps s0, s0 +0+010 <[^>]*> eeb5 0a40 fcmpzs s0 +0+014 <[^>]*> eeb0 0ac0 fabss s0, s0 +0+018 <[^>]*> eeb0 0a40 fcpys s0, s0 +0+01c <[^>]*> eeb1 0a40 fnegs s0, s0 +0+020 <[^>]*> eeb1 0ac0 fsqrts s0, s0 +0+024 <[^>]*> ee30 0a00 fadds s0, s0, s0 +0+028 <[^>]*> ee80 0a00 fdivs s0, s0, s0 +0+02c <[^>]*> ee00 0a00 fmacs s0, s0, s0 +0+030 <[^>]*> ee10 0a00 fmscs s0, s0, s0 +0+034 <[^>]*> ee20 0a00 fmuls s0, s0, s0 +0+038 <[^>]*> ee00 0a40 fnmacs s0, s0, s0 +0+03c <[^>]*> ee10 0a40 fnmscs s0, s0, s0 +0+040 <[^>]*> ee20 0a40 fnmuls s0, s0, s0 +0+044 <[^>]*> ee30 0a40 fsubs s0, s0, s0 +0+048 <[^>]*> ed90 0a00 flds s0, \[r0\] +0+04c <[^>]*> ed80 0a00 fsts s0, \[r0\] +0+050 <[^>]*> ec90 0a01 fldmias r0, {s0} +0+054 <[^>]*> ec90 0a01 fldmias r0, {s0} +0+058 <[^>]*> ecb0 0a01 fldmias r0!, {s0} +0+05c <[^>]*> ecb0 0a01 fldmias r0!, {s0} +0+060 <[^>]*> ed30 0a01 fldmdbs r0!, {s0} +0+064 <[^>]*> ed30 0a01 fldmdbs r0!, {s0} +0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0} +0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0} +0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0} +0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0} +0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0} +0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0} +0+080 <[^>]*> ec80 0a01 fstmias r0, {s0} +0+084 <[^>]*> ec80 0a01 fstmias r0, {s0} +0+088 <[^>]*> eca0 0a01 fstmias r0!, {s0} +0+08c <[^>]*> eca0 0a01 fstmias r0!, {s0} +0+090 <[^>]*> ed20 0a01 fstmdbs r0!, {s0} +0+094 <[^>]*> ed20 0a01 fstmdbs r0!, {s0} +0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0} +0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0} +0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0} +0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0} +0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0} +0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0} +0+0b0 <[^>]*> eeb8 0ac0 fsitos s0, s0 +0+0b4 <[^>]*> eeb8 0a40 fuitos s0, s0 +0+0b8 <[^>]*> eebd 0a40 ftosis s0, s0 +0+0bc <[^>]*> eebd 0ac0 ftosizs s0, s0 +0+0c0 <[^>]*> eebc 0a40 ftouis s0, s0 +0+0c4 <[^>]*> eebc 0ac0 ftouizs s0, s0 +0+0c8 <[^>]*> ee10 0a10 fmrs r0, s0 +0+0cc <[^>]*> eef0 0a10 fmrx r0, fpsid +0+0d0 <[^>]*> eef1 0a10 fmrx r0, fpscr +0+0d4 <[^>]*> eef8 0a10 fmrx r0, fpexc +0+0d8 <[^>]*> ee00 0a10 fmsr s0, r0 +0+0dc <[^>]*> eee0 0a10 fmxr fpsid, r0 +0+0e0 <[^>]*> eee1 0a10 fmxr fpscr, r0 +0+0e4 <[^>]*> eee8 0a10 fmxr fpexc, r0 +0+0e8 <[^>]*> eef5 0a40 fcmpzs s1 +0+0ec <[^>]*> eeb5 1a40 fcmpzs s2 +0+0f0 <[^>]*> eef5 fa40 fcmpzs s31 +0+0f4 <[^>]*> eeb4 0a60 fcmps s0, s1 +0+0f8 <[^>]*> eeb4 0a41 fcmps s0, s2 +0+0fc <[^>]*> eeb4 0a6f fcmps s0, s31 +0+100 <[^>]*> eef4 0a40 fcmps s1, s0 +0+104 <[^>]*> eeb4 1a40 fcmps s2, s0 +0+108 <[^>]*> eef4 fa40 fcmps s31, s0 +0+10c <[^>]*> eef4 aa46 fcmps s21, s12 +0+110 <[^>]*> eeb1 0a60 fnegs s0, s1 +0+114 <[^>]*> eeb1 0a41 fnegs s0, s2 +0+118 <[^>]*> eeb1 0a6f fnegs s0, s31 +0+11c <[^>]*> eef1 0a40 fnegs s1, s0 +0+120 <[^>]*> eeb1 1a40 fnegs s2, s0 +0+124 <[^>]*> eef1 fa40 fnegs s31, s0 +0+128 <[^>]*> eeb1 6a6a fnegs s12, s21 +0+12c <[^>]*> ee30 0a20 fadds s0, s0, s1 +0+130 <[^>]*> ee30 0a01 fadds s0, s0, s2 +0+134 <[^>]*> ee30 0a2f fadds s0, s0, s31 +0+138 <[^>]*> ee30 0a80 fadds s0, s1, s0 +0+13c <[^>]*> ee31 0a00 fadds s0, s2, s0 +0+140 <[^>]*> ee3f 0a80 fadds s0, s31, s0 +0+144 <[^>]*> ee70 0a00 fadds s1, s0, s0 +0+148 <[^>]*> ee30 1a00 fadds s2, s0, s0 +0+14c <[^>]*> ee70 fa00 fadds s31, s0, s0 +0+150 <[^>]*> ee3a 6aa2 fadds s12, s21, s5 +0+154 <[^>]*> eeb8 0ae0 fsitos s0, s1 +0+158 <[^>]*> eeb8 0ac1 fsitos s0, s2 +0+15c <[^>]*> eeb8 0aef fsitos s0, s31 +0+160 <[^>]*> eef8 0ac0 fsitos s1, s0 +0+164 <[^>]*> eeb8 1ac0 fsitos s2, s0 +0+168 <[^>]*> eef8 fac0 fsitos s31, s0 +0+16c <[^>]*> eebd 0a60 ftosis s0, s1 +0+170 <[^>]*> eebd 0a41 ftosis s0, s2 +0+174 <[^>]*> eebd 0a6f ftosis s0, s31 +0+178 <[^>]*> eefd 0a40 ftosis s1, s0 +0+17c <[^>]*> eebd 1a40 ftosis s2, s0 +0+180 <[^>]*> eefd fa40 ftosis s31, s0 +0+184 <[^>]*> ee00 1a10 fmsr s0, r1 +0+188 <[^>]*> ee00 7a10 fmsr s0, r7 +0+18c <[^>]*> ee00 ea10 fmsr s0, lr +0+190 <[^>]*> ee00 0a90 fmsr s1, r0 +0+194 <[^>]*> ee01 0a10 fmsr s2, r0 +0+198 <[^>]*> ee0f 0a90 fmsr s31, r0 +0+19c <[^>]*> ee0a 7a90 fmsr s21, r7 +0+1a0 <[^>]*> eee0 1a10 fmxr fpsid, r1 +0+1a4 <[^>]*> eee0 ea10 fmxr fpsid, lr +0+1a8 <[^>]*> ee10 0a90 fmrs r0, s1 +0+1ac <[^>]*> ee11 0a10 fmrs r0, s2 +0+1b0 <[^>]*> ee1f 0a90 fmrs r0, s31 +0+1b4 <[^>]*> ee10 1a10 fmrs r1, s0 +0+1b8 <[^>]*> ee10 7a10 fmrs r7, s0 +0+1bc <[^>]*> ee10 ea10 fmrs lr, s0 +0+1c0 <[^>]*> ee15 9a90 fmrs r9, s11 +0+1c4 <[^>]*> eef0 1a10 fmrx r1, fpsid +0+1c8 <[^>]*> eef0 ea10 fmrx lr, fpsid +0+1cc <[^>]*> ed91 0a00 flds s0, \[r1\] +0+1d0 <[^>]*> ed9e 0a00 flds s0, \[lr\] +0+1d4 <[^>]*> ed90 0a00 flds s0, \[r0\] +0+1d8 <[^>]*> ed90 0aff flds s0, \[r0, #1020\] +0+1dc <[^>]*> ed10 0aff flds s0, \[r0, #-1020\] +0+1e0 <[^>]*> edd0 0a00 flds s1, \[r0\] +0+1e4 <[^>]*> ed90 1a00 flds s2, \[r0\] +0+1e8 <[^>]*> edd0 fa00 flds s31, \[r0\] +0+1ec <[^>]*> edcc aac9 fsts s21, \[ip, #804\] +0+1f0 <[^>]*> ecd0 0a01 fldmias r0, {s1} +0+1f4 <[^>]*> ec90 1a01 fldmias r0, {s2} +0+1f8 <[^>]*> ecd0 fa01 fldmias r0, {s31} +0+1fc <[^>]*> ec90 0a02 fldmias r0, {s0-s1} +0+200 <[^>]*> ec90 0a03 fldmias r0, {s0-s2} +0+204 <[^>]*> ec90 0a20 fldmias r0, {s0-s31} +0+208 <[^>]*> ecd0 0a1f fldmias r0, {s1-s31} +0+20c <[^>]*> ec90 1a1e fldmias r0, {s2-s31} +0+210 <[^>]*> ec90 fa02 fldmias r0, {s30-s31} +0+214 <[^>]*> ec91 0a01 fldmias r1, {s0} +0+218 <[^>]*> ec9e 0a01 fldmias lr, {s0} +0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1} +0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2} +0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15} +0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1} +0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2} +0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15} +0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15} +0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15} +0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15} +0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0} +0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0} +0+248 <[^>]*> eeb5 0a40 fcmpzs s0 +0+24c <[^>]*> eef5 0a40 fcmpzs s1 +0+250 <[^>]*> eeb5 1a40 fcmpzs s2 +0+254 <[^>]*> eef5 1a40 fcmpzs s3 +0+258 <[^>]*> eeb5 2a40 fcmpzs s4 +0+25c <[^>]*> eef5 2a40 fcmpzs s5 +0+260 <[^>]*> eeb5 3a40 fcmpzs s6 +0+264 <[^>]*> eef5 3a40 fcmpzs s7 +0+268 <[^>]*> eeb5 4a40 fcmpzs s8 +0+26c <[^>]*> eef5 4a40 fcmpzs s9 +0+270 <[^>]*> eeb5 5a40 fcmpzs s10 +0+274 <[^>]*> eef5 5a40 fcmpzs s11 +0+278 <[^>]*> eeb5 6a40 fcmpzs s12 +0+27c <[^>]*> eef5 6a40 fcmpzs s13 +0+280 <[^>]*> eeb5 7a40 fcmpzs s14 +0+284 <[^>]*> eef5 7a40 fcmpzs s15 +0+288 <[^>]*> eeb5 8a40 fcmpzs s16 +0+28c <[^>]*> eef5 8a40 fcmpzs s17 +0+290 <[^>]*> eeb5 9a40 fcmpzs s18 +0+294 <[^>]*> eef5 9a40 fcmpzs s19 +0+298 <[^>]*> eeb5 aa40 fcmpzs s20 +0+29c <[^>]*> eef5 aa40 fcmpzs s21 +0+2a0 <[^>]*> eeb5 ba40 fcmpzs s22 +0+2a4 <[^>]*> eef5 ba40 fcmpzs s23 +0+2a8 <[^>]*> eeb5 ca40 fcmpzs s24 +0+2ac <[^>]*> eef5 ca40 fcmpzs s25 +0+2b0 <[^>]*> eeb5 da40 fcmpzs s26 +0+2b4 <[^>]*> eef5 da40 fcmpzs s27 +0+2b8 <[^>]*> eeb5 ea40 fcmpzs s28 +0+2bc <[^>]*> eef5 ea40 fcmpzs s29 +0+2c0 <[^>]*> eeb5 fa40 fcmpzs s30 +0+2c4 <[^>]*> eef5 fa40 fcmpzs s31 +# The "(eq|)" should be replaces by "eq" once the disassembler is fixed. +0+2c8 <[^>]*> bf01 itttt eq +0+2ca <[^>]*> eef1 fa10 fmstat(eq|) +0+2ce <[^>]*> eef4 1ae3 fcmpes(eq|) s3, s7 +0+2d2 <[^>]*> eef5 2ac0 fcmpezs(eq|) s5 +0+2d6 <[^>]*> eef4 0a41 fcmps(eq|) s1, s2 +0+2da <[^>]*> bf01 itttt eq +0+2dc <[^>]*> eef5 0a40 fcmpzs(eq|) s1 +0+2e0 <[^>]*> eef0 0ae1 fabss(eq|) s1, s3 +0+2e4 <[^>]*> eef0 fa69 fcpys(eq|) s31, s19 +0+2e8 <[^>]*> eeb1 aa44 fnegs(eq|) s20, s8 +0+2ec <[^>]*> bf01 itttt eq +0+2ee <[^>]*> eef1 2ae3 fsqrts(eq|) s5, s7 +0+2f2 <[^>]*> ee32 3a82 fadds(eq|) s6, s5, s4 +0+2f6 <[^>]*> eec1 1a20 fdivs(eq|) s3, s2, s1 +0+2fa <[^>]*> ee4f fa2e fmacs(eq|) s31, s30, s29 +0+2fe <[^>]*> bf01 itttt eq +0+300 <[^>]*> ee1d ea8d fmscs(eq|) s28, s27, s26 +0+304 <[^>]*> ee6c ca2b fmuls(eq|) s25, s24, s23 +0+308 <[^>]*> ee0a baca fnmacs(eq|) s22, s21, s20 +0+30c <[^>]*> ee59 9a68 fnmscs(eq|) s19, s18, s17 +0+310 <[^>]*> bf01 itttt eq +0+312 <[^>]*> ee27 8ac7 fnmuls(eq|) s16, s15, s14 +0+316 <[^>]*> ee76 6a65 fsubs(eq|) s13, s12, s11 +0+31a <[^>]*> ed98 5a00 flds(eq|) s10, \[r8\] +0+31e <[^>]*> edc7 4a00 fsts(eq|) s9, \[r7\] +0+322 <[^>]*> bf01 itttt eq +0+324 <[^>]*> ec91 4a01 fldmias(eq|) r1, {s8} +0+328 <[^>]*> ecd2 3a01 fldmias(eq|) r2, {s7} +0+32c <[^>]*> ecb3 3a01 fldmias(eq|) r3!, {s6} +0+330 <[^>]*> ecf4 2a01 fldmias(eq|) r4!, {s5} +0+334 <[^>]*> bf01 itttt eq +0+336 <[^>]*> ed35 2a01 fldmdbs(eq|) r5!, {s4} +0+33a <[^>]*> ed76 1a01 fldmdbs(eq|) r6!, {s3} +0+33e <[^>]*> ec97 1b03 fldmiax(eq|) r7, {d1} +0+342 <[^>]*> ec98 2b03 fldmiax(eq|) r8, {d2} +0+346 <[^>]*> bf01 itttt eq +0+348 <[^>]*> ecb9 3b03 fldmiax(eq|) r9!, {d3} +0+34c <[^>]*> ecba 4b03 fldmiax(eq|) sl!, {d4} +0+350 <[^>]*> ed3b 5b03 fldmdbx(eq|) fp!, {d5} +0+354 <[^>]*> ed3c 6b03 fldmdbx(eq|) ip!, {d6} +0+358 <[^>]*> bf01 itttt eq +0+35a <[^>]*> ec8d 1a01 fstmias(eq|) sp, {s2} +0+35e <[^>]*> ecce 0a01 fstmias(eq|) lr, {s1} +0+362 <[^>]*> ece1 fa01 fstmias(eq|) r1!, {s31} +0+366 <[^>]*> eca2 fa01 fstmias(eq|) r2!, {s30} +0+36a <[^>]*> bf01 itttt eq +0+36c <[^>]*> ed63 ea01 fstmdbs(eq|) r3!, {s29} +0+370 <[^>]*> ed24 ea01 fstmdbs(eq|) r4!, {s28} +0+374 <[^>]*> ec85 7b03 fstmiax(eq|) r5, {d7} +0+378 <[^>]*> ec86 8b03 fstmiax(eq|) r6, {d8} +0+37c <[^>]*> bf01 itttt eq +0+37e <[^>]*> eca7 9b03 fstmiax(eq|) r7!, {d9} +0+382 <[^>]*> eca8 ab03 fstmiax(eq|) r8!, {d10} +0+386 <[^>]*> ed29 bb03 fstmdbx(eq|) r9!, {d11} +0+38a <[^>]*> ed2a cb03 fstmdbx(eq|) sl!, {d12} +0+38e <[^>]*> bf01 itttt eq +0+390 <[^>]*> eef8 dac3 fsitos(eq|) s27, s6 +0+394 <[^>]*> eefd ca62 ftosis(eq|) s25, s5 +0+398 <[^>]*> eefd bac2 ftosizs(eq|) s23, s4 +0+39c <[^>]*> eefc aa61 ftouis(eq|) s21, s3 +0+3a0 <[^>]*> bf01 itttt eq +0+3a2 <[^>]*> eefc 9ac1 ftouizs(eq|) s19, s2 +0+3a6 <[^>]*> eef8 8a60 fuitos(eq|) s17, s1 +0+3aa <[^>]*> ee11 ba90 fmrs(eq|) fp, s3 +0+3ae <[^>]*> eef0 9a10 fmrx(eq|) r9, fpsid +0+3b2 <[^>]*> bf04 itt eq +0+3b4 <[^>]*> ee01 9a90 fmsr(eq|) s3, r9 +0+3b8 <[^>]*> eee0 8a10 fmxr(eq|) fpsid, r8 +0+3bc <[^>]*> bf00 nop +0+3be <[^>]*> bf00 nop diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.s b/gas/testsuite/gas/arm/vfp1xD_t2.s new file mode 100644 index 0000000..f3087a3 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp1xD_t2.s @@ -0,0 +1,359 @@ +@ VFP Instructions for v1xD variants (Single precision only) +@ Same as vfp1xD.s, but for Thumb-2 + .syntax unified + .thumb + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Most of these tests deliberatly use s0/r0 to avoid setting + @ any more bits than necessary. + + @ Comparison operations + + fmstat + + fcmpes s0, s0 + fcmpezs s0 + fcmps s0, s0 + fcmpzs s0 + + @ Monadic data operations + + fabss s0, s0 + fcpys s0, s0 + fnegs s0, s0 + fsqrts s0, s0 + + @ Dyadic data operations + + fadds s0, s0, s0 + fdivs s0, s0, s0 + fmacs s0, s0, s0 + fmscs s0, s0, s0 + fmuls s0, s0, s0 + fnmacs s0, s0, s0 + fnmscs s0, s0, s0 + fnmuls s0, s0, s0 + fsubs s0, s0, s0 + + @ Load/store operations + + flds s0, [r0] + fsts s0, [r0] + + @ Load/store multiple operations + + fldmias r0, {s0} + fldmfds r0, {s0} + fldmias r0!, {s0} + fldmfds r0!, {s0} + fldmdbs r0!, {s0} + fldmeas r0!, {s0} + + fldmiax r0, {d0} + fldmfdx r0, {d0} + fldmiax r0!, {d0} + fldmfdx r0!, {d0} + fldmdbx r0!, {d0} + fldmeax r0!, {d0} + + fstmias r0, {s0} + fstmeas r0, {s0} + fstmias r0!, {s0} + fstmeas r0!, {s0} + fstmdbs r0!, {s0} + fstmfds r0!, {s0} + + fstmiax r0, {d0} + fstmeax r0, {d0} + fstmiax r0!, {d0} + fstmeax r0!, {d0} + fstmdbx r0!, {d0} + fstmfdx r0!, {d0} + + @ Conversion operations + + fsitos s0, s0 + fuitos s0, s0 + + ftosis s0, s0 + ftosizs s0, s0 + ftouis s0, s0 + ftouizs s0, s0 + + @ ARM from VFP operations + + fmrs r0, s0 + fmrx r0, fpsid + fmrx r0, fpscr + fmrx r0, fpexc + + @ VFP From ARM operations + + fmsr s0, r0 + fmxr fpsid, r0 + fmxr fpscr, r0 + fmxr fpexc, r0 + + @ Now we test that the register fields are updated correctly for + @ each class of instruction. + + @ Single register operations (compare-zero): + + fcmpzs s1 + fcmpzs s2 + fcmpzs s31 + + @ Two register comparison operations: + + fcmps s0, s1 + fcmps s0, s2 + fcmps s0, s31 + fcmps s1, s0 + fcmps s2, s0 + fcmps s31, s0 + fcmps s21, s12 + + @ Two register data operations (monadic) + + fnegs s0, s1 + fnegs s0, s2 + fnegs s0, s31 + fnegs s1, s0 + fnegs s2, s0 + fnegs s31, s0 + fnegs s12, s21 + + @ Three register data operations (dyadic) + + fadds s0, s0, s1 + fadds s0, s0, s2 + fadds s0, s0, s31 + fadds s0, s1, s0 + fadds s0, s2, s0 + fadds s0, s31, s0 + fadds s1, s0, s0 + fadds s2, s0, s0 + fadds s31, s0, s0 + fadds s12, s21, s5 + + @ Conversion operations + + fsitos s0, s1 + fsitos s0, s2 + fsitos s0, s31 + fsitos s1, s0 + fsitos s2, s0 + fsitos s31, s0 + + ftosis s0, s1 + ftosis s0, s2 + ftosis s0, s31 + ftosis s1, s0 + ftosis s2, s0 + ftosis s31, s0 + + @ Move to VFP from ARM + + fmsr s0, r1 + fmsr s0, r7 + fmsr s0, r14 + fmsr s1, r0 + fmsr s2, r0 + fmsr s31, r0 + fmsr s21, r7 + + fmxr fpsid, r1 + fmxr fpsid, r14 + + @ Move to ARM from VFP + + fmrs r0, s1 + fmrs r0, s2 + fmrs r0, s31 + fmrs r1, s0 + fmrs r7, s0 + fmrs r14, s0 + fmrs r9, s11 + + fmrx r1, fpsid + fmrx r14, fpsid + + @ Load/store operations + + flds s0, [r1] + flds s0, [r14] + flds s0, [r0, #0] + flds s0, [r0, #1020] + flds s0, [r0, #-1020] + flds s1, [r0] + flds s2, [r0] + flds s31, [r0] + fsts s21, [r12, #804] + + @ Load/store multiple operations + + fldmias r0, {s1} + fldmias r0, {s2} + fldmias r0, {s31} + fldmias r0, {s0-s1} + fldmias r0, {s0-s2} + fldmias r0, {s0-s31} + fldmias r0, {s1-s31} + fldmias r0, {s2-s31} + fldmias r0, {s30-s31} + fldmias r1, {s0} + fldmias r14, {s0} + + fstmiax r0, {d1} + fstmiax r0, {d2} + fstmiax r0, {d15} + fstmiax r0, {d0-d1} + fstmiax r0, {d0-d2} + fstmiax r0, {d0-d15} + fstmiax r0, {d1-d15} + fstmiax r0, {d2-d15} + fstmiax r0, {d14-d15} + fstmiax r1, {d0} + fstmiax r14, {d0} + + @ Check that we assemble all the register names correctly + + fcmpzs s0 + fcmpzs s1 + fcmpzs s2 + fcmpzs s3 + fcmpzs s4 + fcmpzs s5 + fcmpzs s6 + fcmpzs s7 + fcmpzs s8 + fcmpzs s9 + fcmpzs s10 + fcmpzs s11 + fcmpzs s12 + fcmpzs s13 + fcmpzs s14 + fcmpzs s15 + fcmpzs s16 + fcmpzs s17 + fcmpzs s18 + fcmpzs s19 + fcmpzs s20 + fcmpzs s21 + fcmpzs s22 + fcmpzs s23 + fcmpzs s24 + fcmpzs s25 + fcmpzs s26 + fcmpzs s27 + fcmpzs s28 + fcmpzs s29 + fcmpzs s30 + fcmpzs s31 + + @ Now we check the placement of the conditional execution substring. + @ On VFP this is always at the end of the instruction. + @ We use different register numbers here to check for correct + @ disassembly + + @ Comparison operations + + itttt eq + fmstateq + + fcmpeseq s3, s7 + fcmpezseq s5 + fcmpseq s1, s2 + itttt eq + fcmpzseq s1 + + @ Monadic data operations + + fabsseq s1, s3 + fcpyseq s31, s19 + fnegseq s20, s8 + itttt eq + fsqrtseq s5, s7 + + @ Dyadic data operations + + faddseq s6, s5, s4 + fdivseq s3, s2, s1 + fmacseq s31, s30, s29 + itttt eq + fmscseq s28, s27, s26 + fmulseq s25, s24, s23 + fnmacseq s22, s21, s20 + fnmscseq s19, s18, s17 + itttt eq + fnmulseq s16, s15, s14 + fsubseq s13, s12, s11 + + @ Load/store operations + + fldseq s10, [r8] + fstseq s9, [r7] + + @ Load/store multiple operations + + itttt eq + fldmiaseq r1, {s8} + fldmfdseq r2, {s7} + fldmiaseq r3!, {s6} + fldmfdseq r4!, {s5} + itttt eq + fldmdbseq r5!, {s4} + fldmeaseq r6!, {s3} + + fldmiaxeq r7, {d1} + fldmfdxeq r8, {d2} + itttt eq + fldmiaxeq r9!, {d3} + fldmfdxeq r10!, {d4} + fldmdbxeq r11!, {d5} + fldmeaxeq r12!, {d6} + + itttt eq + fstmiaseq r13, {s2} + fstmeaseq r14, {s1} + fstmiaseq r1!, {s31} + fstmeaseq r2!, {s30} + itttt eq + fstmdbseq r3!, {s29} + fstmfdseq r4!, {s28} + + fstmiaxeq r5, {d7} + fstmeaxeq r6, {d8} + itttt eq + fstmiaxeq r7!, {d9} + fstmeaxeq r8!, {d10} + fstmdbxeq r9!, {d11} + fstmfdxeq r10!, {d12} + + @ Conversion operations + + itttt eq + fsitoseq s27, s6 + ftosiseq s25, s5 + ftosizseq s23, s4 + ftouiseq s21, s3 + itttt eq + ftouizseq s19, s2 + fuitoseq s17, s1 + + @ ARM from VFP operations + + fmrseq r11, s3 + fmrxeq r9, fpsid + + @ VFP From ARM operations + + itt eq + fmsreq s3, r9 + fmxreq fpsid, r8 + + @ 2 nops to pad to 16-byte boundary + nop + nop diff --git a/gas/testsuite/gas/arm/vfp2_t2.d b/gas/testsuite/gas/arm/vfp2_t2.d new file mode 100644 index 0000000..bb988e5 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp2_t2.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Thumb-2 VFP Additional instructions +#as: -mfpu=vfp + +# Test the ARM VFP Double Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> ec4a 5b10 fmdrr d0, r5, sl +0+004 <[^>]*> ec5a 5b10 fmrrd r5, sl, d0 +0+008 <[^>]*> ec4a 5a37 fmsrr r5, sl, {s15, s16} +0+00c <[^>]*> ec5a 5a37 fmrrs r5, sl, {s15, s16} +0+010 <[^>]*> ec45 ab1f fmdrr d15, sl, r5 +0+014 <[^>]*> ec55 ab1f fmrrd sl, r5, d15 +0+018 <[^>]*> ec45 aa38 fmsrr sl, r5, {s17, s18} +0+01c <[^>]*> ec55 aa38 fmrrs sl, r5, {s17, s18} diff --git a/gas/testsuite/gas/arm/vfp2_t2.s b/gas/testsuite/gas/arm/vfp2_t2.s new file mode 100644 index 0000000..ba5551b --- /dev/null +++ b/gas/testsuite/gas/arm/vfp2_t2.s @@ -0,0 +1,21 @@ +@ VFP2 Additional instructions +@ Same as vfp2.s, but for Thumb-2 + .syntax unified + .thumb + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise + @ the full register bitpatterns + + fmdrr d0, r5, r10 + fmrrd r5, r10, d0 + fmsrr {s15, s16}, r5, r10 + fmrrs r5, r10, {s15, s16} + + fmdrr d15, r10, r5 + fmrrd r10, r5, d15 + fmsrr {s17, s18}, r10, r5 + fmrrs r10, r5, {s17, s18} + diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1d8ed02..3b321c4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2005-09-02 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (coprocessor_opcodes): New. + (arm_opcodes, thumb32_opcodes): Remove coprocessor insns. + (print_insn_coprocessor): New function. + (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor + format characters. + (print_insn_thumb32): Use print_insn_coprocessor. + 2005-08-30 Paul Brook <paul@codesourcery.com> * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 0f05501..a785488 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -57,26 +57,13 @@ struct opcode16 const char *assembler; /* How to disassemble this insn. */ }; -/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially - ordered: they must be searched linearly from the top to obtain a correct - match. */ - -/* print_insn_arm recognizes the following format control codes: +/* print_insn_coprocessor recognizes the following format control codes: %% % - %a print address for ldr/str instruction - %s print address for ldr/str halfword/signextend instruction - %b print branch destination %c print condition code (always bits 28-31) - %m print register mask for ldm/stm instruction - %o print operand2 (immediate or register + shift) - %p print 'p' iff bits 12-15 are 15 - %t print 't' iff bit 21 set and bit 24 clear %A print address for ldc/stc/ldf/stf instruction - %B print arm BLX(1) destination %I print cirrus signed shift immediate: bits 0..3|4..6 - %C print the PSR sub type. %F print the COUNT field of a LFM/SFM instruction. %P print floating point precision in arithmetic insn %Q print floating point precision in ldf/stf insn @@ -84,7 +71,6 @@ struct opcode16 %<bitfield>r print as an ARM register %<bitfield>d print the bitfield in decimal - %<bitfield>W print the bitfield plus one in decimal %<bitfield>x print the bitfield in hex %<bitfield>X print the bitfield as 1 hex digit without leading "0x" %<bitfield>f print a floating point constant if >7 else a @@ -103,182 +89,13 @@ struct opcode16 %L print as an iWMMXt N/M width field. %Z print the Immediate of a WSHUFH instruction. - %l like 'A' except use byte offsets for 'B' & 'H' versions. + %l like 'A' except use byte offsets for 'B' & 'H' + versions. */ - %e print arm SMI operand (bits 0..7,8..19). - %E print the LSB and WIDTH fields of a BFI or BFC instruction. - %V print the 16-bit immediate field of a MOVT or MOVW instruction. */ +/* Common coprocessor opcodes shared between Arm and Thumb-2. */ -static const struct opcode32 arm_opcodes[] = +static const struct opcode32 coprocessor_opcodes[] = { - /* ARM instructions. */ - {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, - {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - - /* ARM V6T2 instructions. */ - {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"}, - {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, - {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"}, - {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"}, - {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, - {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, - {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, - - /* ARM V6Z instructions. */ - {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"}, - - /* ARM V6K instructions. */ - {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, - {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"}, - - /* ARM V6K NOP hints. */ - {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, - {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"}, - {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"}, - {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, - {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, - - /* ARM V6 instructions. */ - {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {ARM_EXT_V6, 0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"}, - {ARM_EXT_V6, 0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, - {ARM_EXT_V6, 0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"}, - {ARM_EXT_V6, 0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, - {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"}, - {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, - {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, - {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, - {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {ARM_EXT_V6, 0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, - {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"}, - {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"}, - {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, - {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"}, - {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"}, - {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, - - /* V5J instruction. */ - {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, - /* XScale instructions. */ {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, @@ -339,78 +156,6 @@ static const struct opcode32 arm_opcodes[] = {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, - /* V5 Instructions. */ - {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, - {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, - {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, - {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, - {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - - /* V5E "El Segundo" Instructions. */ - {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"}, - {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"}, - {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, - {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - - {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - - {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - - {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, - - {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, - - {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, - {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, - {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, - {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, - - /* ARM Instructions. */ - {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, - {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, - {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, - {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, - {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, - {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, - {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, - {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"}, - {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, - {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, - {ARM_EXT_V1, 0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, - /* Floating point coprocessor (FPA) instructions */ {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, @@ -626,6 +371,287 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, + /* V6 coprocessor instructions */ + {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + + /* V5 coprocessor instructions */ + {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + +}; + +/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially + ordered: they must be searched linearly from the top to obtain a correct + match. */ + +/* print_insn_arm recognizes the following format control codes: + + %% % + + %a print address for ldr/str instruction + %s print address for ldr/str halfword/signextend instruction + %b print branch destination + %c print condition code (always bits 28-31) + %m print register mask for ldm/stm instruction + %o print operand2 (immediate or register + shift) + %p print 'p' iff bits 12-15 are 15 + %t print 't' iff bit 21 set and bit 24 clear + %B print arm BLX(1) destination + %C print the PSR sub type. + + %<bitfield>r print as an ARM register + %<bitfield>d print the bitfield in decimal + %<bitfield>W print the bitfield plus one in decimal + %<bitfield>x print the bitfield in hex + %<bitfield>X print the bitfield as 1 hex digit without leading "0x" + + %<bitnum>'c print specified char iff bit is one + %<bitnum>`c print specified char iff bit is zero + %<bitnum>?ab print a if bit is one else print b + + %e print arm SMI operand (bits 0..7,8..19). + %E print the LSB and WIDTH fields of a BFI or BFC instruction. + %V print the 16-bit immediate field of a MOVT or MOVW instruction. */ + +static const struct opcode32 arm_opcodes[] = +{ + /* ARM instructions. */ + {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, + {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, + {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, + {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + + /* ARM V6T2 instructions. */ + {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"}, + {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, + {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"}, + {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"}, + {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, + {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, + {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, + + /* ARM V6Z instructions. */ + {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"}, + + /* ARM V6K instructions. */ + {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, + {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"}, + {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"}, + {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"}, + + /* ARM V6K NOP hints. */ + {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, + {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"}, + {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"}, + {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, + {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, + + /* ARM V6 instructions. */ + {ARM_EXT_V6, 0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"}, + {ARM_EXT_V6, 0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_EXT_V6, 0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"}, + {ARM_EXT_V6, 0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, + {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"}, + {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"}, + {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"}, + {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, + {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, + {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, + {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"}, + {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"}, + {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"}, + {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"}, + {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"}, + {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"}, + {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"}, + {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"}, + {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"}, + {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, + {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"}, + {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, + {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"}, + {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"}, + {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, + {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, + {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, + {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"}, + {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"}, + {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, + + /* V5J instruction. */ + {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, + + /* V5 Instructions. */ + {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, + {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, + {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, + + /* V5E "El Segundo" Instructions. */ + {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"}, + {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"}, + {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, + {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + + {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + + {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + + {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, + + {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, + + {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, + {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, + {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, + {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, + + /* ARM Instructions. */ + {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, + {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, + {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, + {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, + {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, + {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, + {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, + {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, + {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, + {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"}, + {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, + {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, + {ARM_EXT_V1, 0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, + /* The rest. */ {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"}, {0, 0x00000000, 0x00000000, 0} @@ -792,7 +818,6 @@ static const struct opcode16 thumb_opcodes[] = %S print a possibly-shifted Rm %a print the address of a plain load/store - %A print the address of a coprocessor load/store %w print the width and signedness of a core load/store %m print register mask for ldm/stm @@ -965,8 +990,6 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt\t%12-15r, %a"}, {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat\t%8-11r, #%0-4d, %16-19r%s"}, {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat\t%8-11r, #%0-4d, %16-19r%s"}, - {ARM_EXT_V6T2, 0xee000010, 0xef1000f0, "mcr%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d"}, - {ARM_EXT_V6T2, 0xee100010, 0xef1000f0, "mrc%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d"}, {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw\t%8-11r, %16-19r, %I"}, {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw\t%8-11r, %J"}, {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw\t%8-11r, %16-19r, %I"}, @@ -982,9 +1005,6 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's.w\t%8-11r, %16-19r, %S"}, {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's\t%8-11r, %16-19r, %S"}, {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xee000000, 0xef0000f0, "cdp%28'2\tp%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d"}, - {ARM_EXT_V6T2, 0xec400000, 0xeff00000, "mcrr%28'2\tp%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {ARM_EXT_V6T2, 0xec500000, 0xeff00000, "mrrc%28'2\tp%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's.w\t%8-11r, %16-19r, %M"}, {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's.w\t%8-11r, %16-19r, %M"}, {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's.w\t%8-11r, %16-19r, %M"}, @@ -1003,13 +1023,8 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd\t%12-15r, %8-11r, [%16-19r]"}, {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"}, {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"}, - {ARM_EXT_V6T2, 0xee000010, 0xef100010, "mcr%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, %5-7d"}, - {ARM_EXT_V6T2, 0xee100010, 0xef100010, "mrc%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, %5-7d"}, {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w.w\t%12-15r, %a"}, {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w.w\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xec000000, 0xee100000, "stc%28'2%22'l\tp%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V6T2, 0xec100000, 0xee100000, "ldc%28'2%22'l\tp%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V6T2, 0xee000000, 0xef000010, "cdp%28'2\tp%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, %5-7d"}, /* Filter out Bcc with cond=E or F, which are used for other instructions. */ {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, @@ -1145,6 +1160,448 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream) } } +/* Print one coprocessor instruction on INFO->STREAM. + Return TRUE if the instuction matched, FALSE if this is not a + recognised coprocessor instruction. */ + +static bfd_boolean +print_insn_coprocessor (struct disassemble_info *info, long given, + bfd_boolean thumb) +{ + const struct opcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + unsigned long mask; + unsigned long value; + + for (insn = coprocessor_opcodes; insn->assembler; insn++) + { + if (insn->value == FIRST_IWMMXT_INSN + && info->mach != bfd_mach_arm_XScale + && info->mach != bfd_mach_arm_iWMMXt) + insn = insn + IWMMXT_INSN_COUNT; + + mask = insn->mask; + value = insn->value; + if (thumb) + { + /* The high 4 bits are 0xe for Arm conditional instructions, and + 0xe for arm unconditional instructions. The rest of the + encoding is the same. */ + mask |= 0xf0000000; + value |= 0xe0000000; + } + else + { + /* Only match unconditional instuctions against unconditional + patterns. */ + if ((given & 0xf0000000) == 0xf0000000) + mask |= 0xf0000000; + } + if ((given & mask) == value) + { + const char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'A': + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + + if ((given & (1 << 24)) != 0) + { + int offset = given & 0xff; + + if (offset) + func (stream, ", #%s%d]%s", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * 4, + ((given & 0x00200000) != 0 ? "!" : "")); + else + func (stream, "]"); + } + else + { + int offset = given & 0xff; + + func (stream, "]"); + + if (given & (1 << 21)) + { + if (offset) + func (stream, ", #%s%d", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * 4); + } + else + func (stream, ", {%d}", offset); + } + break; + + case 'c': + func (stream, "%s", + arm_conditional [(given >> 28) & 0xf]); + break; + + case 'I': + /* Print a Cirrus/DSP shift immediate. */ + /* Immediates are 7bit signed ints with bits 0..3 in + bits 0..3 of opcode and bits 4..6 in bits 5..7 + of opcode. */ + { + int imm; + + imm = (given & 0xf) | ((given & 0xe0) >> 1); + + /* Is ``imm'' a negative number? */ + if (imm & 0x40) + imm |= (-1 << 7); + + func (stream, "%d", imm); + } + + break; + + case 'F': + switch (given & 0x00408000) + { + case 0: + func (stream, "4"); + break; + case 0x8000: + func (stream, "1"); + break; + case 0x00400000: + func (stream, "2"); + break; + default: + func (stream, "3"); + } + break; + + case 'P': + switch (given & 0x00080080) + { + case 0: + func (stream, "s"); + break; + case 0x80: + func (stream, "d"); + break; + case 0x00080000: + func (stream, "e"); + break; + default: + func (stream, _("<illegal precision>")); + break; + } + break; + case 'Q': + switch (given & 0x00408000) + { + case 0: + func (stream, "s"); + break; + case 0x8000: + func (stream, "d"); + break; + case 0x00400000: + func (stream, "e"); + break; + default: + func (stream, "p"); + break; + } + break; + case 'R': + switch (given & 0x60) + { + case 0: + break; + case 0x20: + func (stream, "p"); + break; + case 0x40: + func (stream, "m"); + break; + default: + func (stream, "z"); + break; + } + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + c++; + + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + + if (!bitend) + abort (); + + switch (*c) + { + case 'r': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%s", arm_regnames[reg]); + } + break; + case 'd': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%ld", reg); + } + break; + case 'f': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + if (reg > 7) + func (stream, "#%s", + arm_fp_const[reg & 7]); + else + func (stream, "f%ld", reg); + } + break; + + case 'w': + { + long reg; + + if (bitstart != bitend) + { + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + if (bitend - bitstart == 1) + func (stream, "%s", iwmmxt_wwnames[reg]); + else + func (stream, "%s", iwmmxt_wwssnames[reg]); + } + else + { + reg = (((given >> 8) & 0x1) | + ((given >> 22) & 0x1)); + func (stream, "%s", iwmmxt_wwnames[reg]); + } + } + break; + + case 'g': + { + long reg; + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "%s", iwmmxt_regnames[reg]); + } + break; + + case 'G': + { + long reg; + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "%s", iwmmxt_cregnames[reg]); + } + break; + + default: + abort (); + } + break; + + case 'y': + case 'z': + { + int single = *c == 'y'; + int regno; + + switch (bitstart) + { + case 4: /* Sm pair */ + func (stream, "{"); + /* Fall through. */ + case 0: /* Sm, Dm */ + regno = given & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 5) & 1; + } + break; + + case 1: /* Sd, Dd */ + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + break; + + case 2: /* Sn, Dn */ + regno = (given >> 16) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 7) & 1; + } + break; + + case 3: /* List */ + func (stream, "{"); + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + break; + + + default: + abort (); + } + + func (stream, "%c%d", single ? 's' : 'd', regno); + + if (bitstart == 3) + { + int count = given & 0xff; + + if (single == 0) + count >>= 1; + + if (--count) + { + func (stream, "-%c%d", + single ? 's' : 'd', + regno + count); + } + + func (stream, "}"); + } + else if (bitstart == 4) + func (stream, ", %c%d}", single ? 's' : 'd', + regno + 1); + + break; + } + + break; + + case '`': + c++; + if ((given & (1 << bitstart)) == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + case '?': + ++c; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c++); + else + func (stream, "%c", *++c); + break; + default: + abort (); + } + break; + + case 'L': + switch (given & 0x00400100) + { + case 0x00000000: func (stream, "b"); break; + case 0x00400000: func (stream, "h"); break; + case 0x00000100: func (stream, "w"); break; + case 0x00400100: func (stream, "d"); break; + default: + break; + } + break; + + case 'Z': + { + int value; + /* given (20, 23) | given (0, 3) */ + value = ((given >> 16) & 0xf0) | (given & 0xf); + func (stream, "%d", value); + } + break; + + case 'l': + /* This is like the 'A' operator, except that if + the width field "M" is zero, then the offset is + *not* multiplied by four. */ + { + int offset = given & 0xff; + int multiplier = (given & 0x00000100) ? 4 : 1; + + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + + if (offset) + { + if ((given & 0x01000000) != 0) + func (stream, ", #%s%d]%s", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * multiplier, + ((given & 0x00200000) != 0 ? "!" : "")); + else + func (stream, "], #%s%d", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * multiplier); + } + else + func (stream, "]"); + } + break; + + default: + abort (); + } + } + } + else + func (stream, "%c", *c); + } + return TRUE; + } + } + return FALSE; +} + /* Print one ARM instruction from PC on INFO->STREAM. */ static void @@ -1154,6 +1611,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) void *stream = info->stream; fprintf_ftype func = info->fprintf_func; + if (print_insn_coprocessor (info, given, FALSE)) + return; + for (insn = arm_opcodes; insn->assembler; insn++) { if (insn->value == FIRST_IWMMXT_INSN @@ -1441,25 +1901,6 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) } break; - case 'I': - /* Print a Cirrus/DSP shift immediate. */ - /* Immediates are 7bit signed ints with bits 0..3 in - bits 0..3 of opcode and bits 4..6 in bits 5..7 - of opcode. */ - { - int imm; - - imm = (given & 0xf) | ((given & 0xe0) >> 1); - - /* Is ``imm'' a negative number? */ - if (imm & 0x40) - imm |= (-1 << 7); - - func (stream, "%d", imm); - } - - break; - case 'C': func (stream, "_"); if (given & 0x80000) @@ -1472,74 +1913,6 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "c"); break; - case 'F': - switch (given & 0x00408000) - { - case 0: - func (stream, "4"); - break; - case 0x8000: - func (stream, "1"); - break; - case 0x00400000: - func (stream, "2"); - break; - default: - func (stream, "3"); - } - break; - - case 'P': - switch (given & 0x00080080) - { - case 0: - func (stream, "s"); - break; - case 0x80: - func (stream, "d"); - break; - case 0x00080000: - func (stream, "e"); - break; - default: - func (stream, _("<illegal precision>")); - break; - } - break; - case 'Q': - switch (given & 0x00408000) - { - case 0: - func (stream, "s"); - break; - case 0x8000: - func (stream, "d"); - break; - case 0x00400000: - func (stream, "e"); - break; - default: - func (stream, "p"); - break; - } - break; - case 'R': - switch (given & 0x60) - { - case 0: - break; - case 0x20: - func (stream, "p"); - break; - case 0x40: - func (stream, "m"); - break; - default: - func (stream, "z"); - break; - } - break; - case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { @@ -1618,144 +1991,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "%01lx", reg & 0xf); } break; - case 'f': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - if (reg > 7) - func (stream, "#%s", - arm_fp_const[reg & 7]); - else - func (stream, "f%ld", reg); - } - break; - - case 'w': - { - long reg; - - if (bitstart != bitend) - { - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - if (bitend - bitstart == 1) - func (stream, "%s", iwmmxt_wwnames[reg]); - else - func (stream, "%s", iwmmxt_wwssnames[reg]); - } - else - { - reg = (((given >> 8) & 0x1) | - ((given >> 22) & 0x1)); - func (stream, "%s", iwmmxt_wwnames[reg]); - } - } - break; - - case 'g': - { - long reg; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%s", iwmmxt_regnames[reg]); - } - break; - - case 'G': - { - long reg; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%s", iwmmxt_cregnames[reg]); - } - break; - default: abort (); } break; - case 'y': - case 'z': - { - int single = *c == 'y'; - int regno; - - switch (bitstart) - { - case 4: /* Sm pair */ - func (stream, "{"); - /* Fall through. */ - case 0: /* Sm, Dm */ - regno = given & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 5) & 1; - } - break; - - case 1: /* Sd, Dd */ - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - break; - - case 2: /* Sn, Dn */ - regno = (given >> 16) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 7) & 1; - } - break; - - case 3: /* List */ - func (stream, "{"); - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - break; - - - default: - abort (); - } - - func (stream, "%c%d", single ? 's' : 'd', regno); - - if (bitstart == 3) - { - int count = given & 0xff; - - if (single == 0) - count >>= 1; - - if (--count) - { - func (stream, "-%c%d", - single ? 's' : 'd', - regno + count); - } - - func (stream, "}"); - } - else if (bitstart == 4) - func (stream, ", %c%d}", single ? 's' : 'd', - regno + 1); - - break; - } - case '`': c++; if ((given & (1 << bitstart)) == 0) @@ -1778,54 +2018,6 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) } break; - case 'L': - switch (given & 0x00400100) - { - case 0x00000000: func (stream, "b"); break; - case 0x00400000: func (stream, "h"); break; - case 0x00000100: func (stream, "w"); break; - case 0x00400100: func (stream, "d"); break; - default: - break; - } - break; - - case 'Z': - { - int value; - /* given (20, 23) | given (0, 3) */ - value = ((given >> 16) & 0xf0) | (given & 0xf); - func (stream, "%d", value); - } - break; - - case 'l': - /* This is like the 'A' operator, except that if - the width field "M" is zero, then the offset is - *not* multiplied by four. */ - { - int offset = given & 0xff; - int multiplier = (given & 0x00000100) ? 4 : 1; - - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - - if (offset) - { - if ((given & 0x01000000) != 0) - func (stream, ", #%s%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * multiplier, - ((given & 0x00200000) != 0 ? "!" : "")); - else - func (stream, "], #%s%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * multiplier); - } - else - func (stream, "]"); - } - break; - case 'e': { int imm; @@ -2109,6 +2301,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) void *stream = info->stream; fprintf_ftype func = info->fprintf_func; + if (print_insn_coprocessor (info, given, TRUE)) + return; + for (insn = thumb32_opcodes; insn->assembler; insn++) if ((given & insn->mask) == insn->value) { |