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| author | Indu Bhagat <indu.bhagat@oracle.com> | 2024-01-18 11:38:44 -0800 |
|---|---|---|
| committer | Indu Bhagat <indu.bhagat@oracle.com> | 2024-03-28 16:55:50 -0700 |
| commit | eeadfb158b60a7fa4ffa9c21ee87e4ca489e7aa4 (patch) | |
| tree | 73b67738e99809333774332261aeca6bf76c8686 | |
| parent | 6ea6536f01f1f69bc61eb776c3ea6fe1c1b4397f (diff) | |
| download | gdb-users/ibhagat/try-scfi-next.zip gdb-users/ibhagat/try-scfi-next.tar.gz gdb-users/ibhagat/try-scfi-next.tar.bz2 | |
gas: x86: fix code comments and other nitsusers/ibhagat/try-scfi-next
ChangeLog:
* gas/config/tc-i386.c
| -rw-r--r-- | gas/config/tc-i386.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index dbc05c6..5e4b719 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -5552,7 +5552,7 @@ x86_ginsn_addsub_mem_reg (const symbolS *insn_end_sym) } else if (i.mem_operands) { - mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; + mem_reg = i.base_reg ? i.base_reg : i.index_reg; src1_dw2_regnum = ginsn_dw2_regnum (mem_reg); if (i.disp_operands == 1) gdisp = i.op[0].disps->X_add_number; @@ -5681,7 +5681,7 @@ x86_ginsn_move (const symbolS *insn_end_sym) /* mov disp(%reg), %reg. */ if (i.mem_operands) { - src = (i.base_reg) ? i.base_reg : i.index_reg; + src = i.base_reg ? i.base_reg : i.index_reg; if (i.disp_operands == 1) src_disp = i.op[0].disps->X_add_number; src_type = GINSN_SRC_INDIRECT; @@ -5697,7 +5697,7 @@ x86_ginsn_move (const symbolS *insn_end_sym) src = i.op[0].regs; if (i.mem_operands) { - dst = (i.base_reg) ? i.base_reg : i.index_reg; + dst = i.base_reg ? i.base_reg : i.index_reg; if (i.disp_operands == 1) dst_disp = i.op[1].disps->X_add_number; dst_type = GINSN_DST_INDIRECT; @@ -6232,7 +6232,7 @@ x86_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode) gas_assert (!ginsn_link_next (ginsn, ginsn_next)); break; - /* PS: Opcodes 0x80 ... 0x8f with opcode_space SPACE_0F are present + /* PS: JCC Opcodes 0x80 ... 0x8f (opcode_space SPACE_0F) are present only after relaxation. They do not need to be handled for ginsn creation. */ case 0x70 ... 0x7f: @@ -6271,7 +6271,7 @@ x86_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode) /* pop to reg/mem. */ if (i.mem_operands) { - mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; + mem_reg = i.base_reg ? i.base_reg : i.index_reg; /* Use dummy register if no base or index. Unlike other opcodes, ginsns must be generated as this affect stack pointer. */ dw2_regnum = (mem_reg @@ -6357,7 +6357,7 @@ x86_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode) ginsn_set_where (ginsn); if (i.mem_operands) { - mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; + mem_reg = i.base_reg ? i.base_reg : i.index_reg; /* Use dummy register if no base or index. Unlike other opcodes, ginsns must be generated as this affect stack pointer. */ dw2_regnum = (mem_reg |