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authorIan Lance Taylor <ian@airs.com>1995-07-11 18:25:27 +0000
committerIan Lance Taylor <ian@airs.com>1995-07-11 18:25:27 +0000
commit89abbf9d2cc93accbc7296d409075241f4c3bb3e (patch)
treead736cb6db883003862379b1c8d220172eec935d
parente5fa3f23e8dcc946e6588691f3062958d6a23fad (diff)
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Tue Jul 11 14:23:37 1995 Jeff Spiegel <jeffs@lsil.com>
* mips-opc.c (L1): Define. (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid, addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti, and wb. Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com> * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu if ISA 3 and addu otherwise, replacing or, since some MIPS chips have multiple add units but only a single logical unit.
-rw-r--r--opcodes/ChangeLog11
1 files changed, 11 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 000e61a..393e457 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,16 @@
+Tue Jul 11 14:23:37 1995 Jeff Spiegel <jeffs@lsil.com>
+
+ * mips-opc.c (L1): Define.
+ (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid,
+ addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti,
+ and wb.
+
Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com>
+ * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu
+ if ISA 3 and addu otherwise, replacing or, since some MIPS chips
+ have multiple add units but only a single logical unit.
+
* ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3,
shifted by 18, without any insertion or extraction function.
(insert_cr, extract_cr): Remove.