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| author | Alan Modra <amodra@gmail.com> | 2010-05-19 03:44:36 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2010-05-19 03:44:36 +0000 |
| commit | 51b5d4a8c5e50baae29270983b16cfdd49ed7646 (patch) | |
| tree | 58e6a9fdab5b9e3fe24577cecd6a5d0353315f20 | |
| parent | 7982ccdc5ceb58f910f4581b48e1a0db64a8414f (diff) | |
| download | gdb-51b5d4a8c5e50baae29270983b16cfdd49ed7646.zip gdb-51b5d4a8c5e50baae29270983b16cfdd49ed7646.tar.gz gdb-51b5d4a8c5e50baae29270983b16cfdd49ed7646.tar.bz2 | |
* ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 35 |
2 files changed, 24 insertions, 16 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b59dc13..6725e02 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2010-05-19 Alan Modra <amodra@gmail.com> + + * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde, + divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx. + 2010-05-13 Alan Modra <amodra@gmail.com> * ppc-opc.c (powerpc_opcodes): Correct wclr encoding. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index b51da53..0e882e7 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4110,10 +4110,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"divdeu", XO(31,393,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divweu", XO(31,395,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divweu.", XO(31,395,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, +{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, @@ -4131,10 +4131,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}}, -{"divde", XO(31,425,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divde.", XO(31,425,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divwe", XO(31,427,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divwe.", XO(31,427,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, +{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}}, @@ -4681,10 +4681,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divweuo", XO(31,395,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, +{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, @@ -4719,10 +4719,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, -{"divdeo", XO(31,425,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divweo", XO(31,427,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, -{"divweo.", XO(31,427,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, +{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, @@ -4730,6 +4730,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, +{"icswepx", XRC(31,950,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}}, +{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}}, + {"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, {"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, |