diff options
| author | Doug Evans <dje@google.com> | 2009-11-23 04:12:17 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 2009-11-23 04:12:17 +0000 |
| commit | 197fa1aa2ca7f943805196c37031b44f7b87d5a7 (patch) | |
| tree | 2094056b2e6e8bf0319e70b89af8c9c4b2be2b5a | |
| parent | 1fbb9298a46e1bf9eca8fe24027102cf2fcf01fc (diff) | |
| download | gdb-197fa1aa2ca7f943805196c37031b44f7b87d5a7.zip gdb-197fa1aa2ca7f943805196c37031b44f7b87d5a7.tar.gz gdb-197fa1aa2ca7f943805196c37031b44f7b87d5a7.tar.bz2 | |
* cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define.
(EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define.
(EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype
instead of CGEN_INSN_INT.
plus, cgen files: Regenerate.
43 files changed, 1072 insertions, 957 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index 35055a9..9fca0c6 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,13 @@ +2009-11-22 Doug Evans <dje@sebabeach.org> + + * cris/cpuall.h: Regenerate. + * cris/cpuv10.h: Regenerate. + * cris/cpuv32.h: Regenerate. + * cris/decodev10.c: Regenerate. + * cris/decodev10.h: Regenerate. + * cris/decodev32.c: Regenerate. + * cris/decodev32.h: Regenerate. + 2009-11-12 Tristan Gingold <gingold@adacore.com> * avr/interp.c (sim_write): Allow byte access. diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index b5ef6a9..7f3f0e6 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,5 +1,10 @@ 2009-11-22 Doug Evans <dje@sebabeach.org> + * cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define. + (EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define. + (EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype + instead of CGEN_INSN_INT. + * cgen-trace.h (trace_extract): Add cast to fix warning. 2009-11-05 Doug Evans <dje@sebabeach.org> diff --git a/sim/common/cgen-engine.h b/sim/common/cgen-engine.h index 2433104..69f2ef6 100644 --- a/sim/common/cgen-engine.h +++ b/sim/common/cgen-engine.h @@ -17,9 +17,11 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ -/* This file must be included after eng.h and before ${cpu}.h. +/* This file is included by ${cpu}.h. + It needs CGEN_INSN_WORD which is defined by ${cpu}.h. ??? A lot of this could be moved to genmloop.sh to be put in eng.h - and thus remove some conditional compilation. Worth it? */ + and thus remove some conditional compilation. We'd still need + CGEN_INSN_WORD though. */ /* Semantic functions come in six versions on two axes: fast/full-featured, and using one of the simple/scache/compilation engines. @@ -62,12 +64,26 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */ #define EXTRACT_LSB0_UINT(val, total, start, length) \ (((UINT) (val) << ((sizeof (UINT) * 8) - (start) - 1)) \ >> ((sizeof (UINT) * 8) - (length))) + +#define EXTRACT_MSB0_LGSINT(val, total, start, length) \ +(((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (total) + (start))) \ + >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length))) +#define EXTRACT_MSB0_LGUINT(val, total, start, length) \ +(((CGEN_INSN_UINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (total) + (start))) \ + >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length))) + +#define EXTRACT_LSB0_LGSINT(val, total, start, length) \ +(((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (start) - 1)) \ + >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length))) +#define EXTRACT_LSB0_LGUINT(val, total, start, length) \ +(((CGEN_INSN_LGUINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (start) - 1)) \ + >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length))) /* Semantic routines. */ /* Type of the machine generated extraction fns. */ /* ??? No longer used. */ -typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_INT, ARGBUF *); +typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_WORD, ARGBUF *); /* Type of the machine generated semantic fns. */ @@ -89,9 +105,9 @@ typedef unsigned int SEM_STATUS; /* Instruction fields are extracted by the semantic routine. ??? TODO: multi word insns. */ #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE -typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_INT); +typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_WORD); #else -typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_INT); +typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_WORD); #endif #endif diff --git a/sim/cris/cpuall.h b/sim/cris/cpuall.h index fabbdb2..237594a 100644 --- a/sim/cris/cpuall.h +++ b/sim/cris/cpuall.h @@ -29,35 +29,30 @@ This file is part of the GNU simulators. #ifdef WANT_CPU_CRISV0F #include "engv0.h" -#include "cgen-engine.h" #include "cpuv0.h" #include "decodev0.h" #endif #ifdef WANT_CPU_CRISV3F #include "engv3.h" -#include "cgen-engine.h" #include "cpuv3.h" #include "decodev3.h" #endif #ifdef WANT_CPU_CRISV8F #include "engv8.h" -#include "cgen-engine.h" #include "cpuv8.h" #include "decodev8.h" #endif #ifdef WANT_CPU_CRISV10F #include "engv10.h" -#include "cgen-engine.h" #include "cpuv10.h" #include "decodev10.h" #endif #ifdef WANT_CPU_CRISV32F #include "engv32.h" -#include "cgen-engine.h" #include "cpuv32.h" #include "decodev32.h" #endif diff --git a/sim/cris/cpuv10.h b/sim/cris/cpuv10.h index 03a1be3..d4d7528 100644 --- a/sim/cris/cpuv10.h +++ b/sim/cris/cpuv10.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/cris/cpuv32.h b/sim/cris/cpuv32.h index 9c575f1..421a5ce 100644 --- a/sim/cris/cpuv32.h +++ b/sim/cris/cpuv32.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/cris/decodev10.c b/sim/cris/decodev10.c index 362e8f0..516bb48 100644 --- a/sim/cris/decodev10.c +++ b/sim/cris/decodev10.c @@ -316,14 +316,14 @@ crisv10f_init_idesc_table (SIM_CPU *cpu) const IDESC * crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, + CGEN_INSN_WORD base_insn, ARGBUF *abuf) { /* Result of decoder. */ CRISV10F_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 4) & (255 << 0))); @@ -2413,7 +2413,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -2441,7 +2441,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_d_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -2469,7 +2469,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movepcr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_moveq.f UINT f_operand2; @@ -2493,7 +2493,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_moveq: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_moveq.f UINT f_operand2; INT f_s6; @@ -2520,7 +2520,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movs_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -2548,7 +2548,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movecbr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcbr.f INT f_indir_pc__byte; UINT f_operand2; @@ -2578,7 +2578,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movecwr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcwr.f INT f_indir_pc__word; UINT f_operand2; @@ -2608,7 +2608,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movecdr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cd.f INT f_indir_pc__dword; UINT f_operand2; @@ -2638,7 +2638,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movscbr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f UINT f_operand2; INT f_indir_pc__byte; @@ -2668,7 +2668,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movscwr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f UINT f_operand2; INT f_indir_pc__word; @@ -2698,7 +2698,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movucbr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f UINT f_operand2; INT f_indir_pc__byte; @@ -2728,7 +2728,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movucwr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f UINT f_operand2; INT f_indir_pc__word; @@ -2758,7 +2758,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addq: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addq.f UINT f_operand2; UINT f_u6; @@ -2786,7 +2786,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp_r_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -2814,7 +2814,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -2846,7 +2846,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -2878,7 +2878,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp_m_d_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -2910,7 +2910,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpcbr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f INT f_indir_pc__byte; UINT f_operand2; @@ -2940,7 +2940,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpcwr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f INT f_indir_pc__word; UINT f_operand2; @@ -2970,7 +2970,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpcdr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cd.f INT f_indir_pc__dword; UINT f_operand2; @@ -3000,7 +3000,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpq: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_andq.f UINT f_operand2; INT f_s6; @@ -3027,7 +3027,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpucbr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f INT f_indir_pc__byte; UINT f_operand2; @@ -3057,7 +3057,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpucwr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f INT f_indir_pc__word; UINT f_operand2; @@ -3087,7 +3087,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3119,7 +3119,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3151,7 +3151,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_d_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3183,7 +3183,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movs_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3215,7 +3215,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movs_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3247,7 +3247,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_sprv10: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f UINT f_operand2; UINT f_operand1; @@ -3275,7 +3275,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_spr_rv10: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f UINT f_operand2; UINT f_operand1; @@ -3303,7 +3303,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ret_type: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f UINT f_operand2; @@ -3327,7 +3327,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_sprv10: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f UINT f_operand2; UINT f_memmode; @@ -3359,7 +3359,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_c_sprv10_p5: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f UINT f_operand2; INT f_indir_pc__word; @@ -3389,7 +3389,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_c_sprv10_p9: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; UINT f_operand2; @@ -3419,7 +3419,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_spr_mv10: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f UINT f_operand2; UINT f_memmode; @@ -3464,7 +3464,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movem_r_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_movem_r_m.f UINT f_operand2; UINT f_memmode; @@ -3512,7 +3512,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movem_m_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_movem_m_r.f UINT f_operand2; UINT f_memmode; @@ -3559,7 +3559,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movem_m_pc: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_movem_m_r.f UINT f_memmode; UINT f_operand1; @@ -3602,7 +3602,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -3631,7 +3631,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_d_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -3660,7 +3660,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3693,7 +3693,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3726,7 +3726,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_m_d_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3759,7 +3759,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addcbr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcbr.f INT f_indir_pc__byte; UINT f_operand2; @@ -3790,7 +3790,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addcwr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcwr.f INT f_indir_pc__word; UINT f_operand2; @@ -3821,7 +3821,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addcdr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcdr.f INT f_indir_pc__dword; UINT f_operand2; @@ -3852,7 +3852,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addcpc: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; /* Contents of trailing part of insn. */ @@ -3878,7 +3878,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_adds_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3911,7 +3911,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_adds_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3944,7 +3944,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addscbr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcbr.f INT f_indir_pc__byte; UINT f_operand2; @@ -3975,7 +3975,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addscwr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcwr.f INT f_indir_pc__word; UINT f_operand2; @@ -4025,7 +4025,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_operand1; @@ -4054,7 +4054,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_neg_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -4082,7 +4082,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_neg_d_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -4110,7 +4110,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_test_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f UINT f_memmode; UINT f_operand1; @@ -4138,7 +4138,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_test_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f UINT f_memmode; UINT f_operand1; @@ -4166,7 +4166,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_test_m_d_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f UINT f_memmode; UINT f_operand1; @@ -4194,7 +4194,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -4226,7 +4226,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -4258,7 +4258,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_m_d_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -4290,7 +4290,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_muls_b: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -4320,7 +4320,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mstep: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -4349,7 +4349,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_dstep: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -4378,7 +4378,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -4407,7 +4407,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_d_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -4436,7 +4436,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -4469,7 +4469,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -4502,7 +4502,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_m_d_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -4535,7 +4535,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andcbr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcbr.f INT f_indir_pc__byte; UINT f_operand2; @@ -4566,7 +4566,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andcwr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcwr.f INT f_indir_pc__word; UINT f_operand2; @@ -4597,7 +4597,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andcdr: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcdr.f INT f_indir_pc__dword; UINT f_operand2; @@ -4628,7 +4628,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andq: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_andq.f UINT f_operand2; INT f_s6; @@ -4656,7 +4656,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_swap: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f UINT f_operand2; UINT f_operand1; @@ -4684,7 +4684,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_asrq: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_asrq.f UINT f_operand2; UINT f_u5; @@ -4712,7 +4712,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lsrr_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -4741,7 +4741,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lsrr_d_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -4770,7 +4770,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btst: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -4798,7 +4798,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btstq: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_asrq.f UINT f_operand2; UINT f_u5; @@ -4825,7 +4825,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setf: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_setf.f UINT f_operand2; UINT f_operand1; @@ -4846,7 +4846,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcc_b: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bcc_b.f UINT f_operand2; UINT f_disp9_lo; @@ -4882,7 +4882,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ba_b: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bcc_b.f UINT f_disp9_lo; INT f_disp9_hi; @@ -4915,7 +4915,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcc_w: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bcc_w.f SI f_indir_pc__word_pcrel; UINT f_operand2; @@ -4944,7 +4944,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ba_w: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bcc_w.f SI f_indir_pc__word_pcrel; /* Contents of trailing part of insn. */ @@ -4970,7 +4970,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jump_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f UINT f_operand2; UINT f_operand1; @@ -4998,7 +4998,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jump_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f UINT f_operand2; UINT f_memmode; @@ -5030,7 +5030,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jump_c: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; UINT f_operand2; @@ -5060,7 +5060,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_break: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_break.f UINT f_u4; @@ -5083,7 +5083,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -5116,7 +5116,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -5149,7 +5149,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_m_d_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -5182,7 +5182,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_cb: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f INT f_indir_pc__byte; UINT f_operand2; @@ -5213,7 +5213,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_cw: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f INT f_indir_pc__word; UINT f_operand2; @@ -5244,7 +5244,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_cd: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cd.f INT f_indir_pc__dword; UINT f_operand2; @@ -5275,7 +5275,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_scc: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f UINT f_operand2; UINT f_operand1; @@ -5302,7 +5302,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addoq: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addoq.f UINT f_operand2; INT f_s8; @@ -5329,7 +5329,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bdapqpc: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addoq.f INT f_s8; @@ -5352,7 +5352,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bdap_32_pc: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; /* Contents of trailing part of insn. */ @@ -5378,7 +5378,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_pcplus_p0: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f UINT f_memmode; @@ -5401,7 +5401,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_spplus_p8: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f UINT f_memmode; @@ -5426,7 +5426,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_m_b_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -5458,7 +5458,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_m_w_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -5490,7 +5490,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_m_d_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -5522,7 +5522,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_cb: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f INT f_indir_pc__byte; UINT f_operand2; @@ -5552,7 +5552,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_cw: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f INT f_indir_pc__word; UINT f_operand2; @@ -5582,7 +5582,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_cd: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cd.f INT f_indir_pc__dword; UINT f_operand2; @@ -5612,7 +5612,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_dip_m: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f UINT f_memmode; UINT f_operand1; @@ -5640,7 +5640,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_dip_c: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f INT f_indir_pc__dword; /* Contents of trailing part of insn. */ @@ -5660,7 +5660,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi_acr_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_b_r.f UINT f_operand2; UINT f_operand1; @@ -5688,7 +5688,7 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_biap_pc_b_r: { const IDESC *idesc = &crisv10f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addoq.f UINT f_operand2; diff --git a/sim/cris/decodev10.h b/sim/cris/decodev10.h index 11c11fa..8c0f745 100644 --- a/sim/cris/decodev10.h +++ b/sim/cris/decodev10.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define CRISV10F_DECODE_H extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, + CGEN_INSN_WORD, ARGBUF *); extern void crisv10f_init_idesc_table (SIM_CPU *); extern void crisv10f_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/cris/decodev32.c b/sim/cris/decodev32.c index c2ee3a5..5e580d9 100644 --- a/sim/cris/decodev32.c +++ b/sim/cris/decodev32.c @@ -320,14 +320,14 @@ crisv32f_init_idesc_table (SIM_CPU *cpu) const IDESC * crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, + CGEN_INSN_WORD base_insn, ARGBUF *abuf) { /* Result of decoder. */ CRISV32F_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 4) & (255 << 0))); @@ -1923,7 +1923,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -1951,7 +1951,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_d_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -1979,7 +1979,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_moveq: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_moveq.f UINT f_operand2; INT f_s6; @@ -2006,7 +2006,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movs_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -2034,7 +2034,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movecbr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcbr.f INT f_indir_pc__byte; UINT f_operand2; @@ -2064,7 +2064,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movecwr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcwr.f INT f_indir_pc__word; UINT f_operand2; @@ -2094,7 +2094,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movecdr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cd.f INT f_indir_pc__dword; UINT f_operand2; @@ -2124,7 +2124,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movscbr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f UINT f_operand2; INT f_indir_pc__byte; @@ -2154,7 +2154,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movscwr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f UINT f_operand2; INT f_indir_pc__word; @@ -2184,7 +2184,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movucbr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f UINT f_operand2; INT f_indir_pc__byte; @@ -2214,7 +2214,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movucwr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f UINT f_operand2; INT f_indir_pc__word; @@ -2244,7 +2244,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addq: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addq.f UINT f_operand2; UINT f_u6; @@ -2272,7 +2272,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp_r_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -2300,7 +2300,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -2332,7 +2332,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -2364,7 +2364,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp_m_d_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -2396,7 +2396,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpcbr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f INT f_indir_pc__byte; UINT f_operand2; @@ -2426,7 +2426,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpcwr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f INT f_indir_pc__word; UINT f_operand2; @@ -2456,7 +2456,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpcdr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cd.f INT f_indir_pc__dword; UINT f_operand2; @@ -2486,7 +2486,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpq: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_andq.f UINT f_operand2; INT f_s6; @@ -2513,7 +2513,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpucbr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f INT f_indir_pc__byte; UINT f_operand2; @@ -2543,7 +2543,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpucwr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f INT f_indir_pc__word; UINT f_operand2; @@ -2573,7 +2573,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -2605,7 +2605,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -2637,7 +2637,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_d_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -2669,7 +2669,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movs_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -2701,7 +2701,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movs_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -2733,7 +2733,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_sprv32: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f UINT f_operand2; UINT f_operand1; @@ -2761,7 +2761,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_spr_rv32: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_mcp.f UINT f_operand2; UINT f_operand1; @@ -2789,7 +2789,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_m_sprv32: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f UINT f_operand2; UINT f_memmode; @@ -2821,7 +2821,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_c_sprv32_p2: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f INT f_indir_pc__dword; UINT f_operand2; @@ -2851,7 +2851,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_spr_mv32: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f UINT f_operand2; UINT f_memmode; @@ -2883,7 +2883,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_ss_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f UINT f_operand2; UINT f_operand1; @@ -2910,7 +2910,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_ss: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_mcp.f UINT f_operand2; UINT f_operand1; @@ -2937,7 +2937,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movem_r_m_v32: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f UINT f_operand2; UINT f_memmode; @@ -2985,7 +2985,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movem_m_r_v32: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f UINT f_operand2; UINT f_memmode; @@ -3033,7 +3033,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -3062,7 +3062,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_d_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -3091,7 +3091,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3124,7 +3124,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3157,7 +3157,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_m_d_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3190,7 +3190,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addcbr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcbr.f INT f_indir_pc__byte; UINT f_operand2; @@ -3221,7 +3221,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addcwr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcwr.f INT f_indir_pc__word; UINT f_operand2; @@ -3252,7 +3252,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addcdr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcdr.f INT f_indir_pc__dword; UINT f_operand2; @@ -3283,7 +3283,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_adds_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3316,7 +3316,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_adds_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3349,7 +3349,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addscbr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcbr.f INT f_indir_pc__byte; UINT f_operand2; @@ -3380,7 +3380,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addscwr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcwr.f INT f_indir_pc__word; UINT f_operand2; @@ -3411,7 +3411,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addc_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -3444,7 +3444,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lapc_d: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_lapc_d.f SI f_indir_pc__dword_pcrel; UINT f_operand2; @@ -3474,7 +3474,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lapcq: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_lapcq.f UINT f_operand2; SI f_qo; @@ -3501,7 +3501,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -3530,7 +3530,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_neg_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -3558,7 +3558,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_neg_d_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -3586,7 +3586,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_test_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f UINT f_memmode; UINT f_operand1; @@ -3614,7 +3614,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_test_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f UINT f_memmode; UINT f_operand1; @@ -3642,7 +3642,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_test_m_d_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f UINT f_memmode; UINT f_operand1; @@ -3670,7 +3670,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -3702,7 +3702,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -3734,7 +3734,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_move_r_m_d_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -3766,7 +3766,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_muls_b: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -3796,7 +3796,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mcp: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_mcp.f UINT f_operand2; UINT f_operand1; @@ -3825,7 +3825,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_dstep: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -3854,7 +3854,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -3883,7 +3883,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_d_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -3912,7 +3912,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3945,7 +3945,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -3978,7 +3978,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_m_d_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_add_m_b_m.f UINT f_operand2; UINT f_memmode; @@ -4011,7 +4011,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andcbr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcbr.f INT f_indir_pc__byte; UINT f_operand2; @@ -4042,7 +4042,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andcwr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcwr.f INT f_indir_pc__word; UINT f_operand2; @@ -4073,7 +4073,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andcdr: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addcdr.f INT f_indir_pc__dword; UINT f_operand2; @@ -4104,7 +4104,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andq: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_andq.f UINT f_operand2; INT f_s6; @@ -4132,7 +4132,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_swap: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f UINT f_operand2; UINT f_operand1; @@ -4160,7 +4160,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_asrq: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_asrq.f UINT f_operand2; UINT f_u5; @@ -4188,7 +4188,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lsrr_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -4217,7 +4217,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lsrr_d_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_operand1; @@ -4246,7 +4246,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btst: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -4274,7 +4274,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btstq: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_asrq.f UINT f_operand2; UINT f_u5; @@ -4301,7 +4301,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setf: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_setf.f UINT f_operand2; UINT f_operand1; @@ -4423,7 +4423,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcc_b: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bcc_b.f UINT f_operand2; UINT f_disp9_lo; @@ -4459,7 +4459,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ba_b: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bcc_b.f UINT f_disp9_lo; INT f_disp9_hi; @@ -4492,7 +4492,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcc_w: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bcc_w.f SI f_indir_pc__word_pcrel; UINT f_operand2; @@ -4521,7 +4521,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ba_w: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bcc_w.f SI f_indir_pc__word_pcrel; /* Contents of trailing part of insn. */ @@ -4547,7 +4547,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jas_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f UINT f_operand2; UINT f_operand1; @@ -4575,7 +4575,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jas_c: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f INT f_indir_pc__dword; UINT f_operand2; @@ -4605,7 +4605,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jump_p: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_mcp.f UINT f_operand2; @@ -4629,7 +4629,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bas_c: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bas_c.f SI f_indir_pc__dword_pcrel; UINT f_operand2; @@ -4659,7 +4659,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jasc_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f UINT f_operand2; UINT f_operand1; @@ -4687,7 +4687,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_break: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_break.f UINT f_u4; @@ -4710,7 +4710,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_cb: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f INT f_indir_pc__byte; UINT f_operand2; @@ -4741,7 +4741,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_cw: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f INT f_indir_pc__word; UINT f_operand2; @@ -4772,7 +4772,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bound_cd: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cd.f INT f_indir_pc__dword; UINT f_operand2; @@ -4803,7 +4803,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_scc: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f UINT f_operand2; UINT f_operand1; @@ -4830,7 +4830,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addoq: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addoq.f UINT f_operand2; INT f_s8; @@ -4857,7 +4857,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_m_b_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -4889,7 +4889,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_m_w_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -4921,7 +4921,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_m_d_m: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_addc_m.f UINT f_operand2; UINT f_memmode; @@ -4953,7 +4953,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_cb: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cb.f INT f_indir_pc__byte; UINT f_operand2; @@ -4983,7 +4983,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_cw: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cw.f INT f_indir_pc__word; UINT f_operand2; @@ -5013,7 +5013,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addo_cd: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_bound_cd.f INT f_indir_pc__dword; UINT f_operand2; @@ -5043,7 +5043,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi_acr_b_r: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_muls_b.f UINT f_operand2; UINT f_operand1; @@ -5071,7 +5071,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fidxi: { const IDESC *idesc = &crisv32f_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; #define FLD(f) abuf->fields.sfmt_mcp.f UINT f_operand1; diff --git a/sim/cris/decodev32.h b/sim/cris/decodev32.h index 78a90e2..6eac53e 100644 --- a/sim/cris/decodev32.h +++ b/sim/cris/decodev32.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define CRISV32F_DECODE_H extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, + CGEN_INSN_WORD, ARGBUF *); extern void crisv32f_init_idesc_table (SIM_CPU *); extern void crisv32f_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog index d8e1647..0f429e2 100644 --- a/sim/frv/ChangeLog +++ b/sim/frv/ChangeLog @@ -1,3 +1,10 @@ +2009-11-22 Doug Evans <dje@sebabeach.org> + + * cpu.h: Regenerate. + * cpuall.h: Regenerate. + * decode.c: Regenerate. + * decode.h: Regenerate. + 2009-11-03 Doug Evans <dje@sebabeach.org> * arch.c: Regenerate. diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h index d54a996..17552d1 100644 --- a/sim/frv/cpu.h +++ b/sim/frv/cpu.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 8 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/frv/cpuall.h b/sim/frv/cpuall.h index b1b9ba6..0adce34 100644 --- a/sim/frv/cpuall.h +++ b/sim/frv/cpuall.h @@ -29,7 +29,6 @@ This file is part of the GNU simulators. #ifdef WANT_CPU_FRVBF #include "eng.h" -#include "cgen-engine.h" #include "cpu.h" #include "decode.h" #endif diff --git a/sim/frv/decode.c b/sim/frv/decode.c index e75218d..271ee2a 100644 --- a/sim/frv/decode.c +++ b/sim/frv/decode.c @@ -855,14 +855,14 @@ frvbf_init_idesc_table (SIM_CPU *cpu) const IDESC * frvbf_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ FRVBF_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 18) & (127 << 0))); @@ -3263,7 +3263,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addcc.f UINT f_GRk; UINT f_GRi; @@ -3295,7 +3295,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_not: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_scutss.f UINT f_GRk; UINT f_GRj; @@ -3323,7 +3323,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sdiv: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addcc.f UINT f_GRk; UINT f_GRi; @@ -3355,7 +3355,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_smul: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smulcc.f UINT f_GRk; UINT f_GRi; @@ -3387,7 +3387,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_smu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smass.f UINT f_GRi; UINT f_GRj; @@ -3416,7 +3416,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_smass: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smass.f UINT f_GRi; UINT f_GRj; @@ -3446,7 +3446,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_scutss: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_scutss.f UINT f_GRk; UINT f_GRj; @@ -3475,7 +3475,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cadd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_GRi; @@ -3514,7 +3514,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cnot: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_CCi; @@ -3549,7 +3549,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_csmul: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddu.f UINT f_GRk; UINT f_GRi; @@ -3588,7 +3588,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_csdiv: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_GRi; @@ -3627,7 +3627,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addcc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addcc.f UINT f_GRk; UINT f_GRi; @@ -3664,7 +3664,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andcc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addcc.f UINT f_GRk; UINT f_GRi; @@ -3701,7 +3701,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_smulcc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smulcc.f UINT f_GRk; UINT f_GRi; @@ -3738,7 +3738,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_caddcc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_caddcc.f UINT f_GRk; UINT f_GRi; @@ -3779,7 +3779,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_csmulcc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_csmulcc.f UINT f_GRk; UINT f_GRi; @@ -3820,7 +3820,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addx: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addcc.f UINT f_GRk; UINT f_GRi; @@ -3856,7 +3856,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_swapi.f UINT f_GRk; UINT f_GRi; @@ -3887,7 +3887,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sdivi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_swapi.f UINT f_GRk; UINT f_GRi; @@ -3918,7 +3918,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_smuli: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smuli.f UINT f_GRk; UINT f_GRi; @@ -3949,7 +3949,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addicc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addicc.f UINT f_GRk; UINT f_GRi; @@ -3985,7 +3985,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andicc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addicc.f UINT f_GRk; UINT f_GRi; @@ -4021,7 +4021,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_smulicc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smulicc.f UINT f_GRk; UINT f_GRi; @@ -4057,7 +4057,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addxi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addicc.f UINT f_GRk; UINT f_GRi; @@ -4092,7 +4092,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpb: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smulcc.f UINT f_GRi; UINT f_ICCi_1; @@ -4124,7 +4124,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setlo: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_setlo.f UINT f_GRk; UINT f_u16; @@ -4151,7 +4151,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sethi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_sethi.f UINT f_GRk; UINT f_u16; @@ -4178,7 +4178,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setlos: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_setlos.f UINT f_GRk; INT f_s16; @@ -4205,7 +4205,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldsb: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addcc.f UINT f_GRk; UINT f_GRi; @@ -4237,7 +4237,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldbf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldbfu.f UINT f_FRk; UINT f_GRi; @@ -4269,7 +4269,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ldcu.f UINT f_CPRk; UINT f_GRi; @@ -4301,7 +4301,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldsb: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addcc.f UINT f_GRk; UINT f_GRi; @@ -4333,7 +4333,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldbf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldbfu.f UINT f_FRk; UINT f_GRi; @@ -4365,7 +4365,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smulcc.f UINT f_GRk; UINT f_GRi; @@ -4397,7 +4397,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lddf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddfu.f UINT f_FRk; UINT f_GRi; @@ -4429,7 +4429,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lddc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_lddcu.f UINT f_CPRk; UINT f_GRi; @@ -4461,7 +4461,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smulcc.f UINT f_GRk; UINT f_GRi; @@ -4493,7 +4493,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nlddf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddfu.f UINT f_FRk; UINT f_GRi; @@ -4525,7 +4525,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smulcc.f UINT f_GRk; UINT f_GRi; @@ -4556,7 +4556,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldqf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdfu.f UINT f_FRk; UINT f_GRi; @@ -4587,7 +4587,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldqc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdcu.f UINT f_CPRk; UINT f_GRi; @@ -4618,7 +4618,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smulcc.f UINT f_GRk; UINT f_GRi; @@ -4649,7 +4649,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldqf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdfu.f UINT f_FRk; UINT f_GRi; @@ -4680,7 +4680,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldsbu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldsbu.f UINT f_GRk; UINT f_GRi; @@ -4713,7 +4713,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldsbu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldsbu.f UINT f_GRk; UINT f_GRi; @@ -4746,7 +4746,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldbfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldbfu.f UINT f_FRk; UINT f_GRi; @@ -4779,7 +4779,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldcu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ldcu.f UINT f_CPRk; UINT f_GRi; @@ -4812,7 +4812,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldbfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldbfu.f UINT f_FRk; UINT f_GRi; @@ -4845,7 +4845,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lddu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddu.f UINT f_GRk; UINT f_GRi; @@ -4878,7 +4878,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nlddu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddu.f UINT f_GRk; UINT f_GRi; @@ -4911,7 +4911,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lddfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddfu.f UINT f_FRk; UINT f_GRi; @@ -4944,7 +4944,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lddcu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_lddcu.f UINT f_CPRk; UINT f_GRi; @@ -4977,7 +4977,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nlddfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddfu.f UINT f_FRk; UINT f_GRi; @@ -5010,7 +5010,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldqu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdu.f UINT f_GRk; UINT f_GRi; @@ -5042,7 +5042,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldqu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdu.f UINT f_GRk; UINT f_GRi; @@ -5074,7 +5074,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldqfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdfu.f UINT f_FRk; UINT f_GRi; @@ -5106,7 +5106,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldqcu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdcu.f UINT f_CPRk; UINT f_GRi; @@ -5138,7 +5138,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldqfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdfu.f UINT f_FRk; UINT f_GRi; @@ -5170,7 +5170,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldsbi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_swapi.f UINT f_GRk; UINT f_GRi; @@ -5201,7 +5201,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldbfi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ldbfi.f UINT f_FRk; UINT f_GRi; @@ -5232,7 +5232,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldsbi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_swapi.f UINT f_GRk; UINT f_GRi; @@ -5263,7 +5263,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldbfi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ldbfi.f UINT f_FRk; UINT f_GRi; @@ -5294,7 +5294,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lddi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smuli.f UINT f_GRk; UINT f_GRi; @@ -5325,7 +5325,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lddfi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_lddfi.f UINT f_FRk; UINT f_GRi; @@ -5356,7 +5356,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nlddi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_smuli.f UINT f_GRk; UINT f_GRi; @@ -5387,7 +5387,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nlddfi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_lddfi.f UINT f_FRk; UINT f_GRi; @@ -5418,7 +5418,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldqi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdi.f UINT f_GRk; UINT f_GRi; @@ -5448,7 +5448,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldqfi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdfi.f UINT f_FRk; UINT f_GRi; @@ -5478,7 +5478,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nldqfi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdfi.f UINT f_FRk; UINT f_GRi; @@ -5508,7 +5508,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_GRi; @@ -5540,7 +5540,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stbf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstbfu.f UINT f_FRk; UINT f_GRi; @@ -5572,7 +5572,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stcu.f UINT f_CPRk; UINT f_GRi; @@ -5604,7 +5604,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_std: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdu.f UINT f_GRk; UINT f_GRi; @@ -5636,7 +5636,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stdf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdfu.f UINT f_FRk; UINT f_GRi; @@ -5668,7 +5668,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stdc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdcu.f UINT f_CPRk; UINT f_GRi; @@ -5700,7 +5700,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stbu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstbu.f UINT f_GRk; UINT f_GRi; @@ -5733,7 +5733,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stbfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstbfu.f UINT f_FRk; UINT f_GRi; @@ -5766,7 +5766,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stcu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stcu.f UINT f_CPRk; UINT f_GRi; @@ -5799,7 +5799,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stdu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdu.f UINT f_GRk; UINT f_GRi; @@ -5832,7 +5832,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stdfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdfu.f UINT f_FRk; UINT f_GRi; @@ -5865,7 +5865,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stdcu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdcu.f UINT f_CPRk; UINT f_GRi; @@ -5898,7 +5898,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stqu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdu.f UINT f_GRk; UINT f_GRi; @@ -5930,7 +5930,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cldsb: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_GRi; @@ -5969,7 +5969,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cldbf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldbfu.f UINT f_FRk; UINT f_GRi; @@ -6008,7 +6008,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cldd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddu.f UINT f_GRk; UINT f_GRi; @@ -6047,7 +6047,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clddf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddfu.f UINT f_FRk; UINT f_GRi; @@ -6086,7 +6086,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cldq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_GRi; @@ -6124,7 +6124,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cldsbu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldsbu.f UINT f_GRk; UINT f_GRi; @@ -6164,7 +6164,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cldbfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cldbfu.f UINT f_FRk; UINT f_GRi; @@ -6204,7 +6204,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clddu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddu.f UINT f_GRk; UINT f_GRi; @@ -6244,7 +6244,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clddfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clddfu.f UINT f_FRk; UINT f_GRi; @@ -6284,7 +6284,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cldqu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdu.f UINT f_GRk; UINT f_GRi; @@ -6323,7 +6323,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cstb: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_GRi; @@ -6362,7 +6362,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cstbf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstbfu.f UINT f_FRk; UINT f_GRi; @@ -6401,7 +6401,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cstd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdu.f UINT f_GRk; UINT f_GRi; @@ -6440,7 +6440,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cstdf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdfu.f UINT f_FRk; UINT f_GRi; @@ -6479,7 +6479,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cstbu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstbu.f UINT f_GRk; UINT f_GRi; @@ -6519,7 +6519,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cstbfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstbfu.f UINT f_FRk; UINT f_GRi; @@ -6559,7 +6559,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cstdu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdu.f UINT f_GRk; UINT f_GRi; @@ -6599,7 +6599,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cstdfu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cstdfu.f UINT f_FRk; UINT f_GRi; @@ -6639,7 +6639,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stbi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_swapi.f UINT f_GRk; UINT f_GRi; @@ -6670,7 +6670,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stbfi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stbfi.f UINT f_FRk; UINT f_GRi; @@ -6701,7 +6701,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stdi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdi.f UINT f_GRk; UINT f_GRi; @@ -6732,7 +6732,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stdfi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_stdfi.f UINT f_FRk; UINT f_GRi; @@ -6763,7 +6763,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_swap: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_GRi; @@ -6796,7 +6796,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_swapi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_swapi.f UINT f_GRk; UINT f_GRi; @@ -6828,7 +6828,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cswap: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cswap.f UINT f_GRk; UINT f_GRi; @@ -6868,7 +6868,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movgf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmovgfd.f UINT f_FRk; UINT f_GRj; @@ -6896,7 +6896,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movfg: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmovfgd.f UINT f_FRk; UINT f_GRj; @@ -6924,7 +6924,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movgfd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmovgfd.f UINT f_FRk; UINT f_GRj; @@ -6954,7 +6954,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movfgd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmovfgd.f UINT f_FRk; UINT f_GRj; @@ -6984,7 +6984,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movgfq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movgfq.f UINT f_FRk; UINT f_GRj; @@ -7018,7 +7018,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movfgq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movfgq.f UINT f_FRk; UINT f_GRj; @@ -7052,7 +7052,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmovgf: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmovgfd.f UINT f_FRk; UINT f_CCi; @@ -7087,7 +7087,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmovfg: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmovfgd.f UINT f_FRk; UINT f_CCi; @@ -7122,7 +7122,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmovgfd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmovgfd.f UINT f_FRk; UINT f_CCi; @@ -7159,7 +7159,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmovfgd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmovfgd.f UINT f_FRk; UINT f_CCi; @@ -7196,7 +7196,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movgs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movgs.f UINT f_spr_h; UINT f_spr_l; @@ -7230,7 +7230,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movsg: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movsg.f UINT f_spr_h; UINT f_spr_l; @@ -7264,7 +7264,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fbne.f UINT f_hint; SI f_label16; @@ -7290,7 +7290,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bno: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fbne.f UINT f_hint; SI f_label16; @@ -7310,7 +7310,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_ICCi_2; UINT f_hint; @@ -7340,7 +7340,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fbne: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fbne.f UINT f_FCCi_2; UINT f_hint; @@ -7370,7 +7370,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bctrlr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fcbeqlr.f UINT f_hint; UINT f_ccond; @@ -7399,7 +7399,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bralr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fcbeqlr.f UINT f_hint; @@ -7423,7 +7423,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bnolr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fcbeqlr.f UINT f_hint; @@ -7447,7 +7447,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beqlr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bceqlr.f UINT f_ICCi_2; UINT f_hint; @@ -7475,7 +7475,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fbeqlr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fcbeqlr.f UINT f_FCCi_2; UINT f_hint; @@ -7503,7 +7503,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcralr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fcbeqlr.f UINT f_hint; UINT f_ccond; @@ -7532,7 +7532,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcnolr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fcbeqlr.f UINT f_hint; @@ -7558,7 +7558,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bceqlr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bceqlr.f UINT f_ICCi_2; UINT f_hint; @@ -7591,7 +7591,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcbeqlr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fcbeqlr.f UINT f_FCCi_2; UINT f_hint; @@ -7624,7 +7624,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jmpl: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cjmpl.f UINT f_LI; UINT f_GRi; @@ -7655,7 +7655,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jmpil: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jmpil.f UINT f_LI; UINT f_GRi; @@ -7685,7 +7685,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_call: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_call.f INT f_labelH6; UINT f_labelL18; @@ -7714,7 +7714,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_rett: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_rett.f UINT f_debug; @@ -7750,7 +7750,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_tra: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ftne.f UINT f_GRi; UINT f_GRj; @@ -7783,7 +7783,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_teq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_teq.f UINT f_ICCi_2; UINT f_GRi; @@ -7820,7 +7820,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ftne: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ftne.f UINT f_FCCi_2; UINT f_GRi; @@ -7857,7 +7857,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_tira: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ftine.f UINT f_GRi; INT f_d12; @@ -7889,7 +7889,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_tieq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_tieq.f UINT f_ICCi_2; UINT f_GRi; @@ -7925,7 +7925,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ftine: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ftine.f UINT f_FCCi_2; UINT f_GRi; @@ -7981,7 +7981,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andcr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_andcr.f UINT f_CRk; UINT f_CRi; @@ -8013,7 +8013,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_notcr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_andcr.f UINT f_CRk; UINT f_CRj; @@ -8041,7 +8041,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ckra: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cckeq.f SI f_CRj_int; @@ -8065,7 +8065,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ckeq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cckeq.f SI f_CRj_int; UINT f_ICCi_3; @@ -8093,7 +8093,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fckra: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfckne.f UINT f_CRj_float; @@ -8117,7 +8117,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fckne: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfckne.f UINT f_CRj_float; UINT f_FCCi_3; @@ -8145,7 +8145,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cckra: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cckeq.f SI f_CRj_int; UINT f_CCi; @@ -8176,7 +8176,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cckeq: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cckeq.f SI f_CRj_int; UINT f_CCi; @@ -8211,7 +8211,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfckra: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfckne.f UINT f_CRj_float; UINT f_CCi; @@ -8242,7 +8242,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfckne: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfckne.f UINT f_CRj_float; UINT f_CCi; @@ -8277,7 +8277,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cjmpl: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cjmpl.f UINT f_LI; UINT f_GRi; @@ -8315,7 +8315,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ici: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_icpl.f UINT f_GRi; UINT f_GRj; @@ -8343,7 +8343,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_icei: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_icei.f UINT f_ae; UINT f_GRi; @@ -8374,7 +8374,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_icpl: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_icpl.f UINT f_lock; UINT f_GRi; @@ -8405,7 +8405,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_icul: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jmpil.f UINT f_GRi; @@ -8429,7 +8429,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clrgr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_swapi.f UINT f_GRk; @@ -8453,7 +8453,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clrfr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; @@ -8477,7 +8477,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_commitgr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_setlos.f UINT f_GRk; @@ -8494,7 +8494,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_commitfr: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mhsethis.f UINT f_FRk; @@ -8511,7 +8511,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fitos: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fditos.f UINT f_FRk; UINT f_FRj; @@ -8539,7 +8539,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fstoi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fdstoi.f UINT f_FRk; UINT f_FRj; @@ -8567,7 +8567,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fitod: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fitod.f UINT f_FRk; UINT f_FRj; @@ -8595,7 +8595,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fdtoi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fdtoi.f UINT f_FRk; UINT f_FRj; @@ -8623,7 +8623,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fditos: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fditos.f UINT f_FRk; UINT f_FRj; @@ -8653,7 +8653,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fdstoi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fdstoi.f UINT f_FRk; UINT f_FRj; @@ -8683,7 +8683,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfitos: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfitos.f UINT f_FRk; UINT f_CCi; @@ -8718,7 +8718,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfstoi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfstoi.f UINT f_FRk; UINT f_CCi; @@ -8753,7 +8753,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nfitos: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fditos.f UINT f_FRk; UINT f_FRj; @@ -8781,7 +8781,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nfstoi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fdstoi.f UINT f_FRk; UINT f_FRj; @@ -8809,7 +8809,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmovs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_FRj; @@ -8837,7 +8837,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmovd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fmaddd.f UINT f_FRk; UINT f_FRj; @@ -8865,7 +8865,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fdmovs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fdmadds.f UINT f_FRk; UINT f_FRj; @@ -8895,7 +8895,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfmovs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_CCi; @@ -8930,7 +8930,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nfsqrts: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_FRj; @@ -8958,7 +8958,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fadds: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_FRi; @@ -8990,7 +8990,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_faddd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fmaddd.f UINT f_FRk; UINT f_FRi; @@ -9022,7 +9022,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfadds: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_FRi; @@ -9061,7 +9061,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nfadds: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_FRi; @@ -9093,7 +9093,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcmps: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfcmps.f UINT f_FCCi_2; UINT f_FRi; @@ -9125,7 +9125,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcmpd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fcmpd.f UINT f_FCCi_2; UINT f_FRi; @@ -9157,7 +9157,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfcmps: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfcmps.f UINT f_FCCi_2; UINT f_FRi; @@ -9196,7 +9196,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fdcmps: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_nfdcmps.f UINT f_FCCi_2; UINT f_FRi; @@ -9231,7 +9231,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmadds: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_FRi; @@ -9264,7 +9264,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmaddd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fmaddd.f UINT f_FRk; UINT f_FRi; @@ -9297,7 +9297,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fdmadds: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fdmadds.f UINT f_FRk; UINT f_FRi; @@ -9334,7 +9334,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfmadds: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_FRi; @@ -9374,7 +9374,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nfmadds: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmadds.f UINT f_FRk; UINT f_FRi; @@ -9407,7 +9407,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmas: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fdmadds.f UINT f_FRk; UINT f_FRi; @@ -9442,7 +9442,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fdmas: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fdmas.f UINT f_FRk; UINT f_FRi; @@ -9483,7 +9483,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cfmas: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cfmas.f UINT f_FRk; UINT f_FRi; @@ -9525,7 +9525,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_nfdcmps: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_nfdcmps.f UINT f_FRk; UINT f_FCCi_2; @@ -9563,7 +9563,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mhsetlos: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mhsetlos.f UINT f_FRk; INT f_u12_h; @@ -9596,7 +9596,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mhsethis: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mhsethis.f UINT f_FRk; INT f_u12_h; @@ -9629,7 +9629,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mhdsets: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mhdsets.f UINT f_FRk; INT f_u12_h; @@ -9665,7 +9665,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mhsetloh: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mhsetloh.f UINT f_FRk; INT f_s5; @@ -9693,7 +9693,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mhsethih: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mhsethih.f UINT f_FRk; INT f_s5; @@ -9721,7 +9721,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mhdseth: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mhdseth.f UINT f_FRk; INT f_s5; @@ -9753,7 +9753,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mand: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mwcut.f UINT f_FRk; UINT f_FRi; @@ -9785,7 +9785,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmand: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmand.f UINT f_FRk; UINT f_FRi; @@ -9824,7 +9824,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mnot: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mcut.f UINT f_FRk; UINT f_FRj; @@ -9852,7 +9852,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmnot: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmand.f UINT f_FRk; UINT f_CCi; @@ -9887,7 +9887,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mrotli: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mwcuti.f UINT f_FRk; UINT f_FRi; @@ -9918,7 +9918,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mwcut: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mwcut.f UINT f_FRk; UINT f_FRi; @@ -9951,7 +9951,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mwcuti: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mwcuti.f UINT f_FRk; UINT f_FRi; @@ -9983,7 +9983,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mcut: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mcut.f UINT f_FRk; UINT f_ACC40Si; @@ -10015,7 +10015,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mcuti: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mcuti.f UINT f_FRk; UINT f_ACC40Si; @@ -10046,7 +10046,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mdcutssi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdcutssi.f UINT f_FRk; UINT f_ACC40Si; @@ -10079,7 +10079,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_msllhi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_msllhi.f UINT f_FRk; UINT f_FRi; @@ -10116,7 +10116,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mdrotli: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdrotli.f UINT f_FRk; UINT f_FRi; @@ -10149,7 +10149,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mcplhi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mcplhi.f UINT f_FRk; UINT f_FRi; @@ -10185,7 +10185,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mcpli: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mwcuti.f UINT f_FRk; UINT f_FRi; @@ -10217,7 +10217,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_msaths: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmaddhss.f UINT f_FRk; UINT f_FRi; @@ -10254,7 +10254,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mqsaths: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqaddhss.f UINT f_FRk; UINT f_FRi; @@ -10299,7 +10299,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mcmpsh: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mcmpsh.f UINT f_FCCk; UINT f_FRi; @@ -10336,7 +10336,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mabshs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mabshs.f UINT f_FRk; UINT f_FRj; @@ -10370,7 +10370,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmaddhss: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmaddhss.f UINT f_FRk; UINT f_FRi; @@ -10414,7 +10414,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmqaddhss: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqaddhss.f UINT f_FRk; UINT f_FRi; @@ -10466,7 +10466,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mqsllhi: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mqsllhi.f UINT f_FRk; UINT f_FRi; @@ -10507,7 +10507,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_maddaccs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdasaccs.f UINT f_ACC40Sk; UINT f_ACC40Si; @@ -10536,7 +10536,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mdaddaccs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdasaccs.f UINT f_ACC40Sk; UINT f_ACC40Si; @@ -10568,7 +10568,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_masaccs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdasaccs.f UINT f_ACC40Sk; UINT f_ACC40Si; @@ -10598,7 +10598,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mdasaccs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdasaccs.f UINT f_ACC40Sk; UINT f_ACC40Si; @@ -10632,7 +10632,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mmulhs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -10669,7 +10669,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmmulhs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -10713,7 +10713,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mqmulhs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -10756,7 +10756,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmqmulhs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -10806,7 +10806,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mmachs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -10845,7 +10845,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mmachu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachu.f UINT f_ACC40Uk; UINT f_FRi; @@ -10884,7 +10884,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmmachs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -10930,7 +10930,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmmachu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachu.f UINT f_ACC40Uk; UINT f_FRi; @@ -10976,7 +10976,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mqmachs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -11023,7 +11023,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mqmachu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqmachu.f UINT f_ACC40Uk; UINT f_FRi; @@ -11070,7 +11070,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmqmachs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -11124,7 +11124,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmqmachu: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqmachu.f UINT f_ACC40Uk; UINT f_FRi; @@ -11178,7 +11178,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mcpxrs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -11214,7 +11214,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmcpxrs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -11257,7 +11257,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mqcpxrs: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmqmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -11298,7 +11298,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mexpdhw: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmexpdhw.f UINT f_FRk; UINT f_FRi; @@ -11331,7 +11331,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmexpdhw: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmexpdhw.f UINT f_FRk; UINT f_FRi; @@ -11371,7 +11371,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mexpdhd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmexpdhd.f UINT f_FRk; UINT f_FRi; @@ -11408,7 +11408,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmexpdhd: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmexpdhd.f UINT f_FRk; UINT f_FRi; @@ -11452,7 +11452,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mpackh: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmaddhss.f UINT f_FRk; UINT f_FRi; @@ -11485,7 +11485,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mdpackh: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdpackh.f UINT f_FRk; UINT f_FRi; @@ -11528,7 +11528,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_munpackh: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_munpackh.f UINT f_FRk; UINT f_FRi; @@ -11564,7 +11564,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mdunpackh: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdunpackh.f UINT f_FRk; UINT f_FRi; @@ -11606,7 +11606,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mbtoh: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmbtoh.f UINT f_FRk; UINT f_FRj; @@ -11644,7 +11644,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmbtoh: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmbtoh.f UINT f_FRk; UINT f_CCi; @@ -11689,7 +11689,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mhtob: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmhtob.f UINT f_FRk; UINT f_FRj; @@ -11727,7 +11727,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmhtob: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmhtob.f UINT f_FRk; UINT f_CCi; @@ -11772,7 +11772,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mbtohe: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmbtohe.f UINT f_FRk; UINT f_FRj; @@ -11814,7 +11814,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmbtohe: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmbtohe.f UINT f_FRk; UINT f_CCi; @@ -11863,7 +11863,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mclracc_0: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mdasaccs.f UINT f_ACC40Sk; @@ -11880,7 +11880,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mrdacc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mcuti.f UINT f_FRk; UINT f_ACC40Si; @@ -11908,7 +11908,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mrdaccg: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mrdaccg.f UINT f_FRk; UINT f_ACCGi; @@ -11936,7 +11936,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mwtacc: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_cmmachs.f UINT f_ACC40Sk; UINT f_FRi; @@ -11965,7 +11965,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mwtaccg: { const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mwtaccg.f UINT f_ACCGk; UINT f_FRi; diff --git a/sim/frv/decode.h b/sim/frv/decode.h index b004a2d..4e9e66f 100644 --- a/sim/frv/decode.h +++ b/sim/frv/decode.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define FRVBF_DECODE_H extern const IDESC *frvbf_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void frvbf_init_idesc_table (SIM_CPU *); extern void frvbf_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/iq2000/ChangeLog b/sim/iq2000/ChangeLog index e034ca3..999008f 100644 --- a/sim/iq2000/ChangeLog +++ b/sim/iq2000/ChangeLog @@ -1,3 +1,10 @@ +2009-11-22 Doug Evans <dje@sebabeach.org> + + * cpu.h: Regenerate. + * cpuall.h: Regenerate. + * decode.c: Regenerate. + * decode.h: Regenerate. + 2009-11-03 Doug Evans <dje@sebabeach.org> * arch.c: Regenerate. diff --git a/sim/iq2000/cpu.h b/sim/iq2000/cpu.h index 47ca845..edc50c4 100644 --- a/sim/iq2000/cpu.h +++ b/sim/iq2000/cpu.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/iq2000/cpuall.h b/sim/iq2000/cpuall.h index 51a7d9b..8bac559 100644 --- a/sim/iq2000/cpuall.h +++ b/sim/iq2000/cpuall.h @@ -29,14 +29,12 @@ This file is part of the GNU simulators. #ifdef WANT_CPU_IQ2000BF #include "eng.h" -#include "cgen-engine.h" #include "cpu.h" #include "decode.h" #endif #ifdef WANT_CPU_IQ10BF #include "eng.h" -#include "cgen-engine.h" #include "cpu.h" #include "decode.h" #endif diff --git a/sim/iq2000/decode.c b/sim/iq2000/decode.c index 1bb77b1..1d08454 100644 --- a/sim/iq2000/decode.c +++ b/sim/iq2000/decode.c @@ -256,14 +256,14 @@ iq2000bf_init_idesc_table (SIM_CPU *cpu) const IDESC * iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ IQ2000BF_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 26) & (63 << 0))); @@ -892,7 +892,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mrgb.f UINT f_rs; UINT f_rt; @@ -915,7 +915,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -938,7 +938,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ram: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ram.f UINT f_rs; UINT f_rt; @@ -967,7 +967,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sll: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ram.f UINT f_rt; UINT f_rd; @@ -990,7 +990,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slmv: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ram.f UINT f_rs; UINT f_rt; @@ -1016,7 +1016,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slt: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mrgb.f UINT f_rs; UINT f_rt; @@ -1039,7 +1039,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slti: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1062,7 +1062,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bbi: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bbi.f UINT f_rs; UINT f_rt; @@ -1091,7 +1091,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bbv: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bbi.f UINT f_rs; UINT f_rt; @@ -1120,7 +1120,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bgez: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bbi.f UINT f_rs; SI f_offset; @@ -1146,7 +1146,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bgezal: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bbi.f UINT f_rs; SI f_offset; @@ -1172,7 +1172,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jalr: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mrgb.f UINT f_rs; UINT f_rd; @@ -1198,7 +1198,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jr: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bbi.f UINT f_rs; @@ -1221,7 +1221,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lb: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1244,7 +1244,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lh: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1267,7 +1267,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lui: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rt; UINT f_imm; @@ -1287,7 +1287,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lw: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1310,7 +1310,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sb: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1333,7 +1333,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sh: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1356,7 +1356,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sw: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1411,7 +1411,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andoui: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1434,7 +1434,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mrgb: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mrgb.f UINT f_rs; UINT f_rt; @@ -1473,7 +1473,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldw: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1496,7 +1496,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sdw: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_rs; UINT f_rt; @@ -1519,7 +1519,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_j: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_j.f USI f_jtarg; @@ -1542,7 +1542,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jal: { const IDESC *idesc = &iq2000bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_j.f USI f_jtarg; diff --git a/sim/iq2000/decode.h b/sim/iq2000/decode.h index 75d647e..01f30d6 100644 --- a/sim/iq2000/decode.h +++ b/sim/iq2000/decode.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define IQ2000BF_DECODE_H extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void iq2000bf_init_idesc_table (SIM_CPU *); extern void iq2000bf_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/lm32/ChangeLog b/sim/lm32/ChangeLog index b0eab3b..de8b7bb 100755 --- a/sim/lm32/ChangeLog +++ b/sim/lm32/ChangeLog @@ -1,3 +1,10 @@ +2009-11-22 Doug Evans <dje@sebabeach.org> + + * cpu.h: Regenerate. + * cpuall.h: Regenerate. + * decode.c: Regenerate. + * decode.h: Regenerate. + 2009-11-03 Doug Evans <dje@sebabeach.org> * arch.c: Regenerate. diff --git a/sim/lm32/cpu.h b/sim/lm32/cpu.h index 8b44fa3..3bb7caf 100644 --- a/sim/lm32/cpu.h +++ b/sim/lm32/cpu.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/lm32/cpuall.h b/sim/lm32/cpuall.h index 1bd6404..ad1e10c 100644 --- a/sim/lm32/cpuall.h +++ b/sim/lm32/cpuall.h @@ -29,7 +29,6 @@ This file is part of the GNU simulators. #ifdef WANT_CPU_LM32BF #include "eng.h" -#include "cgen-engine.h" #include "cpu.h" #include "decode.h" #endif diff --git a/sim/lm32/decode.c b/sim/lm32/decode.c index f7f2506..a5d7e2e 100644 --- a/sim/lm32/decode.c +++ b/sim/lm32/decode.c @@ -174,14 +174,14 @@ lm32bf_init_idesc_table (SIM_CPU *cpu) const IDESC * lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ LM32BF_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 26) & (63 << 0))); @@ -361,7 +361,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_user.f UINT f_r0; UINT f_r1; @@ -384,7 +384,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r0; UINT f_r1; @@ -407,7 +407,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andi: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_andi.f UINT f_r0; UINT f_r1; @@ -430,7 +430,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andhii: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_andi.f UINT f_r0; UINT f_r1; @@ -453,7 +453,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_b: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_be.f UINT f_r0; @@ -470,7 +470,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bi: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bi.f SI f_call; @@ -487,7 +487,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_be: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_be.f UINT f_r0; UINT f_r1; @@ -510,7 +510,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_call: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_be.f UINT f_r0; @@ -527,7 +527,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_calli: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bi.f SI f_call; @@ -544,7 +544,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_divu: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_user.f UINT f_r0; UINT f_r1; @@ -567,7 +567,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lb: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r0; UINT f_r1; @@ -590,7 +590,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lh: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r0; UINT f_r1; @@ -613,7 +613,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lw: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r0; UINT f_r1; @@ -636,7 +636,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ori: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_andi.f UINT f_r0; UINT f_r1; @@ -659,7 +659,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_rcsr: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_rcsr.f UINT f_csr; UINT f_r2; @@ -679,7 +679,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sb: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r0; UINT f_r1; @@ -702,7 +702,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sextb: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_user.f UINT f_r0; UINT f_r2; @@ -722,7 +722,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sh: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r0; UINT f_r1; @@ -745,7 +745,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sw: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r0; UINT f_r1; @@ -768,7 +768,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_user: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_user.f UINT f_r0; UINT f_r1; @@ -794,7 +794,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_wcsr: { const IDESC *idesc = &lm32bf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_wcsr.f UINT f_csr; UINT f_r1; diff --git a/sim/lm32/decode.h b/sim/lm32/decode.h index 5327fbf..12d18fd 100644 --- a/sim/lm32/decode.h +++ b/sim/lm32/decode.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define LM32BF_DECODE_H extern const IDESC *lm32bf_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void lm32bf_init_idesc_table (SIM_CPU *); extern void lm32bf_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index 7211f8e..1b28981 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,3 +1,16 @@ +2009-11-22 Doug Evans <dje@sebabeach.org> + + * cpu.h: Regenerate. + * cpu2.h: Regenerate. + * cpux.h: Regenerate. + * cpuall.h: Regenerate. + * decode.c: Regenerate. + * decode.h: Regenerate. + * decode2.c: Regenerate. + * decode2.h: Regenerate. + * decodex.c: Regenerate. + * decodex.h: Regenerate. + 2009-11-03 Doug Evans <dje@sebabeach.org> * arch.c: Regenerate. diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index 7f112d4..b7a684e 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h index 58334e5..6e95104 100644 --- a/sim/m32r/cpu2.h +++ b/sim/m32r/cpu2.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 2 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h index 36e128b..ad6e19a 100644 --- a/sim/m32r/cpuall.h +++ b/sim/m32r/cpuall.h @@ -29,21 +29,18 @@ This file is part of the GNU simulators. #ifdef WANT_CPU_M32RBF #include "eng.h" -#include "cgen-engine.h" #include "cpu.h" #include "decode.h" #endif #ifdef WANT_CPU_M32RXF #include "engx.h" -#include "cgen-engine.h" #include "cpux.h" #include "decodex.h" #endif #ifdef WANT_CPU_M32R2F #include "eng2.h" -#include "cgen-engine.h" #include "cpu2.h" #include "decode2.h" #endif diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h index 784536e..088abd3 100644 --- a/sim/m32r/cpux.h +++ b/sim/m32r/cpux.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 2 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c index e94ff36..96ec765 100644 --- a/sim/m32r/decode.c +++ b/sim/m32r/decode.c @@ -216,14 +216,14 @@ m32rbf_init_idesc_table (SIM_CPU *cpu) const IDESC * m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ M32RBF_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); @@ -586,7 +586,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -617,7 +617,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -650,7 +650,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -683,7 +683,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_or3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -716,7 +716,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -745,7 +745,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -776,7 +776,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -809,7 +809,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addx: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -840,7 +840,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc8: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -863,7 +863,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc24: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -886,7 +886,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beq: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r1; UINT f_r2; @@ -919,7 +919,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beqz: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r2; SI f_disp16; @@ -947,7 +947,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl8: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -971,7 +971,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl24: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -995,7 +995,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra8: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1018,7 +1018,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra24: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1041,7 +1041,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1071,7 +1071,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r2; INT f_simm16; @@ -1099,7 +1099,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_div: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -1130,7 +1130,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jl: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1156,7 +1156,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jmp: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1181,7 +1181,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1211,7 +1211,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1244,7 +1244,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1274,7 +1274,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1307,7 +1307,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1337,7 +1337,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1370,7 +1370,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_plus: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1401,7 +1401,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld24: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld24.f UINT f_r1; UINT f_uimm24; @@ -1429,7 +1429,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi8: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -1457,7 +1457,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi16: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; INT f_simm16; @@ -1485,7 +1485,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lock: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1515,7 +1515,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_machi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1545,7 +1545,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulhi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1575,7 +1575,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mv: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1605,7 +1605,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfachi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_seth.f UINT f_r1; @@ -1630,7 +1630,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfc: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1658,7 +1658,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtachi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; @@ -1683,7 +1683,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtc: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1756,7 +1756,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_seth: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_seth.f UINT f_r1; UINT f_hi16; @@ -1784,7 +1784,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sll3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1817,7 +1817,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slli: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_slli.f UINT f_r1; UINT f_uimm5; @@ -1846,7 +1846,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1876,7 +1876,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -1909,7 +1909,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1939,7 +1939,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -1972,7 +1972,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2002,7 +2002,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2035,7 +2035,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_plus: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2066,7 +2066,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_trap: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_trap.f UINT f_uimm4; @@ -2089,7 +2089,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_unlock: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2119,7 +2119,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clrpsw: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2136,7 +2136,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setpsw: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2153,7 +2153,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bset: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; @@ -2184,7 +2184,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btst: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h index 4930f34..6c5c645 100644 --- a/sim/m32r/decode.h +++ b/sim/m32r/decode.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define M32RBF_DECODE_H extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void m32rbf_init_idesc_table (SIM_CPU *); extern void m32rbf_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c index 66ffa11..e9fccce 100644 --- a/sim/m32r/decode2.c +++ b/sim/m32r/decode2.c @@ -259,14 +259,14 @@ m32r2f_init_idesc_table (SIM_CPU *cpu) const IDESC * m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ M32R2F_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); @@ -775,7 +775,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -806,7 +806,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -839,7 +839,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -872,7 +872,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_or3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -905,7 +905,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -934,7 +934,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -965,7 +965,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -998,7 +998,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addx: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -1029,7 +1029,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1052,7 +1052,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1075,7 +1075,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beq: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r1; UINT f_r2; @@ -1108,7 +1108,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beqz: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r2; SI f_disp16; @@ -1136,7 +1136,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1160,7 +1160,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1184,7 +1184,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcl8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1208,7 +1208,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcl24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1232,7 +1232,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1255,7 +1255,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1278,7 +1278,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1308,7 +1308,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpi: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r2; INT f_simm16; @@ -1336,7 +1336,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpz: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r2; @@ -1361,7 +1361,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_div: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -1392,7 +1392,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jc: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1417,7 +1417,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jl: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1443,7 +1443,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jmp: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1468,7 +1468,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1498,7 +1498,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1531,7 +1531,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1561,7 +1561,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1594,7 +1594,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1624,7 +1624,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1657,7 +1657,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_plus: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1688,7 +1688,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld24.f UINT f_r1; UINT f_uimm24; @@ -1716,7 +1716,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -1744,7 +1744,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi16: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; INT f_simm16; @@ -1772,7 +1772,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lock: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1802,7 +1802,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_machi_a: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_machi_a.f UINT f_r1; UINT f_acc; @@ -1835,7 +1835,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulhi_a: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_machi_a.f UINT f_r1; UINT f_acc; @@ -1868,7 +1868,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mv: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1898,7 +1898,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfachi_a: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mvfachi_a.f UINT f_r1; UINT f_accs; @@ -1926,7 +1926,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfc: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1954,7 +1954,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtachi_a: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mvtachi_a.f UINT f_r1; UINT f_accs; @@ -1982,7 +1982,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtc: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2023,7 +2023,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_rac_dsi: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_rac_dsi.f UINT f_accd; UINT f_accs; @@ -2065,7 +2065,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_seth: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_seth.f UINT f_r1; UINT f_hi16; @@ -2093,7 +2093,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sll3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -2126,7 +2126,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slli: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_slli.f UINT f_r1; UINT f_uimm5; @@ -2155,7 +2155,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2185,7 +2185,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2218,7 +2218,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2248,7 +2248,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2281,7 +2281,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2311,7 +2311,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2344,7 +2344,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_plus: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2375,7 +2375,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_plus: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2406,7 +2406,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_plus: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2437,7 +2437,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_trap: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_trap.f UINT f_uimm4; @@ -2460,7 +2460,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_unlock: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2490,7 +2490,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_satb: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2520,7 +2520,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sat: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2563,7 +2563,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_macwu1: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2593,7 +2593,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_msblo: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2623,7 +2623,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulwu1: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2666,7 +2666,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clrpsw: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2683,7 +2683,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setpsw: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2700,7 +2700,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bset: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; @@ -2731,7 +2731,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btst: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; diff --git a/sim/m32r/decode2.h b/sim/m32r/decode2.h index a04c469..a681a45 100644 --- a/sim/m32r/decode2.h +++ b/sim/m32r/decode2.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define M32R2F_DECODE_H extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void m32r2f_init_idesc_table (SIM_CPU *); extern void m32r2f_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c index f1644b9..1b58320 100644 --- a/sim/m32r/decodex.c +++ b/sim/m32r/decodex.c @@ -252,14 +252,14 @@ m32rxf_init_idesc_table (SIM_CPU *cpu) const IDESC * m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ M32RXF_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); @@ -716,7 +716,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -747,7 +747,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -780,7 +780,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -813,7 +813,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_or3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -846,7 +846,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -875,7 +875,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -906,7 +906,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -939,7 +939,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addx: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -970,7 +970,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -993,7 +993,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1016,7 +1016,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beq: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r1; UINT f_r2; @@ -1049,7 +1049,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beqz: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r2; SI f_disp16; @@ -1077,7 +1077,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1101,7 +1101,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1125,7 +1125,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcl8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1149,7 +1149,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcl24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1173,7 +1173,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1196,7 +1196,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1219,7 +1219,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1249,7 +1249,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpi: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r2; INT f_simm16; @@ -1277,7 +1277,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpz: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r2; @@ -1302,7 +1302,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_div: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -1333,7 +1333,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jc: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1358,7 +1358,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jl: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1384,7 +1384,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jmp: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1409,7 +1409,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1439,7 +1439,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1472,7 +1472,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1502,7 +1502,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1535,7 +1535,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1565,7 +1565,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1598,7 +1598,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_plus: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1629,7 +1629,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld24.f UINT f_r1; UINT f_uimm24; @@ -1657,7 +1657,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -1685,7 +1685,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi16: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; INT f_simm16; @@ -1713,7 +1713,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lock: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1743,7 +1743,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_machi_a: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_machi_a.f UINT f_r1; UINT f_acc; @@ -1776,7 +1776,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulhi_a: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_machi_a.f UINT f_r1; UINT f_acc; @@ -1809,7 +1809,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mv: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1839,7 +1839,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfachi_a: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mvfachi_a.f UINT f_r1; UINT f_accs; @@ -1867,7 +1867,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfc: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1895,7 +1895,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtachi_a: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mvtachi_a.f UINT f_r1; UINT f_accs; @@ -1923,7 +1923,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtc: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1964,7 +1964,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_rac_dsi: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_rac_dsi.f UINT f_accd; UINT f_accs; @@ -2006,7 +2006,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_seth: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_seth.f UINT f_r1; UINT f_hi16; @@ -2034,7 +2034,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sll3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -2067,7 +2067,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slli: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_slli.f UINT f_r1; UINT f_uimm5; @@ -2096,7 +2096,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2126,7 +2126,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2159,7 +2159,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2189,7 +2189,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2222,7 +2222,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2252,7 +2252,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2285,7 +2285,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_plus: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2316,7 +2316,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_plus: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2347,7 +2347,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_plus: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2378,7 +2378,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_trap: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_trap.f UINT f_uimm4; @@ -2401,7 +2401,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_unlock: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2431,7 +2431,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_satb: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2461,7 +2461,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sat: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2504,7 +2504,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_macwu1: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2534,7 +2534,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_msblo: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2564,7 +2564,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulwu1: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2607,7 +2607,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clrpsw: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2624,7 +2624,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setpsw: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2641,7 +2641,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bset: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; @@ -2672,7 +2672,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btst: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h index e6e2395..89b3cbf 100644 --- a/sim/m32r/decodex.h +++ b/sim/m32r/decodex.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define M32RXF_DECODE_H extern const IDESC *m32rxf_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void m32rxf_init_idesc_table (SIM_CPU *); extern void m32rxf_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/sh64/ChangeLog b/sim/sh64/ChangeLog index 849e54b..982e649 100644 --- a/sim/sh64/ChangeLog +++ b/sim/sh64/ChangeLog @@ -1,3 +1,12 @@ +2009-11-22 Doug Evans <dje@sebabeach.org> + + * cpu.h: Regenerate. + * cpuall.h: Regenerate. + * decode-compact.c: Regenerate. + * decode-compact.h: Regenerate. + * decode-media.c: Regenerate. + * decode-media.h: Regenerate. + 2009-11-03 Doug Evans <dje@sebabeach.org> * arch.c: Regenerate. diff --git a/sim/sh64/cpu.h b/sim/sh64/cpu.h index 69e1731..3b6c492 100644 --- a/sim/sh64/cpu.h +++ b/sim/sh64/cpu.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/sh64/cpuall.h b/sim/sh64/cpuall.h index a188f42..83f7521 100644 --- a/sim/sh64/cpuall.h +++ b/sim/sh64/cpuall.h @@ -29,7 +29,6 @@ This file is part of the GNU simulators. #ifdef WANT_CPU_SH64 #include "eng.h" -#include "cgen-engine.h" #include "cpu.h" #include "decode.h" #endif diff --git a/sim/sh64/decode-compact.c b/sim/sh64/decode-compact.c index c2042ca..d762b3d 100644 --- a/sim/sh64/decode-compact.c +++ b/sim/sh64/decode-compact.c @@ -306,14 +306,14 @@ sh64_compact_init_idesc_table (SIM_CPU *cpu) const IDESC * sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ SH64_COMPACT_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 5) & (15 << 7)) | ((insn >> 0) & (127 << 0))); @@ -2658,7 +2658,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -2687,7 +2687,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_rn; UINT f_imm8; @@ -2715,7 +2715,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addc_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -2744,7 +2744,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -2773,7 +2773,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -2802,7 +2802,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andi_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; @@ -2827,7 +2827,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_andb_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; @@ -2851,7 +2851,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bf_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bf_compact.f SI f_disp8; @@ -2874,7 +2874,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bfs_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bf_compact.f SI f_disp8; @@ -2897,7 +2897,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bra_compact.f SI f_disp12; @@ -2920,7 +2920,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_braf_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -2963,7 +2963,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bsr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bra_compact.f SI f_disp12; @@ -2986,7 +2986,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bsrf_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3049,7 +3049,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpeq_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3077,7 +3077,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpeqi_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; @@ -3101,7 +3101,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmppl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3125,7 +3125,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_div0s_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3166,7 +3166,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_div1_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3195,7 +3195,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_divu_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3221,7 +3221,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_dmulsl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3249,7 +3249,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_dt_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3274,7 +3274,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_extsb_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3302,7 +3302,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fabs_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3327,7 +3327,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fadd_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3356,7 +3356,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcmpeq_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3384,7 +3384,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcnvds_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fmov8_compact.f SI f_dn; @@ -3409,7 +3409,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcnvsd_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fmov8_compact.f SI f_dn; @@ -3434,7 +3434,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fipr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fipr_compact.f SI f_vn; SI f_vm; @@ -3454,7 +3454,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_flds_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3479,7 +3479,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fldi0_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3503,7 +3503,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_float_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3528,7 +3528,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmac_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3558,7 +3558,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov1_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3586,7 +3586,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov2_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3614,7 +3614,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov3_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3643,7 +3643,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov4_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3672,7 +3672,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov5_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3700,7 +3700,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov6_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3729,7 +3729,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov7_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -3758,7 +3758,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov8_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fmov8_compact.f SI f_dn; UINT f_rm; @@ -3789,7 +3789,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmov9_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fmov9_compact.f UINT f_rn; SI f_dm; @@ -3846,7 +3846,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fsts_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3871,7 +3871,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ftrc_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3896,7 +3896,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ftrv_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fipr_compact.f SI f_vn; @@ -3913,7 +3913,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldc_gbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3937,7 +3937,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldc_vbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3961,7 +3961,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldc_sr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -3985,7 +3985,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldcl_gbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4010,7 +4010,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldcl_vbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4035,7 +4035,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lds_fpscr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4059,7 +4059,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldsl_fpscr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4084,7 +4084,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lds_fpul_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4109,7 +4109,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldsl_fpul_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4135,7 +4135,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lds_mach_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4159,7 +4159,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldsl_mach_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4184,7 +4184,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lds_macl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4208,7 +4208,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldsl_macl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4233,7 +4233,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lds_pr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4257,7 +4257,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldsl_pr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -4282,7 +4282,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_macl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4312,7 +4312,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_macw_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4342,7 +4342,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mov_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4370,7 +4370,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movi_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_rn; UINT f_imm8; @@ -4397,7 +4397,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movi20_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movi20_compact.f UINT f_rn; INT f_imm20_hi; @@ -4428,7 +4428,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb1_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4456,7 +4456,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb2_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4485,7 +4485,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb3_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4514,7 +4514,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb4_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; @@ -4538,7 +4538,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb5_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movb5_compact.f UINT f_rm; UINT f_imm4; @@ -4566,7 +4566,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb6_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4594,7 +4594,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb7_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4623,7 +4623,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb8_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4652,7 +4652,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb9_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; @@ -4676,7 +4676,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movb10_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movb5_compact.f UINT f_rm; UINT f_imm4; @@ -4704,7 +4704,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl1_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4732,7 +4732,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl2_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4761,7 +4761,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl3_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4790,7 +4790,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl4_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl10_compact.f SI f_imm8x4; @@ -4814,7 +4814,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl5_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl5_compact.f UINT f_rn; UINT f_rm; @@ -4845,7 +4845,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl6_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4873,7 +4873,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl7_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4903,7 +4903,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl8_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -4932,7 +4932,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl9_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl10_compact.f SI f_imm8x4; @@ -4956,7 +4956,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl10_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl10_compact.f UINT f_rn; SI f_imm8x4; @@ -4983,7 +4983,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl11_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl5_compact.f UINT f_rn; UINT f_rm; @@ -5014,7 +5014,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl12_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5045,7 +5045,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movl13_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5076,7 +5076,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw1_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5104,7 +5104,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw2_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5133,7 +5133,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw3_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5162,7 +5162,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw4_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f SI f_imm8x2; @@ -5186,7 +5186,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw5_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw5_compact.f UINT f_rm; SI f_imm4x2; @@ -5214,7 +5214,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw6_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5242,7 +5242,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw7_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5271,7 +5271,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw8_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5300,7 +5300,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw9_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f SI f_imm8x2; @@ -5324,7 +5324,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw10_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; SI f_imm8x2; @@ -5351,7 +5351,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movw11_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw5_compact.f UINT f_rm; SI f_imm4x2; @@ -5379,7 +5379,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mova_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl10_compact.f SI f_imm8x4; @@ -5403,7 +5403,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movcal_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5428,7 +5428,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movcol_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5453,7 +5453,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movt_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5477,7 +5477,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movual_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5502,7 +5502,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movual2_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5528,7 +5528,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mull_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5556,7 +5556,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_negc_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5597,7 +5597,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_pref_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5621,7 +5621,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_rotcl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5665,7 +5665,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_shad_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; @@ -5694,7 +5694,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stc_gbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5718,7 +5718,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stc_vbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5742,7 +5742,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stcl_gbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5767,7 +5767,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stcl_vbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5792,7 +5792,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sts_fpscr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5816,7 +5816,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stsl_fpscr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5841,7 +5841,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sts_fpul_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5866,7 +5866,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stsl_fpul_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5892,7 +5892,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sts_mach_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5916,7 +5916,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stsl_mach_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5941,7 +5941,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sts_macl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5965,7 +5965,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stsl_macl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -5990,7 +5990,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sts_pr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -6014,7 +6014,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stsl_pr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -6039,7 +6039,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_tasb_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; @@ -6063,7 +6063,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_trapa_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; @@ -6086,7 +6086,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_tsti_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; @@ -6110,7 +6110,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_tstb_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; diff --git a/sim/sh64/decode-compact.h b/sim/sh64/decode-compact.h index 554856a..d39c6b0 100644 --- a/sim/sh64/decode-compact.h +++ b/sim/sh64/decode-compact.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define SH64_COMPACT_DECODE_H extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void sh64_compact_init_idesc_table (SIM_CPU *); extern void sh64_compact_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/sh64/decode-media.c b/sim/sh64/decode-media.c index 4ee6093..c08dc77 100644 --- a/sim/sh64/decode-media.c +++ b/sim/sh64/decode-media.c @@ -320,14 +320,14 @@ sh64_media_init_idesc_table (SIM_CPU *cpu) const IDESC * sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ SH64_MEDIA_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 22) & (63 << 4)) | ((insn >> 16) & (15 << 0))); @@ -1548,7 +1548,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -1580,7 +1580,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_left; INT f_disp10; @@ -1611,7 +1611,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_alloco: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; @@ -1636,7 +1636,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_left; UINT f_right; @@ -1668,7 +1668,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beqi: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beqi.f UINT f_left; INT f_imm6; @@ -1699,7 +1699,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_blink: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_blink.f UINT f_trb; UINT f_dest; @@ -1746,7 +1746,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_byterev: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; UINT f_dest; @@ -1774,7 +1774,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmveq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -1806,7 +1806,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fabsd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fabsd.f UINT f_left; UINT f_right; @@ -1838,7 +1838,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fabss: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fabsd.f UINT f_left; UINT f_right; @@ -1870,7 +1870,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_faddd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -1902,7 +1902,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fadds: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -1934,7 +1934,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcmpeqd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -1966,7 +1966,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcmpeqs: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -1998,7 +1998,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcnvds: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fabsd.f UINT f_left; UINT f_right; @@ -2030,7 +2030,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fcnvsd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fabsd.f UINT f_left; UINT f_right; @@ -2062,7 +2062,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fgetscr: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_shori.f UINT f_dest; @@ -2086,7 +2086,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fiprs: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -2120,7 +2120,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fldd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fldd.f UINT f_left; SI f_disp10x8; @@ -2151,7 +2151,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fldp: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fldd.f UINT f_left; SI f_disp10x8; @@ -2183,7 +2183,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_flds: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_flds.f UINT f_left; SI f_disp10x4; @@ -2214,7 +2214,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fldxd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -2246,7 +2246,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fldxp: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -2279,7 +2279,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fldxs: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -2311,7 +2311,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmacs: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -2344,7 +2344,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmovdq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fabsd.f UINT f_left; UINT f_right; @@ -2376,7 +2376,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmovls: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; UINT f_dest; @@ -2404,7 +2404,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmovqd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; UINT f_dest; @@ -2432,7 +2432,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fmovsl: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fabsd.f UINT f_left; UINT f_right; @@ -2464,7 +2464,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fputscr: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fabsd.f UINT f_left; UINT f_right; @@ -2492,7 +2492,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fstd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fldd.f UINT f_left; SI f_disp10x8; @@ -2523,7 +2523,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fsts: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_flds.f UINT f_left; SI f_disp10x4; @@ -2554,7 +2554,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fstxd: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -2586,7 +2586,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_fstxs: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -2618,7 +2618,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ftrvs: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -2653,7 +2653,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_getcfg: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -2684,7 +2684,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_getcon: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; UINT f_dest; @@ -2711,7 +2711,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_gettr: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_blink.f UINT f_trb; UINT f_dest; @@ -2739,7 +2739,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_left; INT f_disp10; @@ -2770,7 +2770,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldl: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_flds.f UINT f_left; SI f_disp10x4; @@ -2801,7 +2801,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fldd.f UINT f_left; SI f_disp10x8; @@ -2832,7 +2832,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lduw: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_lduw.f UINT f_left; SI f_disp10x2; @@ -2863,7 +2863,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldhil: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -2894,7 +2894,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldhiq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -2925,7 +2925,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldlol: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -2956,7 +2956,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldloq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -2987,7 +2987,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldxb: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3019,7 +3019,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldxl: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3051,7 +3051,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldxq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3083,7 +3083,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldxub: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3115,7 +3115,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldxuw: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3147,7 +3147,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldxw: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3179,7 +3179,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mcmv: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3212,7 +3212,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_movi: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movi.f INT f_imm16; UINT f_dest; @@ -3252,7 +3252,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ori: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ori.f UINT f_left; INT f_imm10; @@ -3283,7 +3283,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_pta: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_pta.f DI f_disp16; UINT f_tra; @@ -3310,7 +3310,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ptabs: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_right; UINT f_tra; @@ -3338,7 +3338,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ptrel: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_right; UINT f_tra; @@ -3366,7 +3366,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_putcfg: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -3397,7 +3397,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_putcon: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; UINT f_dest; @@ -3424,7 +3424,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_shari: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_shari.f UINT f_left; UINT f_uimm6; @@ -3455,7 +3455,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_shori: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_shori.f UINT f_uimm16; UINT f_dest; @@ -3483,7 +3483,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_left; INT f_disp10; @@ -3514,7 +3514,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stl: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_flds.f UINT f_left; SI f_disp10x4; @@ -3545,7 +3545,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_fldd.f UINT f_left; SI f_disp10x8; @@ -3576,7 +3576,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stw: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_lduw.f UINT f_left; SI f_disp10x2; @@ -3607,7 +3607,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sthil: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -3638,7 +3638,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sthiq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -3669,7 +3669,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stlol: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -3700,7 +3700,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stloq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; @@ -3731,7 +3731,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stxb: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3763,7 +3763,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stxl: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3795,7 +3795,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stxq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3827,7 +3827,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stxw: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3859,7 +3859,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_swapq: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_left; UINT f_right; @@ -3892,7 +3892,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_trapa: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; @@ -3916,7 +3916,7 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_xori: { const IDESC *idesc = &sh64_media_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; INT f_imm6; diff --git a/sim/sh64/decode-media.h b/sim/sh64/decode-media.h index 8f317c6..358052f 100644 --- a/sim/sh64/decode-media.h +++ b/sim/sh64/decode-media.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define SH64_MEDIA_DECODE_H extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void sh64_media_init_idesc_table (SIM_CPU *); extern void sh64_media_sem_init_idesc_table (SIM_CPU *); |