opcodes:

	* ppc-opc.c (MO): Make optional.
	(RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
	(tlbwe): Accept for both PPC403 and BOOKE.  Make all operands optional.
gas:
	* tc-ppc.c (md_assemble): Rewrite comment about optional operands
	to indicate that 'all or none' is also handled.  Pluralize a
	word in another comment.
gas/testsuite:
	* gas/ppc/booke.s: Add two more forms of the mbar instruction
	and three forms of the tlbwe instruction.
	* gas/ppc/booke.d: Update to match.

7 files changed, 126 insertions, 86 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2ce547e..677e0d0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2003-12-10  Zack Weinberg  <zack@codesourcery.com>
+
+	* tc-ppc.c (md_assemble): Rewrite comment about optional operands
+	to indicate that 'all or none' is also handled.  Pluralize a
+	word in another comment.
+
 2003-12-10  Paul Brook  <paul@codesourcery.com>
 
 	* config/tc-arm.c (FPU_MAVERICK): Define.
@@ -32,7 +38,7 @@
 2003-12-05  Ricardo Anguiano <anguiano@codesourcery.com>
 	    Mark Mitchell  <mark@codesourcery.com>
 	    Richard Earnshaw  <rearnsha@arm.com>
-	
+
 	Add V6 support.
 	* config/tc-arm.c (ARM_EXT_V6): New macro.
 	(ARM_ARCH_V6): Likewise.
@@ -96,11 +102,11 @@
 
 	* config/tc-sh.c: Add support for sh4a and no-fpu variants.
 	* testsuite/gas/sh/basic.exp: Call tests for sh4a.
-	* testsuite/gas/sh/{err-sh4a-fp.s, err-sh4a.s, 
-	err-sh4al-dsp.s, sh4a-dsp.d, sh4a-dsp.s, sh4a-fp.d, 
+	* testsuite/gas/sh/{err-sh4a-fp.s, err-sh4a.s,
+	err-sh4al-dsp.s, sh4a-dsp.d, sh4a-dsp.s, sh4a-fp.d,
 	sh4a-fp.s, sh4a.d, sh4a.s, sh4al-dsp.d, sh4al-dsp.s:
 	New files, tests for sh4a and related variants.
-	
+
 2003-12-05  Michael Snyder  <msnyder@redhat.com>
 
 	* config/tc-sh.c (md_show_usage): Mention new -isa options.
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 84698be..f4cf419 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -2136,13 +2136,14 @@ md_assemble (str)
 
   /* PowerPC operands are just expressions.  The only real issue is
      that a few operand types are optional.  All cases which might use
-     an optional operand separate the operands only with commas (in
-     some cases parentheses are used, as in ``lwz 1,0(1)'' but such
-     cases never have optional operands).  There is never more than
-     one optional operand for an instruction.  So, before we start
-     seriously parsing the operands, we check to see if we have an
-     optional operand, and, if we do, we count the number of commas to
-     see whether the operand should be omitted.  */
+     an optional operand separate the operands only with commas (in some
+     cases parentheses are used, as in ``lwz 1,0(1)'' but such cases never
+     have optional operands).  Most instructions with optional operands
+     have only one.  Those that have more than one optional operand can
+     take either all their operands or none.  So, before we start seriously
+     parsing the operands, we check to see if we have optional operands,
+     and if we do, we count the number of commas to see which operands
+     have been omitted.  */
   skip_optional = 0;
   for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
     {
@@ -2178,7 +2179,7 @@ md_assemble (str)
 
 	  /* If there are fewer operands in the line then are called
 	     for by the instruction, we want to skip the optional
-	     operand.  */
+	     operands.  */
 	  if (opcount < num_operands_expected)
 	    skip_optional = 1;
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index b8cfb69..8c2996a 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2003-12-10  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/ppc/booke.s: Add two more forms of the mbar instruction
+	and three forms of the tlbwe instruction.
+	* gas/ppc/booke.d: Update to match.
+
 2003-12-10  Paul Brook  <paul@codesourcery.com>
 
 	* gas/arm/arm.exp: Add r15-bad.
@@ -95,13 +101,13 @@
 2003-11-14  Nick Clifton  <nickc@redhat.com>
 
 	* gas/arm/arm7.d: Pass -D instead of -d to objdump in order to
-        display the contents of data fields in the .text section.
-        This change is necessary after the addition of arm elf mapping
-        symbol support to gas.
-        * gas/arm/pic.d: Expect addresses with function name offsets.
-        This change is necessary after the addition of arm elf mapping
-        symbol support to gas.
-        
+	display the contents of data fields in the .text section.
+	This change is necessary after the addition of arm elf mapping
+	symbol support to gas.
+	* gas/arm/pic.d: Expect addresses with function name offsets.
+	This change is necessary after the addition of arm elf mapping
+	symbol support to gas.
+
 2003-11-13  Nick Clifton  <nickc@redhat.com>
 
 	* gas/arm/mapping.s: New test: Source for ARM ELF mapping
@@ -215,10 +221,10 @@
 	* gas/z8k/jr-back.d: New file.
 	* gas/z8k/jr-forw.d: New file.
 	* gas/z8k/jr-back.s: Fix displacement length. Add some more jumps
-	for jr-back.d. 
+	for jr-back.d.
 	* gas/z8k/jr-backf.s: Fix displacement length.
 	* gas/z8k/jr-forw.s: Fix displacement length. Add some more jumps
-	for jr-forw.d. 
+	for jr-forw.d.
 	* gas/z8k/jr-forwf.s: Fix displacement length.
 	* gas/z8k/z8k.exp: Run new tests.
 
@@ -372,11 +378,11 @@
 
 2003-09-01  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 
-        * gas/mips/elf-rel-got-n32.d: Fix ulw and usw patterns for
-        little-endian.
-        * gas/mips/elf-rel-got-n64.d: Likewise.
-        * gas/mips/elf-rel-xgot-n32.d: Likewise.
-        * gas/mips/elf-rel-xgot-n64.d: Likewise.
+	* gas/mips/elf-rel-got-n32.d: Fix ulw and usw patterns for
+	little-endian.
+	* gas/mips/elf-rel-got-n64.d: Likewise.
+	* gas/mips/elf-rel-xgot-n32.d: Likewise.
+	* gas/mips/elf-rel-xgot-n64.d: Likewise.
 
 2003-08-29  Jakub Jelinek  <jakub@redhat.com>
 
diff --git a/gas/testsuite/gas/ppc/booke.d b/gas/testsuite/gas/ppc/booke.d
index 44b74a4..595424c 100644
--- a/gas/testsuite/gas/ppc/booke.d
+++ b/gas/testsuite/gas/ppc/booke.d
@@ -81,59 +81,64 @@ Disassembly of section \.text:
   dc:	7c 09 56 26 	tlbivaxe	r9,r10
   e0:	7c 0b 67 24 	tlbsx	r11,r12
   e4:	7c 0d 77 26 	tlbsxe	r13,r14
+  e8:	7c 00 07 a4 	tlbwe	
+  ec:	7c 00 07 a4 	tlbwe	
+  f0:	7c 21 0f a4 	tlbwe	r1,r1,1
 
-0+00000e8 <branch_target_7>:
-  e8:	7c 22 1b 14 	adde64	r1,r2,r3
-  ec:	7c 85 37 14 	adde64o	r4,r5,r6
-  f0:	7c e8 03 d4 	addme64	r7,r8
-  f4:	7d 2a 07 d4 	addme64o	r9,r10
-  f8:	7d 6c 03 94 	addze64	r11,r12
-  fc:	7d ae 07 94 	addze64o	r13,r14
- 100:	7e 80 04 40 	mcrxr64	cr5
- 104:	7d f0 8b 10 	subfe64	r15,r16,r17
- 108:	7e 53 a7 10 	subfe64o	r18,r19,r20
- 10c:	7e b6 03 d0 	subfme64	r21,r22
- 110:	7e f8 07 d0 	subfme64o	r23,r24
- 114:	7f 3a 03 90 	subfze64	r25,r26
- 118:	7f 7c 07 90 	subfze64o	r27,r28
+0+00000f4 <branch_target_7>:
+  f4:	7c 22 1b 14 	adde64	r1,r2,r3
+  f8:	7c 85 37 14 	adde64o	r4,r5,r6
+  fc:	7c e8 03 d4 	addme64	r7,r8
+ 100:	7d 2a 07 d4 	addme64o	r9,r10
+ 104:	7d 6c 03 94 	addze64	r11,r12
+ 108:	7d ae 07 94 	addze64o	r13,r14
+ 10c:	7e 80 04 40 	mcrxr64	cr5
+ 110:	7d f0 8b 10 	subfe64	r15,r16,r17
+ 114:	7e 53 a7 10 	subfe64o	r18,r19,r20
+ 118:	7e b6 03 d0 	subfme64	r21,r22
+ 11c:	7e f8 07 d0 	subfme64o	r23,r24
+ 120:	7f 3a 03 90 	subfze64	r25,r26
+ 124:	7f 7c 07 90 	subfze64o	r27,r28
 
-0+000011c <branch_target_8>:
- 11c:	e8 22 03 28 	stbe	r1,50\(r2\)
- 120:	e8 64 02 89 	stbue	r3,40\(r4\)
- 124:	7c a6 39 fe 	stbuxe	r5,r6,r7
- 128:	7d 09 51 be 	stbxe	r8,r9,r10
- 12c:	7d 6c 6b ff 	stdcxe\.	r11,r12,r13
- 130:	f9 cf 00 78 	stde	r14,28\(r15\)
- 134:	fa 11 00 59 	stdue	r16,20\(r17\)
- 138:	7e 53 a7 3e 	stdxe	r18,r19,r20
- 13c:	7e b6 bf 7e 	stduxe	r21,r22,r23
- 140:	f8 38 00 3e 	stfde	f1,12\(r24\)
- 144:	f8 59 00 0f 	stfdue	f2,0\(r25\)
- 148:	7c 7a dd be 	stfdxe	f3,r26,r27
- 14c:	7c 9c ed fe 	stfduxe	f4,r28,r29
- 150:	7c be ff be 	stfiwxe	f5,r30,r31
- 154:	f8 de 00 6c 	stfse	f6,24\(r30\)
- 158:	f8 fd 00 5d 	stfsue	f7,20\(r29\)
- 15c:	7d 1c dd 3e 	stfsxe	f8,r28,r27
- 160:	7d 3a cd 7e 	stfsuxe	f9,r26,r25
- 164:	7f 17 b7 3c 	sthbrxe	r24,r23,r22
- 168:	ea b4 01 ea 	sthe	r21,30\(r20\)
- 16c:	ea 72 02 8b 	sthue	r19,40\(r18\)
- 170:	7e 30 7b 7e 	sthuxe	r17,r16,r15
- 174:	7d cd 63 3e 	sthxe	r14,r13,r12
- 178:	7d 6a 4d 3c 	stwbrxe	r11,r10,r9
- 17c:	7d 07 31 3d 	stwcxe\.	r8,r7,r6
- 180:	e8 a4 03 2e 	stwe	r5,50\(r4\)
- 184:	e8 62 02 8f 	stwue	r3,40\(r2\)
- 188:	7c 22 19 7e 	stwuxe	r1,r2,r3
- 18c:	7c 85 31 3e 	stwxe	r4,r5,r6
- 190:	4c 00 00 66 	rfci
- 194:	7c 60 01 06 	wrtee	r3
- 198:	7c 00 81 46 	wrteei	1
- 19c:	7c 85 02 06 	mfdcrx	r4,r5
- 1a0:	7c aa 3a 86 	mfdcr	r5,234
- 1a4:	7c e6 03 06 	mtdcrx	r6,r7
- 1a8:	7d 10 6b 86 	mtdcr	432,r8
- 1ac:	7c 00 04 ac 	msync
- 1b0:	7c 09 55 ec 	dcba	r9,r10
- 1b4:	7c 00 06 ac 	mbar	0
+0+0000128 <branch_target_8>:
+ 128:	e8 22 03 28 	stbe	r1,50\(r2\)
+ 12c:	e8 64 02 89 	stbue	r3,40\(r4\)
+ 130:	7c a6 39 fe 	stbuxe	r5,r6,r7
+ 134:	7d 09 51 be 	stbxe	r8,r9,r10
+ 138:	7d 6c 6b ff 	stdcxe\.	r11,r12,r13
+ 13c:	f9 cf 00 78 	stde	r14,28\(r15\)
+ 140:	fa 11 00 59 	stdue	r16,20\(r17\)
+ 144:	7e 53 a7 3e 	stdxe	r18,r19,r20
+ 148:	7e b6 bf 7e 	stduxe	r21,r22,r23
+ 14c:	f8 38 00 3e 	stfde	f1,12\(r24\)
+ 150:	f8 59 00 0f 	stfdue	f2,0\(r25\)
+ 154:	7c 7a dd be 	stfdxe	f3,r26,r27
+ 158:	7c 9c ed fe 	stfduxe	f4,r28,r29
+ 15c:	7c be ff be 	stfiwxe	f5,r30,r31
+ 160:	f8 de 00 6c 	stfse	f6,24\(r30\)
+ 164:	f8 fd 00 5d 	stfsue	f7,20\(r29\)
+ 168:	7d 1c dd 3e 	stfsxe	f8,r28,r27
+ 16c:	7d 3a cd 7e 	stfsuxe	f9,r26,r25
+ 170:	7f 17 b7 3c 	sthbrxe	r24,r23,r22
+ 174:	ea b4 01 ea 	sthe	r21,30\(r20\)
+ 178:	ea 72 02 8b 	sthue	r19,40\(r18\)
+ 17c:	7e 30 7b 7e 	sthuxe	r17,r16,r15
+ 180:	7d cd 63 3e 	sthxe	r14,r13,r12
+ 184:	7d 6a 4d 3c 	stwbrxe	r11,r10,r9
+ 188:	7d 07 31 3d 	stwcxe\.	r8,r7,r6
+ 18c:	e8 a4 03 2e 	stwe	r5,50\(r4\)
+ 190:	e8 62 02 8f 	stwue	r3,40\(r2\)
+ 194:	7c 22 19 7e 	stwuxe	r1,r2,r3
+ 198:	7c 85 31 3e 	stwxe	r4,r5,r6
+ 19c:	4c 00 00 66 	rfci
+ 1a0:	7c 60 01 06 	wrtee	r3
+ 1a4:	7c 00 81 46 	wrteei	1
+ 1a8:	7c 85 02 06 	mfdcrx	r4,r5
+ 1ac:	7c aa 3a 86 	mfdcr	r5,234
+ 1b0:	7c e6 03 06 	mtdcrx	r6,r7
+ 1b4:	7d 10 6b 86 	mtdcr	432,r8
+ 1b8:	7c 00 04 ac 	msync
+ 1bc:	7c 09 55 ec 	dcba	r9,r10
+ 1c0:	7c 00 06 ac 	mbar	
+ 1c4:	7c 00 06 ac 	mbar	
+ 1c8:	7c 20 06 ac 	mbar	1
diff --git a/gas/testsuite/gas/ppc/booke.s b/gas/testsuite/gas/ppc/booke.s
index f0bbecc..4c40b49 100644
--- a/gas/testsuite/gas/ppc/booke.s
+++ b/gas/testsuite/gas/ppc/booke.s
@@ -72,6 +72,9 @@ branch_target_6:
 	tlbivaxe 9, 10	
 	tlbsx	11, 12
 	tlbsxe	13, 14
+	tlbwe
+	tlbwe	0,0,0
+	tlbwe	1,1,1
 
 branch_target_7:
 	adde64	1, 2, 3
@@ -128,4 +131,6 @@ branch_target_8:
 	mtdcr	432, 8
 	msync
 	dcba	9, 10
+	mbar
 	mbar	0
+	mbar	1
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1d181fd..046e268 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2003-12-10  Zack Weinberg  <zack@codesourcery.com>
+
+	* ppc-opc.c (MO): Make optional.
+	(RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
+	(tlbwe): Accept for both PPC403 and BOOKE.  Make all operands optional.
+
 2003-12-05  Ricardo Anguiano <anguiano@codesourcery.com>
 	    Mark Mitchell  <mark@codesourcery.com>
 	    Richard Earnshaw  <rearnsha@arm.com>
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 0da244c..d011edf 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -344,7 +344,7 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The MO field in an mbar instruction.  */
 #define MO MB6 + 1
-  { 5, 21, 0, 0, 0 },
+  { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 
   /* The NB field in an X form instruction.  The value 32 is stored as
      0.  */
@@ -384,8 +384,12 @@ const struct powerpc_operand powerpc_operands[] =
 #define RAS RAM + 1
   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 
+  /* The RA field of the tlbwe instruction, which is optional.  */
+#define RAO RAS + 1
+  { 5, 16, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+
   /* The RB field in an X, XO, M, or MDS form instruction.  */
-#define RB RAS + 1
+#define RB RAO + 1
 #define RB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 
@@ -413,8 +417,12 @@ const struct powerpc_operand powerpc_operands[] =
 #define RTQ RSQ + 1
   { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
 
+  /* The RS field of the tlbwe instruction, which is optional.  */
+#define RSO RTQ + 1
+  { 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+
   /* The SH field in an X or M form instruction.  */
-#define SH RTQ + 1
+#define SH RSO + 1
 #define SH_MASK (0x1f << 11)
   { 5, 11, 0, 0, 0 },
 
@@ -423,8 +431,12 @@ const struct powerpc_operand powerpc_operands[] =
 #define SH6_MASK ((0x1f << 11) | (1 << 1))
   { 6, 1, insert_sh6, extract_sh6, 0 },
 
+  /* The SH field of the tlbwe instruction, which is optional.  */
+#define SHO SH6 + 1
+  { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
+
   /* The SI field in a D form instruction.  */
-#define SI SH6 + 1
+#define SI SHO + 1
   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 
   /* The SI field in a D form instruction when we accept a wide range
@@ -4256,8 +4268,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "tlbwehi", XTLB(31,978,0), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,	PPC403,		{ RT, RA } },
-{ "tlbwe",   X(31,978),	X_MASK,		BOOKE,		{ 0 } },
-{ "tlbwe",   X(31,978),	X_MASK,		PPC403,		{ RS, RA, SH } },
+{ "tlbwe",   X(31,978),	X_MASK,		PPC403|BOOKE,	{ RSO, RAO, SHO } },
 { "tlbld",   X(31,978),	XRTRA_MASK,	PPC,		{ RB } },
 
 { "icbi",    X(31,982),	XRT_MASK,	PPC,		{ RA, RB } },