diff options
| author | Joseph Myers <joseph@codesourcery.com> | 2009-01-29 11:56:19 +0000 |
|---|---|---|
| committer | Joseph Myers <joseph@codesourcery.com> | 2009-01-29 11:56:19 +0000 |
| commit | fdfde340537dfac5eec37e75399069cb76717c0c (patch) | |
| tree | a74ade99daf4b36a0c8bd05d046025a6e28e8306 | |
| parent | 1c444d06c11062e157693de027f26a6ed2e85119 (diff) | |
| download | gdb-fdfde340537dfac5eec37e75399069cb76717c0c.zip gdb-fdfde340537dfac5eec37e75399069cb76717c0c.tar.gz gdb-fdfde340537dfac5eec37e75399069cb76717c0c.tar.bz2 | |
gas:
2009-01-29 Mark Mitchell <mark@codesourcery.com>
* config/tc-arm.c (BAD_SP): Define.
(s_arm_unwind_fnstart): Use REG_SP.
(s_arm_unwind_setfp): Likewise.
(reject_bad_reg): New macro.
(do_co_reg): Check for bad registers.
(do_co_reg2c): Likewise.
(do_srs): Use REG_SP.
(do_t_add_sub): Check for bad registers.
(do_t_adr): Likewise.
(do_t_arit3): Likewise.
(do_t_arit3c): Likewise.
(do_t_bfc): Likewise.
(do_t_bfi): Likewise.
(do_t_bfx): Likewise.
(do_t_blx): Likewise.
(do_t_bx): Likewise.
(do_t_bxj): Likewise.
(do_t_clz): Likewise.
(do_t_div): Likewise.
(do_t_mla): Likewise.
(do_t_mlal): Likewise.
(do_t_mov_cmp): Likewise.
(do_t_mov16): Likewise.
(do_t_mvn_tst): Likewise.
(do_t_mrs): Likewise.
(do_t_msr): Likewise.
(do_t_mul): Likewise.
(do_t_mull): Likewise.
(do_t_orn): Likewise.
(do_t_pkhbt): Likewise.
(do_t_pld): Likewise.
(do_t_rbit): Likewise.
(do_t_rev): Likewise.
(do_t_rrx): Likewise.
(do_t_rsb): Likewise.
(do_t_shift): Likewise.
(do_t_simd): Likewise.
(do_t_ssat): Likewise.
(do_t_ssat16): Likewise.
(do_t_sxtah): Likewise.
(do_t_sxth): Likewise.
(do_t_tb): Likewise.
(do_t_usat): Likewise.
(do_t_usat16): Likewise.
(nysn_insert_sp): Use REG_SP.
gas/testsuite:
2009-01-29 Mark Mitchell <mark@codesourcery.com>
* gas/arm/copro.s: Avoid using r15 where not permitted.
* gas/arm/copro.d: Adjust accordingly.
* gas/arm/thumb2_bad_reg.s: New.
* gas/arm/thumb2_bad_reg.l: Likewise.
* gas/arm/thumb2_bad_reg.d: Likewise.
| -rw-r--r-- | gas/ChangeLog | 48 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 595 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/copro.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/copro.s | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/thumb2_bad_reg.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/thumb2_bad_reg.l | 781 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/thumb2_bad_reg.s | 969 |
8 files changed, 2273 insertions, 135 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 13aac0f..376e896 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,53 @@ 2009-01-29 Mark Mitchell <mark@codesourcery.com> + * config/tc-arm.c (BAD_SP): Define. + (s_arm_unwind_fnstart): Use REG_SP. + (s_arm_unwind_setfp): Likewise. + (reject_bad_reg): New macro. + (do_co_reg): Check for bad registers. + (do_co_reg2c): Likewise. + (do_srs): Use REG_SP. + (do_t_add_sub): Check for bad registers. + (do_t_adr): Likewise. + (do_t_arit3): Likewise. + (do_t_arit3c): Likewise. + (do_t_bfc): Likewise. + (do_t_bfi): Likewise. + (do_t_bfx): Likewise. + (do_t_blx): Likewise. + (do_t_bx): Likewise. + (do_t_bxj): Likewise. + (do_t_clz): Likewise. + (do_t_div): Likewise. + (do_t_mla): Likewise. + (do_t_mlal): Likewise. + (do_t_mov_cmp): Likewise. + (do_t_mov16): Likewise. + (do_t_mvn_tst): Likewise. + (do_t_mrs): Likewise. + (do_t_msr): Likewise. + (do_t_mul): Likewise. + (do_t_mull): Likewise. + (do_t_orn): Likewise. + (do_t_pkhbt): Likewise. + (do_t_pld): Likewise. + (do_t_rbit): Likewise. + (do_t_rev): Likewise. + (do_t_rrx): Likewise. + (do_t_rsb): Likewise. + (do_t_shift): Likewise. + (do_t_simd): Likewise. + (do_t_ssat): Likewise. + (do_t_ssat16): Likewise. + (do_t_sxtah): Likewise. + (do_t_sxth): Likewise. + (do_t_tb): Likewise. + (do_t_usat): Likewise. + (do_t_usat16): Likewise. + (nysn_insert_sp): Use REG_SP. + +2009-01-29 Mark Mitchell <mark@codesourcery.com> + * config/tc-arm.c (do_t_orn): New function. (do_t_rrx): Likewise. (insns): Add orn and rrx. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index a8fe667..3b13c49 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -660,6 +660,7 @@ struct asm_opcode #define THUMB2_LOAD_BIT 0x00100000 #define BAD_ARGS _("bad arguments to instruction") +#define BAD_SP _("r13 not allowed here") #define BAD_PC _("r15 not allowed here") #define BAD_COND _("instruction cannot be conditional") #define BAD_OVERLAP _("registers may not be the same") @@ -3092,7 +3093,7 @@ s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) unwind.personality_index = -1; unwind.frame_size = 0; unwind.fp_offset = 0; - unwind.fp_reg = 13; + unwind.fp_reg = REG_SP; unwind.fp_used = 0; unwind.sp_restored = 0; } @@ -3805,7 +3806,7 @@ s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) demand_empty_rest_of_line (); - if (sp_reg != 13 && sp_reg != unwind.fp_reg) + if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) { as_bad (_("register must be either sp or set by a previous" "unwind_movsp directive")); @@ -3815,7 +3816,7 @@ s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) /* Don't generate any opcodes, just record the information for later. */ unwind.fp_reg = fp_reg; unwind.fp_used = 1; - if (sp_reg == 13) + if (sp_reg == REG_SP) unwind.fp_offset = unwind.frame_size - offset; else unwind.fp_offset -= offset; @@ -6123,6 +6124,18 @@ parse_operands (char *str, const unsigned char *pattern) } \ } while (0) +/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 + instructions are unpredictable if these registers are used. This + is the BadReg predicate in ARM's Thumb-2 documentation. */ +#define reject_bad_reg(reg) \ + do \ + if (reg == REG_SP || reg == REG_PC) \ + { \ + inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ + return; \ + } \ + while (0) + /* Functions for operand encoding. ARM, then Thumb. */ #define rotate_left(v, n) (v << n | v >> (32 - n)) @@ -6847,9 +6860,30 @@ do_cmp (void) static void do_co_reg (void) { + unsigned Rd; + + Rd = inst.operands[2].reg; + if (thumb_mode) + { + if (inst.instruction == 0xee000010 + || inst.instruction == 0xfe000010) + /* MCR, MCR2 */ + reject_bad_reg (Rd); + else + /* MRC, MRC2 */ + constraint (Rd == REG_SP, BAD_SP); + } + else + { + /* MCR */ + if (inst.instruction == 0xe000010) + constraint (Rd == REG_PC, BAD_PC); + } + + inst.instruction |= inst.operands[0].reg << 8; inst.instruction |= inst.operands[1].imm << 21; - inst.instruction |= inst.operands[2].reg << 12; + inst.instruction |= Rd << 12; inst.instruction |= inst.operands[3].reg << 16; inst.instruction |= inst.operands[4].reg; inst.instruction |= inst.operands[5].imm << 5; @@ -6871,10 +6905,26 @@ do_co_reg (void) static void do_co_reg2c (void) { + unsigned Rd, Rn; + + Rd = inst.operands[2].reg; + Rn = inst.operands[3].reg; + + if (thumb_mode) + { + reject_bad_reg (Rd); + reject_bad_reg (Rn); + } + else + { + constraint (Rd == REG_PC, BAD_PC); + constraint (Rn == REG_PC, BAD_PC); + } + inst.instruction |= inst.operands[0].reg << 8; inst.instruction |= inst.operands[1].imm << 4; - inst.instruction |= inst.operands[2].reg << 12; - inst.instruction |= inst.operands[3].reg << 16; + inst.instruction |= Rd << 12; + inst.instruction |= Rn << 16; inst.instruction |= inst.operands[4].reg; } @@ -7504,10 +7554,10 @@ do_srs (void) if (inst.operands[0].present) { reg = inst.operands[0].reg; - constraint (reg != 13, _("SRS base register must be r13")); + constraint (reg != REG_SP, _("SRS base register must be r13")); } else - reg = 13; + reg = REG_SP; inst.instruction |= reg << 16; inst.instruction |= inst.operands[1].imm; @@ -8397,7 +8447,10 @@ do_t_add_sub_w (void) Rd = inst.operands[0].reg; Rn = inst.operands[1].reg; - constraint (Rd == 15, _("PC not allowed as destination")); + /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this is the + SP-{plus,minute}-immediate form of the instruction. */ + reject_bad_reg (Rd); + inst.instruction |= (Rn << 16) | (Rd << 8); inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; } @@ -8431,6 +8484,8 @@ do_t_add_sub (void) { int add; + constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); + add = (inst.instruction == T_MNEM_add || inst.instruction == T_MNEM_adds); opcode = 0; @@ -8467,6 +8522,7 @@ do_t_add_sub (void) { if (Rd == REG_PC) { + constraint (add, BAD_PC); constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, _("only SUBS PC, LR, #const allowed")); constraint (inst.reloc.exp.X_op != O_constant, @@ -8539,6 +8595,12 @@ do_t_add_sub (void) } } } + + constraint (Rd == REG_PC, BAD_PC); + constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); + constraint (Rs == REG_PC, BAD_PC); + reject_bad_reg (Rn); + /* If we get here, it can't be done in 16 bits. */ constraint (inst.operands[2].shifted && inst.operands[2].immisreg, _("shift must be constant")); @@ -8597,18 +8659,23 @@ do_t_add_sub (void) static void do_t_adr (void) { - if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) + unsigned Rd; + + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + + if (unified_syntax && inst.size_req == 0 && Rd <= 7) { /* Defer to section relaxation. */ inst.relax = inst.instruction; inst.instruction = THUMB_OP16 (inst.instruction); - inst.instruction |= inst.operands[0].reg << 4; + inst.instruction |= Rd << 4; } else if (unified_syntax && inst.size_req != 2) { /* Generate a 32-bit opcode. */ inst.instruction = THUMB_OP32 (inst.instruction); - inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= Rd << 8; inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; inst.reloc.pc_rel = 1; } @@ -8620,7 +8687,7 @@ do_t_adr (void) inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ inst.reloc.pc_rel = 1; - inst.instruction |= inst.operands[0].reg << 4; + inst.instruction |= Rd << 4; } } @@ -8641,6 +8708,11 @@ do_t_arit3 (void) : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ Rn = inst.operands[2].reg; + reject_bad_reg (Rd); + reject_bad_reg (Rs); + if (inst.operands[2].isreg) + reject_bad_reg (Rn); + if (unified_syntax) { if (!inst.operands[2].isreg) @@ -8723,6 +8795,11 @@ do_t_arit3c (void) ? inst.operands[1].reg /* Rd, Rs, foo */ : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rs); + if (inst.operands[2].isreg) + reject_bad_reg (Rn); if (unified_syntax) { @@ -8821,11 +8898,14 @@ do_t_barrier (void) static void do_t_bfc (void) { + unsigned Rd; unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; constraint (msb > 32, _("bit-field extends past end of register")); /* The instruction encoding stores the LSB and MSB, not the LSB and width. */ - inst.instruction |= inst.operands[0].reg << 8; + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + inst.instruction |= Rd << 8; inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; inst.instruction |= (inst.operands[1].imm & 0x03) << 6; inst.instruction |= msb - 1; @@ -8834,19 +8914,28 @@ do_t_bfc (void) static void do_t_bfi (void) { + int Rd, Rn; unsigned int msb; + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + /* #0 in second position is alternative syntax for bfc, which is the same instruction but with REG_PC in the Rm field. */ if (!inst.operands[1].isreg) - inst.operands[1].reg = REG_PC; + Rn = REG_PC; + else + { + Rn = inst.operands[1].reg; + reject_bad_reg (Rn); + } msb = inst.operands[2].imm + inst.operands[3].imm; constraint (msb > 32, _("bit-field extends past end of register")); /* The instruction encoding stores the LSB and MSB, not the LSB and width. */ - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; inst.instruction |= (inst.operands[2].imm & 0x03) << 6; inst.instruction |= msb - 1; @@ -8855,10 +8944,18 @@ do_t_bfi (void) static void do_t_bfx (void) { + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + constraint (inst.operands[2].imm + inst.operands[3].imm > 32, _("bit-field extends past end of register")); - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; inst.instruction |= (inst.operands[2].imm & 0x03) << 6; inst.instruction |= inst.operands[3].imm - 1; @@ -8879,8 +8976,11 @@ do_t_blx (void) { constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); if (inst.operands[0].isreg) - /* We have a register, so this is BLX(2). */ - inst.instruction |= inst.operands[0].reg << 3; + { + constraint (inst.operands[0].reg == REG_PC, BAD_PC); + /* We have a register, so this is BLX(2). */ + inst.instruction |= inst.operands[0].reg << 3; + } else { /* No register. This must be BLX(1). */ @@ -8992,19 +9092,29 @@ do_t_bx (void) static void do_t_bxj (void) { - constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); - if (inst.operands[0].reg == REG_PC) - as_tsktsk (_("use of r15 in bxj is not really useful")); + int Rm; - inst.instruction |= inst.operands[0].reg << 16; + constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); + Rm = inst.operands[0].reg; + reject_bad_reg (Rm); + inst.instruction |= Rm << 16; } static void do_t_clz (void) { - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[1].reg; + unsigned Rd; + unsigned Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rm << 16; + inst.instruction |= Rm; } static void @@ -9080,11 +9190,20 @@ do_t_dbg (void) static void do_t_div (void) { - if (!inst.operands[1].present) - inst.operands[1].reg = inst.operands[0].reg; - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[2].reg; + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rn = (inst.operands[1].present + ? inst.operands[1].reg : Rd); + Rm = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; } static void @@ -9489,24 +9608,53 @@ do_t_ldstt (void) static void do_t_mla (void) { - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[2].reg; - inst.instruction |= inst.operands[3].reg << 12; + unsigned Rd, Rn, Rm, Ra; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + Ra = inst.operands[3].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + reject_bad_reg (Ra); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; + inst.instruction |= Ra << 12; } static void do_t_mlal (void) { - inst.instruction |= inst.operands[0].reg << 12; - inst.instruction |= inst.operands[1].reg << 8; - inst.instruction |= inst.operands[2].reg << 16; - inst.instruction |= inst.operands[3].reg; + unsigned RdLo, RdHi, Rn, Rm; + + RdLo = inst.operands[0].reg; + RdHi = inst.operands[1].reg; + Rn = inst.operands[2].reg; + Rm = inst.operands[3].reg; + + reject_bad_reg (RdLo); + reject_bad_reg (RdHi); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= RdLo << 12; + inst.instruction |= RdHi << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; } static void do_t_mov_cmp (void) { + unsigned Rn, Rm; + + Rn = inst.operands[0].reg; + Rm = inst.operands[1].reg; + if (unified_syntax) { int r0off = (inst.instruction == T_MNEM_mov @@ -9515,7 +9663,7 @@ do_t_mov_cmp (void) bfd_boolean narrow; bfd_boolean low_regs; - low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); + low_regs = (Rn <= 7 && Rm <= 7); opcode = inst.instruction; if (current_it_mask) narrow = opcode != T_MNEM_movs; @@ -9528,13 +9676,36 @@ do_t_mov_cmp (void) /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ if (opcode == T_MNEM_movs && inst.operands[1].isreg && !inst.operands[1].shifted - && inst.operands[0].reg == REG_PC - && inst.operands[1].reg == REG_LR) + && Rn == REG_PC + && Rm == REG_LR) { inst.instruction = T2_SUBS_PC_LR; return; } + if (opcode == T_MNEM_cmp) + { + constraint (Rn == REG_PC, BAD_PC); + reject_bad_reg (Rm); + } + else if (opcode == T_MNEM_mov + || opcode == T_MNEM_movs) + { + if (inst.operands[1].isreg) + { + if (opcode == T_MNEM_movs) + { + reject_bad_reg (Rn); + reject_bad_reg (Rm); + } + else if ((Rn == REG_SP || Rn == REG_PC) + && (Rm == REG_SP || Rm == REG_PC)) + reject_bad_reg (Rm); + } + else + reject_bad_reg (Rn); + } + if (!inst.operands[1].isreg) { /* Immediate operand. */ @@ -9543,7 +9714,7 @@ do_t_mov_cmp (void) if (low_regs && narrow) { inst.instruction = THUMB_OP16 (opcode); - inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= Rn << 8; if (inst.size_req == 2) inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; else @@ -9553,7 +9724,7 @@ do_t_mov_cmp (void) { inst.instruction = THUMB_OP32 (inst.instruction); inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; - inst.instruction |= inst.operands[0].reg << r0off; + inst.instruction |= Rn << r0off; inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; } } @@ -9575,7 +9746,7 @@ do_t_mov_cmp (void) if (!low_regs || inst.operands[1].imm > 7) narrow = FALSE; - if (inst.operands[0].reg != inst.operands[1].reg) + if (Rn != Rm) narrow = FALSE; switch (inst.operands[1].shift_kind) @@ -9599,7 +9770,7 @@ do_t_mov_cmp (void) inst.instruction = opcode; if (narrow) { - inst.instruction |= inst.operands[0].reg; + inst.instruction |= Rn; inst.instruction |= inst.operands[1].imm << 3; } else @@ -9607,8 +9778,8 @@ do_t_mov_cmp (void) if (flags) inst.instruction |= CONDS_BIT; - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= Rn << 8; + inst.instruction |= Rm << 16; inst.instruction |= inst.operands[1].imm; } } @@ -9639,14 +9810,14 @@ do_t_mov_cmp (void) if (narrow) { - inst.instruction |= inst.operands[0].reg; - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= Rn; + inst.instruction |= Rm << 3; inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; } else { inst.instruction = THUMB_OP32 (inst.instruction); - inst.instruction |= inst.operands[0].reg << r0off; + inst.instruction |= Rn << r0off; encode_thumb32_shifted_operand (1); } } @@ -9655,32 +9826,32 @@ do_t_mov_cmp (void) { case T_MNEM_mov: inst.instruction = T_OPCODE_MOV_HR; - inst.instruction |= (inst.operands[0].reg & 0x8) << 4; - inst.instruction |= (inst.operands[0].reg & 0x7); - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= (Rn & 0x8) << 4; + inst.instruction |= (Rn & 0x7); + inst.instruction |= Rm << 3; break; case T_MNEM_movs: /* We know we have low registers at this point. Generate ADD Rd, Rs, #0. */ inst.instruction = T_OPCODE_ADD_I3; - inst.instruction |= inst.operands[0].reg; - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= Rn; + inst.instruction |= Rm << 3; break; case T_MNEM_cmp: if (low_regs) { inst.instruction = T_OPCODE_CMP_LR; - inst.instruction |= inst.operands[0].reg; - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= Rn; + inst.instruction |= Rm << 3; } else { inst.instruction = T_OPCODE_CMP_HR; - inst.instruction |= (inst.operands[0].reg & 0x8) << 4; - inst.instruction |= (inst.operands[0].reg & 0x7); - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= (Rn & 0x8) << 4; + inst.instruction |= (Rn & 0x7); + inst.instruction |= Rm << 3; } break; } @@ -9690,7 +9861,7 @@ do_t_mov_cmp (void) inst.instruction = THUMB_OP16 (inst.instruction); if (inst.operands[1].isreg) { - if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) + if (Rn < 8 && Rm < 8) { /* A move of two lowregs is encoded as ADD Rd, Rs, #0 since a MOV instruction produces unpredictable results. */ @@ -9699,8 +9870,8 @@ do_t_mov_cmp (void) else inst.instruction = T_OPCODE_CMP_LR; - inst.instruction |= inst.operands[0].reg; - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= Rn; + inst.instruction |= Rm << 3; } else { @@ -9713,9 +9884,9 @@ do_t_mov_cmp (void) } else { - constraint (inst.operands[0].reg > 7, + constraint (Rn > 7, _("only lo regs allowed with immediate")); - inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= Rn << 8; inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; } } @@ -9723,6 +9894,7 @@ do_t_mov_cmp (void) static void do_t_mov16 (void) { + unsigned Rd; bfd_vma imm; bfd_boolean top; @@ -9738,7 +9910,10 @@ do_t_mov16 (void) inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; } - inst.instruction |= inst.operands[0].reg << 8; + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + + inst.instruction |= Rd << 8; if (inst.reloc.type == BFD_RELOC_UNUSED) { imm = inst.reloc.exp.X_add_number; @@ -9752,6 +9927,18 @@ do_t_mov16 (void) static void do_t_mvn_tst (void) { + unsigned Rn, Rm; + + Rn = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + if (inst.instruction == T_MNEM_cmp + || inst.instruction == T_MNEM_cmn) + constraint (Rn == REG_PC, BAD_PC); + else + reject_bad_reg (Rn); + reject_bad_reg (Rm); + if (unified_syntax) { int r0off = (inst.instruction == T_MNEM_mvn @@ -9761,7 +9948,7 @@ do_t_mvn_tst (void) if (inst.size_req == 4 || inst.instruction > 0xffff || inst.operands[1].shifted - || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) + || Rn > 7 || Rm > 7) narrow = FALSE; else if (inst.instruction == T_MNEM_cmn) narrow = TRUE; @@ -9777,7 +9964,7 @@ do_t_mvn_tst (void) if (inst.instruction < 0xffff) inst.instruction = THUMB_OP32 (inst.instruction); inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; - inst.instruction |= inst.operands[0].reg << r0off; + inst.instruction |= Rn << r0off; inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; } else @@ -9786,8 +9973,8 @@ do_t_mvn_tst (void) if (narrow) { inst.instruction = THUMB_OP16 (inst.instruction); - inst.instruction |= inst.operands[0].reg; - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= Rn; + inst.instruction |= Rm << 3; } else { @@ -9796,7 +9983,7 @@ do_t_mvn_tst (void) _("shift must be constant")); if (inst.instruction < 0xffff) inst.instruction = THUMB_OP32 (inst.instruction); - inst.instruction |= inst.operands[0].reg << r0off; + inst.instruction |= Rn << r0off; encode_thumb32_shifted_operand (1); } } @@ -9807,18 +9994,19 @@ do_t_mvn_tst (void) || inst.instruction == T_MNEM_mvns, BAD_THUMB32); constraint (!inst.operands[1].isreg || inst.operands[1].shifted, _("unshifted register required")); - constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, + constraint (Rn > 7 || Rm > 7, BAD_HIREG); inst.instruction = THUMB_OP16 (inst.instruction); - inst.instruction |= inst.operands[0].reg; - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= Rn; + inst.instruction |= Rm << 3; } } static void do_t_mrs (void) { + unsigned Rd; int flags; if (do_vfp_nsyn_mrs () == SUCCESS) @@ -9841,7 +10029,10 @@ do_t_mrs (void) _("'CPSR' or 'SPSR' expected")); } - inst.instruction |= inst.operands[0].reg << 8; + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + + inst.instruction |= Rd << 8; inst.instruction |= (flags & SPSR_BIT) >> 2; inst.instruction |= inst.operands[1].imm & 0xff; } @@ -9850,6 +10041,7 @@ static void do_t_msr (void) { int flags; + unsigned Rn; if (do_vfp_nsyn_msr () == SUCCESS) return; @@ -9870,27 +10062,36 @@ do_t_msr (void) "requested special purpose register")); flags |= PSR_f; } + + Rn = inst.operands[1].reg; + reject_bad_reg (Rn); + inst.instruction |= (flags & SPSR_BIT) >> 2; inst.instruction |= (flags & ~SPSR_BIT) >> 8; inst.instruction |= (flags & 0xff); - inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= Rn << 16; } static void do_t_mul (void) { bfd_boolean narrow; + unsigned Rd, Rn, Rm; if (!inst.operands[2].present) inst.operands[2].reg = inst.operands[0].reg; + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + if (unified_syntax) { if (inst.size_req == 4 - || (inst.operands[0].reg != inst.operands[1].reg - && inst.operands[0].reg != inst.operands[2].reg) - || inst.operands[1].reg > 7 - || inst.operands[2].reg > 7) + || (Rd != Rn + && Rd != Rm) + || Rn > 7 + || Rm > 7) narrow = FALSE; else if (inst.instruction == T_MNEM_muls) narrow = (current_it_mask == 0); @@ -9900,7 +10101,7 @@ do_t_mul (void) else { constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); - constraint (inst.operands[1].reg > 7 || inst.operands[2].reg > 7, + constraint (Rn > 7 || Rm > 7, BAD_HIREG); narrow = TRUE; } @@ -9909,12 +10110,12 @@ do_t_mul (void) { /* 16-bit MULS/Conditional MUL. */ inst.instruction = THUMB_OP16 (inst.instruction); - inst.instruction |= inst.operands[0].reg; + inst.instruction |= Rd; - if (inst.operands[0].reg == inst.operands[1].reg) - inst.instruction |= inst.operands[2].reg << 3; - else if (inst.operands[0].reg == inst.operands[2].reg) - inst.instruction |= inst.operands[1].reg << 3; + if (Rd == Rn) + inst.instruction |= Rm << 3; + else if (Rd == Rm) + inst.instruction |= Rn << 3; else constraint (1, _("dest must overlap one source register")); } @@ -9924,21 +10125,37 @@ do_t_mul (void) _("Thumb-2 MUL must not set flags")); /* 32-bit MUL. */ inst.instruction = THUMB_OP32 (inst.instruction); - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[2].reg << 0; + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm << 0; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); } } static void do_t_mull (void) { - inst.instruction |= inst.operands[0].reg << 12; - inst.instruction |= inst.operands[1].reg << 8; - inst.instruction |= inst.operands[2].reg << 16; - inst.instruction |= inst.operands[3].reg; + unsigned RdLo, RdHi, Rn, Rm; - if (inst.operands[0].reg == inst.operands[1].reg) + RdLo = inst.operands[0].reg; + RdHi = inst.operands[1].reg; + Rn = inst.operands[2].reg; + Rm = inst.operands[3].reg; + + reject_bad_reg (RdLo); + reject_bad_reg (RdHi); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= RdLo << 12; + inst.instruction |= RdHi << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; + + if (RdLo == RdHi) as_tsktsk (_("rdhi and rdlo must be different")); } @@ -10022,6 +10239,10 @@ do_t_orn (void) Rd = inst.operands[0].reg; Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; + reject_bad_reg (Rd); + /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ + reject_bad_reg (Rn); + inst.instruction |= Rd << 8; inst.instruction |= Rn << 16; @@ -10035,6 +10256,7 @@ do_t_orn (void) unsigned Rm; Rm = inst.operands[2].reg; + reject_bad_reg (Rm); constraint (inst.operands[2].shifted && inst.operands[2].immisreg, @@ -10046,9 +10268,19 @@ do_t_orn (void) static void do_t_pkhbt (void) { - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[2].reg; + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; if (inst.operands[3].present) { unsigned int val = inst.reloc.exp.X_add_number; @@ -10070,6 +10302,9 @@ do_t_pkhtb (void) static void do_t_pld (void) { + if (inst.operands[0].immisreg) + reject_bad_reg (inst.operands[0].imm); + encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); } @@ -10110,27 +10345,43 @@ do_t_push_pop (void) static void do_t_rbit (void) { - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[1].reg; + unsigned Rd, Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rm << 16; + inst.instruction |= Rm; } static void do_t_rev (void) { - if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 + unsigned Rd, Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + + if (Rd <= 7 && Rm <= 7 && inst.size_req != 4) { inst.instruction = THUMB_OP16 (inst.instruction); - inst.instruction |= inst.operands[0].reg; - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= Rd; + inst.instruction |= Rm << 3; } else if (unified_syntax) { inst.instruction = THUMB_OP32 (inst.instruction); - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[1].reg; + inst.instruction |= Rd << 8; + inst.instruction |= Rm << 16; + inst.instruction |= Rm; } else inst.error = BAD_HIREG; @@ -10144,6 +10395,9 @@ do_t_rrx (void) Rd = inst.operands[0].reg; Rm = inst.operands[1].reg; + reject_bad_reg (Rd); + reject_bad_reg (Rm); + inst.instruction |= Rd << 8; inst.instruction |= Rm; } @@ -10151,13 +10405,18 @@ do_t_rrx (void) static void do_t_rsb (void) { - int Rd, Rs; + unsigned Rd, Rs; Rd = inst.operands[0].reg; Rs = (inst.operands[1].present ? inst.operands[1].reg /* Rd, Rs, foo */ : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ + reject_bad_reg (Rd); + reject_bad_reg (Rs); + if (inst.operands[2].isreg) + reject_bad_reg (inst.operands[2].reg); + inst.instruction |= Rd << 8; inst.instruction |= Rs << 16; if (!inst.operands[2].isreg) @@ -10245,10 +10504,14 @@ do_t_shift (void) if (inst.size_req == 4) narrow = FALSE; + reject_bad_reg (inst.operands[0].reg); + reject_bad_reg (inst.operands[1].reg); + if (!narrow) { if (inst.operands[2].isreg) { + reject_bad_reg (inst.operands[2].reg); inst.instruction = THUMB_OP32 (inst.instruction); inst.instruction |= inst.operands[0].reg << 8; inst.instruction |= inst.operands[1].reg << 16; @@ -10341,9 +10604,19 @@ do_t_shift (void) static void do_t_simd (void) { - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[2].reg; + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; } static void @@ -10361,9 +10634,17 @@ do_t_smc (void) static void do_t_ssat (void) { - inst.instruction |= inst.operands[0].reg << 8; + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + + inst.instruction |= Rd << 8; inst.instruction |= inst.operands[1].imm - 1; - inst.instruction |= inst.operands[2].reg << 16; + inst.instruction |= Rn << 16; if (inst.operands[3].present) { @@ -10384,9 +10665,17 @@ do_t_ssat (void) static void do_t_ssat16 (void) { - inst.instruction |= inst.operands[0].reg << 8; + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + + inst.instruction |= Rd << 8; inst.instruction |= inst.operands[1].imm - 1; - inst.instruction |= inst.operands[2].reg << 16; + inst.instruction |= Rn << 16; } static void @@ -10425,29 +10714,47 @@ do_t_strexd (void) static void do_t_sxtah (void) { - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg << 16; - inst.instruction |= inst.operands[2].reg; + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; inst.instruction |= inst.operands[3].imm << 4; } static void do_t_sxth (void) { + unsigned Rd, Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + if (inst.instruction <= 0xffff && inst.size_req != 4 - && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 + && Rd <= 7 && Rm <= 7 && (!inst.operands[2].present || inst.operands[2].imm == 0)) { inst.instruction = THUMB_OP16 (inst.instruction); - inst.instruction |= inst.operands[0].reg; - inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= Rd; + inst.instruction |= Rm << 3; } else if (unified_syntax) { if (inst.instruction <= 0xffff) inst.instruction = THUMB_OP32 (inst.instruction); - inst.instruction |= inst.operands[0].reg << 8; - inst.instruction |= inst.operands[1].reg; + inst.instruction |= Rd << 8; + inst.instruction |= Rm; inst.instruction |= inst.operands[2].imm << 4; } else @@ -10467,25 +10774,39 @@ do_t_swi (void) static void do_t_tb (void) { + unsigned Rn, Rm; int half; half = (inst.instruction & 0x10) != 0; constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); constraint (inst.operands[0].immisreg, _("instruction requires register index")); - constraint (inst.operands[0].imm == 15, - _("PC is not a valid index register")); + + Rn = inst.operands[0].reg; + Rm = inst.operands[0].imm; + + constraint (Rn == REG_SP, BAD_SP); + reject_bad_reg (Rm); + constraint (!half && inst.operands[0].shifted, _("instruction does not allow shifted index")); - inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; + inst.instruction |= (Rn << 16) | Rm; } static void do_t_usat (void) { - inst.instruction |= inst.operands[0].reg << 8; + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + + inst.instruction |= Rd << 8; inst.instruction |= inst.operands[1].imm; - inst.instruction |= inst.operands[2].reg << 16; + inst.instruction |= Rn << 16; if (inst.operands[3].present) { @@ -10506,9 +10827,17 @@ do_t_usat (void) static void do_t_usat16 (void) { - inst.instruction |= inst.operands[0].reg << 8; + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + + inst.instruction |= Rd << 8; inst.instruction |= inst.operands[1].imm; - inst.instruction |= inst.operands[2].reg << 16; + inst.instruction |= Rn << 16; } /* Neon instruction encoder helpers. */ @@ -11550,7 +11879,7 @@ nsyn_insert_sp (void) { inst.operands[1] = inst.operands[0]; memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); - inst.operands[0].reg = 13; + inst.operands[0].reg = REG_SP; inst.operands[0].isreg = 1; inst.operands[0].writeback = 1; inst.operands[0].present = 1; diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 6b14d43..9c4a9fb 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,13 @@ 2009-01-29 Mark Mitchell <mark@codesourcery.com> + * gas/arm/copro.s: Avoid using r15 where not permitted. + * gas/arm/copro.d: Adjust accordingly. + * gas/arm/thumb2_bad_reg.s: New. + * gas/arm/thumb2_bad_reg.l: Likewise. + * gas/arm/thumb2_bad_reg.d: Likewise. + +2009-01-29 Mark Mitchell <mark@codesourcery.com> + * gas/arm/thumb32.s: Add tests for orn and rrx. * gas/arm/thumb32.d: Adjust accordingly. * gas/arm/thumb32.l: Likewise. diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d index 37d0f2d..ce79031 100644 --- a/gas/testsuite/gas/arm/copro.d +++ b/gas/testsuite/gas/arm/copro.d @@ -21,7 +21,7 @@ Disassembly of section .text: 0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] 0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\} 0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, pc, cr1, cr2, \{7\} -0+038 <[^>]*> ee21f711 mcr 7, 1, pc, cr1, cr1, \{0\} +0+038 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\} 0+03c <[^>]*> be228519 mcrlt 5, 1, r8, cr2, cr9, \{0\} 0+040 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\} 0+044 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\} diff --git a/gas/testsuite/gas/arm/copro.s b/gas/testsuite/gas/arm/copro.s index e697632..b9ef056 100644 --- a/gas/testsuite/gas/arm/copro.s +++ b/gas/testsuite/gas/arm/copro.s @@ -20,7 +20,7 @@ bar: mrc 2, 3, r5, c1, c2 mrcge p4, 5, r15, cr1, cr2, 7 - mcr p7, 1, r15, cr1, cr1 + mcr p7, 1, r5, cr1, cr1 mcrlt 5, 1, r8, cr2, cr9, 0 @ The following patterns test Addressing Mode 5 "Unindexed" diff --git a/gas/testsuite/gas/arm/thumb2_bad_reg.d b/gas/testsuite/gas/arm/thumb2_bad_reg.d new file mode 100644 index 0000000..8712855 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_bad_reg.d @@ -0,0 +1,3 @@ +#name: Invalid r13/r15 register usage +#as: -march=armv7r +#error-output: thumb2_bad_reg.l diff --git a/gas/testsuite/gas/arm/thumb2_bad_reg.l b/gas/testsuite/gas/arm/thumb2_bad_reg.l new file mode 100644 index 0000000..46b4924 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_bad_reg.l @@ -0,0 +1,781 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `addw r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `addw r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adds.w r15,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r1,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adds.w r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `addw r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r13,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r0,r13,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r13,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adr.w r13,test' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adr.w r15,test' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bfc r13,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bfc r15,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bfi r13,r0,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bfi r15,r0,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bfi r0,r13,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bfi r0,r15,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r0,r1,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `blx r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bxj r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bxj r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `clz r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `clz r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `clz r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `clz r0,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn r15,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `cmn.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn.w r0,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r15,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp r15,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `cmp.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mcr p0,#1,r13,cr0,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mcr p0,#1,r15,cr0,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mcrr p0,#1,r13,r0,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mcrr p0,#1,r15,r0,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mcrr p0,#1,r0,r13,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mcrr p0,#1,r0,r15,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mov.w r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `movs.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `movs.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `movs.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `movs.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mov.w r13,r13' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mov.w r15,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r13,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r15,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `movt r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `movt r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mrc p0,#1,r13,cr0,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mrrc p0,#1,r13,r0,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mrrc p0,#1,r15,r0,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mrrc p0,#1,r0,r13,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mrrc p0,#1,r0,r15,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mrs r13,cpsr' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mrs r15,cpsr' +[^:]*:[0-9]+: Error: r13 not allowed here -- `msr cpsr,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `msr cpsr,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pld \[r0,r13\]' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pld \[r0,r15\]' +[^:]*:[0-9]+: Error: cannot use register index with PC-relative addressing -- `pld \[r15,r0\]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pli \[r0,r13\]' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pli \[r0,r15\]' +[^:]*:[0-9]+: Error: cannot use register index with PC-relative addressing -- `pli \[r15,r0\]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rbit r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rbit r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rbit r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rbit r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rev.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rev.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rev.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rev.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rev16.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rev16.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rev16.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rev16.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `revsh.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `revsh.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `revsh.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `revsh.w r0,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rfedb r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rfeia r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rrx r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rrx r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rrx r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rrx r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb.w r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb.w r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb.w r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb.w r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbfx r13,r0,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbfx r15,r0,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbfx r0,r13,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbfx r0,r15,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat r13,#1,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat r15,#1,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat r0,#1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat r0,#1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat16 r13,#1,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat16 r15,#1,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat16 r0,#1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat16 r0,#1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r13,r0,#1' +[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `sub.w r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `subw r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `subw r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r15,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r1,r15' +[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `sub.w r15,r13,#1' +[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `subs.w r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `subw r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r15,r13,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r0,r13,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r13,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb16 r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb16 r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb16 r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb16 r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxth r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxth r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxth r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxth r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tbb \[r13,r0]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tbb \[r0,r13]' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tbb \[r0,r15]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tbh \[r13,r0]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tbh \[r0,r13]' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tbh \[r0,r15]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tst r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tst r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tst.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tst.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tst.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tst.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ubfx r13,r0,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ubfx r15,r0,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ubfx r0,r13,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ubfx r0,r15,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usat r13,#1,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usat r15,#1,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usat r0,#1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usat r0,#1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usat16 r13,#1,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usat16 r15,#1,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usat16 r0,#1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usat16 r0,#1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb16 r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb16 r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb16 r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb16 r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxth r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxth r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxth r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxth r0,r15' diff --git a/gas/testsuite/gas/arm/thumb2_bad_reg.s b/gas/testsuite/gas/arm/thumb2_bad_reg.s new file mode 100644 index 0000000..77134c3 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_bad_reg.s @@ -0,0 +1,969 @@ + .syntax unified + .text + .align 2 + .thumb + .thumb_func +test: + @ ADC (immediate) + adc r13, r0, #1 + adc r15, r0, #1 + adc r0, r13, #1 + adc r0, r15, #1 + @ ADC (register) + adc.w r13, r0, r1 + adc.w r15, r0, r1 + adc.w r0, r13, r1 + adc.w r0, r15, r1 + adc.w r0, r1, r13 + adc.w r0, r1, r15 + @ ADD (immediate) + add.w r13, r0, #1 + add.w r15, r0, #1 + add.w r0, r13, #1 @ ADD (SP plus immediate) + add.w r0, r15, #1 @ Converted implicitly to ADDW + addw r13, r0, #1 + addw r15, r0, #1 + addw r0, r13, #1 @ ADD (SP plus immediate) + addw r0, r15, #1 @ ADR + @ ADD (register) + add.w r13, r0, r1 + add.w r15, r0, r1 + adds.w r15, r0, r1 + add.w r0, r13, r1 @ ADD (SP plus register) + add.w r0, r15, r1 + add.w r0, r1, r13 + add.w r0, r1, r15 + @ ADD (SP plus immediate) + add.w r0, r13, #1 @ OK + add.w r15, r13, #1 + adds.w r15, r13, #1 + addw r15, r13, #1 + @ ADD (SP plus register) + add.w r15, r13, r0 + add.w r0, r13, r13 + add.w r0, r13, r15 + @ ADR + adr.w r13, test + adr.w r15, test + @ AND (immediate) + and r13, r0, #1 + and r15, r0, #1 + and r0, r13, #1 + and r0, r15, #1 + @ AND (register) + and.w r13, r0, r1 + and.w r15, r0, r1 + and.w r0, r13, r1 + and.w r0, r15, r1 + and.w r0, r1, r13 + and.w r0, r1, r15 + @ ASR (immediate) + asr r13, r0, #1 + asr r15, r0, #1 + asr r0, r13, #1 + asr r0, r15, #1 + @ ASR (register) + asr.w r13, r0, r1 + asr.w r15, r0, r1 + asr.w r0, r13, r1 + asr.w r0, r15, r1 + asr.w r0, r1, r13 + asr.w r0, r1, r15 + @ BFC + bfc r13, #1, #1 + bfc r15, #1, #1 + @ BFI + bfi r13, r0, #1, #1 + bfi r15, r0, #1, #1 + bfi r0, r13, #1, #1 + bfi r0, r15, #1, #1 + @ BIC (immediate) + bic r13, r0, #1 + bic r15, r0, #1 + bic r0, r13, #1 + bic r0, r15, #1 + @ BIC (register) + bic.w r13, r0, r1 + bic.w r15, r0, r1 + bic.w r0, r13, r1 + bic.w r0, r15, r1 + bic.w r0, r1, r13 + bic.w r0, r1, r15 + @ BLX (register) + blx r13 @ OK + blx r15 + @ BXJ + bxj r13 + bxj r15 + @ CLZ + clz r13, r0 + clz r15, r0 + clz r0, r13 + clz r0, r15 + @ CMN (immediate) + cmn r13, #1 @ OK + cmn r15, #1 + @ CMN (register) + cmn.w r13, r0 @ OK + cmn.w r15, r0 + cmn.w r0, r13 + cmn.w r0, r15 + @ CMP (immediate) + cmp.w r13, #1 @ OK + cmp.w r15, #1 + @ CMP (register) + cmp r13, r0 @ OK + cmp r15, r0 + cmp.w r13, r0 @ OK + cmp.w r15, r0 + cmp.w r0, r13 + cmp.w r0, r15 + @ EOR (immediate) + eor r13, r0, #1 + eor r15, r0, #1 + eor r0, r13, #1 + eor r0, r15, #1 + @ EOR (register) + eor.w r13, r0, r1 + eor.w r15, r0, r1 + eor.w r0, r13, r1 + eor.w r0, r15, r1 + eor.w r0, r1, r13 + eor.w r0, r1, r15 + @ LSL (immediate) + lsl r13, r0, #1 + lsl r15, r0, #1 + lsl r0, r13, #1 + lsl r0, r15, #1 + @ LSL (register) + lsl.w r13, r0, r1 + lsl.w r15, r0, r1 + lsl.w r0, r13, r1 + lsl.w r0, r15, r1 + lsl.w r0, r1, r13 + lsl.w r0, r1, r15 + @ LSR (immediate) + lsr r13, r0, #1 + lsr r15, r0, #1 + lsr r0, r13, #1 + lsr r0, r15, #1 + @ LSR (register) + lsr.w r13, r0, r1 + lsr.w r15, r0, r1 + lsr.w r0, r13, r1 + lsr.w r0, r15, r1 + lsr.w r0, r1, r13 + lsr.w r0, r1, r15 + @ MCR + mcr p0, #1, r13, cr0, cr0 + mcr p0, #1, r15, cr0, cr0 @ OK + @ MCRR + mcrr p0, #1, r13, r0, cr0 + mcrr p0, #1, r15, r0, cr0 + mcrr p0, #1, r0, r13, cr0 + mcrr p0, #1, r0, r15, cr0 + @ MLA + mla r13, r0, r0, r0 + mla r15, r0, r0, r0 + mla r0, r13, r0, r0 + mla r0, r15, r0, r0 + mla r0, r0, r13, r0 + mla r0, r0, r15, r0 + mla r0, r0, r0, r13 + mla r0, r0, r0, r15 + @ MLS + mls r13, r0, r0, r0 + mls r15, r0, r0, r0 + mls r0, r13, r0, r0 + mls r0, r15, r0, r0 + mls r0, r0, r13, r0 + mls r0, r0, r15, r0 + mls r0, r0, r0, r13 + mls r0, r0, r0, r15 + @ MOV (immediate) + mov.w r13, #1 + mov.w r15, #1 + @ MOV (register) + mov r13, r0 @ OK + mov r15, r0 @ OK + mov.w r0, r13 @ OK + mov.w r0, r15 @ OK + mov.w r15, r0 @ OK + mov.w r13, r0 @ OK + movs.w r0, r13 + movs.w r0, r15 + movs.w r13, r0 + movs.w r15, r0 + mov.w r13, r13 + mov.w r15, r13 + mov.w r13, r15 + mov.w r15, r15 + @ MOVT + movt r13, #1 + movt r15, #1 + @ MRC + mrc p0, #1, r13, cr0, cr0 + mrc p0, #1, r15, cr0, cr0 @ OK + @ MRCC + mrrc p0, #1, r13, r0, cr0 + mrrc p0, #1, r15, r0, cr0 + mrrc p0, #1, r0, r13, cr0 + mrrc p0, #1, r0, r15, cr0 + @ MRS + mrs r13, cpsr + mrs r15, cpsr + @ MSR (register) + msr cpsr, r13 + msr cpsr, r15 + @ MUL + mul r13, r0, r0 + mul r15, r0, r0 + mul r0, r13, r0 + mul r0, r15, r0 + mul r0, r0, r13 + mul r0, r0, r15 + @ MVN (immediate) + mvn r13, #1 + mvn r15, #1 + @ MVN (register) + mvn.w r13, r0 + mvn.w r15, r0 + mvn.w r0, r13 + mvn.w r0, r15 + @ ORN (immediate) + orn r13, r0, #1 + orn r15, r0, #1 + orn r0, r13, #1 + orn r0, r15, #1 + @ ORN (register) + orn r13, r0, r0 + orn r15, r0, r0 + orn r0, r13, r0 + orn r0, r15, r0 + orn r0, r0, r13 + orn r0, r0, r15 + @ ORR (immediate) + orr r13, r0, #1 + orr r15, r0, #1 + orr r0, r13, #1 + orr r0, r15, #1 + @ ORR (register) + orr r13, r0, r0 + orr r15, r0, r0 + orr r0, r13, r0 + orr r0, r15, r0 + orr r0, r0, r13 + orr r0, r0, r15 + @ PKH + pkhbt r13, r0, r0 + pkhbt r15, r0, r0 + pkhbt r0, r13, r0 + pkhbt r0, r15, r0 + pkhbt r0, r0, r13 + pkhbt r0, r0, r15 + @ PLD (register) + pld [r0, r13] + pld [r0, r15] + pld [r13, r0] @ OK + pld [r15, r0] + @ PLI (register) + pli [r0, r13] + pli [r0, r15] + pli [r13, r0] @ OK + pli [r15, r0] + @ QADD + qadd r13, r0, r0 + qadd r15, r0, r0 + qadd r0, r13, r0 + qadd r0, r15, r0 + qadd r0, r0, r13 + qadd r0, r0, r15 + @ QADD16 + qadd16 r13, r0, r0 + qadd16 r15, r0, r0 + qadd16 r0, r13, r0 + qadd16 r0, r15, r0 + qadd16 r0, r0, r13 + qadd16 r0, r0, r15 + @ QADD8 + qadd8 r13, r0, r0 + qadd8 r15, r0, r0 + qadd8 r0, r13, r0 + qadd8 r0, r15, r0 + qadd8 r0, r0, r13 + qadd8 r0, r0, r15 + @ QASX + qasx r13, r0, r0 + qasx r15, r0, r0 + qasx r0, r13, r0 + qasx r0, r15, r0 + qasx r0, r0, r13 + qasx r0, r0, r15 + @ QDADD + qdadd r13, r0, r0 + qdadd r15, r0, r0 + qdadd r0, r13, r0 + qdadd r0, r15, r0 + qdadd r0, r0, r13 + qdadd r0, r0, r15 + @ QDSUB + qdsub r13, r0, r0 + qdsub r15, r0, r0 + qdsub r0, r13, r0 + qdsub r0, r15, r0 + qdsub r0, r0, r13 + qdsub r0, r0, r15 + @ QSAX + qsax r13, r0, r0 + qsax r15, r0, r0 + qsax r0, r13, r0 + qsax r0, r15, r0 + qsax r0, r0, r13 + qsax r0, r0, r15 + @ QSUB + qsub r13, r0, r0 + qsub r15, r0, r0 + qsub r0, r13, r0 + qsub r0, r15, r0 + qsub r0, r0, r13 + qsub r0, r0, r15 + @ QSUB16 + qsub16 r13, r0, r0 + qsub16 r15, r0, r0 + qsub16 r0, r13, r0 + qsub16 r0, r15, r0 + qsub16 r0, r0, r13 + qsub16 r0, r0, r15 + @ QSUB8 + qsub8 r13, r0, r0 + qsub8 r15, r0, r0 + qsub8 r0, r13, r0 + qsub8 r0, r15, r0 + qsub8 r0, r0, r13 + qsub8 r0, r0, r15 + @ RBIT + rbit r13, r0 + rbit r15, r0 + rbit r0, r13 + rbit r0, r15 + @ REV + rev.w r13, r0 + rev.w r15, r0 + rev.w r0, r13 + rev.w r0, r15 + @ REV16 + rev16.w r13, r0 + rev16.w r15, r0 + rev16.w r0, r13 + rev16.w r0, r15 + @ REVSH + revsh.w r13, r0 + revsh.w r15, r0 + revsh.w r0, r13 + revsh.w r0, r15 + @ RFE + rfedb r15 + rfeia r15 + @ ROR (immediate) + ror r13, r0, #1 + ror r15, r0, #1 + ror r0, r13, #1 + ror r0, r15, #1 + @ ROR (register) + ror.w r13, r0, r1 + ror.w r15, r0, r1 + ror.w r0, r13, r1 + ror.w r0, r15, r1 + ror.w r0, r1, r13 + ror.w r0, r1, r15 + @ RRX + rrx r13, r0 + rrx r15, r0 + rrx r0, r13 + rrx r0, r15 + @ RSB (immediate) + rsb.w r13, r0, #1 + rsb.w r15, r0, #1 + rsb.w r0, r13, #1 + rsb.w r0, r15, #1 + @ RSB (register) + rsb r13, r0, r1 + rsb r15, r0, r1 + rsb r0, r13, r1 + rsb r0, r15, r1 + rsb r0, r1, r13 + rsb r0, r1, r15 + @ SADD16 + sadd16 r13, r0, r0 + sadd16 r15, r0, r0 + sadd16 r0, r13, r0 + sadd16 r0, r15, r0 + sadd16 r0, r0, r13 + sadd16 r0, r0, r15 + @ SADD8 + sadd8 r13, r0, r0 + sadd8 r15, r0, r0 + sadd8 r0, r13, r0 + sadd8 r0, r15, r0 + sadd8 r0, r0, r13 + sadd8 r0, r0, r15 + @ SASX + sasx r13, r0, r0 + sasx r15, r0, r0 + sasx r0, r13, r0 + sasx r0, r15, r0 + sasx r0, r0, r13 + sasx r0, r0, r15 + @ SBC (immediate) + sbc r13, r0, #1 + sbc r15, r0, #1 + sbc r0, r13, #1 + sbc r0, r15, #1 + @ SBC (register) + sbc r13, r0, r1 + sbc r15, r0, r1 + sbc r0, r13, r1 + sbc r0, r15, r1 + sbc r0, r1, r13 + sbc r0, r1, r15 + @ SBFX (immediate) + sbfx r13, r0, #1, #1 + sbfx r15, r0, #1, #1 + sbfx r0, r13, #1, #1 + sbfx r0, r15, #1, #1 + @ SDIV (register) + sdiv r13, r0, r1 + sdiv r15, r0, r1 + sdiv r0, r13, r1 + sdiv r0, r15, r1 + sdiv r0, r1, r13 + sdiv r0, r1, r15 + @ SEL (register) + sel r13, r0, r1 + sel r15, r0, r1 + sel r0, r13, r1 + sel r0, r15, r1 + sel r0, r1, r13 + sel r0, r1, r15 + @ SHADD16 + shadd16 r13, r0, r0 + shadd16 r15, r0, r0 + shadd16 r0, r13, r0 + shadd16 r0, r15, r0 + shadd16 r0, r0, r13 + shadd16 r0, r0, r15 + @ SHADD8 + shadd8 r13, r0, r0 + shadd8 r15, r0, r0 + shadd8 r0, r13, r0 + shadd8 r0, r15, r0 + shadd8 r0, r0, r13 + shadd8 r0, r0, r15 + @ SHASX + shasx r13, r0, r0 + shasx r15, r0, r0 + shasx r0, r13, r0 + shasx r0, r15, r0 + shasx r0, r0, r13 + shasx r0, r0, r15 + @ SHSAX + shsax r13, r0, r0 + shsax r15, r0, r0 + shsax r0, r13, r0 + shsax r0, r15, r0 + shsax r0, r0, r13 + shsax r0, r0, r15 + @ SHSUB16 + shsub16 r13, r0, r0 + shsub16 r15, r0, r0 + shsub16 r0, r13, r0 + shsub16 r0, r15, r0 + shsub16 r0, r0, r13 + shsub16 r0, r0, r15 + @ SHSUB8 + shsub8 r13, r0, r0 + shsub8 r15, r0, r0 + shsub8 r0, r13, r0 + shsub8 r0, r15, r0 + shsub8 r0, r0, r13 + shsub8 r0, r0, r15 + @ SMLABB + smlabb r13, r0, r0, r0 + smlabb r15, r0, r0, r0 + smlabb r0, r13, r0, r0 + smlabb r0, r15, r0, r0 + smlabb r0, r0, r13, r0 + smlabb r0, r0, r15, r0 + smlabb r0, r0, r0, r13 + smlabb r0, r0, r0, r15 + @ SMLAD + smlad r13, r0, r0, r0 + smlad r15, r0, r0, r0 + smlad r0, r13, r0, r0 + smlad r0, r15, r0, r0 + smlad r0, r0, r13, r0 + smlad r0, r0, r15, r0 + smlad r0, r0, r0, r13 + smlad r0, r0, r0, r15 + @ SMLAL + smlal r13, r0, r0, r0 + smlal r15, r0, r0, r0 + smlal r0, r13, r0, r0 + smlal r0, r15, r0, r0 + smlal r0, r0, r13, r0 + smlal r0, r0, r15, r0 + smlal r0, r0, r0, r13 + smlal r0, r0, r0, r15 + @ SMLALBB + smlalbb r13, r0, r0, r0 + smlalbb r15, r0, r0, r0 + smlalbb r0, r13, r0, r0 + smlalbb r0, r15, r0, r0 + smlalbb r0, r0, r13, r0 + smlalbb r0, r0, r15, r0 + smlalbb r0, r0, r0, r13 + smlalbb r0, r0, r0, r15 + @ SMLALD + smlald r13, r0, r0, r0 + smlald r15, r0, r0, r0 + smlald r0, r13, r0, r0 + smlald r0, r15, r0, r0 + smlald r0, r0, r13, r0 + smlald r0, r0, r15, r0 + smlald r0, r0, r0, r13 + smlald r0, r0, r0, r15 + @ SMLAWB + smlawb r13, r0, r0, r0 + smlawb r15, r0, r0, r0 + smlawb r0, r13, r0, r0 + smlawb r0, r15, r0, r0 + smlawb r0, r0, r13, r0 + smlawb r0, r0, r15, r0 + smlawb r0, r0, r0, r13 + smlawb r0, r0, r0, r15 + @ SMLSD + smlsd r13, r0, r0, r0 + smlsd r15, r0, r0, r0 + smlsd r0, r13, r0, r0 + smlsd r0, r15, r0, r0 + smlsd r0, r0, r13, r0 + smlsd r0, r0, r15, r0 + smlsd r0, r0, r0, r13 + smlsd r0, r0, r0, r15 + @ SMLSLD + smlsld r13, r0, r0, r0 + smlsld r15, r0, r0, r0 + smlsld r0, r13, r0, r0 + smlsld r0, r15, r0, r0 + smlsld r0, r0, r13, r0 + smlsld r0, r0, r15, r0 + smlsld r0, r0, r0, r13 + smlsld r0, r0, r0, r15 + @ SMMLA + smmla r13, r0, r0, r0 + smmla r15, r0, r0, r0 + smmla r0, r13, r0, r0 + smmla r0, r15, r0, r0 + smmla r0, r0, r13, r0 + smmla r0, r0, r15, r0 + smmla r0, r0, r0, r13 + smmla r0, r0, r0, r15 + @ SMMLS + smmls r13, r0, r0, r0 + smmls r15, r0, r0, r0 + smmls r0, r13, r0, r0 + smmls r0, r15, r0, r0 + smmls r0, r0, r13, r0 + smmls r0, r0, r15, r0 + smmls r0, r0, r0, r13 + smmls r0, r0, r0, r15 + @ SMMUL + smmul r13, r0, r0 + smmul r15, r0, r0 + smmul r0, r13, r0 + smmul r0, r15, r0 + smmul r0, r0, r13 + smmul r0, r0, r15 + @ SMUAD + smuad r13, r0, r0 + smuad r15, r0, r0 + smuad r0, r13, r0 + smuad r0, r15, r0 + smuad r0, r0, r13 + smuad r0, r0, r15 + @ SMULBB + smulbb r13, r0, r0 + smulbb r15, r0, r0 + smulbb r0, r13, r0 + smulbb r0, r15, r0 + smulbb r0, r0, r13 + smulbb r0, r0, r15 + @ SMULL + smull r13, r0, r0, r0 + smull r15, r0, r0, r0 + smull r0, r13, r0, r0 + smull r0, r15, r0, r0 + smull r0, r0, r13, r0 + smull r0, r0, r15, r0 + smull r0, r0, r0, r13 + smull r0, r0, r0, r15 + @ SMULWB + smulwb r13, r0, r0 + smulwb r15, r0, r0 + smulwb r0, r13, r0 + smulwb r0, r15, r0 + smulwb r0, r0, r13 + smulwb r0, r0, r15 + @ SMUSD + smusd r13, r0, r0 + smusd r15, r0, r0 + smusd r0, r13, r0 + smusd r0, r15, r0 + smusd r0, r0, r13 + smusd r0, r0, r15 + @ SSAT + ssat r13, #1, r0 + ssat r15, #1, r0 + ssat r0, #1, r13 + ssat r0, #1, r15 + @ SSAT16 + ssat16 r13, #1, r0 + ssat16 r15, #1, r0 + ssat16 r0, #1, r13 + ssat16 r0, #1, r15 + @ SSAX + ssax r13, r0, r1 + ssax r15, r0, r1 + ssax r0, r13, r1 + ssax r0, r15, r1 + ssax r0, r1, r13 + ssax r0, r1, r15 + @ SSUB16 + ssub16 r13, r0, r1 + ssub16 r15, r0, r1 + ssub16 r0, r13, r1 + ssub16 r0, r15, r1 + ssub16 r0, r1, r13 + ssub16 r0, r1, r15 + @ SSUB8 + ssub8 r13, r0, r1 + ssub8 r15, r0, r1 + ssub8 r0, r13, r1 + ssub8 r0, r15, r1 + ssub8 r0, r1, r13 + ssub8 r0, r1, r15 + @ SUB (immediate) + sub.w r13, r0, #1 + sub.w r15, r0, #1 + sub.w r0, r13, #1 @ SUB (SP minus immediate) + sub.w r0, r15, #1 @ ADR + subw r13, r0, #1 + subw r15, r0, #1 + subw r0, r13, #1 @ SUB (SP minus immediate) + subw r0, r15, #1 @ ADR + @ SUB (register) + sub.w r13, r0, r1 + sub.w r15, r0, r1 + sub.w r0, r13, r1 @ SUB (SP minus register) + sub.w r0, r15, r1 + sub.w r0, r1, r13 + sub.w r0, r1, r15 + @ SUB (SP minus immediate) + sub.w r0, r13, #1 @ OK + sub.w r15, r13, #1 + subs.w r15, r13, #1 + subw r15, r13, #1 + @ SUB (SP minus register) + sub.w r13, r13, r0 @ OK + sub.w r15, r13, r0 + sub.w r0, r13, r13 + sub.w r0, r13, r15 + @ SXTAB + sxtab r13, r0, r1 + sxtab r15, r0, r1 + sxtab r0, r13, r1 + sxtab r0, r15, r1 + sxtab r0, r1, r13 + sxtab r0, r1, r15 + @ SXTAB16 + sxtab16 r13, r0, r1 + sxtab16 r15, r0, r1 + sxtab16 r0, r13, r1 + sxtab16 r0, r15, r1 + sxtab16 r0, r1, r13 + sxtab16 r0, r1, r15 + @ SXTAH + sxtah r13, r0, r1 + sxtah r15, r0, r1 + sxtah r0, r13, r1 + sxtah r0, r15, r1 + sxtah r0, r1, r13 + sxtah r0, r1, r15 + @ SXTB + sxtb r13, r0 + sxtb r15, r0 + sxtb r0, r13 + sxtb r0, r15 + @ SXTB16 + sxtb16 r13, r0 + sxtb16 r15, r0 + sxtb16 r0, r13 + sxtb16 r0, r15 + @ SXTH + sxth r13, r0 + sxth r15, r0 + sxth r0, r13 + sxth r0, r15 + @ TBB + tbb [r13, r0] + tbb [r15, r0] @ OK + tbb [r0, r13] + tbb [r0, r15] + @ TBH + tbh [r13, r0] + tbh [r15, r0] @ OK + tbh [r0, r13] + tbh [r0, r15] + @ TEQ (immediate) + teq r13, #1 + teq r15, #1 + @ TEQ (register) + teq r13, r0 + teq r15, r0 + teq r0, r13 + teq r0, r15 + @ TST (immediate) + tst r13, #1 + tst r15, #1 + @ TST (register) + tst.w r13, r0 + tst.w r15, r0 + tst.w r0, r13 + tst.w r0, r15 + @ UADD16 + uadd16 r13, r0, r0 + uadd16 r15, r0, r0 + uadd16 r0, r13, r0 + uadd16 r0, r15, r0 + uadd16 r0, r0, r13 + uadd16 r0, r0, r15 + @ UADD8 + uadd8 r13, r0, r0 + uadd8 r15, r0, r0 + uadd8 r0, r13, r0 + uadd8 r0, r15, r0 + uadd8 r0, r0, r13 + uadd8 r0, r0, r15 + @ UASX + uasx r13, r0, r0 + uasx r15, r0, r0 + uasx r0, r13, r0 + uasx r0, r15, r0 + uasx r0, r0, r13 + uasx r0, r0, r15 + @ UBFX (immediate) + ubfx r13, r0, #1, #1 + ubfx r15, r0, #1, #1 + ubfx r0, r13, #1, #1 + ubfx r0, r15, #1, #1 + @ UDIV (register) + udiv r13, r0, r1 + udiv r15, r0, r1 + udiv r0, r13, r1 + udiv r0, r15, r1 + udiv r0, r1, r13 + udiv r0, r1, r15 + @ UHADD16 + uhadd16 r13, r0, r0 + uhadd16 r15, r0, r0 + uhadd16 r0, r13, r0 + uhadd16 r0, r15, r0 + uhadd16 r0, r0, r13 + uhadd16 r0, r0, r15 + @ UHADD8 + uhadd8 r13, r0, r0 + uhadd8 r15, r0, r0 + uhadd8 r0, r13, r0 + uhadd8 r0, r15, r0 + uhadd8 r0, r0, r13 + uhadd8 r0, r0, r15 + @ UHASX + uhasx r13, r0, r0 + uhasx r15, r0, r0 + uhasx r0, r13, r0 + uhasx r0, r15, r0 + uhasx r0, r0, r13 + uhasx r0, r0, r15 + @ UHSAX + uhsax r13, r0, r0 + uhsax r15, r0, r0 + uhsax r0, r13, r0 + uhsax r0, r15, r0 + uhsax r0, r0, r13 + uhsax r0, r0, r15 + @ UHSUB16 + uhsub16 r13, r0, r0 + uhsub16 r15, r0, r0 + uhsub16 r0, r13, r0 + uhsub16 r0, r15, r0 + uhsub16 r0, r0, r13 + uhsub16 r0, r0, r15 + @ UHSUB8 + uhsub8 r13, r0, r0 + uhsub8 r15, r0, r0 + uhsub8 r0, r13, r0 + uhsub8 r0, r15, r0 + uhsub8 r0, r0, r13 + uhsub8 r0, r0, r15 + @ UMAAL + umaal r13, r0, r0, r0 + umaal r15, r0, r0, r0 + umaal r0, r13, r0, r0 + umaal r0, r15, r0, r0 + umaal r0, r0, r13, r0 + umaal r0, r0, r15, r0 + umaal r0, r0, r0, r13 + umaal r0, r0, r0, r15 + @ UMLAL + umlal r13, r0, r0, r0 + umlal r15, r0, r0, r0 + umlal r0, r13, r0, r0 + umlal r0, r15, r0, r0 + umlal r0, r0, r13, r0 + umlal r0, r0, r15, r0 + umlal r0, r0, r0, r13 + umlal r0, r0, r0, r15 + @ UMULL + umull r13, r0, r0, r0 + umull r15, r0, r0, r0 + umull r0, r13, r0, r0 + umull r0, r15, r0, r0 + umull r0, r0, r13, r0 + umull r0, r0, r15, r0 + umull r0, r0, r0, r13 + umull r0, r0, r0, r15 + @ UQADD16 + uqadd16 r13, r0, r0 + uqadd16 r15, r0, r0 + uqadd16 r0, r13, r0 + uqadd16 r0, r15, r0 + uqadd16 r0, r0, r13 + uqadd16 r0, r0, r15 + @ UQADD8 + uqadd8 r13, r0, r0 + uqadd8 r15, r0, r0 + uqadd8 r0, r13, r0 + uqadd8 r0, r15, r0 + uqadd8 r0, r0, r13 + uqadd8 r0, r0, r15 + @ UQASX + uqasx r13, r0, r0 + uqasx r15, r0, r0 + uqasx r0, r13, r0 + uqasx r0, r15, r0 + uqasx r0, r0, r13 + uqasx r0, r0, r15 + @ UQSAX + uqsax r13, r0, r0 + uqsax r15, r0, r0 + uqsax r0, r13, r0 + uqsax r0, r15, r0 + uqsax r0, r0, r13 + uqsax r0, r0, r15 + @ UQSUB16 + uqsub16 r13, r0, r0 + uqsub16 r15, r0, r0 + uqsub16 r0, r13, r0 + uqsub16 r0, r15, r0 + uqsub16 r0, r0, r13 + uqsub16 r0, r0, r15 + @ UQSUB8 + uqsub8 r13, r0, r0 + uqsub8 r15, r0, r0 + uqsub8 r0, r13, r0 + uqsub8 r0, r15, r0 + uqsub8 r0, r0, r13 + uqsub8 r0, r0, r15 + @ USAD8 + usad8 r13, r0, r0 + usad8 r15, r0, r0 + usad8 r0, r13, r0 + usad8 r0, r15, r0 + usad8 r0, r0, r13 + usad8 r0, r0, r15 + @ USADA8 + usada8 r13, r0, r0, r0 + usada8 r15, r0, r0, r0 + usada8 r0, r13, r0, r0 + usada8 r0, r15, r0, r0 + usada8 r0, r0, r13, r0 + usada8 r0, r0, r15, r0 + usada8 r0, r0, r0, r13 + usada8 r0, r0, r0, r15 + @ USAT + usat r13, #1, r0 + usat r15, #1, r0 + usat r0, #1, r13 + usat r0, #1, r15 + @ USAT16 + usat16 r13, #1, r0 + usat16 r15, #1, r0 + usat16 r0, #1, r13 + usat16 r0, #1, r15 + @ USAX + usax r13, r0, r1 + usax r15, r0, r1 + usax r0, r13, r1 + usax r0, r15, r1 + usax r0, r1, r13 + usax r0, r1, r15 + @ USUB16 + usub16 r13, r0, r1 + usub16 r15, r0, r1 + usub16 r0, r13, r1 + usub16 r0, r15, r1 + usub16 r0, r1, r13 + usub16 r0, r1, r15 + @ USUB8 + usub8 r13, r0, r1 + usub8 r15, r0, r1 + usub8 r0, r13, r1 + usub8 r0, r15, r1 + usub8 r0, r1, r13 + usub8 r0, r1, r15 + @ UXTAB + uxtab r13, r0, r1 + uxtab r15, r0, r1 + uxtab r0, r13, r1 + uxtab r0, r15, r1 + uxtab r0, r1, r13 + uxtab r0, r1, r15 + @ UXTAB16 + uxtab16 r13, r0, r1 + uxtab16 r15, r0, r1 + uxtab16 r0, r13, r1 + uxtab16 r0, r15, r1 + uxtab16 r0, r1, r13 + uxtab16 r0, r1, r15 + @ UXTAH + uxtah r13, r0, r1 + uxtah r15, r0, r1 + uxtah r0, r13, r1 + uxtah r0, r15, r1 + uxtah r0, r1, r13 + uxtah r0, r1, r15 + @ UXTB + uxtb r13, r0 + uxtb r15, r0 + uxtb r0, r13 + uxtb r0, r15 + @ UXTB16 + uxtb16 r13, r0 + uxtb16 r15, r0 + uxtb16 r0, r13 + uxtb16 r0, r15 + @ UXTH + uxth r13, r0 + uxth r15, r0 + uxth r0, r13 + uxth r0, r15 |