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authorPaul Brook <paul@codesourcery.com>2008-03-28 18:13:52 +0000
committerPaul Brook <paul@codesourcery.com>2008-03-28 18:13:52 +0000
commit4641781c11cd6f48238c8eaac249d98a84110428 (patch)
tree6397b70e66c61edad7d0359d478098a7e17370a6
parentdf3ac6063598d164bad5c3775c792c0d7b375f09 (diff)
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2008-03-28 Paul Brook <paul@codesourcery.com>
gas/ * config/tc-arm.c (parse_neon_mov): Parse register before immediate to avoid spurious symbols.
-rw-r--r--gas/ChangeLog11
-rw-r--r--gas/config/tc-arm.c20
2 files changed, 18 insertions, 13 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d5a6e2b..8d1b4a2 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2008-03-28 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (parse_neon_mov): Parse register before immediate
+ to avoid spurious symbols.
+
2008-03-28 Nathan Sidwell <nathan@codesourcery.com>
* config/tc-m68k.c (md_convert_frag_1): Replace as_fatal with
@@ -21,15 +26,15 @@
instructions. And call yyerror when comparing PREG with
DREG.
(check_macfunc_option): New.
- (check_macfuncs): Check option by calling check_macfunc_option.
+ (check_macfuncs): Check option by calling check_macfunc_option.
Fix comparison always true warnings. Both scalar instructions
of vector instruction must share the same mode option. Only allow
option mode at the end of the second instruction of the vector.
- (asm_1): Check option by calling check_macfunc_option.
+ (asm_1): Check option by calling check_macfunc_option.
* config/bfin-parse.y (check_macfunc_option): Allow (IU)
option for multiply and multiply-accumulate to data register
- instruction.
+ instruction.
(check_macfuncs): Don't check if accumulator matches the data register
here.
(assign_macfunc): Check if accumulator matches the
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3fbbdeb..8965356 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -5209,16 +5209,6 @@ parse_neon_mov (char **str, int *which_operand)
inst.operands[i].present = 1;
}
}
- else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
- /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
- Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
- Case 10: VMOV.F32 <Sd>, #<imm>
- Case 11: VMOV.F64 <Dd>, #<imm> */
- inst.operands[i].immisfloat = 1;
- else if (parse_big_immediate (&ptr, i) == SUCCESS)
- /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
- Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
- ;
else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
&optype)) != FAIL)
{
@@ -5258,6 +5248,16 @@ parse_neon_mov (char **str, int *which_operand)
inst.operands[i++].present = 1;
}
}
+ else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
+ /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
+ Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
+ Case 10: VMOV.F32 <Sd>, #<imm>
+ Case 11: VMOV.F64 <Dd>, #<imm> */
+ inst.operands[i].immisfloat = 1;
+ else if (parse_big_immediate (&ptr, i) == SUCCESS)
+ /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
+ Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
+ ;
else
{
first_error (_("expected <Rm> or <Dm> or <Qm> operand"));