opcodes/

2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>

	PR gas/15220
	* mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
	Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.

gas/testsuite/
	* gas/mips/loongson-2f.d: Fix expected output for madd.ps,
	msub.ps, nmadd.ps and nmsub.ps.

4 files changed, 19 insertions, 8 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index f6c38f0..2ae3425 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2013-07-25  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* gas/mips/loongson-2f.d: Fix expected output for madd.ps,
+	msub.ps, nmadd.ps and nmsub.ps.
+
 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 
 	* gas/i386/sha.d: New.
diff --git a/gas/testsuite/gas/mips/loongson-2f.d b/gas/testsuite/gas/mips/loongson-2f.d
index a47441a..8d1d8f7 100644
--- a/gas/testsuite/gas/mips/loongson-2f.d
+++ b/gas/testsuite/gas/mips/loongson-2f.d
@@ -28,16 +28,16 @@ Disassembly of section .text:
 [0-9a-f]+ <fpu_insns>:
 .*:	72020818 	madd.s	\$f0,\$f1,\$f2
 .*:	722520d8 	madd.d	\$f3,\$f4,\$f5
-.*:	71683998 	madd.ps	\$f6,\$f7,\$f8
+.*:	72c83998 	madd.ps	\$f6,\$f7,\$f8
 .*:	720b5259 	msub.s	\$f9,\$f10,\$f11
 .*:	722e6b19 	msub.d	\$f12,\$f13,\$f14
-.*:	717183d9 	msub.ps	\$f15,\$f16,\$f17
+.*:	72d183d9 	msub.ps	\$f15,\$f16,\$f17
 .*:	72149c9a 	nmadd.s	\$f18,\$f19,\$f20
 .*:	7237b55a 	nmadd.d	\$f21,\$f22,\$f23
-.*:	717ace1a 	nmadd.ps	\$f24,\$f25,\$f26
+.*:	72dace1a 	nmadd.ps	\$f24,\$f25,\$f26
 .*:	721de6db 	nmsub.s	\$f27,\$f28,\$f29
 .*:	7222081b 	nmsub.d	\$f0,\$f1,\$f2
-.*:	716520db 	nmsub.ps	\$f3,\$f4,\$f5
+.*:	72c520db 	nmsub.ps	\$f3,\$f4,\$f5
 
 [0-9a-f]+ <simd_insns>:
 .*:	4b420802 	packsshb	\$f0,\$f1,\$f2
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a369c44..f8ea1e2 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
+
+	PR gas/15220
+	* mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
+	Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
+
 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 
 	* i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 28aa387..59a63dd 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1073,7 +1073,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd.s",		"D,S,T",	0x4600001c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,	     0,		EE,		0,	0 },
 {"madd.ps",		"D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I5_33,		0,	0 },
 {"madd.ps",		"D,S,T",	0x45600018, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	     0,		IL2E,		0,	0 },
-{"madd.ps",		"D,S,T",	0x71600018, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	     0,		IL2F,		0,	0 },
+{"madd.ps",		"D,S,T",	0x72c00018, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	     0,		IL2F,		0,	0 },
 {"madd",		"s,t",		0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1,		0,	0 },
 {"madd",		"s,t",		0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55,	0,	0 },
 {"madd",		"s,t",		0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1,		0,	0 },
@@ -1197,7 +1197,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.s",		"D,S,T",	0x4600001d, 0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,		EE,		0,	0 },
 {"msub.ps",		"D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5_33,		0,	0 },
 {"msub.ps",		"D,S,T",	0x45600019, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
-{"msub.ps",		"D,S,T",	0x71600019, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F,		0,	0 },
+{"msub.ps",		"D,S,T",	0x72c00019, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F,		0,	0 },
 {"msub",		"s,t",		0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1,		0,	0 },
 {"msub",		"s,t",		0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55,	0,	0 },
 {"msub",		"7,s,t",	0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,		D32,	0 },
@@ -1321,7 +1321,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nmadd.s",		"D,S,T",	0x7200001a, 0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,		IL2F,		0,	0 },
 {"nmadd.ps",		"D,R,S,T",	0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5_33,		0,	0 },
 {"nmadd.ps",		"D,S,T",	0x4560001a, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
-{"nmadd.ps",		"D,S,T",	0x7160001a, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F,		0,	0 },
+{"nmadd.ps",		"D,S,T",	0x72c0001a, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F,		0,	0 },
 {"nmsub.d",		"D,R,S,T",	0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4_33,		0,	0 },
 {"nmsub.d",		"D,S,T",	0x4620001b, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
 {"nmsub.d",		"D,S,T",	0x7220001b, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F,		0,	0 },
@@ -1330,7 +1330,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nmsub.s",		"D,S,T",	0x7200001b, 0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,		IL2F,		0,	0 },
 {"nmsub.ps",		"D,R,S,T",	0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5_33,		0,	0 },
 {"nmsub.ps",		"D,S,T",	0x4560001b, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
-{"nmsub.ps",		"D,S,T",	0x7160001b, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F,		0,	0 },
+{"nmsub.ps",		"D,S,T",	0x72c0001b, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F,		0,	0 },
 /* nop is at the start of the table.  */
 {"nor",			"d,v,t",	0x00000027, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1,		0,	0 },
 {"nor",			"t,r,I",	0,    (int) M_NOR_I,	INSN_MACRO,		0,		I1,		0,	0 },