diff options
author | Andrew Cagney <cagney@redhat.com> | 1998-02-03 05:39:15 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 1998-02-03 05:39:15 +0000 |
commit | 37379a256bf9e85add0024d7e13f43aa0eba4282 (patch) | |
tree | 19cdf90a93fdfda5365083158138807156b533a6 | |
parent | 229811d19034006249ce7e2e2b76f526557d9cc0 (diff) | |
download | gdb-37379a256bf9e85add0024d7e13f43aa0eba4282.zip gdb-37379a256bf9e85add0024d7e13f43aa0eba4282.tar.gz gdb-37379a256bf9e85add0024d7e13f43aa0eba4282.tar.bz2 |
IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro,
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
-rw-r--r-- | sim/common/ChangeLog | 6 | ||||
-rw-r--r-- | sim/mips/ChangeLog | 41 | ||||
-rw-r--r-- | sim/mips/Makefile.in | 138 | ||||
-rwxr-xr-x | sim/mips/configure | 56 | ||||
-rw-r--r-- | sim/mips/configure.in | 16 | ||||
-rw-r--r-- | sim/mips/interp.c | 38 | ||||
-rw-r--r-- | sim/tic80/ChangeLog | 5 | ||||
-rw-r--r-- | sim/tic80/alu.h | 4 |
8 files changed, 229 insertions, 75 deletions
diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index eb00325..765cc69 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,7 @@ +Tue Feb 3 16:31:56 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-run.c (sim_engine_run): Assume IMEM is 32 bit. + Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> * configure: Regenerated to track ../common/aclocal.m4 changes. @@ -2028,7 +2032,9 @@ Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> * Make-common.in (SIM_EXTRA_DEPS): New config var. (sim_main_headers): Define. (sim-*.o): Depend on $(SIM_EXTRA_DEPS). +start-sanitize-d30v (BUILT_SRC_FROM_COMMON): Move here from ../d30v/Makefile.in. +end-sanitize-d30v (clean): Use it. (sim-utils.o): Add rule for. * sim-utils.o: New file. diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index ba1ba1a..a823f12 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,44 @@ +Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * interp.c (ifetch16): New function. + + * sim-main.h (IMEM32): Rename IMEM. + (IMEM16_IMMED): Define. + (IMEM16): Define. + (DELAY_SLOT): Update. + + * m16run.c (sim_engine_run): New file. + + * m16.igen: All instructions except LB. + (LB): Call do_load_byte. + * mips.igen (do_load_byte): New function. + (LB): Call do_load_byte. + + * mips.igen: Move spec for insn bit size and high bit from here. + * Makefile.in (tmp-igen, tmp-m16): To here. + + * m16.dc: New file, decode mips16 instructions. + + * Makefile.in (SIM_NO_ALL): Define. + (tmp-m16): Generate both 16 bit and 32 bit simulator engines. + +start-sanitize-tx19 + * m16.igen: Mark all mips16 insns as being part of the tx19 insn + set. + +end-sanitize-tx19 +Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * configure.in (mips_fpu_bitsize): For tx39, restrict floating + point unit to 32 bit registers. + * configure: Re-generate. + +Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * configure.in (sim_use_gen): Make IGEN the default simulator + generator for generic 32 and 64 bit mips targets. + * configure: Re-generate. + Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com> * sim-main.h (SizeFGR): Determine from floating-point and not gpr diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in index 608486a..83b89c4 100644 --- a/sim/mips/Makefile.in +++ b/sim/mips/Makefile.in @@ -15,41 +15,31 @@ SIM_IGEN_OBJ = \ idecode.o \ icache.o \ engine.o \ - irun.o + irun.o \ SIM_M16_OBJ = \ - $(SIM_IGEN_OBJ) = \ m16_support.o \ - m16_itable.o \ m16_semantics.o \ m16_idecode.o \ m16_icache.o \ - m16_engine.o \ - m16_irun.o + \ + m32_support.o \ + m32_semantics.o \ + m32_idecode.o \ + m32_icache.o \ + \ + itable.o \ + m16run.o \ SIM_OBJS = \ $(SIM_@sim_gen@_OBJ) \ + $(SIM_NEW_COMMON_OBJS) \ interp.o \ - sim-bits.o \ - sim-load.o \ - sim-utils.o \ sim-hload.o \ - sim-io.o \ - sim-config.o \ - sim-endian.o \ sim-engine.o \ - sim-memopt.o \ sim-stop.o \ sim-resume.o \ sim-reason.o \ - sim-events.o \ - sim-module.o \ - sim-trace.o \ - sim-options.o \ - sim-profile.o \ - sim-core.o \ - sim-watch.o - # List of flags to always pass to $(CC). @@ -77,7 +67,16 @@ SIM_RUN_OBJS = nrun.o ## COMMON_POST_CONFIG_FRAG -interp.o: $(srcdir)/interp.c config.h sim-main.h oengine.c +SIM_NO_INTERP = oengine.c +interp.o: $(srcdir)/interp.c config.h sim-main.h $(SIM_@sim_gen@_INTERP) + + + +# +# Old deprecated generator +# + +SIM_NO_ALL = oengine.c oengine.c: gencode ./gencode @SIMCONF@ > tmp-oengine @@ -95,18 +94,21 @@ getopt1.o: $(srcdir)/../../libiberty/getopt1.c $(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt1.c + ../igen/igen: cd ../igen && $(MAKE) IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries IGEN_INSN=$(srcdir)/mips.igen IGEN_DC=$(srcdir)/mips.dc +M16_DC=$(srcdir)/m16.dc IGEN_INCLUDE=\ $(start-sanitize-r5900) \ $(srcdir)/r5900.igen \ $(end-sanitize-r5900) \ $(start-sanitize-vr5400) \ $(srcdir)/vr5400.igen \ + $(srcdir)/mdmx.igen \ $(end-sanitize-vr5400) \ $(srcdir)/m16.igen @@ -145,6 +147,9 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE) -Wnodiscard \ @sim_igen_flags@ \ -G gen-direct-access \ + -G gen-zero-r0 \ + -B 32 \ + -H 31 \ -i $(IGEN_INSN) \ -o $(IGEN_DC) \ -x \ @@ -188,7 +193,7 @@ itable.o: sim-main.h $(SIM_EXTRA_DEPS) -SIM_M16_ALL = tmp-igen $(SIM_M16_ALL) +SIM_M16_ALL = tmp-m16 BUILT_SRC_FROM_M16 = \ m16_icache.h \ @@ -201,11 +206,20 @@ BUILT_SRC_FROM_M16 = \ m16_model.c \ m16_support.h \ m16_support.c \ - m16_itable.h \ - m16_itable.c \ - m16_engine.h \ - m16_engine.c \ - m16_irun.c + \ + m32_icache.h \ + m32_icache.c \ + m32_idecode.h \ + m32_idecode.c \ + m32_semantics.h \ + m32_semantics.c \ + m32_model.h \ + m32_model.c \ + m32_support.h \ + m32_support.c \ + \ + itable.h \ + itable.c \ $(BUILT_SRC_FROM_M16): tmp-m16 @@ -221,11 +235,14 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE) -I $(srcdir) \ -Werror \ -Wnodiscard \ - -F 16 \ - -M mips16 \ + @sim_m16_flags@ \ -G gen-direct-access \ + -G gen-zero-r0 \ + -B 16 \ + -H 15 \ -i $(IGEN_INSN) \ - -o $(IGEN_DC) \ + -o $(M16_DC) \ + -P m16_ \ -x \ -n m16_icache.h -hc tmp-icache.h \ -n m16_icache.c -c tmp-icache.c \ @@ -237,11 +254,7 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE) -n m16_model.c -m tmp-model.c \ -n m16_support.h -hf tmp-support.h \ -n m16_support.c -f tmp-support.c \ - -n m16_itable.h -ht tmp-itable.h \ - -n m16_itable.c -t tmp-itable.c \ - -n m16_engine.h -he tmp-engine.h \ - -n m16_engine.c -e tmp-engine.c \ - -n m16_irun.c -r tmp-irun.c + # $(srcdir)/../../move-if-change tmp-icache.h m16_icache.h $(srcdir)/../../move-if-change tmp-icache.c m16_icache.c $(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h @@ -252,11 +265,56 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE) $(srcdir)/../../move-if-change tmp-model.c m16_model.c $(srcdir)/../../move-if-change tmp-support.h m16_support.h $(srcdir)/../../move-if-change tmp-support.c m16_support.c - $(srcdir)/../../move-if-change tmp-itable.h m16_itable.h - $(srcdir)/../../move-if-change tmp-itable.c m16_itable.c - $(srcdir)/../../move-if-change tmp-engine.h m16_engine.h - $(srcdir)/../../move-if-change tmp-engine.c m16_engine.c - $(srcdir)/../../move-if-change tmp-irun.c m16_irun.c + ../igen/igen \ + $(IGEN_TRACE) \ + -I $(srcdir) \ + -Werror \ + -Wnodiscard \ + @sim_igen_flags@ \ + -G gen-direct-access \ + -G gen-zero-r0 \ + -B 32 \ + -H 31 \ + -i $(IGEN_INSN) \ + -o $(IGEN_DC) \ + -P m32_ \ + -x \ + -n m32_icache.h -hc tmp-icache.h \ + -n m32_icache.c -c tmp-icache.c \ + -n m32_semantics.h -hs tmp-semantics.h \ + -n m32_semantics.c -s tmp-semantics.c \ + -n m32_idecode.h -hd tmp-idecode.h \ + -n m32_idecode.c -d tmp-idecode.c \ + -n m32_model.h -hm tmp-model.h \ + -n m32_model.c -m tmp-model.c \ + -n m32_support.h -hf tmp-support.h \ + -n m32_support.c -f tmp-support.c \ + # + $(srcdir)/../../move-if-change tmp-icache.h m32_icache.h + $(srcdir)/../../move-if-change tmp-icache.c m32_icache.c + $(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h + $(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c + $(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h + $(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c + $(srcdir)/../../move-if-change tmp-model.h m32_model.h + $(srcdir)/../../move-if-change tmp-model.c m32_model.c + $(srcdir)/../../move-if-change tmp-support.h m32_support.h + $(srcdir)/../../move-if-change tmp-support.c m32_support.c + ../igen/igen \ + $(IGEN_TRACE) \ + -I $(srcdir) \ + -Werror \ + -Wnodiscard \ + -Wnowidth \ + @sim_igen_flags@ @sim_m16_flags@ \ + -G gen-direct-access \ + -G gen-zero-r0 \ + -i $(IGEN_INSN) \ + -n itable.h -ht tmp-itable.h \ + -n itable.c -t tmp-itable.c \ + # + $(srcdir)/../../move-if-change tmp-itable.h itable.h + $(srcdir)/../../move-if-change tmp-itable.c itable.c touch tmp-m16 diff --git a/sim/mips/configure b/sim/mips/configure index 80b7918..46e46f1 100755 --- a/sim/mips/configure +++ b/sim/mips/configure @@ -1620,7 +1620,7 @@ fi -# Ensure a reasonable default simulator is constructed: +# Ensure a reasonable default simulator is constructed: (DEPRECATED) case "${target}" in # start-sanitize-tx19 mipstx19*-*-*) SIMCONF="-mips1 -mcpu=r1900 -mno-fp --warnings";; @@ -1638,6 +1638,7 @@ case "${target}" in esac +# DEPRECATED case "${target}" in # start-sanitize-tx19 mipstx19*-*-*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";; @@ -1647,6 +1648,7 @@ esac + # # Select the byte order of the target # @@ -1712,6 +1714,7 @@ fi + # # Select the bitsize of the target # @@ -1789,14 +1792,19 @@ fi + # # Select the floating hardware support of the target # mips_fpu=HARDWARE_FLOATING_POINT +mips_fpu_bitsize= case "${target}" in # start-sanitize-tx19 mipstx19*-*-*) mips_fpu=SOFT_FLOATING_POINT ;; # end-sanitize-tx19 + mipstx39*-*-*) mips_fpu=HARD_FLOATING_POINT + mips_fpu_bitsize=32 + ;; # start-sanitize-r5900 mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ;; # end-sanitize-r5900 @@ -1807,7 +1815,7 @@ case "${target}" in esac default_sim_float="$mips_fpu" -default_sim_float_bitsize="" +default_sim_float_bitsize="$mips_fpu_bitsize" # Check whether --enable-sim-float or --disable-sim-float was given. if test "${enable_sim_float+set}" = set; then enableval="$enable_sim_float" @@ -1835,6 +1843,7 @@ fi + # # Select the level of SMP support # @@ -1866,24 +1875,31 @@ fi + # # Select the IGEN architecture # -sim_use_gen=NO +sim_use_gen=IGEN sim_igen_machine="-M mipsIV" sim_m16_machine="-M mips16" sim_igen_filter="32,64,f" sim_m16_filter="16" - case "${target}" in # start-sanitize-tx19 mipstx19*-*-*) sim_default_gen=M16 + #sim_use_gen=M16 + sim_use_gen=NO sim_igen_machine="-M tx19" sim_m16_machine="-M tx19" sim_igen_filter="32" sim_m16_filter="16" ;; # end-sanitize-tx19 + mipstx39*-*-*) sim_default_gen=IGEN + sim_use_gen=IGEN + sim_igen_filter="32,f" + sim_igen_machine="-M r3900" + ;; # start-sanitize-r5900 mips64r59*-*-*) sim_default_gen=IGEN sim_use_gen=IGEN @@ -1903,12 +1919,18 @@ case "${target}" in sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5000" # end-sanitize-vr5400 ;; + mips64*-*-*) sim_default_gen=IGEN + sim_igen_filter="32,64,f" + sim_use_gen=IGEN + ;; mips16*-*-*) sim_default_gen=M16 + sim_igen_filter="32,64,f" + sim_m16_filter="16" + sim_use_igen=NO ;; - mips32*-*-*) sim_default_gen=IGEN + mips*-*-*) sim_default_gen=IGEN sim_igen_filter="32,f" - ;; - *) sim_default_gen=IGEN + sim_use_gen=IGEN ;; esac sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}" @@ -1916,6 +1938,8 @@ sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}" + + # # Enable igen # @@ -1942,17 +1966,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:1946: checking for $ac_hdr" >&5 +echo "configure:1970: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1951 "configure" +#line 1975 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1956: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1980: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then rm -rf conftest* @@ -1979,7 +2003,7 @@ fi done echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6 -echo "configure:1983: checking for fabs in -lm" >&5 +echo "configure:2007: checking for fabs in -lm" >&5 ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1987,7 +2011,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lm $LIBS" cat > conftest.$ac_ext <<EOF -#line 1991 "configure" +#line 2015 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -1998,7 +2022,7 @@ int main() { fabs() ; return 0; } EOF -if { (eval echo configure:2002: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then +if { (eval echo configure:2026: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -2028,12 +2052,12 @@ fi for ac_func in aint anint sqrt do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:2032: checking for $ac_func" >&5 +echo "configure:2056: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2037 "configure" +#line 2061 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -2056,7 +2080,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:2060: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then +if { (eval echo configure:2084: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else diff --git a/sim/mips/configure.in b/sim/mips/configure.in index cef211d..47f9a6a 100644 --- a/sim/mips/configure.in +++ b/sim/mips/configure.in @@ -85,10 +85,14 @@ SIM_AC_OPTION_BITSIZE($mips_bitsize,$mips_msb) # Select the floating hardware support of the target # mips_fpu=HARDWARE_FLOATING_POINT +mips_fpu_bitsize= case "${target}" in # start-sanitize-tx19 mipstx19*-*-*) mips_fpu=SOFT_FLOATING_POINT ;; # end-sanitize-tx19 + mipstx39*-*-*) mips_fpu=HARD_FLOATING_POINT + mips_fpu_bitsize=32 + ;; # start-sanitize-r5900 mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ;; # end-sanitize-r5900 @@ -97,7 +101,7 @@ case "${target}" in mips*-*-*) mips_fpu=HARD_FLOATING_POINT ;; *) mips_fpu=HARD_FLOATING_POINT ;; esac -SIM_AC_OPTION_FLOAT($mips_fpu) +SIM_AC_OPTION_FLOAT($mips_fpu,$mips_fpu_bitsize) @@ -117,7 +121,7 @@ SIM_AC_OPTION_SMP($mips_smp) # # Select the IGEN architecture # -sim_use_gen=NO +sim_use_gen=IGEN sim_igen_machine="-M mipsIV" sim_m16_machine="-M mips16" sim_igen_filter="32,64,f" @@ -125,12 +129,19 @@ sim_m16_filter="16" case "${target}" in # start-sanitize-tx19 mipstx19*-*-*) sim_default_gen=M16 + #sim_use_gen=M16 + sim_use_gen=NO sim_igen_machine="-M tx19" sim_m16_machine="-M tx19" sim_igen_filter="32" sim_m16_filter="16" ;; # end-sanitize-tx19 + mipstx39*-*-*) sim_default_gen=IGEN + sim_use_gen=IGEN + sim_igen_filter="32,f" + sim_igen_machine="-M r3900" + ;; # start-sanitize-r5900 mips64r59*-*-*) sim_default_gen=IGEN sim_use_gen=IGEN @@ -157,6 +168,7 @@ case "${target}" in mips16*-*-*) sim_default_gen=M16 sim_igen_filter="32,64,f" sim_m16_filter="16" + sim_use_igen=NO ;; mips*-*-*) sim_default_gen=IGEN sim_igen_filter="32,f" diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 6de127a..9045004 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -339,7 +339,6 @@ sim_open (kind, cb, abfd, argv) registers: */ { int rn; -<<<<<<< interp.c for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) { if (rn < 32) @@ -353,20 +352,6 @@ sim_open (kind, cb, abfd, argv) else cpu->register_widths[rn] = 0; } -======= - for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) { - if (rn < 32) - cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; - else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32))) - cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; - else if ((rn >= 33) && (rn <= 37)) - cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; - else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) - cpu->register_widths[rn] = 32; - else - cpu->register_widths[rn] = 0; - } ->>>>>>> 1.94 /* start-sanitize-r5900 */ /* set the 5900 "upper" registers to 64 bits */ @@ -1580,6 +1565,29 @@ ifetch32 (SIM_DESC sd, } +unsigned16 +ifetch16 (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + address_word vaddr) +{ + /* Copy the action of the LW instruction */ + address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); + address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); + unsigned64 value; + address_word paddr; + unsigned16 instruction; + unsigned byte; + int cca; + AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); + paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); + LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); + byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); + instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); + return instruction; +} + + /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ /* Order loads and stores to synchronise shared memory. Perform the action necessary to make the effects of groups of synchronizable diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index a89dd25..6bd219c 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,8 @@ +Tue Feb 3 16:25:47 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * alu.h (IMEM32, IMEM32_IMMED): Rename IMEM and IMEM_IMMED so that + in sync with recent igen change. + Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/tic80/alu.h b/sim/tic80/alu.h index 8d4e38b..4def0ee 100644 --- a/sim/tic80/alu.h +++ b/sim/tic80/alu.h @@ -38,10 +38,10 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Bring data in from the cold */ -#define IMEM(CIA) \ +#define IMEM32(CIA) \ (sim_core_read_aligned_4(STATE_CPU (sd, 0), CIA, sim_core_execute_map, (CIA).ip)) -#define IMEM_IMMED(CIA, N) \ +#define IMEM32_IMMED(CIA, N) \ (sim_core_read_aligned_4 (STATE_CPU (sd, 0), CIA, sim_core_execute_map, (CIA).ip + 4 * (N))) #define MEM(SIGN, EA, NR_BYTES) \ |