[bfd]

	* reloc.c: Remove unused M32C relocs, add BFD_RELOC_M32C_HI8.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.

	* elf32-m32c.c (m32c_elf_howto_table): Add R_M32C_8, R_M32C_LO16,
	R_M32C_HI8, R_M32C_HI16.
	(m32c_reloc_map): Likewise.
	(m32c_elf_relocate_section): Add R_M32C_HI8 and R_M32C_HI16.

[cpu]
	* m32c.opc (parse_unsigned8): Add %dsp8().
	(parse_signed8): Add %hi8().
	(parse_unsigned16): Add %dsp16().
	(parse_signed16): Add %lo16() and %hi16().
	(parse_lab_5_3): Make valuep a bfd_vma *.

[gas]
	* config/tc-m32c.c (md_cgen_lookup_reloc): Add 8 bit operands.
	Support %mod() modifiers from opcodes.
	* doc/c-m32c.texi (M32C-Modifiers): New section.

[include/elf]

	* m32c.h: Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, and R_M32C_HI16.

[opcodes]
	* m32c-asm.c Regenerate.
	* m32c-dis.c Regenerate.

15 files changed, 436 insertions, 77 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index e59ec83..bc71060 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,14 @@
+2005-07-25  DJ Delorie  <dj@redhat.com>
+
+	* reloc.c: Remove unused M32C relocs, add BFD_RELOC_M32C_HI8.
+	* libbfd.h: Regenerate.
+	* bfd-in2.h: Regenerate.
+
+	* elf32-m32c.c (m32c_elf_howto_table): Add R_M32C_8, R_M32C_LO16,
+	R_M32C_HI8, R_M32C_HI16.
+	(m32c_reloc_map): Likewise.
+	(m32c_elf_relocate_section): Add R_M32C_HI8 and R_M32C_HI16.
+
 2005-07-25  Jan Hubicka  <jh@suse.cz>
 	    H.J. Lu  <hongjiu.lu@intel.com>
 
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 7dbfe95..519dce8 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3077,23 +3077,7 @@ of the container.  */
   BFD_RELOC_DLX_JMP26,
 
 /* Renesas M16C/M32C Relocations.  */
-  BFD_RELOC_M16C_8_PCREL8,
-  BFD_RELOC_M16C_16_PCREL8,
-  BFD_RELOC_M16C_8_PCREL16,
-  BFD_RELOC_M16C_8_ELABEL24,
-  BFD_RELOC_M16C_8_ABS16,
-  BFD_RELOC_M16C_16_ABS16,
-  BFD_RELOC_M16C_16_ABS24,
-  BFD_RELOC_M16C_16_ABS32,
-  BFD_RELOC_M16C_24_ABS16,
-  BFD_RELOC_M16C_24_ABS24,
-  BFD_RELOC_M16C_24_ABS32,
-  BFD_RELOC_M16C_32_ABS16,
-  BFD_RELOC_M16C_32_ABS24,
-  BFD_RELOC_M16C_32_ABS32,
-  BFD_RELOC_M16C_40_ABS16,
-  BFD_RELOC_M16C_40_ABS24,
-  BFD_RELOC_M16C_40_ABS32,
+  BFD_RELOC_M32C_HI8,
 
 /* Renesas M32R (formerly Mitsubishi M32R) relocs.
 This is a 24 bit absolute address.  */
diff --git a/bfd/elf32-m32c.c b/bfd/elf32-m32c.c
index 3f9bb4e..35136af 100644
--- a/bfd/elf32-m32c.c
+++ b/bfd/elf32-m32c.c
@@ -132,6 +132,62 @@ static reloc_howto_type m32c_elf_howto_table [] =
 	 0,     		/* src_mask */
 	 0,             	/* dst_mask */
 	 TRUE), 		/* pcrel_offset */
+
+  HOWTO (R_M32C_8,		/* type */
+	 0,			/* rightshift */
+	 0,			/* size (0 = byte, 1 = short, 2 = long) */
+	 8,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_unsigned, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_M32C_8",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,     		/* src_mask */
+	 0x000000ff,		/* dst_mask */
+	 FALSE), 		/* pcrel_offset */
+
+  HOWTO (R_M32C_LO16,		/* type */
+	 0,			/* rightshift */
+	 1,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_M32C_LO16",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,     		/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 FALSE), 		/* pcrel_offset */
+
+  HOWTO (R_M32C_HI8,		/* type */
+	 0,			/* rightshift */
+	 0,			/* size (0 = byte, 1 = short, 2 = long) */
+	 8,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_M32C_HI8",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,     		/* src_mask */
+	 0x000000ff,		/* dst_mask */
+	 FALSE), 		/* pcrel_offset */
+
+  HOWTO (R_M32C_HI16,		/* type */
+	 0,			/* rightshift */
+	 1,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_M32C_HI16",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,     		/* src_mask */
+	 0x0000ffff,		/* dst_mask */
+	 FALSE), 		/* pcrel_offset */
 };
 
 /* Map BFD reloc types to M32C ELF reloc types.  */
@@ -149,7 +205,11 @@ static const struct m32c_reloc_map m32c_reloc_map [] =
   { BFD_RELOC_24,               R_M32C_24 },
   { BFD_RELOC_32,		R_M32C_32 },
   { BFD_RELOC_8_PCREL,          R_M32C_8_PCREL },
-  { BFD_RELOC_16_PCREL,         R_M32C_16_PCREL }
+  { BFD_RELOC_16_PCREL,         R_M32C_16_PCREL },
+  { BFD_RELOC_8,		R_M32C_8 },
+  { BFD_RELOC_LO16,		R_M32C_LO16 },
+  { BFD_RELOC_HI16,		R_M32C_HI16 },
+  { BFD_RELOC_M32C_HI8,		R_M32C_HI8 }
 };
 
 static reloc_howto_type *
@@ -372,6 +432,11 @@ m32c_elf_relocate_section
 	      }
 	  }
 	  break;
+
+	case R_M32C_HI8:
+	case R_M32C_HI16:
+	  relocation >>= 16;
+	  break;
 	}
 
       r = _bfd_final_link_relocate (howto, input_bfd, input_section,
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 2a83aae..6e73163 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1338,23 +1338,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_DLX_HI16_S",
   "BFD_RELOC_DLX_LO16",
   "BFD_RELOC_DLX_JMP26",
-  "BFD_RELOC_M16C_8_PCREL8",
-  "BFD_RELOC_M16C_16_PCREL8",
-  "BFD_RELOC_M16C_8_PCREL16",
-  "BFD_RELOC_M16C_8_ELABEL24",
-  "BFD_RELOC_M16C_8_ABS16",
-  "BFD_RELOC_M16C_16_ABS16",
-  "BFD_RELOC_M16C_16_ABS24",
-  "BFD_RELOC_M16C_16_ABS32",
-  "BFD_RELOC_M16C_24_ABS16",
-  "BFD_RELOC_M16C_24_ABS24",
-  "BFD_RELOC_M16C_24_ABS32",
-  "BFD_RELOC_M16C_32_ABS16",
-  "BFD_RELOC_M16C_32_ABS24",
-  "BFD_RELOC_M16C_32_ABS32",
-  "BFD_RELOC_M16C_40_ABS16",
-  "BFD_RELOC_M16C_40_ABS24",
-  "BFD_RELOC_M16C_40_ABS32",
+  "BFD_RELOC_M32C_HI8",
   "BFD_RELOC_M32R_24",
   "BFD_RELOC_M32R_10_PCREL",
   "BFD_RELOC_M32R_18_PCREL",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index fb8a9db..671746f 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3069,39 +3069,7 @@ ENUMDOC
   DLX relocs
 
 ENUM
-  BFD_RELOC_M16C_8_PCREL8
-ENUMX
-  BFD_RELOC_M16C_16_PCREL8
-ENUMX
-  BFD_RELOC_M16C_8_PCREL16
-ENUMX
-  BFD_RELOC_M16C_8_ELABEL24
-ENUMX
-  BFD_RELOC_M16C_8_ABS16
-ENUMX
-  BFD_RELOC_M16C_16_ABS16
-ENUMX
-  BFD_RELOC_M16C_16_ABS24
-ENUMX
-  BFD_RELOC_M16C_16_ABS32
-ENUMX
-  BFD_RELOC_M16C_24_ABS16
-ENUMX
-  BFD_RELOC_M16C_24_ABS24
-ENUMX
-  BFD_RELOC_M16C_24_ABS32
-ENUMX
-  BFD_RELOC_M16C_32_ABS16
-ENUMX
-  BFD_RELOC_M16C_32_ABS24
-ENUMX
-  BFD_RELOC_M16C_32_ABS32
-ENUMX
-  BFD_RELOC_M16C_40_ABS16
-ENUMX
-  BFD_RELOC_M16C_40_ABS24
-ENUMX
-  BFD_RELOC_M16C_40_ABS32
+  BFD_RELOC_M32C_HI8
 ENUMDOC
   Renesas M16C/M32C Relocations.
 
diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index ca2b7c1..6c9a90d 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,11 @@
+2005-07-25  DJ Delorie  <dj@redhat.com>
+
+	* m32c.opc (parse_unsigned8): Add %dsp8().
+	(parse_signed8): Add %hi8().
+	(parse_unsigned16): Add %dsp16().
+	(parse_signed16): Add %lo16() and %hi16().
+	(parse_lab_5_3): Make valuep a bfd_vma *.
+
 2005-07-18  Nick Clifton  <nickc@redhat.com>
 
 	* m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
diff --git a/cpu/m32c.opc b/cpu/m32c.opc
index 7caf21d..19547ae 100644
--- a/cpu/m32c.opc
+++ b/cpu/m32c.opc
@@ -153,6 +153,28 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp,
   unsigned long value;
   long have_zero = 0;
 
+  if (strncasecmp (*strp, "%dsp8(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_8,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  return _("%dsp8() takes a symbolic address, not a number");
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
   if (strncmp (*strp, "0x0", 3) == 0 
       || (**strp == '0' && *(*strp + 1) != 'x'))
     have_zero = 1;
@@ -201,7 +223,29 @@ parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
 {
   const char *errmsg = 0;
   signed long value;
-  
+
+  if (strncasecmp (*strp, "%hi8(", 5) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 5;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32C_HI8,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  value >>= 16;
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
   PARSE_SIGNED;
 
   if (value <= 255 && value > 127)
@@ -221,7 +265,29 @@ parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp,
   const char *errmsg = 0;
   unsigned long value;
   long have_zero = 0;
- 
+
+  if (strncasecmp (*strp, "%dsp16(", 7) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 7;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  return _("%dsp16() takes a symbolic address, not a number");
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
   /* Don't successfully parse literals beginning with '['.  */
   if (**strp == '[')
     return "Invalid literal"; /* Anything -- will not be seen.  */
@@ -259,6 +325,50 @@ parse_signed16 (CGEN_CPU_DESC cd, const char **strp,
   const char *errmsg = 0;
   signed long value;
 
+  if (strncasecmp (*strp, "%lo16(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  value &= 0xffff;
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
+  if (strncasecmp (*strp, "%hi16(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  value >>= 16;
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
   PARSE_SIGNED;
 
   if (value <= 65535 && value > 32767)
@@ -380,10 +490,10 @@ parse_lab_5_3 (CGEN_CPU_DESC cd,
 	       int opindex ATTRIBUTE_UNUSED,
 	       int opinfo,
 	       enum cgen_parse_operand_result *type_addr,
-	       unsigned long *valuep)
+	       bfd_vma *valuep)
 {
   const char *errmsg = 0;
-  unsigned long value;
+  bfd_vma value;
   enum cgen_parse_operand_result op_res;
 
   errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3,
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9ffaff5..8a6d0c0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2005-07-25  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.c (md_cgen_lookup_reloc): Add 8 bit operands.
+	Support %mod() modifiers from opcodes.
+	* doc/c-m32c.texi (M32C-Modifiers): New section.
+
 2005-07-25  Jan Hubicka  <jh@suse.cz>
 	    H.J. Lu  <hongjiu.lu@intel.com>
 
diff --git a/gas/config/tc-m32c.c b/gas/config/tc-m32c.c
index 1a9ca40..9ccc9a7 100644
--- a/gas/config/tc-m32c.c
+++ b/gas/config/tc-m32c.c
@@ -738,6 +738,27 @@ md_cgen_lookup_reloc (const CGEN_INSN *    insn ATTRIBUTE_UNUSED,
     int offset;
   } op_reloc_table[] = {
 
+    /* Absolute relocs for 8-bit fields.  */
+    { M32C_OPERAND_IMM_8_QI,   BFD_RELOC_8, 1 },
+    { M32C_OPERAND_IMM_16_QI,  BFD_RELOC_8, 2 },
+    { M32C_OPERAND_IMM_24_QI,  BFD_RELOC_8, 3 },
+    { M32C_OPERAND_IMM_32_QI,  BFD_RELOC_8, 4 },
+    { M32C_OPERAND_IMM_40_QI,  BFD_RELOC_8, 5 },
+    { M32C_OPERAND_IMM_48_QI,  BFD_RELOC_8, 6 },
+    { M32C_OPERAND_IMM_56_QI,  BFD_RELOC_8, 7 },
+    { M32C_OPERAND_DSP_8_S8,   BFD_RELOC_8, 1 },
+    { M32C_OPERAND_DSP_16_S8,  BFD_RELOC_8, 2 },
+    { M32C_OPERAND_DSP_24_S8,  BFD_RELOC_8, 3 },
+    { M32C_OPERAND_DSP_32_S8,  BFD_RELOC_8, 4 },
+    { M32C_OPERAND_DSP_40_S8,  BFD_RELOC_8, 5 },
+    { M32C_OPERAND_DSP_48_S8,  BFD_RELOC_8, 6 },
+    { M32C_OPERAND_DSP_8_U8,   BFD_RELOC_8, 1 },
+    { M32C_OPERAND_DSP_16_U8,  BFD_RELOC_8, 2 },
+    { M32C_OPERAND_DSP_24_U8,  BFD_RELOC_8, 3 },
+    { M32C_OPERAND_DSP_32_U8,  BFD_RELOC_8, 4 },
+    { M32C_OPERAND_DSP_40_U8,  BFD_RELOC_8, 5 },
+    { M32C_OPERAND_DSP_48_U8,  BFD_RELOC_8, 6 },
+
     /* Absolute relocs for 16-bit fields.  */
     { M32C_OPERAND_IMM_16_HI,  BFD_RELOC_16, 2 },
     { M32C_OPERAND_IMM_24_HI,  BFD_RELOC_16, 3 },
@@ -777,6 +798,11 @@ md_cgen_lookup_reloc (const CGEN_INSN *    insn ATTRIBUTE_UNUSED,
         {
           fixP->fx_where += or->offset;
           fixP->fx_size -= or->offset;
+
+	  if (fixP->fx_cgen.opinfo
+	      && fixP->fx_cgen.opinfo != BFD_RELOC_NONE)
+	    return fixP->fx_cgen.opinfo;
+
           return or->reloc;
         }
     }
diff --git a/gas/doc/c-m32c.texi b/gas/doc/c-m32c.texi
index 83cda7d..a49fe20 100644
--- a/gas/doc/c-m32c.texi
+++ b/gas/doc/c-m32c.texi
@@ -21,6 +21,7 @@ change the default to the M32C microprocessor.
 
 @menu
 * M32C-Opts::                   M32C Options
+* M32C-Modifiers::              Symbolic Operand Modifiers
 @end menu
  
 @node M32C-Opts
@@ -46,3 +47,70 @@ Assemble M32C instructions.
 Assemble M16C instructions (default).
  
 @end table
+
+@node M32C-Modifiers
+@section Symbolic Operand Modifiers
+
+@cindex M32C modifiers
+@cindex syntax, M32C
+
+The assembler supports several modifiers when using symbol addresses
+in M32C instruction operands.  The general syntax is the following:
+
+@smallexample
+%modifier(symbol)
+@end smallexample
+
+@table @code
+@cindex symbol modifiers
+
+@item %dsp8
+@itemx %dsp16
+
+These modifiers override the assembler's assumptions about how big a
+symbol's address is.  Normally, when it sees an operand like
+@samp{sym[a0]} it assumes @samp{sym} may require the widest
+displacement field (16 bits for @samp{-m16c}, 24 bits for
+@samp{-m32c}).  These modifiers tell it to assume the address will fit
+in an 8 or 16 bit (respectively) unsigned displacement.  Note that, of
+course, if it doesn't actually fit you will get linker errors.  Example:
+
+@smallexample
+mov.w %dsp8(sym)[a0],r1
+mov.b #0,%dsp8(sym)[a0]
+@end smallexample
+
+@item %hi8
+
+This modifier allows you to load bits 16 through 23 of a 24 bit
+address into an 8 bit register.  This is useful with, for example, the
+M16C @samp{smovf} instruction, which expects a 20 bit address in
+@samp{r1h} and @samp{a0}.  Example:
+
+@smallexample
+mov.b #%hi8(sym),r1h
+mov.w #%lo16(sym),a0
+smovf.b
+@end smallexample
+
+@item %lo16
+
+Likewise, this modifier allows you to load bits 0 through 15 of a 24
+bit address into a 16 bit register.
+
+@item %hi16
+
+This modifier allows you to load bits 16 through 31 of a 32 bit
+address into a 16 bit register.  While the M32C family only has 24
+bits of address space, it does support addresses in pairs of 16 bit
+registers (like @samp{a1a0} for the @samp{lde} instruction).  This
+modifier is for loading the upper half in such cases.  Example:
+
+@smallexample
+mov.w #%hi16(sym),a1
+mov.w #%lo16(sym),a0
+@dots{}
+lde.w [a1a0],r1
+@end smallexample
+
+@end table
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 2947b66..b137091 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2005-07-25  DJ Delorie  <dj@redhat.com>
+
+	* m32c.h: Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, and R_M32C_HI16.
+
 2005-07-25  Jan Hubicka  <jh@suse.cz>
 
 	* x86-64.h (SHN_X86_64_LCOMMON): New.
diff --git a/include/elf/m32c.h b/include/elf/m32c.h
index 5d8a9a3..8054173 100644
--- a/include/elf/m32c.h
+++ b/include/elf/m32c.h
@@ -30,6 +30,16 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
      RELOC_NUMBER (R_M32C_32, 3)
      RELOC_NUMBER (R_M32C_8_PCREL, 4)
      RELOC_NUMBER (R_M32C_16_PCREL, 5)
+
+    /* 8 bit unsigned address, used for dsp8[a0] etc */
+     RELOC_NUMBER (R_M32C_8, 6)
+    /* Bits 0..15 of an address, for SMOVF's A0, A1A0, etc. */
+     RELOC_NUMBER (R_M32C_LO16, 7)
+    /* Bits 16..23 of an address, for SMOVF's R1H etc. */
+     RELOC_NUMBER (R_M32C_HI8, 8)
+    /* Bits 16..31 of an address, for LDE's A1A0 etc. */
+     RELOC_NUMBER (R_M32C_HI16, 9)
+
      END_RELOC_NUMBERS (R_M32C_max)
 
 #define EF_M32C_CPU_M16C	0x00000075      /* default */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2a5d475..f764d0e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2005-07-25  DJ Delorie  <dj@redhat.com>
+
+	* m32c-asm.c Regenerate.
+	* m32c-dis.c Regenerate.
+
 2005-07-20  DJ Delorie  <dj@redhat.com>
 
 	* disassemble.c (disassemble_init_for_target): M32C ISAs are
diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c
index 60c1055..1bfa926 100644
--- a/opcodes/m32c-asm.c
+++ b/opcodes/m32c-asm.c
@@ -127,6 +127,28 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp,
   unsigned long value;
   long have_zero = 0;
 
+  if (strncasecmp (*strp, "%dsp8(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_8,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  return _("%dsp8() takes a symbolic address, not a number");
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
   if (strncmp (*strp, "0x0", 3) == 0 
       || (**strp == '0' && *(*strp + 1) != 'x'))
     have_zero = 1;
@@ -175,7 +197,29 @@ parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
 {
   const char *errmsg = 0;
   signed long value;
-  
+
+  if (strncasecmp (*strp, "%hi8(", 5) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 5;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32C_HI8,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  value >>= 16;
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
   PARSE_SIGNED;
 
   if (value <= 255 && value > 127)
@@ -195,7 +239,29 @@ parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp,
   const char *errmsg = 0;
   unsigned long value;
   long have_zero = 0;
- 
+
+  if (strncasecmp (*strp, "%dsp16(", 7) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 7;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  return _("%dsp16() takes a symbolic address, not a number");
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
   /* Don't successfully parse literals beginning with '['.  */
   if (**strp == '[')
     return "Invalid literal"; /* Anything -- will not be seen.  */
@@ -233,6 +299,50 @@ parse_signed16 (CGEN_CPU_DESC cd, const char **strp,
   const char *errmsg = 0;
   signed long value;
 
+  if (strncasecmp (*strp, "%lo16(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  value &= 0xffff;
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
+  if (strncasecmp (*strp, "%hi16(", 6) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+				   & result_type, & value);
+      if (**strp != ')')
+	return _("missing `)'");
+      (*strp) ++;
+
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  value >>= 16;
+	}
+      *valuep = value;
+      return errmsg;
+    }
+
   PARSE_SIGNED;
 
   if (value <= 65535 && value > 32767)
@@ -354,10 +464,10 @@ parse_lab_5_3 (CGEN_CPU_DESC cd,
 	       int opindex ATTRIBUTE_UNUSED,
 	       int opinfo,
 	       enum cgen_parse_operand_result *type_addr,
-	       unsigned long *valuep)
+	       bfd_vma *valuep)
 {
   const char *errmsg = 0;
-  unsigned long value;
+  bfd_vma value;
   enum cgen_parse_operand_result op_res;
 
   errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3,
diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c
index b2ddb16..70dc85f 100644
--- a/opcodes/m32c-dis.c
+++ b/opcodes/m32c-dis.c
@@ -1229,7 +1229,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
 	      break;
 	    }
 	}
-    }
+    } 
 
   /* If we haven't initialized yet, initialize the opcode table.  */
   if (! cd)