Add ColfFire v4 support

author: Nick Clifton <nickc@redhat.com> 2003-10-21 13:28:59 +0000
committer: Nick Clifton <nickc@redhat.com> 2003-10-21 13:28:59 +0000
commit: 3e602632663c14cea25d8b12d1306eccbc1c9be3 (patch)
tree: b81f6d5469007aef81bccd5c8a1e2ff151de70fe
parent: 8b7d96c1c421f4cb319e3a49e943f862171387d6 (diff)
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15 files changed, 896 insertions, 403 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 6e2e095..7ae6b66 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,15 @@
+2003-10-21  Thorsten Brehm  <brehm@gmx.net>
+
+	* archures.c (bfd_default_scan): Add support for mcf528x.
+	* ieee.c (ieee_write_processor): Likewise.
+
+2003-10-21  Peter Barada  <pbarada@mail.wm.sps.mot.com>
+            Bernardo Innocenti  <bernie@develer.com>
+
+	* archures.c: Add MCF528x (MCFv4) support.
+	* bfd/cpu-m68k.c (arch_info_struct): Likewise.
+	* bfd-in2.h: Regenerate.
+
 2003-10-20  Andrew Cagney  <cagney@redhat.com>
 
 	* targets.c: Replace "struct sec" with "struct bfd_section"
diff --git a/bfd/archures.c b/bfd/archures.c
index 271b031..b71434e 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -84,6 +84,7 @@ DESCRIPTION
 .#define bfd_mach_mcf5206e 10
 .#define bfd_mach_mcf5307  11
 .#define bfd_mach_mcf5407  12
+.#define bfd_mach_mcf528x  13
 .  bfd_arch_vax,       {* DEC Vax *}
 .  bfd_arch_i960,      {* Intel 960 *}
 .    {* The order of the following is important.
@@ -959,6 +960,10 @@ bfd_default_scan (const bfd_arch_info_type *info, const char *string)
       arch = bfd_arch_m68k;
       number = bfd_mach_mcf5407;
       break;
+    case 5282:
+      arch = bfd_arch_m68k;
+      number = bfd_mach_mcf528x;
+      break;
 
     case 32000:
       arch = bfd_arch_we32k;
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index e7d25cb..b58d6ca 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1519,6 +1519,7 @@ enum bfd_architecture
 #define bfd_mach_mcf5206e 10
 #define bfd_mach_mcf5307  11
 #define bfd_mach_mcf5407  12
+#define bfd_mach_mcf528x  13
   bfd_arch_vax,       /* DEC Vax */
   bfd_arch_i960,      /* Intel 960 */
     /* The order of the following is important.
diff --git a/bfd/cpu-m68k.c b/bfd/cpu-m68k.c
index 1648340..71c7029 100644
--- a/bfd/cpu-m68k.c
+++ b/bfd/cpu-m68k.c
@@ -1,23 +1,23 @@
 /* BFD library support routines for architectures.
-   Copyright 1990, 1991, 1992, 1993, 1994, 1997, 1998, 2000, 2001, 2002
-   Free Software Foundation, Inc.
+   Copyright 1990, 1991, 1992, 1993, 1994, 1997, 1998, 2000, 2001, 2002,
+   2003 Free Software Foundation, Inc.
    Hacked by Steve Chamberlain of Cygnus Support.
 
-This file is part of BFD, the Binary File Descriptor library.
+   This file is part of BFD, the Binary File Descriptor library.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include "bfd.h"
 #include "sysdep.h"
@@ -28,18 +28,19 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 static const bfd_arch_info_type arch_info_struct[] =
   {
-    N(bfd_mach_m68000, "m68k:68000", FALSE, &arch_info_struct[1]),
-    N(bfd_mach_m68008, "m68k:68008", FALSE, &arch_info_struct[2]),
-    N(bfd_mach_m68010, "m68k:68010", FALSE, &arch_info_struct[3]),
-    N(bfd_mach_m68020, "m68k:68020", FALSE, &arch_info_struct[4]),
-    N(bfd_mach_m68030, "m68k:68030", FALSE, &arch_info_struct[5]),
-    N(bfd_mach_m68040, "m68k:68040", FALSE, &arch_info_struct[6]),
-    N(bfd_mach_cpu32,  "m68k:cpu32", FALSE, &arch_info_struct[7]),
-    N(bfd_mach_mcf5200,"m68k:5200",  FALSE, &arch_info_struct[8]),
-    N(bfd_mach_mcf5206e,"m68k:5206e",FALSE, &arch_info_struct[9]),
-    N(bfd_mach_mcf5307, "m68k:5307", FALSE, &arch_info_struct[10]),
-    N(bfd_mach_mcf5407, "m68k:5407", FALSE, &arch_info_struct[11]),
-    N(bfd_mach_m68060, "m68k:68060", FALSE, 0),
+    N(bfd_mach_m68000,  "m68k:68000", FALSE, &arch_info_struct[1]),
+    N(bfd_mach_m68008,  "m68k:68008", FALSE, &arch_info_struct[2]),
+    N(bfd_mach_m68010,  "m68k:68010", FALSE, &arch_info_struct[3]),
+    N(bfd_mach_m68020,  "m68k:68020", FALSE, &arch_info_struct[4]),
+    N(bfd_mach_m68030,  "m68k:68030", FALSE, &arch_info_struct[5]),
+    N(bfd_mach_m68040,  "m68k:68040", FALSE, &arch_info_struct[6]),
+    N(bfd_mach_cpu32,   "m68k:cpu32", FALSE, &arch_info_struct[7]),
+    N(bfd_mach_mcf5200, "m68k:5200",  FALSE, &arch_info_struct[8]),
+    N(bfd_mach_mcf5206e,"m68k:5206e", FALSE, &arch_info_struct[9]),
+    N(bfd_mach_mcf5307, "m68k:5307",  FALSE, &arch_info_struct[10]),
+    N(bfd_mach_mcf5407, "m68k:5407",  FALSE, &arch_info_struct[11]),
+    N(bfd_mach_m68060,  "m68k:68060", FALSE, &arch_info_struct[12]),
+    N(bfd_mach_mcf528x, "m68k:528x",  FALSE, 0),
   };
 
 const bfd_arch_info_type bfd_m68k_arch =
diff --git a/bfd/ieee.c b/bfd/ieee.c
index 4e1631a..0445a6d 100644
--- a/bfd/ieee.c
+++ b/bfd/ieee.c
@@ -3704,6 +3704,7 @@ ieee_write_processor (abfd)
 	  case bfd_mach_mcf5206e:id = "5206e"; break;
 	  case bfd_mach_mcf5307:id = "5307";  break;
 	  case bfd_mach_mcf5407:id = "5407";  break;
+	  case bfd_mach_mcf528x:id = "5282";  break;
 	  }
 
 	if (! ieee_write_id (abfd, id))
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 669faad..0c61c8b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2003-10-21  Peter Barada  <pbarada@mail.wm.sps.mot.com>
+            Bernardo Innocenti  <bernie@develer.com>
+
+	* config/tc-m68k.c: Add MCF528x (MCFv4) support.
+	* config/m68k-parse.h: Likewise.
+	* NEWS: Mention the new support.
+	* doc/c-m68k.texi: Document new processor selection switch.
+
 2003-10-19  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
 
 	* config/tc-mips.c (normalize_constant_expr): New function to fix sign
diff --git a/gas/NEWS b/gas/NEWS
index cec4132..d4c373c 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Support for Motorola ColdFire MCF528x added.
+
 * Added --gstabs+ switch to enable the generation of STABS debug format
   information with GNU extensions.
  
diff --git a/gas/config/m68k-parse.h b/gas/config/m68k-parse.h
index 6482007..c82e69f 100644
--- a/gas/config/m68k-parse.h
+++ b/gas/config/m68k-parse.h
@@ -1,6 +1,6 @@
 /* m68k-parse.h -- header file for m68k assembler
-   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000
-   Free Software Foundation, Inc.
+   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
+   2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -105,14 +105,23 @@ enum m68k_register
   TC,
   SRP,
   URP,
-  BUSCR,			/* 68060 added these */
+  BUSCR,			/* 68060 added these.  */
   PCR,
-  ROMBAR,			/* mcf5200 added these */
+  ROMBAR,			/* mcf5200 added these.  */
   RAMBAR0,
   RAMBAR1,
+  MMUBAR,			/* mcfv4e added these.  */
+  ROMBAR1,			/* mcfv4e added these.  */
+  MPCR, EDRAMBAR, SECMBAR,	/* mcfv4e added these.  */
+  PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
+  PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
+  PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
+  MBAR0, MBAR1,			/* mcfv4e added these.  */
+  ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
+  FLASHBAR, RAMBAR,  		/* mcf528x added these.  */
   MBAR,
 #define last_movec_reg MBAR
-  /* end of movec ordering constraints */
+  /* End of movec ordering constraints.  */
 
   FPI,
   FPS,
diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c
index 5539ed1..5d53fa8 100644
--- a/gas/config/tc-m68k.c
+++ b/gas/config/tc-m68k.c
@@ -1,7 +1,6 @@
 /* tc-m68k.c -- Assemble for the m68k family
    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   2000, 2001, 2002, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -168,10 +167,21 @@ static const enum m68k_register m68060_control_regs[] = {
   0
 };
 static const enum m68k_register mcf_control_regs[] = {
-  CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
+  CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
   RAMBAR0, RAMBAR1, MBAR,
   0
 };
+static const enum m68k_register mcf528x_control_regs[] = {
+  CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
+  0
+};
+static const enum m68k_register mcfv4e_control_regs[] = {
+  CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
+  ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
+  PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
+  PCR3U0, PCR3L0, PCR3U1, PCR3L1,
+  0
+};
 #define cpu32_control_regs m68010_control_regs
 
 static const enum m68k_register *control_regs;
@@ -225,13 +235,14 @@ struct m68k_it
   reloc[5];			/* Five is enough???  */
 };
 
-#define cpu_of_arch(x)		((x) & (m68000up|mcf))
+#define cpu_of_arch(x)		((x) & (m68000up | mcf))
 #define float_of_arch(x)	((x) & mfloat)
 #define mmu_of_arch(x)		((x) & mmmu)
-#define arch_coldfire_p(x)	(((x) & mcf) != 0)
+#define arch_coldfire_p(x)	((x) & mcf)
+#define arch_coldfire_v4e_p(x)	((x) & mcfv4e)
 
 /* Macros for determining if cpu supports a specific addressing mode.  */
-#define HAVE_LONG_BRANCH(x)     ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
+#define HAVE_LONG_BRANCH(x)     ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407|mcfv4e))
 
 static struct m68k_it the_ins;	/* The instruction being assembled.  */
 
@@ -360,19 +371,21 @@ struct m68k_cpu
 
 static const struct m68k_cpu archs[] =
   {
-    { m68000, "68000", 0 },
-    { m68010, "68010", 0 },
-    { m68020, "68020", 0 },
-    { m68030, "68030", 0 },
-    { m68040, "68040", 0 },
-    { m68060, "68060", 0 },
-    { cpu32,  "cpu32", 0 },
-    { m68881, "68881", 0 },
-    { m68851, "68851", 0 },
-    { mcf5200, "5200", 0 },
-    { mcf5206e, "5206e", 0 },
-    { mcf5307, "5307", 0},
-    { mcf5407, "5407", 0},
+    { m68000,  "68000", 0 },
+    { m68010,  "68010", 0 },
+    { m68020,  "68020", 0 },
+    { m68030,  "68030", 0 },
+    { m68040,  "68040", 0 },
+    { m68060,  "68060", 0 },
+    { cpu32,   "cpu32", 0 },
+    { m68881,  "68881", 0 },
+    { m68851,  "68851", 0 },
+    { mcf5200, "5200",  0 },
+    { mcf5206e,"5206e", 0 },
+    { mcf528x, "528x",  0 },
+    { mcf5307, "5307",  0 },
+    { mcf5407, "5407",  0 },
+    { mcfv4e,  "cfv4e", 0 },
     /* Aliases (effectively, so far as gas is concerned) for the above
        cpus.  */
     { m68020, "68k", 1 },
@@ -403,6 +416,7 @@ static const struct m68k_cpu archs[] =
     { mcf5200, "5202", 1 },
     { mcf5200, "5204", 1 },
     { mcf5200, "5206", 1 },
+    { mcf5407, "cfv4", 1 },
   };
 
 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
@@ -1498,6 +1512,24 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+                case 'b':
+                  switch (opP->mode)
+                    {
+                    case IMMED:
+                    case ABSL:
+                    case AREG:
+                    case FPREG:
+                    case CONTROL:
+                    case POST:
+                    case PRE:
+                    case REGLST:
+		      losing++;
+		      break;
+		    default:
+		      break;
+                    }
+                  break;
+
 		case 'C':
 		  if (opP->mode != CONTROL || opP->reg != CCR)
 		    losing++;
@@ -1702,6 +1734,16 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'x':
+		  if (opP->mode != IMMED)
+		    losing++;
+		  else if (opP->disp.exp.X_op != O_constant
+			   || opP->disp.exp.X_add_number < -1
+                           || opP->disp.exp.X_add_number > 7
+                           || opP->disp.exp.X_add_number == 0)
+		    losing++;
+		  break;
+
 		  /* JF these are out of order.  We could put them
 		     in order if we were willing to put up with
 		     bunches of #ifdef m68851s in the code.
@@ -1763,6 +1805,25 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'w':
+		  switch (opP->mode)
+		    {
+		      case IMMED:
+		      case ABSL:
+		      case AREG:
+		      case DREG:
+		      case FPREG:
+		      case CONTROL:
+		      case POST:
+		      case PRE:
+		      case REGLST:
+			losing++;
+			break;
+		      default:
+			break;
+		    }
+		  break;
+
 		case 'X':
 		  if (opP->mode != CONTROL
 		      || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
@@ -1807,6 +1868,18 @@ m68k_ip (instring)
 		    opP->mode = AREG;
 		  break;
 
+		 case 'y':
+		   if (!(opP->mode == AINDR
+			 || (opP->mode == DISP && !(opP->reg == PC ||
+						    opP->reg == ZPC))))
+		     losing++;
+		   break;
+
+		 case 'z':
+		   if (!(opP->mode == AINDR || opP->mode == DISP))
+		     losing++;
+		   break;
+
 		default:
 		  abort ();
 		}
@@ -1833,6 +1906,9 @@ m68k_ip (instring)
 	      cp = buf + strlen (buf);
 	      switch (ok_arch)
 		{
+		case cfloat:
+		  strcpy (cp, _("ColdFire fpu (cfv4e)"));
+		  break;
 		case mfloat:
 		  strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
 		  break;
@@ -1908,12 +1984,16 @@ m68k_ip (instring)
 	case '/':
 	case '<':
 	case '>':
+	case 'b':
 	case 'm':
 	case 'n':
 	case 'o':
 	case 'p':
 	case 'q':
 	case 'v':
+	case 'w':
+	case 'y':
+	case 'z':
 #ifndef NO_68851
 	case '|':
 #endif
@@ -1922,7 +2002,7 @@ m68k_ip (instring)
 	    case IMMED:
 	      tmpreg = 0x3c;	/* 7.4 */
 	      if (strchr ("bwl", s[1]))
-		nextword = get_num (&opP->disp, 80);
+		nextword = get_num (&opP->disp, 90);
 	      else
 		nextword = get_num (&opP->disp, 0);
 	      if (isvar (&opP->disp))
@@ -2034,7 +2114,7 @@ m68k_ip (instring)
 	      break;
 	    case DISP:
 
-	      nextword = get_num (&opP->disp, 80);
+	      nextword = get_num (&opP->disp, 90);
 
 	      if (opP->reg == PC
 		  && ! isvar (&opP->disp)
@@ -2130,9 +2210,9 @@ m68k_ip (instring)
 	    case PRE:
 	    case BASE:
 	      nextword = 0;
-	      baseo = get_num (&opP->disp, 80);
+	      baseo = get_num (&opP->disp, 90);
 	      if (opP->mode == POST || opP->mode == PRE)
-		outro = get_num (&opP->odisp, 80);
+		outro = get_num (&opP->odisp, 90);
 	      /* Figure out the `addressing mode'.
 		 Also turn on the BASE_DISABLE bit, if needed.  */
 	      if (opP->reg == PC || opP->reg == ZPC)
@@ -2175,7 +2255,8 @@ m68k_ip (instring)
 		  if ((opP->index.scale != 1
 		       && cpu_of_arch (current_architecture) < m68020)
 		      || (opP->index.scale == 8
-			  && arch_coldfire_p (current_architecture)))
+			  && (arch_coldfire_p (current_architecture)
+                              && !arch_coldfire_v4e_p(current_architecture))))
 		    {
 		      opP->error =
 			_("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
@@ -2380,7 +2461,7 @@ m68k_ip (instring)
 	      break;
 
 	    case ABSL:
-	      nextword = get_num (&opP->disp, 80);
+	      nextword = get_num (&opP->disp, 90);
 	      switch (opP->disp.size)
 		{
 		default:
@@ -2456,7 +2537,7 @@ m68k_ip (instring)
 	      break;
 	    case '3':
 	    default:
-	      tmpreg = 80;
+	      tmpreg = 90;
 	      break;
 	    }
 	  tmpreg = get_num (&opP->disp, tmpreg);
@@ -2523,7 +2604,7 @@ m68k_ip (instring)
 	  break;
 
 	case 'B':
-	  tmpreg = get_num (&opP->disp, 80);
+	  tmpreg = get_num (&opP->disp, 90);
 	  switch (s[1])
 	    {
 	    case 'B':
@@ -2643,7 +2724,7 @@ m68k_ip (instring)
 
 	case 'd':		/* JF this is a kludge.  */
 	  install_operand ('s', opP->reg - ADDR);
-	  tmpreg = get_num (&opP->disp, 80);
+	  tmpreg = get_num (&opP->disp, 90);
 	  if (!issword (tmpreg))
 	    {
 	      as_warn (_("Expression out of range, using 0"));
@@ -2687,15 +2768,19 @@ m68k_ip (instring)
 	    case TC:
 	      tmpreg = 0x003;
 	      break;
+	    case ACR0:
 	    case ITT0:
 	      tmpreg = 0x004;
 	      break;
+	    case ACR1:
 	    case ITT1:
 	      tmpreg = 0x005;
 	      break;
+	    case ACR2:
 	    case DTT0:
 	      tmpreg = 0x006;
 	      break;
+	    case ACR3:
 	    case DTT1:
 	      tmpreg = 0x007;
 	      break;
@@ -2733,15 +2818,67 @@ m68k_ip (instring)
             case ROMBAR:
 	      tmpreg = 0xC00;
 	      break;
+            case ROMBAR1:
+              tmpreg = 0xC01;
+              break;
+	    case FLASHBAR:
 	    case RAMBAR0:
 	      tmpreg = 0xC04;
 	      break;
+	    case RAMBAR:
 	    case RAMBAR1:
 	      tmpreg = 0xC05;
 	      break;
+            case MPCR:
+              tmpreg = 0xC0C;
+              break;
+            case EDRAMBAR:
+              tmpreg = 0xC0D;
+              break;
+            case MBAR0:
+            case SECMBAR:
+              tmpreg = 0xC0E;
+              break;
+            case MBAR1:
 	    case MBAR:
 	      tmpreg = 0xC0F;
 	      break;
+            case PCR1U0:
+              tmpreg = 0xD02;
+              break;
+            case PCR1L0:
+              tmpreg = 0xD03;
+              break;
+            case PCR2U0:
+              tmpreg = 0xD04;
+              break;
+            case PCR2L0:
+              tmpreg = 0xD05;
+              break;
+            case PCR3U0:
+              tmpreg = 0xD06;
+              break;
+            case PCR3L0:
+              tmpreg = 0xD07;
+              break;
+            case PCR1L1:
+              tmpreg = 0xD0A;
+              break;
+            case PCR1U1:
+              tmpreg = 0xD0B;
+              break;
+            case PCR2L1:
+              tmpreg = 0xD0C;
+              break;
+            case PCR2U1:
+              tmpreg = 0xD0D;
+              break;
+            case PCR3L1:
+              tmpreg = 0xD0E;
+              break;
+            case PCR3U1:
+              tmpreg = 0xD0F;
+              break;
 	    default:
 	      abort ();
 	    }
@@ -2990,7 +3127,7 @@ m68k_ip (instring)
 	case '_':	/* used only for move16 absolute 32-bit address.  */
 	  if (isvar (&opP->disp))
 	    add_fix ('l', &opP->disp, 0, 0);
-	  tmpreg = get_num (&opP->disp, 80);
+	  tmpreg = get_num (&opP->disp, 90);
 	  addword (tmpreg >> 16);
 	  addword (tmpreg & 0xFFFF);
 	  break;
@@ -2999,6 +3136,12 @@ m68k_ip (instring)
 	  opP->reg -= (DATA0L);
 	  opP->reg &= 0x0F;	/* remove upper/lower bit.  */
 	  break;
+	case 'x':
+	  tmpreg = get_num (&opP->disp, 80);
+	  if (tmpreg == -1)
+	    tmpreg = 0;
+	  install_operand (s[1], tmpreg);
+	  break;
 	default:
 	  abort ();
 	}
@@ -3394,10 +3537,10 @@ static const struct init_entry init_table[] =
   /* mcf5200 versions of same.  The ColdFire programmer's reference
      manual indicated that the order is 2,3,0,1, but Ken Rose
      <rose@netcom.com> says that 0,1,2,3 is the correct order.  */
-  { "acr0", ITT0 },		/* Access Control Unit 0.  */
-  { "acr1", ITT1 },		/* Access Control Unit 1.  */
-  { "acr2", DTT0 },		/* Access Control Unit 2.  */
-  { "acr3", DTT1 },		/* Access Control Unit 3.  */
+  { "acr0", ACR0 },		/* Access Control Unit 0.  */
+  { "acr1", ACR1 },		/* Access Control Unit 1.  */
+  { "acr2", ACR2 },		/* Access Control Unit 2.  */
+  { "acr3", ACR3 },		/* Access Control Unit 3.  */
 
   { "tc", TC },			/* MMU Translation Control Register.  */
   { "tcr", TC },
@@ -3413,6 +3556,31 @@ static const struct init_entry init_table[] =
   { "rambar0", RAMBAR0 },	/* ROM Base Address Register.  */
   { "rambar1", RAMBAR1 },	/* ROM Base Address Register.  */
   { "mbar", MBAR },		/* Module Base Address Register.  */
+
+  { "mbar0",    MBAR0 },	/* mcfv4e registers.  */
+  { "mbar1",    MBAR1 },	/* mcfv4e registers.  */
+  { "rombar0",  ROMBAR },	/* mcfv4e registers.  */
+  { "rombar1",  ROMBAR1 },	/* mcfv4e registers.  */
+  { "mpcr",     MPCR },		/* mcfv4e registers.  */
+  { "edrambar", EDRAMBAR },	/* mcfv4e registers.  */
+  { "secmbar",  SECMBAR },	/* mcfv4e registers.  */
+  { "asid",     TC },		/* mcfv4e registers.  */
+  { "mmubar",   BUSCR },	/* mcfv4e registers.  */
+  { "pcr1u0",   PCR1U0 },	/* mcfv4e registers.  */
+  { "pcr1l0",   PCR1L0 },	/* mcfv4e registers.  */
+  { "pcr2u0",   PCR2U0 },	/* mcfv4e registers.  */
+  { "pcr2l0",   PCR2L0 },	/* mcfv4e registers.  */
+  { "pcr3u0",   PCR3U0 },	/* mcfv4e registers.  */
+  { "pcr3l0",   PCR3L0 },	/* mcfv4e registers.  */
+  { "pcr1u1",   PCR1U1 },	/* mcfv4e registers.  */
+  { "pcr1l1",   PCR1L1 },	/* mcfv4e registers.  */
+  { "pcr2u1",   PCR2U1 },	/* mcfv4e registers.  */
+  { "pcr2l1",   PCR2L1 },	/* mcfv4e registers.  */
+  { "pcr3u1",   PCR3U1 },	/* mcfv4e registers.  */
+  { "pcr3l1",   PCR3L1 },	/* mcfv4e registers.  */
+
+  { "flashbar", FLASHBAR }, 	/* mcf528x registers.  */
+  { "rambar",   RAMBAR },  	/* mcf528x registers.  */
   /* End of control registers.  */
 
   { "ac", AC },
@@ -3970,6 +4138,12 @@ select_control_regs ()
     case mcf5407:
       control_regs = mcf_control_regs;
       break;
+    case mcf528x:
+      control_regs = mcf528x_control_regs;
+      break;
+    case mcfv4e:
+      control_regs = mcfv4e_control_regs;
+      break;
     default:
       abort ();
     }
@@ -4808,17 +4982,16 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
    aren't OK are an error (what a shock, no?)
 
    0:  Everything is OK
-   10:  Absolute 1:8	only
-   20:  Absolute 0:7	only
-   30:  absolute 0:15	only
-   40:  Absolute 0:31	only
-   50:  absolute 0:127	only
+   10:  Absolute 1:8	   only
+   20:  Absolute 0:7	   only
+   30:  absolute 0:15	   only
+   40:  Absolute 0:31	   only
+   50:  absolute 0:127	   only
    55:  absolute -64:63    only
-   60:  absolute -128:127	only
-   70:  absolute 0:4095	only
-   80:  No bignums
-
-   */
+   60:  absolute -128:127  only
+   70:  absolute 0:4095	   only
+   80:  absolute -1, 1:7   only
+   90:  No bignums.          */
 
 static int
 get_num (exp, ok)
@@ -4881,6 +5054,15 @@ get_num (exp, ok)
 	      offs (exp) = 0;
 	    }
 	  break;
+	case 80:
+	  if (offs (exp) < -1
+              || offs (exp) > 7
+              || offs (exp) == 0)
+	    {
+	      as_warn (_("expression out of range: defaulting to 1"));
+	      offs (exp) = 1;
+	    }
+	  break;
 	default:
 	  break;
 	}
@@ -4888,7 +5070,7 @@ get_num (exp, ok)
   else if (exp->exp.X_op == O_big)
     {
       if (offs (exp) <= 0	/* flonum.  */
-	  && (ok == 80		/* no bignums.  */
+	  && (ok == 90		/* no bignums */
 	      || (ok > 10	/* Small-int ranges including 0 ok.  */
 		  /* If we have a flonum zero, a zero integer should
 		     do as well (e.g., in moveq).  */
@@ -4916,7 +5098,7 @@ get_num (exp, ok)
     }
   else
     {
-      if (ok >= 10 && ok <= 70)
+      if (ok >= 10 && ok <= 80)
 	{
 	  op (exp) = O_constant;
 	  adds (exp) = 0;
@@ -6951,7 +7133,8 @@ md_show_usage (stream)
 -l			use 1 word for refs to undefined symbols [default 2]\n\
 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
--m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m5307  | -m5407\n\
+-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m528x  | -m5307  |\n\
+-m5407  | -mcfv4  | -mcfv4e\n\
 			specify variant of 680X0 architecture [default %s]\n\
 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
 			target has/lacks floating-point coprocessor\n\
diff --git a/gas/doc/c-m68k.texi b/gas/doc/c-m68k.texi
index 15c9968..cafad4d 100644
--- a/gas/doc/c-m68k.texi
+++ b/gas/doc/c-m68k.texi
@@ -1,4 +1,4 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -165,6 +165,15 @@ Assemble for the 68060.
 Assemble for the CPU32 family of chips.
 
 @item -m5200
+@item -m5202
+@item -m5204
+@item -m5206
+@item -m5206e
+@item -m528x
+@item -m5307
+@item -m5407
+@item -mcfv4
+@item -mcfv4e
 Assemble for the ColdFire family of chips.
 
 @item -m68881
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index b557db5..42cf9a5 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2003-10-21  Peter Barada  <pbarada@mail.wm.sps.mot.com>
+            Bernardo Innocenti  <bernie@develer.com>
+
+	* m68k.h: Add MCFv4/MCF5528x support.
+
 2003-10-19  Hans-Peter Nilsson  <hp@bitrange.com>
 
 	* mmix.h (JMP_INSN_BYTE): Define.
diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h
index 3371d38..3f18984 100644
--- a/include/opcode/m68k.h
+++ b/include/opcode/m68k.h
@@ -1,55 +1,61 @@
 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
-   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001
-   Free Software Foundation, Inc.
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
+   2003 Free Software Foundation, Inc.
 
-This file is part of GDB, GAS, and the GNU binutils.
+   This file is part of GDB, GAS, and the GNU binutils.
 
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   1, or (at your option) any later version.
 
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
 
 /* These are used as bit flags for the arch field in the m68k_opcode
    structure.  */
 #define	_m68k_undef  0
-#define	m68000  0x001
-#define	m68008  m68000 /* synonym for -m68000.  otherwise unused. */
-#define	m68010  0x002
-#define	m68020  0x004
-#define	m68030  0x008
-#define m68ec030 m68030 /* similar enough to -m68030 to ignore differences;
+#define	m68000   0x001
+#define	m68008   m68000 /* Synonym for -m68000.  otherwise unused.  */
+#define	m68010   0x002
+#define	m68020   0x004
+#define	m68030   0x008
+#define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
 			   gas will deal with the few differences.  */
-#define	m68040  0x010
-/* there is no 68050 */
-#define m68060  0x020
-#define	m68881  0x040
-#define	m68882  m68881 /* synonym for -m68881.  otherwise unused. */
-#define	m68851  0x080
-#define cpu32	0x100	/* e.g., 68332 */
-#define mcf5200 0x200
+#define	m68040   0x010
+/* There is no 68050.  */
+#define m68060   0x020
+#define	m68881   0x040
+#define	m68882   m68881 /* Synonym for -m68881.  otherwise unused.  */
+#define	m68851   0x080
+#define cpu32	 0x100	/* e.g., 68332 */
+#define mcf5200  0x200
 #define mcf5206e 0x400
-#define mcf5307 0x800
-#define mcf5407 0x1000
-
- /* handy aliases */
-#define	m68040up  (m68040 | m68060)
-#define	m68030up  (m68030 | m68040up)
-#define	m68020up  (m68020 | m68030up)
-#define	m68010up  (m68010 | cpu32 | m68020up)
-#define	m68000up  (m68000 | m68010up)
-#define mcf       (mcf5200 | mcf5206e | mcf5307 | mcf5407)
-#define mcf5307up (mcf5307 | mcf5407)
-
+#define mcf5307  0x800
+#define mcf5407  0x1000
+#define mcfv4e   0x2000
+#define mcf528x  0x4000
+
+ /* Handy aliases.  */
+#define	m68040up   (m68040 | m68060)
+#define	m68030up   (m68030 | m68040up)
+#define	m68020up   (m68020 | m68030up)
+#define	m68010up   (m68010 | cpu32 | m68020up)
+#define	m68000up   (m68000 | m68010up)
+#define mcf        (mcf5200 | mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e)
+#define mcf5206eup (mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e)
+#define mcf5307up  (mcf5307 | mcf5407 | mcfv4e)
+#define mcfv4up    (mcf5407 | mcfv4e)
+#define mcfv4eup   (mcfv4e)
+
+#define cfloat  (mcfv4e)
 #define	mfloat  (m68881 | m68882 | m68040 | m68060)
 #define	mmmu    (m68851 | m68030 | m68040 | m68060)
 
@@ -93,7 +99,7 @@ struct m68k_opcode_alias
    operand; the second, the place it is stored.  */
 
 /* Kinds of operands:
-   Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+-
+   Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+-
 
    D  data register only.  Stored as 3 bits.
    A  address register only.  Stored as 3 bits.
@@ -141,7 +147,7 @@ struct m68k_opcode_alias
 	Possible values:
 	0x000	SFC	Source Function Code reg	[60, 40, 30, 20, 10]
 	0x001	DFC	Data Function Code reg		[60, 40, 30, 20, 10]
-	0x002	CACR	Cache Control Register		[60, 40, 30, 20]
+	0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
 	0x003	TC	MMU Translation Control		[60, 40]
 	0x004	ITT0	Instruction Transparent
 				Translation reg 0	[60, 40]
@@ -153,7 +159,7 @@ struct m68k_opcode_alias
 				Translation reg 1	[60, 40]
 	0x008	BUSCR	Bus Control Register		[60]
 	0x800	USP	User Stack Pointer		[60, 40, 30, 20, 10]
-	0x801	VBR	Vector Base reg			[60, 40, 30, 20, 10]
+        0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
 	0x802	CAAR	Cache Address Register		[        30, 20]
 	0x803	MSP	Master Stack Pointer		[    40, 30, 20]
 	0x804	ISP	Interrupt Stack Pointer		[    40, 30, 20]
@@ -165,6 +171,8 @@ struct m68k_opcode_alias
 	0xC04	RAMBAR0	RAM Base Address Register 0	[520X]
 	0xC05	RAMBAR1	RAM Base Address Register 0	[520X]
 	0xC0F	MBAR0	RAM Base Address Register 0	[520X]
+        0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
+        0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
 
     L  Register list of the type d0-d7/a0-a7 etc.
        (New!  Improved!  Can also hold fp0-fp7, as well!)
@@ -218,11 +226,14 @@ struct m68k_opcode_alias
    coldfire bset/bclr/btst/mulsl/mulul operands:
    q						(modes 0,2-5)
    v						(modes 0,2-5,7.0,7.1)
-*/
-
-/* For the 68851: */
-/*
-   I didn't use much imagination in choosing the 
+   b                                            (modes 0,2-5,7.2)
+   w                                            (modes 2-5,7.2)
+   y						(modes 2,5)
+   z						(modes 2,5,7.2)
+   x  mov3q immediate operand.  */
+
+/* For the 68851:  */
+/* I didn't use much imagination in choosing the
    following codes, so many of them aren't very
    mnemonic. -rab
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 996aee6..b7defcd 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2003-10-21  Peter Barada  <pbarada@mail.wm.sps.mot.com>
+            Bernardo Innocenti  <bernie@develer.com>
+
+	* m68k-dis.c: Add MCFv4/MCF5528x support.
+	* m68k-opc.c: Likewise.
+
 2003-10-10  Dave Brolley  <brolley@redhat.com>
 
 	* frv-asm.c,frv-desc.c,frv-opc.c: Regenerated.
diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c
index 12c0b94..bfd8c89 100644
--- a/opcodes/m68k-dis.c
+++ b/opcodes/m68k-dis.c
@@ -1,21 +1,21 @@
 /* Print Motorola 68k instructions.
    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002
+   1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
 
-This file is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -263,6 +263,9 @@ print_insn_m68k (memaddr, info)
     case bfd_mach_mcf5200:
       arch_mask = mcf5200;
       break;
+    case bfd_mach_mcf528x:
+      arch_mask = mcf528x;
+      break;
     case bfd_mach_mcf5206e:
       arch_mask = mcf5206e;
       break;
@@ -342,7 +345,7 @@ print_insn_m68k (memaddr, info)
   /* Point at first word of argument data,
      and at descriptor for first argument.  */
   p = buffer + 2;
-  
+
   /* Figure out how long the fixed-size portion of the instruction is.
      The only place this is stored in the opcode table is
      in the arguments--look for arguments which specify fields in the 2nd
@@ -406,10 +409,10 @@ print_insn_m68k (memaddr, info)
     }
 
   FETCH_DATA (info, p);
-  
+
   d = best->args;
 
-  /* We can the operands twice.  The first time we don't print anything,
+  /* We scan the operands twice.  The first time we don't print anything,
      but look for errors. */
 
   save_p = p;
@@ -537,12 +540,16 @@ print_insn_arg (d, buffer, p0, addr, info)
 
     case 'J':
       {
+	/* FIXME: There's a problem here, different m68k processors call the
+	   same address different names. This table can't get it right
+	   because it doesn't know which processor it's disassembling for.  */
 	static const struct { char *name; int value; } names[]
 	  = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
 	     {"%tc",  0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
              {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
 	     {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
 	     {"%msp", 0x803}, {"%isp", 0x804},
+	     {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these.  */
 
 	     /* Should we be calling this psr like we do in case 'Y'?  */
 	     {"%mmusr",0x805},
@@ -569,6 +576,14 @@ print_insn_arg (d, buffer, p0, addr, info)
       (*info->fprintf_func) (info->stream, "#%d", val);
       break;
 
+    case 'x':
+      val = fetch_arg (buffer, place, 3, info);
+      /* 0 means -1.  */
+      if (val == 0)
+	val = -1;
+      (*info->fprintf_func) (info->stream, "#%d", val);
+      break;
+
     case 'M':
       if (place == 'h')
 	{
@@ -724,7 +739,7 @@ print_insn_arg (d, buffer, p0, addr, info)
     case 'I':
       /* Get coprocessor ID... */
       val = fetch_arg (buffer, 'd', 3, info);
-      
+
       if (val != 1)				/* Unusual coprocessor ID? */
 	(*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
       break;
@@ -748,7 +763,10 @@ print_insn_arg (d, buffer, p0, addr, info)
     case 'p':
     case 'q':
     case 'v':
-
+    case 'b':
+    case 'w':
+    case 'y':
+    case 'z':
       if (place == 'd')
 	{
 	  val = fetch_arg (buffer, 'x', 6, info);
@@ -1023,7 +1041,7 @@ print_insn_arg (d, buffer, p0, addr, info)
       {
 	short is_upper = 0;
 	int reg = fetch_arg (buffer, place, 5, info);
-	
+
 	if (reg & 0x10)
 	  {
 	    is_upper = 1;
@@ -1034,7 +1052,7 @@ print_insn_arg (d, buffer, p0, addr, info)
 			       is_upper ? "u" : "l");
       }
       break;
-	
+
     default:
       return -2;
     }
@@ -1121,7 +1139,7 @@ fetch_arg (buffer, code, bits, info)
       val = (buffer[2] << 8) + buffer[3];
       val >>= 7;
       break;
-      
+
     case '8':
       FETCH_DATA (info, buffer + 3);
       val = (buffer[2] << 8) + buffer[3];
@@ -1138,13 +1156,13 @@ fetch_arg (buffer, code, bits, info)
       val = (buffer[1] >> 6);
       break;
 
-    case 'm': 
+    case 'm':
       val = (buffer[1] & 0x40 ? 0x8 : 0)
 	| ((buffer[0] >> 1) & 0x7)
 	| (buffer[3] & 0x80 ? 0x10 : 0);
       break;
 
-    case 'n': 
+    case 'n':
       val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
       break;
 
diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c
index 79d7db0..a2b2a5e 100644
--- a/opcodes/m68k-opc.c
+++ b/opcodes/m68k-opc.c
@@ -1,24 +1,24 @@
 /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001
+   2000, 2001, 2003
    Free Software Foundation, Inc.
 
-This file is part of GDB, GAS, and the GNU binutils.
+   This file is part of GDB, GAS, and the GNU binutils.
 
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   1, or (at your option) any later version.
 
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
 
 #include "sysdep.h"
 #include "opcode/m68k.h"
@@ -131,20 +131,20 @@ const struct m68k_opcode m68k_opcodes[] =
 {"bgtw",	one(0067000),	one(0177777), "BW", m68000up | mcf },
 {"blew",	one(0067400),	one(0177777), "BW", m68000up | mcf },
 
-{"bhil",	one(0061377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"blsl",	one(0061777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bccl",	one(0062377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bcsl",	one(0062777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bnel",	one(0063377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"beql",	one(0063777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bvcl",	one(0064377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bvsl",	one(0064777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bpll",	one(0065377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bmil",	one(0065777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bgel",	one(0066377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bltl",	one(0066777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"bgtl",	one(0067377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
-{"blel",	one(0067777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bhil",	one(0061377),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"blsl",	one(0061777),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bccl",	one(0062377),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bcsl",	one(0062777),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bnel",	one(0063377),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"beql",	one(0063777),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bvcl",	one(0064377),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bvsl",	one(0064777),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bpll",	one(0065377),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bmil",	one(0065777),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bgel",	one(0066377),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bltl",	one(0066777),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"bgtl",	one(0067377),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
+{"blel",	one(0067777),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
 
 {"bhis",	one(0061000),	one(0177400), "BB", m68000up | mcf },
 {"blss",	one(0061400),	one(0177400), "BB", m68000up | mcf },
@@ -180,8 +180,7 @@ const struct m68k_opcode m68k_opcodes[] =
 {"bchg",	one(0004100),	one(0177700), "#b$s", m68000up },
 {"bchg",	one(0004100),	one(0177700), "#bqs", mcf },
 
-{"bclr",	one(0000600),	one(0170700), "Dd$s", m68000up },
-{"bclr",	one(0000600),	one(0170700), "Ddvs", mcf },
+{"bclr",	one(0000600),	one(0170700), "Dd$s", m68000up | mcf },
 {"bclr",	one(0004200),	one(0177700), "#b$s", m68000up },
 {"bclr",	one(0004200),	one(0177700), "#bqs", mcf },
 
@@ -194,28 +193,32 @@ const struct m68k_opcode m68k_opcodes[] =
 {"bfset",	two(0167300, 0), two(0177700, 0170000),	"?sO2O3",   m68020up },
 {"bftst",	two(0164300, 0), two(0177700, 0170000),	"/sO2O3",   m68020up },
 
-{"bgnd",	one(0045372),		one(0177777), "", cpu32 },
+{"bgnd",	one(0045372),	one(0177777), "", cpu32 },
 
-{"bkpt",	one(0044110),		one(0177770), "ts", m68010up },
+{"bitrev",	one(0000300),	one(0177770), "Ds", mcf528x},
+
+{"bkpt",	one(0044110),	one(0177770), "ts", m68010up },
 
 {"braw",	one(0060000),	one(0177777), "BW", m68000up | mcf },
-{"bral",	one(0060377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bral",	one(0060377),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
 {"bras",	one(0060000),	one(0177400), "BB", m68000up | mcf },
 
-{"bset",	one(0000700),	one(0170700), "Dd$s", m68000up },
+{"bset",	one(0000700),	one(0170700), "Dd$s", m68000up | mcf },
 {"bset",	one(0000700),	one(0170700), "Ddvs", mcf },
 {"bset",	one(0004300),	one(0177700), "#b$s", m68000up },
 {"bset",	one(0004300),	one(0177700), "#bqs", mcf },
 
 {"bsrw",	one(0060400),	one(0177777), "BW", m68000up | mcf },
-{"bsrl",	one(0060777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bsrl",	one(0060777),	one(0177777), "BL", m68020up | cpu32 | mcfv4up},
 {"bsrs",	one(0060400),	one(0177400), "BB", m68000up | mcf },
 
 {"btst",	one(0000400),	one(0170700), "Dd;b", m68000up | mcf },
 {"btst",	one(0004000),	one(0177700), "#b@s", m68000up },
 {"btst",	one(0004000),	one(0177700), "#bqs", mcf },
 
-{"callm",	one(0003300),		one(0177700), "#b!s", m68020 },
+{"byterev",	one(0001300),	one(0177770), "Ds", mcf528x},
+
+{"callm",	one(0003300),	one(0177700), "#b!s", m68020 },
 
 {"cas2w",     two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
 {"cas2w",     two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
@@ -261,9 +264,9 @@ const struct m68k_opcode m68k_opcodes[] =
 {"cmpal",	one(0130700),	one(0170700), "*lAd", m68000up | mcf },
 
 {"cmpib",	one(0006000),	one(0177700), "#b@s", m68000up },
-{"cmpib",	one(0006000),	one(0177700), "#bDs", mcf5407 },
+{"cmpib",	one(0006000),	one(0177700), "#bDs", mcfv4up },
 {"cmpiw",	one(0006100),	one(0177700), "#w@s", m68000up },
-{"cmpiw",	one(0006100),	one(0177700), "#wDs", mcf5407 },
+{"cmpiw",	one(0006100),	one(0177700), "#wDs", mcfv4up },
 {"cmpil",	one(0006200),	one(0177700), "#l@s", m68000up },
 {"cmpil",	one(0006200),	one(0177700), "#lDs", mcf },
 
@@ -273,15 +276,15 @@ const struct m68k_opcode m68k_opcodes[] =
 
 /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions.  */
 {"cmpb",	one(0006000),	one(0177700), "#b@s", m68000up },
-{"cmpb",	one(0006000),	one(0177700), "#bDs", mcf5407 },
+{"cmpb",	one(0006000),	one(0177700), "#bDs", mcfv4up },
 {"cmpb",	one(0130410),	one(0170770), "+s+d", m68000up },
 {"cmpb",	one(0130000),	one(0170700), ";bDd", m68000up },
-{"cmpb",	one(0130000),	one(0170700), "*bDd", mcf5407 },
+{"cmpb",	one(0130000),	one(0170700), "*bDd", mcfv4up },
 {"cmpw",	one(0130300),	one(0170700), "*wAd", m68000up },
 {"cmpw",	one(0006100),	one(0177700), "#w@s", m68000up },
-{"cmpw",	one(0006100),	one(0177700), "#wDs", mcf5407 },
+{"cmpw",	one(0006100),	one(0177700), "#wDs", mcfv4up },
 {"cmpw",	one(0130510),	one(0170770), "+s+d", m68000up },
-{"cmpw",	one(0130100),	one(0170700), "*wDd", m68000up | mcf5407 },
+{"cmpw",	one(0130100),	one(0170700), "*wDd", m68000up | mcfv4up },
 {"cmpl",	one(0130700),	one(0170700), "*lAd", m68000up | mcf },
 {"cmpl",	one(0006200),	one(0177700), "#l@s", m68000up },
 {"cmpl",	one(0006200),	one(0177700), "#lDs", mcf },
@@ -305,20 +308,20 @@ const struct m68k_opcode m68k_opcodes[] =
 {"dbvc",	one(0054310),	one(0177770), "DsBw", m68000up },
 {"dbvs",	one(0054710),	one(0177770), "DsBw", m68000up },
 
-{"divsw",	one(0100700),	one(0170700), ";wDd", m68000up | mcf5307up | mcf5206e },
+{"divsw",	one(0100700),	one(0170700), ";wDd", m68000up | mcf5206eup },
 
 {"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
 {"divsl", two(0046100,0004000),two(0177700,0107770),";lDD",   m68020up|cpu32 },
-{"divsl", two(0046100,0004000),two(0177700,0107770),"qsDD",   mcf5307up | mcf5206e },
+{"divsl", two(0046100,0004000),two(0177700,0107770),"qsDD",   mcf5206eup },
 
 {"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
 {"divsll", two(0046100,0004000),two(0177700,0107770),";lDD",  m68020up|cpu32 },
 
-{"divuw",	one(0100300),		one(0170700), ";wDd", m68000up | mcf5307up | mcf5206e },
+{"divuw",	one(0100300),		one(0170700), ";wDd", m68000up | mcf5206eup },
 
 {"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
 {"divul", two(0046100,0000000),two(0177700,0107770),";lDD",   m68020up|cpu32 },
-{"divul", two(0046100,0000000),two(0177700,0107770),"qsDD",   mcf5307up | mcf5206e },
+{"divul", two(0046100,0000000),two(0177700,0107770),"qsDD",   mcf5206eup },
 
 {"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
 {"divull", two(0046100,0000000),two(0177700,0107770),";lDD",  m68020up|cpu32 },
@@ -357,33 +360,56 @@ const struct m68k_opcode m68k_opcodes[] =
 {"extl",	one(0044300),	one(0177770), "Ds", m68000up|mcf },
 {"extbl",	one(0044700),	one(0177770), "Ds", m68020up|cpu32|mcf },
 
+{"ff1",   one(0002300), one(0177770), "Ds", mcf528x},
+
 /* float stuff starts here */
 
 {"fabsb",	two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"fabsb",	two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fabsd",	two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fabsd",	two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat },
 {"fabsd",	two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fabsd",	two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fabsl",	two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fabsl",	two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fabsp",	two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
+{"fabss",	two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat },
 {"fabss",	two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
 {"fabsw",	two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fabsw",	two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fabsx",	two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fabsx",	two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 {"fabsx",	two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
 {"fsabsb",	two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fsabsb",	two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsabsd",	two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fsabsd",	two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat },
 {"fsabsd",	two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fsabsd",	two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fsabsl",	two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fsabsl",	two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsabsp",	two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
+{"fsabss",	two(0xF000, 0x4258), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsabss",	two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
 {"fsabsw",	two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fsabsw",	two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsabsx",	two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fsabsx",	two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 {"fsabsx",	two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt",   m68040up },
 
+{"fdabsb",	two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdabsb",	two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up},
+{"fdabsd",	two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fdabsd",	two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat },
+{"fdabsd",	two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fdabsd",	two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up},
+{"fdabsl",	two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdabsl",	two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up},
 {"fdabsp",	two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up},
+{"fdabss",	two(0xF000, 0x425C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdabss",	two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up},
+{"fdabsw",	two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdabsw",	two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up},
 {"fdabsx",	two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up},
 {"fdabsx",	two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up},
@@ -400,28 +426,47 @@ const struct m68k_opcode m68k_opcodes[] =
 {"facosx",	two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
 {"faddb",	two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"faddb",	two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"faddd",	two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"faddd",	two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"faddd",	two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"faddd",	two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"faddl",	two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"faddl",	two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"faddp",	two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fadds",	two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fadds",	two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"faddw",	two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"faddw",	two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"faddx",	two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"faddx",	two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 
 {"fsaddb",	two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fsaddb",	two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsaddd",	two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fsaddd",	two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fsaddd",	two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fsaddl",	two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fsaddl",	two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsaddp",	two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fsadds",	two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fsadds",	two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsaddw",	two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fsaddw",	two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsaddx",	two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fsaddx",	two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 
+{"fdaddb",	two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdaddb",	two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fdaddd",	two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fdaddd",	two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdaddd",	two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fdaddl",	two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fdaddl",	two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
 {"fdaddp",	two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fdadds",	two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fdadds",	two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdaddw",	two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdaddw",	two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
 {"fdaddx",	two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fdaddx",	two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
@@ -456,111 +501,117 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fatanhx",	two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 {"fatanhx",	two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
-{"fbeq",	one(0xF081),		one(0xF1FF), "IdBW", mfloat },
-{"fbf",		one(0xF080),		one(0xF1FF), "IdBW", mfloat },
-{"fbge",	one(0xF093),		one(0xF1FF), "IdBW", mfloat },
-{"fbgl",	one(0xF096),		one(0xF1FF), "IdBW", mfloat },
-{"fbgle",	one(0xF097),		one(0xF1FF), "IdBW", mfloat },
-{"fbgt",	one(0xF092),		one(0xF1FF), "IdBW", mfloat },
-{"fble",	one(0xF095),		one(0xF1FF), "IdBW", mfloat },
-{"fblt",	one(0xF094),		one(0xF1FF), "IdBW", mfloat },
-{"fbne",	one(0xF08E),		one(0xF1FF), "IdBW", mfloat },
-{"fbnge",	one(0xF09C),		one(0xF1FF), "IdBW", mfloat },
-{"fbngl",	one(0xF099),		one(0xF1FF), "IdBW", mfloat },
-{"fbngle",	one(0xF098),		one(0xF1FF), "IdBW", mfloat },
-{"fbngt",	one(0xF09D),		one(0xF1FF), "IdBW", mfloat },
-{"fbnle",	one(0xF09A),		one(0xF1FF), "IdBW", mfloat },
-{"fbnlt",	one(0xF09B),		one(0xF1FF), "IdBW", mfloat },
-{"fboge",	one(0xF083),		one(0xF1FF), "IdBW", mfloat },
-{"fbogl",	one(0xF086),		one(0xF1FF), "IdBW", mfloat },
-{"fbogt",	one(0xF082),		one(0xF1FF), "IdBW", mfloat },
-{"fbole",	one(0xF085),		one(0xF1FF), "IdBW", mfloat },
-{"fbolt",	one(0xF084),		one(0xF1FF), "IdBW", mfloat },
-{"fbor",	one(0xF087),		one(0xF1FF), "IdBW", mfloat },
-{"fbseq",	one(0xF091),		one(0xF1FF), "IdBW", mfloat },
-{"fbsf",	one(0xF090),		one(0xF1FF), "IdBW", mfloat },
-{"fbsne",	one(0xF09E),		one(0xF1FF), "IdBW", mfloat },
-{"fbst",	one(0xF09F),		one(0xF1FF), "IdBW", mfloat },
-{"fbt",		one(0xF08F),		one(0xF1FF), "IdBW", mfloat },
-{"fbueq",	one(0xF089),		one(0xF1FF), "IdBW", mfloat },
-{"fbuge",	one(0xF08B),		one(0xF1FF), "IdBW", mfloat },
-{"fbugt",	one(0xF08A),		one(0xF1FF), "IdBW", mfloat },
-{"fbule",	one(0xF08D),		one(0xF1FF), "IdBW", mfloat },
-{"fbult",	one(0xF08C),		one(0xF1FF), "IdBW", mfloat },
-{"fbun",	one(0xF088),		one(0xF1FF), "IdBW", mfloat },
-
-{"fbeql",	one(0xF0C1),		one(0xF1FF), "IdBC", mfloat },
-{"fbfl",	one(0xF0C0),		one(0xF1FF), "IdBC", mfloat },
-{"fbgel",	one(0xF0D3),		one(0xF1FF), "IdBC", mfloat },
-{"fbgll",	one(0xF0D6),		one(0xF1FF), "IdBC", mfloat },
-{"fbglel",	one(0xF0D7),		one(0xF1FF), "IdBC", mfloat },
-{"fbgtl",	one(0xF0D2),		one(0xF1FF), "IdBC", mfloat },
-{"fblel",	one(0xF0D5),		one(0xF1FF), "IdBC", mfloat },
-{"fbltl",	one(0xF0D4),		one(0xF1FF), "IdBC", mfloat },
-{"fbnel",	one(0xF0CE),		one(0xF1FF), "IdBC", mfloat },
-{"fbngel",	one(0xF0DC),		one(0xF1FF), "IdBC", mfloat },
-{"fbngll",	one(0xF0D9),		one(0xF1FF), "IdBC", mfloat },
-{"fbnglel",	one(0xF0D8),		one(0xF1FF), "IdBC", mfloat },
-{"fbngtl",	one(0xF0DD),		one(0xF1FF), "IdBC", mfloat },
-{"fbnlel",	one(0xF0DA),		one(0xF1FF), "IdBC", mfloat },
-{"fbnltl",	one(0xF0DB),		one(0xF1FF), "IdBC", mfloat },
-{"fbogel",	one(0xF0C3),		one(0xF1FF), "IdBC", mfloat },
-{"fbogll",	one(0xF0C6),		one(0xF1FF), "IdBC", mfloat },
-{"fbogtl",	one(0xF0C2),		one(0xF1FF), "IdBC", mfloat },
-{"fbolel",	one(0xF0C5),		one(0xF1FF), "IdBC", mfloat },
-{"fboltl",	one(0xF0C4),		one(0xF1FF), "IdBC", mfloat },
-{"fborl",	one(0xF0C7),		one(0xF1FF), "IdBC", mfloat },
-{"fbseql",	one(0xF0D1),		one(0xF1FF), "IdBC", mfloat },
-{"fbsfl",	one(0xF0D0),		one(0xF1FF), "IdBC", mfloat },
-{"fbsnel",	one(0xF0DE),		one(0xF1FF), "IdBC", mfloat },
-{"fbstl",	one(0xF0DF),		one(0xF1FF), "IdBC", mfloat },
-{"fbtl",	one(0xF0CF),		one(0xF1FF), "IdBC", mfloat },
-{"fbueql",	one(0xF0C9),		one(0xF1FF), "IdBC", mfloat },
-{"fbugel",	one(0xF0CB),		one(0xF1FF), "IdBC", mfloat },
-{"fbugtl",	one(0xF0CA),		one(0xF1FF), "IdBC", mfloat },
-{"fbulel",	one(0xF0CD),		one(0xF1FF), "IdBC", mfloat },
-{"fbultl",	one(0xF0CC),		one(0xF1FF), "IdBC", mfloat },
-{"fbunl",	one(0xF0C8),		one(0xF1FF), "IdBC", mfloat },
-
-{"fjeq",	one(0xF081),		one(0xF1BF), "IdBc", mfloat },
-{"fjf",		one(0xF080),		one(0xF1BF), "IdBc", mfloat },
-{"fjge",	one(0xF093),		one(0xF1BF), "IdBc", mfloat },
-{"fjgl",	one(0xF096),		one(0xF1BF), "IdBc", mfloat },
-{"fjgle",	one(0xF097),		one(0xF1BF), "IdBc", mfloat },
-{"fjgt",	one(0xF092),		one(0xF1BF), "IdBc", mfloat },
-{"fjle",	one(0xF095),		one(0xF1BF), "IdBc", mfloat },
-{"fjlt",	one(0xF094),		one(0xF1BF), "IdBc", mfloat },
-{"fjne",	one(0xF08E),		one(0xF1BF), "IdBc", mfloat },
-{"fjnge",	one(0xF09C),		one(0xF1BF), "IdBc", mfloat },
-{"fjngl",	one(0xF099),		one(0xF1BF), "IdBc", mfloat },
-{"fjngle",	one(0xF098),		one(0xF1BF), "IdBc", mfloat },
-{"fjngt",	one(0xF09D),		one(0xF1BF), "IdBc", mfloat },
-{"fjnle",	one(0xF09A),		one(0xF1BF), "IdBc", mfloat },
-{"fjnlt",	one(0xF09B),		one(0xF1BF), "IdBc", mfloat },
-{"fjoge",	one(0xF083),		one(0xF1BF), "IdBc", mfloat },
-{"fjogl",	one(0xF086),		one(0xF1BF), "IdBc", mfloat },
-{"fjogt",	one(0xF082),		one(0xF1BF), "IdBc", mfloat },
-{"fjole",	one(0xF085),		one(0xF1BF), "IdBc", mfloat },
-{"fjolt",	one(0xF084),		one(0xF1BF), "IdBc", mfloat },
-{"fjor",	one(0xF087),		one(0xF1BF), "IdBc", mfloat },
-{"fjseq",	one(0xF091),		one(0xF1BF), "IdBc", mfloat },
-{"fjsf",	one(0xF090),		one(0xF1BF), "IdBc", mfloat },
-{"fjsne",	one(0xF09E),		one(0xF1BF), "IdBc", mfloat },
-{"fjst",	one(0xF09F),		one(0xF1BF), "IdBc", mfloat },
-{"fjt",		one(0xF08F),		one(0xF1BF), "IdBc", mfloat },
-{"fjueq",	one(0xF089),		one(0xF1BF), "IdBc", mfloat },
-{"fjuge",	one(0xF08B),		one(0xF1BF), "IdBc", mfloat },
-{"fjugt",	one(0xF08A),		one(0xF1BF), "IdBc", mfloat },
-{"fjule",	one(0xF08D),		one(0xF1BF), "IdBc", mfloat },
-{"fjult",	one(0xF08C),		one(0xF1BF), "IdBc", mfloat },
-{"fjun",	one(0xF088),		one(0xF1BF), "IdBc", mfloat },
-
+{"fbeq",	one(0xF081),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbf",		one(0xF080),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbge",	one(0xF093),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbgl",	one(0xF096),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbgle",	one(0xF097),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbgt",	one(0xF092),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fble",	one(0xF095),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fblt",	one(0xF094),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbne",	one(0xF08E),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbnge",	one(0xF09C),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbngl",	one(0xF099),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbngle",	one(0xF098),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbngt",	one(0xF09D),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbnle",	one(0xF09A),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbnlt",	one(0xF09B),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fboge",	one(0xF083),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbogl",	one(0xF086),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbogt",	one(0xF082),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbole",	one(0xF085),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbolt",	one(0xF084),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbor",	one(0xF087),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbseq",	one(0xF091),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbsf",	one(0xF090),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbsne",	one(0xF09E),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbst",	one(0xF09F),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbt",		one(0xF08F),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbueq",	one(0xF089),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbuge",	one(0xF08B),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbugt",	one(0xF08A),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbule",	one(0xF08D),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbult",	one(0xF08C),		one(0xF1FF), "IdBW", mfloat | cfloat },
+{"fbun",	one(0xF088),		one(0xF1FF), "IdBW", mfloat | cfloat },
+
+{"fbeql",	one(0xF0C1),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbfl",	one(0xF0C0),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbgel",	one(0xF0D3),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbgll",	one(0xF0D6),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbglel",	one(0xF0D7),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbgtl",	one(0xF0D2),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fblel",	one(0xF0D5),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbltl",	one(0xF0D4),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbnel",	one(0xF0CE),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbngel",	one(0xF0DC),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbngll",	one(0xF0D9),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbnglel",	one(0xF0D8),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbngtl",	one(0xF0DD),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbnlel",	one(0xF0DA),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbnltl",	one(0xF0DB),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbogel",	one(0xF0C3),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbogll",	one(0xF0C6),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbogtl",	one(0xF0C2),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbolel",	one(0xF0C5),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fboltl",	one(0xF0C4),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fborl",	one(0xF0C7),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbseql",	one(0xF0D1),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbsfl",	one(0xF0D0),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbsnel",	one(0xF0DE),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbstl",	one(0xF0DF),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbtl",	one(0xF0CF),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbueql",	one(0xF0C9),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbugel",	one(0xF0CB),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbugtl",	one(0xF0CA),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbulel",	one(0xF0CD),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbultl",	one(0xF0CC),		one(0xF1FF), "IdBC", mfloat | cfloat },
+{"fbunl",	one(0xF0C8),		one(0xF1FF), "IdBC", mfloat | cfloat },
+
+{"fjeq",	one(0xF081),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjf",		one(0xF080),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjge",	one(0xF093),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjgl",	one(0xF096),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjgle",	one(0xF097),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjgt",	one(0xF092),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjle",	one(0xF095),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjlt",	one(0xF094),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjne",	one(0xF08E),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjnge",	one(0xF09C),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjngl",	one(0xF099),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjngle",	one(0xF098),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjngt",	one(0xF09D),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjnle",	one(0xF09A),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjnlt",	one(0xF09B),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjoge",	one(0xF083),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjogl",	one(0xF086),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjogt",	one(0xF082),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjole",	one(0xF085),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjolt",	one(0xF084),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjor",	one(0xF087),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjseq",	one(0xF091),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjsf",	one(0xF090),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjsne",	one(0xF09E),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjst",	one(0xF09F),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjt",		one(0xF08F),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjueq",	one(0xF089),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjuge",	one(0xF08B),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjugt",	one(0xF08A),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjule",	one(0xF08D),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjult",	one(0xF08C),		one(0xF1BF), "IdBc", mfloat | cfloat },
+{"fjun",	one(0xF088),		one(0xF1BF), "IdBc", mfloat | cfloat },
+
+{"fcmpb",	two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fcmpb",	two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
 {"fcmpd",	two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fcmpd",	two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
+{"fcmpd",	two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fcmpl",	two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fcmpl",	two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fcmpp",	two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fcmps",	two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fcmps",	two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fcmpw",	two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fcmpw",	two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fcmpx",	two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fcmpx",	two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 
@@ -618,29 +669,47 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fdbun",	two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
 
 {"fdivb",	two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"fdivb",	two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdivd",	two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fdivd",	two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fdivd",	two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fdivl",	two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fdivl",	two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdivp",	two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fdivs",	two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fdivs",	two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdivw",	two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fdivw",	two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdivx",	two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fdivx",	two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 
 {"fsdivb",	two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fsdivb",	two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsdivd",	two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fsdivd",	two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fsdivd",	two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fsdivl",	two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fsdivl",	two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsdivp",	two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fsdivs",	two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fsdivs",	two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsdivw",	two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fsdivw",	two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsdivx",	two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fsdivx",	two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 
 {"fddivb",	two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fddivb",	two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fddivd",	two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fddivd",	two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fddivd",	two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fddivl",	two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fddivl",	two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fddivp",	two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fddivs",	two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fddivs",	two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fddivw",	two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fddivw",	two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fddivx",	two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fddivx",	two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 
@@ -685,21 +754,35 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fgetmanx",	two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
 {"fintb",	two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"fintb",	two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fintd",	two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fintd",	two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat },
 {"fintd",	two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fintd",	two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fintl",	two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fintl",	two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fintp",	two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fints",	two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fints",	two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fintw",	two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fintw",	two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fintx",	two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fintx",	two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 {"fintx",	two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
 {"fintrzb",	two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"fintrzb",	two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fintrzd",	two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fintrzd",	two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt",   cfloat },
 {"fintrzd",	two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fintrzd",	two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fintrzl",	two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fintrzl",	two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fintrzp",	two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fintrzs",	two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fintrzs",	two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fintrzw",	two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fintrzw",	two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fintrzx",	two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fintrzx",	two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 {"fintrzx",	two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
@@ -753,12 +836,22 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fmodx",	two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fmodx",	two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 
+{"fmoveb",	two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fmoveb",	two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat },
 {"fmoveb",	two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
 {"fmoveb",	two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat },
 {"fmoved",	two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
 {"fmoved",	two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat },
+{"fmoved",	two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fmoved",	two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
+{"fmoved",	two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat },
 {"fmovel",	two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
 {"fmovel",	two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat },
+{"fmovel",	two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fmovel",	two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat },
+  /* Move the FP control registers */
+{"fmovel",	two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat },
+{"fmovel",	two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat },
 /* FIXME: the next two variants should not permit moving an address
    register to anything but the floating point instruction register.  */
 {"fmovel",	two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat },
@@ -768,32 +861,63 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fmovep",	two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat },
 {"fmoves",	two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
 {"fmoves",	two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat },
+{"fmoves",	two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fmoves",	two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fmovew",	two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
 {"fmovew",	two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat },
+{"fmovew",	two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fmovew",	two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fmovex",	two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat },
 {"fmovex",	two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 {"fmovex",	two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat },
 
 {"fsmoveb",	two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fsmoveb",	two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsmoveb",	two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
+{"fsmoved",	two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fsmoved",	two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fsmoved",	two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
+{"fsmoved",	two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat },
 {"fsmovel",	two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fsmovel",	two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsmovel",	two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fsmoves",	two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fsmoves",	two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsmoves",	two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fsmovew",	two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fsmovew",	two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsmovew",	two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fsmovex",	two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fsmovex",	two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 {"fsmovep",	two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 
 {"fdmoveb",	two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fdmoveb",	two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdmoveb",	two(0xF000, 0x7844), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
+{"fdmoved",	two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fdmoved",	two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fdmoved",	two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
+{"fdmoved",	two(0xF000, 0x7444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fdmovel",	two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fdmovel",	two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdmovel",	two(0xF000, 0x6044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fdmoves",	two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fdmoves",	two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdmoves",	two(0xF000, 0x6444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fdmovew",	two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fdmovew",	two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdmovew",	two(0xF000, 0x7044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
 {"fdmovex",	two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fdmovex",	two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 {"fdmovep",	two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 
 {"fmovecrx",	two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat },
 
+{"fmovemd",	two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizsl3", cfloat },
+{"fmovemd",	two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat },
+{"fmovemd",	two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat },
+{"fmovemd",	two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Iil3ys", cfloat },
+
 {"fmovemx",	two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat },
 {"fmovemx",	two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat },
 {"fmovemx",	two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat },
@@ -814,6 +938,11 @@ const struct m68k_opcode m68k_opcodes[] =
    target is a single %fpiar.  */
 {"fmoveml",	two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat },
 
+{"fmovem",	two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "IizsL3", cfloat },
+{"fmovem",	two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat },
+{"fmovem",	two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat },
+{"fmovem",	two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "IiL3ys", cfloat },
+
 {"fmovem",	two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat },
 {"fmovem",	two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat },
 {"fmovem",	two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat },
@@ -832,63 +961,102 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fmovem",	two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat },
 
 {"fmulb",	two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"fmulb",	two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fmuld",	two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fmuld",	two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fmuld",	two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fmull",	two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fmull",	two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fmulp",	two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fmuls",	two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fmuls",	two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fmulw",	two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fmulw",	two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fmulx",	two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fmulx",	two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 
 {"fsmulb",	two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fsmulb",	two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsmuld",	two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fsmuld",	two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fsmuld",	two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fsmull",	two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fsmull",	two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsmulp",	two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fsmuls",	two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fsmuls",	two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsmulw",	two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fsmulw",	two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsmulx",	two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fsmulx",	two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 
 {"fdmulb",	two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fdmulb",	two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdmuld",	two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fdmuld",	two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fdmuld",	two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fdmull",	two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fdmull",	two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdmulp",	two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fdmuls",	two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fdmuls",	two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdmulw",	two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fdmulw",	two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdmulx",	two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fdmulx",	two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 
 {"fnegb",	two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"fnegb",	two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fnegd",	two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fnegd",	two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt",   cfloat },
 {"fnegd",	two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fnegd",	two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fnegl",	two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fnegl",	two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fnegp",	two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fnegs",	two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fnegs",	two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fnegw",	two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fnegw",	two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fnegx",	two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fnegx",	two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 {"fnegx",	two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
 {"fsnegb",	two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fsnegb",	two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsnegd",	two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fsnegd",	two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt",   cfloat },
 {"fsnegd",	two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fsnegd",	two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fsnegl",	two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fsnegl",	two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsnegp",	two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fsnegs",	two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fsnegs",	two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsnegw",	two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fsnegw",	two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsnegx",	two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fsnegx",	two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 {"fsnegx",	two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt",   m68040up },
 
 {"fdnegb",	two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fdnegb",	two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdnegd",	two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fdnegd",	two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt",   cfloat },
 {"fdnegd",	two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fdnegd",	two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fdnegl",	two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fdnegl",	two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdnegp",	two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fdnegs",	two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fdnegs",	two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdnegw",	two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fdnegw",	two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdnegx",	two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fdnegx",	two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 {"fdnegx",	two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt",   m68040up },
 
-{"fnop",	two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat },
+{"fnop",	two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat },
 
 {"fremb",	two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
 {"fremd",	two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
@@ -900,8 +1068,10 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fremx",	two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 
 {"frestore",	one(0xF140),		one(0xF1C0), "Id<s", mfloat },
+{"frestore",	one(0xF140),		one(0xF1C0), "Idys", cfloat },
 
 {"fsave",	one(0xF100),		one(0xF1C0), "Id>s", mfloat },
+{"fsave",	one(0xF100),		one(0xF1C0), "Idzs", cfloat },
 
 {"fscaleb",	two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
 {"fscaled",	two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
@@ -998,60 +1168,98 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fsinhx",	two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
 {"fsqrtb",	two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"fsqrtb",	two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsqrtd",	two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fsqrtd",	two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt",   cfloat },
 {"fsqrtd",	two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fsqrtd",	two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fsqrtl",	two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fsqrtl",	two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsqrtp",	two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fsqrts",	two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fsqrts",	two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsqrtw",	two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fsqrtw",	two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsqrtx",	two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fsqrtx",	two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 {"fsqrtx",	two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
 {"fssqrtb",	two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fssqrtb",	two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fssqrtd",	two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fssqrtd",	two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt",   cfloat },
 {"fssqrtd",	two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fssqrtd",	two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fssqrtl",	two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fssqrtl",	two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fssqrtp",	two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fssqrts",	two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fssqrts",	two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fssqrtw",	two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fssqrtw",	two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fssqrtx",	two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fssqrtx",	two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 {"fssqrtx",	two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt",   m68040up },
 
 {"fdsqrtb",	two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fdsqrtb",	two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fdsqrtd",	two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fdsqrtd",	two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt",   cfloat },
 {"fdsqrtd",	two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
 {"fdsqrtl",	two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fdsqrtl",	two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdsqrtp",	two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fdsqrts",	two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fdsqrts",	two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdsqrtw",	two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fdsqrtw",	two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdsqrtx",	two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fdsqrtx",	two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 {"fdsqrtx",	two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt",   m68040up },
 
 {"fsubb",	two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
+{"fsubb",	two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
+{"fsubd",	two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fsubd",	two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
+{"fsubd",	two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fsubl",	two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
+{"fsubl",	two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsubp",	two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
 {"fsubs",	two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
+{"fsubs",	two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsubw",	two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
+{"fsubw",	two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fsubx",	two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fsubx",	two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 {"fsubx",	two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt",   mfloat },
 
+{"fssubb",	two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fssubb",	two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fssubd",	two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
 {"fssubd",	two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fssubd",	two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fssubl",	two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
+{"fssubl",	two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fssubp",	two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
 {"fssubs",	two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fssubs",	two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fssubw",	two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
+{"fssubw",	two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fssubx",	two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fssubx",	two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
 {"fssubx",	two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt",   m68040up },
 
+{"fdsubb",	two(0xF000, 0x586A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdsubb",	two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
+{"fdsubd",	two(0xF000, 0x006A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
+{"fdsubd",	two(0xF000, 0x546A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
 {"fdsubd",	two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
+{"fdsubl",	two(0xF000, 0x406A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdsubl",	two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
 {"fdsubp",	two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
+{"fdsubs",	two(0xF000, 0x446A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdsubs",	two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
+{"fdsubw",	two(0xF000, 0x506A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
 {"fdsubw",	two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
 {"fdsubx",	two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
 {"fdsubx",	two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
@@ -1119,7 +1327,7 @@ const struct m68k_opcode m68k_opcodes[] =
 {"ftrapule",	two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat },
 {"ftrapult",	two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat },
 {"ftrapun",	two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat },
-        
+
 {"ftrapeqw",	two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
 {"ftrapfw",	two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
 {"ftrapgew",	two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
@@ -1187,11 +1395,17 @@ const struct m68k_opcode m68k_opcodes[] =
 {"ftrapunl",	two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
 
 {"ftstb",	two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat },
+{"ftstb",	two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
+{"ftstd",	two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", cfloat },
 {"ftstd",	two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat },
+{"ftstd",	two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
 {"ftstl",	two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat },
+{"ftstl",	two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
 {"ftstp",	two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat },
 {"ftsts",	two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat },
+{"ftsts",	two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
 {"ftstw",	two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat },
+{"ftstw",	two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
 {"ftstx",	two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat },
 {"ftstx",	two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat },
 
@@ -1207,7 +1421,8 @@ const struct m68k_opcode m68k_opcodes[] =
 
 {"halt",	one(0045310),	one(0177777), "",     m68060 | mcf },
 
-{"illegal",	one(0045374),	one(0177777), "",     m68000up },
+{"illegal",	one(0045374),	one(0177777), "",     m68000up | mcf },
+{"intouch",	one(0xf428),	one(0xfff8), "As",    mcfv4eup },
 
 {"jmp",		one(0047300),	one(0177700), "!s", m68000up | mcf },
 
@@ -1245,57 +1460,57 @@ const struct m68k_opcode m68k_opcodes[] =
 {"lsrl",	one(0160250),	one(0170770), "DdDs", m68000up | mcf },
 
   /* FIXME: add MAM mode (`&' after <ea> operand) / remove MACM */
-{"macw",  two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5307up | mcf5206e },
-{"macw",  two(0120000, 0001000), two(0170660, 0005400), "uMumMh",mcf5307up | mcf5206e },
-{"macw",  two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e },
-{"macw",  two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e },
-{"macw",  two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e },
-{"macw",  two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e },
-{"macw",  two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e },
-{"macw",  two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e },
-{"macw",  two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e },
-{"macw",  two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e },
-{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e },
-{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e },
-{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e },
-{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e },
-{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e },
-{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e },
-{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e },
-{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e },
-
-{"macl",  two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5307up | mcf5206e },
-{"macl",  two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5307up | mcf5206e },
-{"macl",  two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e },
-{"macl",  two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e },
-{"macl",  two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e },
-{"macl",  two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e },
-{"macl",  two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e },
-{"macl",  two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e },
-{"macl",  two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e },
-{"macl",  two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e },
-{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e },
-{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e },
-{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e },
-{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e },
-{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e },
-{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e },
-{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e },
-{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e },
-
-/* NOTE: The mcf5200 family programmer's reference manual does not 
+{"macw",  two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5206eup },
+{"macw",  two(0120000, 0001000), two(0170660, 0005400), "uMumMh",mcf5206eup },
+{"macw",  two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
+{"macw",  two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
+{"macw",  two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
+{"macw",  two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
+{"macw",  two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
+{"macw",  two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
+{"macw",  two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
+{"macw",  two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
+{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
+{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
+{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
+{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
+{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
+{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
+{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
+{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
+
+{"macl",  two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5206eup },
+{"macl",  two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5206eup },
+{"macl",  two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
+{"macl",  two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
+{"macl",  two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
+{"macl",  two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
+{"macl",  two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
+{"macl",  two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
+{"macl",  two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
+{"macl",  two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
+{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
+{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
+{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
+{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
+{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
+{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
+{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
+{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
+
+/* NOTE: The mcf5200 family programmer's reference manual does not
    indicate the byte form of the movea instruction is invalid (as it
    is on 68000 family cpus).  However, experiments on the 5202 yeild
    unexpected results.  The value is copied, but it is not sign extended
-   (as is done with movea.w) and the top three bytes in the address 
+   (as is done with movea.w) and the top three bytes in the address
    register are not disturbed.  I don't know if this is the intended
    behavior --- it could be a hole in instruction decoding (Motorola
    decided not to trap all invalid instructions for performance reasons)
-   --- but I suspect that it is not.   
+   --- but I suspect that it is not.
 
-   I reported this to Motorola ISD Technical Communications Support, 
-   which replied that other coldfire assemblers reject movea.b.  For 
-   this reason I've decided to not allow moveab. 
+   I reported this to Motorola ISD Technical Communications Support,
+   which replied that other coldfire assemblers reject movea.b.  For
+   this reason I've decided to not allow moveab.
 
 	jtc@cygnus.com - 97/01/24
  */
@@ -1347,13 +1562,13 @@ const struct m68k_opcode m68k_opcodes[] =
 {"moveb",	one(0010200),	one(0170700), "obad", mcf },
 {"moveb",	one(0010300),	one(0170700), "ob+d", mcf },
 {"moveb",	one(0010400),	one(0170700), "ob-d", mcf },
-{"moveb",	one(0010000),	one(0170000), "obnd", mcf5407 },
+{"moveb",	one(0010000),	one(0170000), "obnd", mcfv4up },
 
 {"movew",	one(0030000),	one(0170000), "*w%d", m68000up },
 {"movew",	one(0030000),	one(0170000), "ms%d", mcf },
 {"movew",	one(0030000),	one(0170000), "nspd", mcf },
 {"movew",	one(0030000),	one(0170000), "owmd", mcf },
-{"movew",	one(0030000),	one(0170000), "ownd", mcf5407 },
+{"movew",	one(0030000),	one(0170000), "ownd", mcfv4up },
 {"movew",	one(0040300),	one(0177700), "Ss$s", m68000up },
 {"movew",	one(0040300),	one(0177770), "SsDs", mcf },
 {"movew",	one(0041300),	one(0177700), "Cs$s", m68010up },
@@ -1370,25 +1585,25 @@ const struct m68k_opcode m68k_opcodes[] =
 {"movel",	one(0020000),	one(0170000), "ms%d", mcf },
 {"movel",	one(0020000),	one(0170000), "nspd", mcf },
 {"movel",	one(0020000),	one(0170000), "olmd", mcf },
-{"movel",	one(0020000),	one(0170000), "olnd", mcf5407 },
-{"movel",	one(0047140),	one(0177770), "AsUd", m68000up },
-{"movel",	one(0047150),	one(0177770), "UdAs", m68000up },
-{"movel",	one(0120600),	one(0177760), "EsRs", mcf5307up | mcf5206e },
-{"movel",	one(0120400),	one(0177760), "RsEs", mcf5307up | mcf5206e },
-{"movel",	one(0120474),	one(0177777), "#lEs", mcf5307up | mcf5206e },
-{"movel",	one(0124600),	one(0177760), "GsRs", mcf5307up | mcf5206e },
-{"movel",	one(0124400),	one(0177760), "RsGs", mcf5307up | mcf5206e },
-{"movel",	one(0124474),	one(0177777), "#lGs", mcf5307up | mcf5206e },
-{"movel",	one(0126600),	one(0177760), "HsRs", mcf5307up | mcf5206e },
-{"movel",	one(0126400),	one(0177760), "RsHs", mcf5307up | mcf5206e },
-{"movel",	one(0126474),	one(0177777), "#lHs", mcf5307up | mcf5206e },
-{"movel",	one(0124700),	one(0177777), "GsCs", mcf5307up | mcf5206e },
+{"movel",	one(0020000),	one(0170000), "olnd", mcfv4up },
+{"movel",	one(0047140),	one(0177770), "AsUd", m68000up | mcfv4e },
+{"movel",	one(0047150),	one(0177770), "UdAs", m68000up | mcfv4e },
+{"movel",	one(0120600),	one(0177760), "EsRs", mcf5206eup },
+{"movel",	one(0120400),	one(0177760), "RsEs", mcf5206eup },
+{"movel",	one(0120474),	one(0177777), "#lEs", mcf5206eup },
+{"movel",	one(0124600),	one(0177760), "GsRs", mcf5206eup },
+{"movel",	one(0124400),	one(0177760), "RsGs", mcf5206eup },
+{"movel",	one(0124474),	one(0177777), "#lGs", mcf5206eup },
+{"movel",	one(0126600),	one(0177760), "HsRs", mcf5206eup },
+{"movel",	one(0126400),	one(0177760), "RsHs", mcf5206eup },
+{"movel",	one(0126474),	one(0177777), "#lHs", mcf5206eup },
+{"movel",	one(0124700),	one(0177777), "GsCs", mcf5206eup },
 
 {"move",	one(0030000),	one(0170000), "*w%d", m68000up },
 {"move",	one(0030000),	one(0170000), "ms%d", mcf },
 {"move",	one(0030000),	one(0170000), "nspd", mcf },
 {"move",	one(0030000),	one(0170000), "owmd", mcf },
-{"move",	one(0030000),	one(0170000), "ownd", mcf5407 },
+{"move",	one(0030000),	one(0170000), "ownd", mcfv4up },
 {"move",	one(0040300),	one(0177700), "Ss$s", m68000up },
 {"move",	one(0040300),	one(0177770), "SsDs", mcf },
 {"move",	one(0041300),	one(0177700), "Cs$s", m68010up },
@@ -1403,11 +1618,11 @@ const struct m68k_opcode m68k_opcodes[] =
 {"move",	one(0047140),	one(0177770), "AsUd", m68000up },
 {"move",	one(0047150),	one(0177770), "UdAs", m68000up },
 
-{"mov3ql",	one(0120500),	one(0170700), "Qd%s", mcf5407 },
-{"mvsb",	one(0070400),	one(0170700), "*bDd", mcf5407 },
-{"mvsw",	one(0070500),	one(0170700), "*wDd", mcf5407 },
-{"mvzb",	one(0070600),	one(0170700), "*bDd", mcf5407 },
-{"mvzw",	one(0070700),	one(0170700), "*wDd", mcf5407 },
+{"mov3ql",	one(0120500),	one(0170700), "xd%s", mcfv4up },
+{"mvsb",	one(0070400),	one(0170700), "*bDd", mcfv4up },
+{"mvsw",	one(0070500),	one(0170700), "*wDd", mcfv4up },
+{"mvzb",	one(0070600),	one(0170700), "*bDd", mcfv4up },
+{"mvzw",	one(0070700),	one(0170700), "*wDd", mcfv4up },
 
 {"movesb",	two(0007000, 0),     two(0177700, 07777), "~sR1", m68010up },
 {"movesb",	two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up },
@@ -1423,43 +1638,43 @@ const struct m68k_opcode m68k_opcodes[] =
 {"move16",	one(0xf618),		one(0xfff8), "_Las", m68040up },
 
   /* FIXME: add MAM mode (`&' after <ea> operand) / remove MSACM */
-{"msacw",  two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5307up | mcf5206e },
-{"msacw",  two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5307up | mcf5206e },
-{"msacw",  two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e },
-{"msacw",  two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e },
-{"msacw",  two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e },
-{"msacw",  two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e },
-{"msacw",  two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e },
-{"msacw",  two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e },
-{"msacw",  two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e },
-{"msacw",  two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e },
-{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e },
-{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e },
-{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e },
-{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e },
-{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e },
-{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e },
-{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e },
-{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e },
-
-{"msacl",  two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5307up | mcf5206e },
-{"msacl",  two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5307up | mcf5206e },
-{"msacl",  two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e },
-{"msacl",  two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e },
-{"msacl",  two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e },
-{"msacl",  two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e },
-{"msacl",  two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e },
-{"msacl",  two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e },
-{"msacl",  two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e },
-{"msacl",  two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e },
-{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e },
-{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e },
-{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e },
-{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e },
-{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e },
-{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e },
-{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e },
-{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e },
+{"msacw",  two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5206eup },
+{"msacw",  two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5206eup },
+{"msacw",  two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
+{"msacw",  two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
+{"msacw",  two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
+{"msacw",  two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
+{"msacw",  two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
+{"msacw",  two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
+{"msacw",  two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
+{"msacw",  two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
+{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
+{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
+{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
+{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
+{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
+{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
+{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
+{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
+
+{"msacl",  two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5206eup },
+{"msacl",  two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5206eup },
+{"msacl",  two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
+{"msacl",  two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
+{"msacl",  two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
+{"msacl",  two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
+{"msacl",  two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
+{"msacl",  two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
+{"msacl",  two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
+{"msacl",  two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
+{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
+{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
+{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
+{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
+{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
+{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
+{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
+{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
 
 {"mulsw",	one(0140700),		one(0170700), ";wDd", m68000up|mcf },
 {"mulsl",	two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
@@ -1736,8 +1951,8 @@ const struct m68k_opcode m68k_opcodes[] =
 {"pvalid",	two(0xf000, 0x2c00),	two(0xffc0, 0xfff8), "A3&s", m68851 },
 
   /* FIXME: don't allow Dw==Dx. */
-{"remsl",       two(0x4c40, 0x0800),    two(0xffc0, 0x8ff8), "qsD3D1", mcf5307up | mcf5206e },
-{"remul",       two(0x4c40, 0x0000),    two(0xffc0, 0x8ff8), "qsD3D1", mcf5307up | mcf5206e },
+{"remsl",       two(0x4c40, 0x0800),    two(0xffc0, 0x8ff8), "qsD3D1", mcf5206eup },
+{"remul",       two(0x4c40, 0x0000),    two(0xffc0, 0x8ff8), "qsD3D1", mcf5206eup },
 
 {"reset",	one(0047160),		one(0177777), "", m68000up },
 
@@ -1783,7 +1998,7 @@ const struct m68k_opcode m68k_opcodes[] =
 
 {"rts",		one(0047165),		one(0177777), "",   m68000up | mcf },
 
-{"satsl",	one(0046200),		one(0177770), "Ds", mcf5407 },
+{"satsl",	one(0046200),		one(0177770), "Ds", mcfv4up },
 
 {"sbcd",	one(0100400),		one(0170770), "DsDd", m68000up },
 {"sbcd",	one(0100410),		one(0170770), "-s-d", m68000up },
@@ -1823,6 +2038,8 @@ const struct m68k_opcode m68k_opcodes[] =
 
 {"stop",	one(0047162),	one(0177777), "#w", m68000up | mcf },
 
+{"strldsr", two(0040347,0043374), two(0177777,0177777), "#w", mcf528x},
+
 {"subal",	one(0110700),	one(0170700), "*lAd", m68000up | mcf },
 {"subaw",	one(0110300),	one(0170700), "*wAd", m68000up },
 
@@ -1870,7 +2087,7 @@ const struct m68k_opcode m68k_opcodes[] =
 {"swbeg",	one(0045374),	one(0177777), "#w",   m68000up | mcf },
 {"swbegl",	one(0045375),	one(0177777), "#l",   m68000up | mcf },
 
-{"tas",		one(0045300),	one(0177700), "$s", m68000up | mcf5407},
+{"tas",		one(0045300),	one(0177700), "$s", m68000up | mcfv4up},
 
 #define TBL1(name,signed,round,size)					\
   {name, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400),	\
@@ -2205,6 +2422,11 @@ const struct m68k_opcode_alias m68k_opcode_aliases[] =
   { "ftests",	"ftsts", },
   { "ftestw",	"ftstw", },
   { "ftestx",	"ftstx", },
+
+  { "bitrevl",  "bitrev", },  /* for mcf528x only */
+  { "byterevl", "byterev", },
+  { "ff1l",     "ff1", },
+
 };
 
 const int m68k_numaliases =
author	Nick Clifton <nickc@redhat.com>	2003-10-21 13:28:59 +0000
committer	Nick Clifton <nickc@redhat.com>	2003-10-21 13:28:59 +0000
commit	3e602632663c14cea25d8b12d1306eccbc1c9be3 (patch)
tree	b81f6d5469007aef81bccd5c8a1e2ff151de70fe
parent	8b7d96c1c421f4cb319e3a49e943f862171387d6 (diff)
download	gdb-3e602632663c14cea25d8b12d1306eccbc1c9be3.zip gdb-3e602632663c14cea25d8b12d1306eccbc1c9be3.tar.gz gdb-3e602632663c14cea25d8b12d1306eccbc1c9be3.tar.bz2