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authorDoug Evans <dje@google.com>2009-02-06 23:14:34 +0000
committerDoug Evans <dje@google.com>2009-02-06 23:14:34 +0000
commitfedc618eee02ae10102122a38fb696d520186b63 (patch)
tree1410f0ec1f0f23153c4da32ed180c3ca13dcbfcd
parent5b009018d2759269b0fd192077a391c795ebfa97 (diff)
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* i386.h: Add comment regarding sse* insns and prefixes.
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/i386.h5
2 files changed, 9 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index e256e6e..adf3940 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2009-02-06 Doug Evans <dje@google.com>
+
+ * i386.h: Add comment regarding sse* insns and prefixes.
+
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (INSN_XLR): Define.
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 4311cd6..d60db76 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -59,6 +59,11 @@
/* The opcode for the fwait instruction, which disassembler treats as a
prefix when it can. */
#define FWAIT_OPCODE 0x9b
+
+/* Instruction prefixes.
+ NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
+ part of the opcode. Other prefixes may still appear between them
+ and the 0x0f part of the opcode. */
#define ADDR_PREFIX_OPCODE 0x67
#define DATA_PREFIX_OPCODE 0x66
#define LOCK_PREFIX_OPCODE 0xf0