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| author | Nick Clifton <nickc@redhat.com> | 2012-05-15 12:55:51 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2012-05-15 12:55:51 +0000 |
| commit | 6927f98292aaa6f7fcb3152d5d902758538e626c (patch) | |
| tree | b459b91d4d7f001cc57214f7c4a554b7ab3cb192 | |
| parent | 9cc815f56d3c2f1fc8f033b869693975bceb9633 (diff) | |
| download | gdb-6927f98292aaa6f7fcb3152d5d902758538e626c.zip gdb-6927f98292aaa6f7fcb3152d5d902758538e626c.tar.gz gdb-6927f98292aaa6f7fcb3152d5d902758538e626c.tar.bz2 | |
* config/tc-m68hc11.c: Add S12X and XGATE co-processor support.
Add option to offset S12 addresses into XGATE memory space.
Tweak target flags to match other tools. (i.e. -m m68hc11).
* doc/as.texinfo: Mention new options.
* doc/c-m68hc11.texi: Document new options.
* NEWS: Mention new support.
* archures.c: Add bfd_arch_m9s12x and bfd_arch_m9s12xg.
* config.bfd: Likewise.
* cpu-m9s12x.c: New.
* cpu-m9s12xg.c: New.
* elf32-m68hc12.c: Add S12X and XGATE co-processor support.
Add option to offset S12 addresses into XGATE memory space.
Fix carry bug in IMM16 (IMM8 low/high) relocate.
* Makefile.am (ALL_MACHINES): Add cpu-m9s12x and cpu-m9s12xg.
(ALL_MACHINES_CFILES): Likewise.
* reloc.c: Add S12X relocs.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* gas/m68hc11/insns9s12x.s: New
* gas/m68hc11/insns9s12x.d: New
* gas/m68hc11/hexprefix.s: New
* gas/m68hc11/hexprefix.d: New
* gas/m68hc11/9s12x-exg-sex-tfr.s: New
* gas/m68hc11/9s12x-exg-sex-tfr.d: New
* gas/m68hc11/insns9s12xg.s: New
* gas/m68hc11/insns9s12xg.d: New
* gas/m68hc11/9s12x-mov.s: New
* gas/m68hc11/9s12x-mov.d: New
* gas/m68hc11/m68hc11.exp: Updated
* gas/m68hc11/*.d: Brought in line with changed objdump output.
* gas/all/gas.exp: XFAIL all hc11/12 targets for redef2,3.
* gas/elf/elf.exp: XFAIL all hc11/12 targets for redef.
* gas/elf/dwarf2-1.d: Skip for hc11/12 targets.
* gas/elf/dwarf2-2.d: Likewise.
* ld-m68hc11/xgate-link.s: New.
* ld-m68hc11/xgate-link.d: New.
* ld-m68hc11/xgate-offset.s: New.
* ld-m68hc11/xgate-offset.d: New.
* ld-m68hc11/xgate1.s: New.
* ld-m68hc11/xgate1.d: New.
* ld-m68hc11/xgate2.s: New.
* ld-m68hc11/m68hc11.exp: Updated.
* ld-m68hc11/*.d: Brought in line with changed objdump output.
* ld-gc/gc.exp: Update CFLAGS for m68hc11.
* ld-plugin/plugin.exp: Likewise.
* ld-srec/srec.exp: XFAIL for m68hc11 and m68hc12.
* configure.in: Add S12X and XGATE co-processor support to m68hc11
target.
* disassemble.c: Likewise.
* configure: Regenerate.
* m68hc11-dis.c: Make objdump output more consistent, use hex
instead of decimal and use 0x prefix for hex.
* m68hc11-opc.c: Add S12X and XGATE opcodes.
* dis-asm.h (print_insn_m9s12x): Prototype.
(print_insn_m9s12xg): Prototype.
* m68hc11.h (R_M68HC12_16B, R_M68HC12_PCREL_9, R_M68HC12_PCREL_10)
R_M68HC12_HI8XG, R_M68HC12_LO8XG): New relocations.
(E_M68HC11_XGATE_RAMOFFSET): Define.
* m68hc11.h: Add XGate definitions.
(struct m68hc11_opcode): Add xg_mask field.
82 files changed, 6088 insertions, 2621 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index be53666..05bc0de 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,20 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + Stephane Carrez <stcarrez@nerim.fr> + + * archures.c: Add bfd_arch_m9s12x and bfd_arch_m9s12xg. + * config.bfd: Likewise. + * cpu-m9s12x.c: New. + * cpu-m9s12xg.c: New. + * elf32-m68hc12.c: Add S12X and XGATE co-processor support. + Add option to offset S12 addresses into XGATE memory space. + Fix carry bug in IMM16 (IMM8 low/high) relocate. + * Makefile.am (ALL_MACHINES): Add cpu-m9s12x and cpu-m9s12xg. + (ALL_MACHINES_CFILES): Likewise. + * reloc.c: Add S12X relocs. + * Makefile.in: Regenerate. + * bfd-in2.h: Regenerate. + * libbfd.h: Regenerate. + 2012-05-14 James Lemke <jwlemke@codesourcery.com> Catherine Moore <clm@codesourcery.com> @@ -36,7 +53,7 @@ (elf_backend_lookup_section_flags_hook): Define. (elf_backend_section_flags): Define. (elf_backend_section_processing): Define. - * elf32-ppc.h (ppc_elf_section_processing): Declare. + * elf32-ppc.h (ppc_elf_section_processing): Declare. * libbfd.h: Regenerated. * reloc.c (BFD_RELOC_PPC_VLE_REL8, BFD_RELOC_PPC_VLE_REL15, BFD_RELOC_PPC_VLE_REL24, BFD_RELOC_PPC_VLE_LO16A, diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 0414cc7..b7271cc 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -105,6 +105,8 @@ ALL_MACHINES = \ cpu-m32r.lo \ cpu-m68hc11.lo \ cpu-m68hc12.lo \ + cpu-m9s12x.lo \ + cpu-m9s12xg.lo \ cpu-m68k.lo \ cpu-m88k.lo \ cpu-mcore.lo \ @@ -183,6 +185,8 @@ ALL_MACHINES_CFILES = \ cpu-m32r.c \ cpu-m68hc11.c \ cpu-m68hc12.c \ + cpu-m9s12x.c \ + cpu-m9s12xg.c \ cpu-m68k.c \ cpu-m88k.c \ cpu-mcore.c \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index bf3a162..7a48fda 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -404,6 +404,8 @@ ALL_MACHINES = \ cpu-m32r.lo \ cpu-m68hc11.lo \ cpu-m68hc12.lo \ + cpu-m9s12x.lo \ + cpu-m9s12xg.lo \ cpu-m68k.lo \ cpu-m88k.lo \ cpu-mcore.lo \ @@ -482,6 +484,8 @@ ALL_MACHINES_CFILES = \ cpu-m32r.c \ cpu-m68hc11.c \ cpu-m68hc12.c \ + cpu-m9s12x.c \ + cpu-m9s12xg.c \ cpu-m68k.c \ cpu-m88k.c \ cpu-mcore.c \ diff --git a/bfd/archures.c b/bfd/archures.c index c6f1c2a..a23534b 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -266,6 +266,8 @@ DESCRIPTION .#define bfd_mach_m6812_default 0 .#define bfd_mach_m6812 1 .#define bfd_mach_m6812s 2 +. bfd_arch_m9s12x, {* Freescale S12X *} +. bfd_arch_m9s12xg, {* Freescale XGATE *} . bfd_arch_z8k, {* Zilog Z8000 *} .#define bfd_mach_z8001 1 .#define bfd_mach_z8002 2 @@ -535,6 +537,8 @@ extern const bfd_arch_info_type bfd_m32c_arch; extern const bfd_arch_info_type bfd_m32r_arch; extern const bfd_arch_info_type bfd_m68hc11_arch; extern const bfd_arch_info_type bfd_m68hc12_arch; +extern const bfd_arch_info_type bfd_m9s12x_arch; +extern const bfd_arch_info_type bfd_m9s12xg_arch; extern const bfd_arch_info_type bfd_m68k_arch; extern const bfd_arch_info_type bfd_m88k_arch; extern const bfd_arch_info_type bfd_mcore_arch; @@ -618,6 +622,8 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_m32r_arch, &bfd_m68hc11_arch, &bfd_m68hc12_arch, + &bfd_m9s12x_arch, + &bfd_m9s12xg_arch, &bfd_m68k_arch, &bfd_m88k_arch, &bfd_mcore_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 8e6ff42..fa2b9a5 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1958,6 +1958,8 @@ enum bfd_architecture #define bfd_mach_m6812_default 0 #define bfd_mach_m6812 1 #define bfd_mach_m6812s 2 + bfd_arch_m9s12x, /* Freescale S12X */ + bfd_arch_m9s12xg, /* Freescale XGATE */ bfd_arch_z8k, /* Zilog Z8000 */ #define bfd_mach_z8001 1 #define bfd_mach_z8002 2 @@ -4546,6 +4548,32 @@ This is a 4-bit pc-relative reloc. */ This is a 5-bit pc-relative reloc. */ BFD_RELOC_XGATE_IMM5, +/* Motorola 68HC12 reloc. +This is the 9 bits of a value. */ + BFD_RELOC_M68HC12_9B, + +/* Motorola 68HC12 reloc. +This is the 16 bits of a value. */ + BFD_RELOC_M68HC12_16B, + +/* Motorola 68HC12/XGATE reloc. +This is a PCREL9 branch. */ + BFD_RELOC_M68HC12_9_PCREL, + +/* Motorola 68HC12/XGATE reloc. +This is a PCREL10 branch. */ + BFD_RELOC_M68HC12_10_PCREL, + +/* Motorola 68HC12/XGATE reloc. +This is the 8 bit low part of an absolute address and immediately precedes +a matching HI8XG part. */ + BFD_RELOC_M68HC12_LO8XG, + +/* Motorola 68HC12/XGATE reloc. +This is the 8 bit high part of an absolute address and immediately follows +a matching LO8XG part. */ + BFD_RELOC_M68HC12_HI8XG, + /* NS CR16C Relocations. */ BFD_RELOC_16C_NUM08, BFD_RELOC_16C_NUM08_C, diff --git a/bfd/config.bfd b/bfd/config.bfd index 3f758c0..783d1f3 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -85,8 +85,8 @@ hppa*) targ_archs=bfd_hppa_arch ;; i[3-7]86) targ_archs=bfd_i386_arch ;; i370) targ_archs=bfd_i370_arch ;; lm32) targ_archs=bfd_lm32_arch ;; -m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch" ;; -m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;; +m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;; +m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;; m68*) targ_archs=bfd_m68k_arch ;; m88*) targ_archs=bfd_m88k_arch ;; microblaze*) targ_archs=bfd_microblaze_arch ;; diff --git a/bfd/cpu-m9s12x.c b/bfd/cpu-m9s12x.c new file mode 100644 index 0000000..d224b83 --- /dev/null +++ b/bfd/cpu-m9s12x.c @@ -0,0 +1,41 @@ +/* BFD support for the Freescale 9S12X processor + Copyright 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_m9s12x_arch = +{ + 16, /* 16 bits in a word. */ + 32, /* 16 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_m9s12x, + 0, + "m9s12x", + "m9s12x", + 4, /* Section alignment power. */ + TRUE, + bfd_default_compatible, + bfd_default_scan, + bfd_arch_default_fill, + 0, +}; + diff --git a/bfd/cpu-m9s12xg.c b/bfd/cpu-m9s12xg.c new file mode 100644 index 0000000..6958a13 --- /dev/null +++ b/bfd/cpu-m9s12xg.c @@ -0,0 +1,41 @@ +/* BFD support for the Freescale 9S12-XGATE co-processor + Copyright 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_m9s12xg_arch = +{ + 16, /* 16 bits in a word. */ + 32, /* 16 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_m9s12xg, + 0, + "m9s12xg", + "m9s12xg", + 4, /* Section alignment power. */ + TRUE, + bfd_default_compatible, + bfd_default_scan, + bfd_arch_default_fill, + 0, +}; + diff --git a/bfd/elf32-m68hc12.c b/bfd/elf32-m68hc12.c index 2b16641..448853d 100644 --- a/bfd/elf32-m68hc12.c +++ b/bfd/elf32-m68hc12.c @@ -324,11 +324,81 @@ static reloc_howto_type elf_m68hc11_howto_table[] = { FALSE), /* pcrel_offset */ EMPTY_HOWTO (14), - EMPTY_HOWTO (15), - EMPTY_HOWTO (16), - EMPTY_HOWTO (17), - EMPTY_HOWTO (18), - EMPTY_HOWTO (19), + + /* A 16 bit absolute relocation. */ + HOWTO (R_M68HC12_16B, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC12_16B", /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 9 bit PC-rel relocation. */ + HOWTO (R_M68HC12_PCREL_9, /* type */ + 1, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 10, /* bitsize (result is >>1) */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC12_PCREL_9", /* name */ + TRUE, /* partial_inplace */ + 0xfe00, /* src_mask */ + 0x01ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* A 10 bit PC-rel relocation. */ + HOWTO (R_M68HC12_PCREL_10, /* type */ + 1, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 11, /* bitsize (result is >>1) */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC12_PCREL_10", /* name */ + TRUE, /* partial_inplace */ + 0xfc00, /* src_mask */ + 0x03ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* A 8 bit absolute relocation (upper address). */ + HOWTO (R_M68HC12_HI8XG, /* type */ + 8, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC12_HI8XG", /* name */ + FALSE, /* partial_inplace */ + 0x00ff, /* src_mask */ + 0x00ff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 8 bit absolute relocation (lower address). */ + HOWTO (R_M68HC12_LO8XG, /* type */ + 8, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC12_LO8XG", /* name */ + FALSE, /* partial_inplace */ + 0x00ff, /* src_mask */ + 0x00ff, /* dst_mask */ + FALSE), /* pcrel_offset */ /* Mark beginning of a jump instruction (any form). */ HOWTO (R_M68HC11_RL_JUMP, /* type */ @@ -369,7 +439,8 @@ struct m68hc11_reloc_map unsigned char elf_reloc_val; }; -static const struct m68hc11_reloc_map m68hc11_reloc_map[] = { +static const struct m68hc11_reloc_map m68hc11_reloc_map[] = +{ {BFD_RELOC_NONE, R_M68HC11_NONE,}, {BFD_RELOC_8, R_M68HC11_8}, {BFD_RELOC_M68HC11_HI8, R_M68HC11_HI8}, @@ -389,6 +460,13 @@ static const struct m68hc11_reloc_map m68hc11_reloc_map[] = { {BFD_RELOC_M68HC11_RL_JUMP, R_M68HC11_RL_JUMP}, {BFD_RELOC_M68HC11_RL_GROUP, R_M68HC11_RL_GROUP}, + + {BFD_RELOC_M68HC12_16B, R_M68HC12_16B}, + + {BFD_RELOC_M68HC12_9_PCREL, R_M68HC12_PCREL_9}, + {BFD_RELOC_M68HC12_10_PCREL, R_M68HC12_PCREL_10}, + {BFD_RELOC_M68HC12_HI8XG, R_M68HC12_HI8XG}, + {BFD_RELOC_M68HC12_LO8XG, R_M68HC12_LO8XG}, }; static reloc_howto_type * diff --git a/bfd/elf32-m68hc1x.c b/bfd/elf32-m68hc1x.c index f5762a4..70bf09e 100644 --- a/bfd/elf32-m68hc1x.c +++ b/bfd/elf32-m68hc1x.c @@ -949,6 +949,7 @@ elf32_m68hc11_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, bfd_vma insn_page; bfd_boolean is_far = FALSE; struct elf_link_hash_entry *h; + bfd_vma val; r_symndx = ELF32_R_SYM (rel->r_info); r_type = ELF32_R_TYPE (rel->r_info); @@ -1029,6 +1030,50 @@ elf32_m68hc11_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, phys_page = m68hc11_phys_page (pinfo, relocation + rel->r_addend); switch (r_type) { + case R_M68HC12_LO8XG: + /* This relocation is specific to XGATE IMM16 calls and will precede + a HI8. tc-m68hc11 only generates them in pairs. + Leave the relocation to the HI8XG step. */ + r = bfd_reloc_ok; + r_type = R_M68HC11_NONE; + break; + + case R_M68HC12_HI8XG: + /* This relocation is specific to XGATE IMM16 calls and must follow + a LO8XG. Does not actually check that it was a LO8XG. + Adjusts high and low bytes. */ + relocation = phys_addr; + if ((elf_elfheader (input_bfd)->e_flags & E_M68HC11_XGATE_RAMOFFSET) + && (relocation >= 0x2000)) + relocation += 0xc000; /* HARDCODED RAM offset for XGATE. */ + + /* Fetch 16 bit value including low byte in previous insn. */ + val = (bfd_get_8 (input_bfd, (bfd_byte*) contents + rel->r_offset) << 8) + | bfd_get_8 (input_bfd, (bfd_byte*) contents + rel->r_offset - 2); + + /* Add on value to preserve carry, then write zero to high byte. */ + relocation += val; + + /* Write out top byte. */ + bfd_put_8 (input_bfd, (relocation >> 8) & 0xff, + (bfd_byte*) contents + rel->r_offset); + + /* Write out low byte to previous instruction. */ + bfd_put_8 (input_bfd, relocation & 0xff, + (bfd_byte*) contents + rel->r_offset - 2); + + /* Mark as relocation completed. */ + r = bfd_reloc_ok; + r_type = R_M68HC11_NONE; + break; + + /* The HI8 and LO8 relocs are generated by %hi(expr) %lo(expr) + assembler directives. %hi does not support carry. */ + case R_M68HC11_HI8: + case R_M68HC11_LO8: + relocation = phys_addr; + break; + case R_M68HC11_24: /* Reloc used by 68HC12 call instruction. */ bfd_put_16 (input_bfd, phys_addr, @@ -1123,10 +1168,18 @@ elf32_m68hc11_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, relocation = phys_addr; break; } + if (r_type != R_M68HC11_NONE) - r = _bfd_final_link_relocate (howto, input_bfd, input_section, + { + if ((r_type == R_M68HC12_PCREL_9) || (r_type == R_M68HC12_PCREL_10)) + r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents, rel->r_offset, - relocation, rel->r_addend); + relocation - 2, rel->r_addend); + else + r = _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, + relocation, rel->r_addend); + } if (r != bfd_reloc_ok) { @@ -1317,6 +1370,9 @@ _bfd_m68hc11_elf_print_private_bfd_data (bfd *abfd, void *ptr) else fprintf (file, _(" [memory=flat]")); + if (elf_elfheader (abfd)->e_flags & E_M68HC11_XGATE_RAMOFFSET) + fprintf (file, _(" [XGATE RAM offsetting]")); + fputc ('\n', file); return TRUE; diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 94fb0a1..173c009 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -2125,6 +2125,12 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_XGATE_IMM3", "BFD_RELOC_XGATE_IMM4", "BFD_RELOC_XGATE_IMM5", + "BFD_RELOC_M68HC12_9B", + "BFD_RELOC_M68HC12_16B", + "BFD_RELOC_M68HC12_9_PCREL", + "BFD_RELOC_M68HC12_10_PCREL", + "BFD_RELOC_M68HC12_LO8XG", + "BFD_RELOC_M68HC12_HI8XG", "BFD_RELOC_16C_NUM08", "BFD_RELOC_16C_NUM08_C", "BFD_RELOC_16C_NUM16", diff --git a/bfd/reloc.c b/bfd/reloc.c index a9fd397..978fe8d 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -5092,6 +5092,38 @@ ENUMDOC Freescale XGATE reloc. This is a 5-bit pc-relative reloc. ENUM + BFD_RELOC_M68HC12_9B +ENUMDOC + Motorola 68HC12 reloc. + This is the 9 bits of a value. +ENUM + BFD_RELOC_M68HC12_16B +ENUMDOC + Motorola 68HC12 reloc. + This is the 16 bits of a value. +ENUM + BFD_RELOC_M68HC12_9_PCREL +ENUMDOC + Motorola 68HC12/XGATE reloc. + This is a PCREL9 branch. +ENUM + BFD_RELOC_M68HC12_10_PCREL +ENUMDOC + Motorola 68HC12/XGATE reloc. + This is a PCREL10 branch. +ENUM + BFD_RELOC_M68HC12_LO8XG +ENUMDOC + Motorola 68HC12/XGATE reloc. + This is the 8 bit low part of an absolute address and immediately precedes + a matching HI8XG part. +ENUM + BFD_RELOC_M68HC12_HI8XG +ENUMDOC + Motorola 68HC12/XGATE reloc. + This is the 8 bit high part of an absolute address and immediately follows + a matching LO8XG part. +ENUM BFD_RELOC_16C_NUM08 ENUMX BFD_RELOC_16C_NUM08_C diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 7072d1e..fc8420c 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,7 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + + * readelf.c (get_machine_name): Update m68hc12 entry. + 2012-05-13 H.J. Lu <hongjiu.lu@intel.com> * objdump.c (disassemble_bytes): Print addend as signed. diff --git a/binutils/readelf.c b/binutils/readelf.c index a2884b2..212f70e 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -1868,7 +1868,6 @@ get_machine_name (unsigned e_machine) case EM_IA_64: return "Intel IA-64"; case EM_MIPS_X: return "Stanford MIPS-X"; case EM_COLDFIRE: return "Motorola Coldfire"; - case EM_68HC12: return "Motorola M68HC12"; case EM_ALPHA: return "Alpha"; case EM_CYGNUS_D10V: case EM_D10V: return "d10v"; @@ -1903,6 +1902,7 @@ get_machine_name (unsigned e_machine) case EM_ST9PLUS: return "STMicroelectronics ST9+ 8/16 bit microcontroller"; case EM_ST7: return "STMicroelectronics ST7 8-bit microcontroller"; case EM_68HC16: return "Motorola MC68HC16 Microcontroller"; + case EM_68HC12: return "Motorola MC68HC12 Microcontroller"; case EM_68HC11: return "Motorola MC68HC11 Microcontroller"; case EM_68HC08: return "Motorola MC68HC08 Microcontroller"; case EM_68HC05: return "Motorola MC68HC05 Microcontroller"; diff --git a/gas/ChangeLog b/gas/ChangeLog index 680a659..80e1518 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,12 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + + * config/tc-m68hc11.c: Add S12X and XGATE co-processor support. + Add option to offset S12 addresses into XGATE memory space. + Tweak target flags to match other tools. (i.e. -m m68hc11). + * doc/as.texinfo: Mention new options. + * doc/c-m68hc11.texi: Document new options. + * NEWS: Mention new support. + 2012-05-14 DJ Delorie <dj@redhat.com> * config/rx-parse.y (rx_range): declare. @@ -50,7 +59,7 @@ (md_show_usage): Document -mvle. (ppc_arch): Recognize VLE. (ppc_mach): Recognize bfd_mach_ppc_vle. - (ppc_setup_opcodes): Print the opcode table if + (ppc_setup_opcodes): Print the opcode table if * config/tc-ppc.h (ppc_frag_check): Declare. * doc/c-ppc.texi: Document -mvle. * NEWS: Mention PowerPC VLE port. @@ -61,7 +70,7 @@ (DWARF2_LINE_MIN_INSN_LENGTH): Redefine. * config/tc-ppc.c (ppc_dw2_line_min_insn_length): New. * dwarf2dbg.c (scale_addr_delta): Handle values of 1 - for DWARF2_LINE_MIN_INSN_LENGTH. + for DWARF2_LINE_MIN_INSN_LENGTH. 2012-05-12 H.J. Lu <hongjiu.lu@intel.com> @@ -1,5 +1,7 @@ -*- text -*- +* Add support for S12X processor. + * Add support for the VLE extension to the PowerPC architecture. * Add support for the Freescale XGATE architecture. diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c index 2e328ea..6211f9d 100644 --- a/gas/config/tc-m68hc11.c +++ b/gas/config/tc-m68hc11.c @@ -1,7 +1,9 @@ /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12. - Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010 + Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010, + 2011, 2012 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) + XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk) This file is part of GAS, the GNU Assembler. @@ -65,7 +67,8 @@ const char FLT_CHARS[] = "dD"; How many bytes this mode will add to the size of the frag. Which mode to go to if the offset won't fit in this one. */ -relax_typeS md_relax_table[] = { +relax_typeS md_relax_table[] = +{ {1, 1, 0, 0}, /* First entries aren't used. */ {1, 1, 0, 0}, /* For no good reason except. */ {1, 1, 0, 0}, /* that the VAX doesn't either. */ @@ -116,7 +119,8 @@ relax_typeS md_relax_table[] = { }; /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */ -typedef enum register_id { +typedef enum register_id +{ REG_NONE = -1, REG_A = 0, REG_B = 1, @@ -125,17 +129,30 @@ typedef enum register_id { REG_X = 5, REG_Y = 6, REG_SP = 7, - REG_PC = 8 + REG_PC = 8, + REG_R0 = 0, + REG_R1 = 1, + REG_R2 = 2, + REG_R3 = 3, + REG_R4 = 4, + REG_R5 = 5, + REG_R6 = 6, + REG_R7 = 7, + REG_SP_XG = 8, + REG_PC_XG = 9, + REG_CCR_XG = 10 } register_id; -typedef struct operand { +typedef struct operand +{ expressionS exp; register_id reg1; register_id reg2; int mode; } operand; -struct m68hc11_opcode_def { +struct m68hc11_opcode_def +{ long format; int min_operands; int max_operands; @@ -147,18 +164,30 @@ struct m68hc11_opcode_def { static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0; static int m68hc11_nb_opcode_defs = 0; -typedef struct alias { +typedef struct alias +{ const char *name; const char *alias; } alias; -static alias alias_opcodes[] = { +static alias alias_opcodes[] = +{ {"cpd", "cmpd"}, {"cpx", "cmpx"}, {"cpy", "cmpy"}, {0, 0} }; +struct m9s12xg_opcode_def +{ + long format; + int min_operands; + int max_operands; + int nb_modes; + int used; + struct m9s12xg_opcode *opcode; +}; + /* Local functions. */ static register_id reg_name_search (char *); static register_id register_name (void); @@ -173,6 +202,7 @@ static int get_operand (operand *, int, long); static void fixup8 (expressionS *, int, int); static void fixup16 (expressionS *, int, int); static void fixup24 (expressionS *, int, int); +static void fixup8_xg (expressionS *, int, int); static unsigned char convert_branch (unsigned char); static char *m68hc11_new_insn (int); static void build_dbranch_insn (struct m68hc11_opcode *, @@ -185,6 +215,7 @@ static struct m68hc11_opcode *find (struct m68hc11_opcode_def *, static struct m68hc11_opcode *find_opcode (struct m68hc11_opcode_def *, operand *, int *); static void build_jump_insn (struct m68hc11_opcode *, operand *, int, int); +static void build_insn_xg (struct m68hc11_opcode *, operand *, int); static void build_insn (struct m68hc11_opcode *, operand *, int); static int relaxable_symbol (symbolS *); @@ -259,10 +290,12 @@ static int elf_flags = E_M68HC11_F64; pseudo-op name without dot function to call to execute this pseudo-op Integer arg to pass to the function. */ -const pseudo_typeS md_pseudo_table[] = { +const pseudo_typeS md_pseudo_table[] = +{ /* The following pseudo-ops are supported for MRI compatibility. */ {"fcb", cons, 1}, {"fdb", cons, 2}, + {"fqb", cons, 4}, {"fcc", stringer, 8 + 1}, {"rmb", s_space, 0}, @@ -288,7 +321,8 @@ const pseudo_typeS md_pseudo_table[] = { const char *md_shortopts = "Sm:"; -struct option md_longopts[] = { +struct option md_longopts[] = +{ #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE) {"force-long-branches", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelt version kept for backwards compatibility. */ @@ -321,6 +355,9 @@ struct option md_longopts[] = { #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9) {"mlong-double", no_argument, NULL, OPTION_MLONG_DOUBLE}, +#define OPTION_XGATE_RAMOFFSET (OPTION_MD_BASE + 10) + {"xgate-ramoffset", no_argument, NULL, OPTION_XGATE_RAMOFFSET}, + {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof (md_longopts); @@ -360,6 +397,10 @@ m68hc11_listing_header (void) { if (current_architecture & cpu6811) return "M68HC11 GAS "; + else if (current_architecture & cpuxgate) + return "XGATE GAS "; + else if (current_architecture & cpu9s12x) + return "S12X GAS "; else return "M68HC12 GAS "; } @@ -371,7 +412,8 @@ md_show_usage (FILE *stream) fprintf (stream, _("\ Motorola 68HC11/68HC12/68HCS12 options:\n\ -m68hc11 | -m68hc12 |\n\ - -m68hcs12 specify the processor [default %s]\n\ + -m68hcs12 | -mm9s12x |\n\ + -mm9s12xg specify the processor [default %s]\n\ -mshort use 16-bit int ABI (default)\n\ -mlong use 32-bit int ABI\n\ -mshort-double use 32-bit double ABI\n\ @@ -383,6 +425,7 @@ Motorola 68HC11/68HC12/68HCS12 options:\n\ when the instruction does not support direct mode\n\ --print-insn-syntax print the syntax of instruction in case of error\n\ --print-opcodes print the list of instructions with syntax\n\ + --xgate-ramoffset offset ram addresses by 0xc000\n\ --generate-example generate an example of each instruction\n\ (used for testing)\n"), default_cpu); @@ -490,13 +533,26 @@ md_parse_option (int c, char *arg) elf_flags |= E_M68HC11_F64; break; + case OPTION_XGATE_RAMOFFSET: + elf_flags |= E_M68HC11_XGATE_RAMOFFSET; + break; + case 'm': - if (strcasecmp (arg, "68hc11") == 0) + if ((strcasecmp (arg, "68hc11") == 0) + || (strcasecmp (arg, "m68hc11") == 0)) current_architecture = cpu6811; - else if (strcasecmp (arg, "68hc12") == 0) + else if ((strcasecmp (arg, "68hc12") == 0) + || (strcasecmp (arg, "m68hc12") == 0)) current_architecture = cpu6812; - else if (strcasecmp (arg, "68hcs12") == 0) + else if ((strcasecmp (arg, "68hcs12") == 0) + || (strcasecmp (arg, "m68hcs12") == 0)) current_architecture = cpu6812 | cpu6812s; + else if (strcasecmp (arg, "m9s12x") == 0) + current_architecture = cpu6812 | cpu6812s | cpu9s12x; + else if ((strcasecmp (arg, "m9s12xg") == 0) + || (strcasecmp (arg, "xgate") == 0)) + /* xgate for backwards compatability */ + current_architecture = cpuxgate; else as_bad (_("Option `%s' is not recognized."), arg); break; @@ -614,23 +670,39 @@ md_begin (void) /* See how many operands this opcode needs. */ expect = 0; - if (opcodes->format & M6811_OP_MASK) - expect++; - if (opcodes->format & M6811_OP_BITMASK) - expect++; - if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) - expect++; - if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) - expect++; - /* Special case for call instruction. */ - if ((opcodes->format & M6812_OP_PAGE) - && !(opcodes->format & M6811_OP_IND16)) - expect++; + if (opcodes->arch == cpuxgate) + { + if (opcodes->format & (M68XG_OP_IMM3 | M68XG_OP_R | M68XG_OP_REL9 + | M68XG_OP_REL10 )) + expect = 1; + else if (opcodes->format & (M68XG_OP_R_R | M68XG_OP_R_IMM4 + | M68XG_OP_R_IMM8 | M68XG_OP_R_IMM8)) + expect = 2; + else if (opcodes->format & (M68XG_OP_R_R_R | M68XG_OP_R_R_OFFS5 + | M68XG_OP_RD_RB_RI | M68XG_OP_RD_RB_RIp + | M68XG_OP_RD_RB_mRI)) + expect = 3; + } + else + { + if (opcodes->format & M6811_OP_MASK) + expect++; + if (opcodes->format & M6811_OP_BITMASK) + expect++; + if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) + expect++; + if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) + expect++; + /* Special case for call instruction. */ + if ((opcodes->format & M6812_OP_PAGE) + && !(opcodes->format & M6811_OP_IND16)) + expect++; + } if (expect < opc->min_operands) opc->min_operands = expect; if (IS_CALL_SYMBOL (opcodes->format)) - expect++; + expect++; if (expect > opc->max_operands) opc->max_operands = expect; } @@ -654,6 +726,7 @@ m68hc11_init_after_args (void) /* Return a string that represents the operand format for the instruction. When example is true, this generates an example of operand. This is used to give an example and also to generate a test. */ + static char * print_opcode_format (struct m68hc11_opcode *opcode, int example) { @@ -663,111 +736,222 @@ print_opcode_format (struct m68hc11_opcode *opcode, int example) p = buf; buf[0] = 0; - if (format & M6811_OP_IMM8) - { - if (example) - sprintf (p, "#%d", rand () & 0x0FF); - else - strcpy (p, _("#<imm8>")); - p = &p[strlen (p)]; - } - if (format & M6811_OP_IMM16) + if (current_architecture == cpuxgate) { - if (example) - sprintf (p, "#%d", rand () & 0x0FFFF); - else - strcpy (p, _("#<imm16>")); - p = &p[strlen (p)]; + if (format & M68XG_OP_IMM3) + { + if (example) + sprintf (p, "#%d", rand () & 0x007); + else + strcpy (p, _("imm3")); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_R) + { + if (example) + sprintf (p, "R%d", rand () & 0x07); + else + strcpy (p, _("RD")); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_R_R) + { + if (example) + sprintf (p, "R%d,R%d", rand () & 0x07, rand () & 0x07); + else + strcpy (p, _("RD,RS")); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_R_IMM4) + { + if (example) + sprintf (p, "R%d,#%d", rand () & 0x07, rand () & 0x0f); + else + strcpy (p, _("RI, #imm4")); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_R_R_R) + { + if (example) + sprintf (p, "R%d,R%d,R%d", rand () & 0x07, rand () & 0x07, rand () & 0x07); + else + strcpy (p, "RD,RS1,RS2"); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_REL9) + { + if (example) + sprintf (p, "%d", rand () & 0x1FF); + else + strcpy (p, "<rel9>"); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_REL10) + { + if (example) + sprintf (p, "%d", rand () & 0x3FF); + else + strcpy (p, "<rel10>"); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_R_R_OFFS5) + { + if (example) + sprintf (p, "R%d, (R%d, #0x%x)", rand () & 0x07, rand () & 0x07, rand () & 0x1f); + else + strcpy (p, _("RD, (RI,#offs5)")); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_RD_RB_RI) + { + if (example) + sprintf (p, "R%d, (R%d, R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07); + else + strcpy (p, "RD, (RB, RI)"); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_RD_RB_RIp) + { + if (example) + sprintf (p, "R%d, (R%d, R%d+)", rand () & 0x07, rand () & 0x07, rand () & 0x07); + else + strcpy (p, "RD, (RB, RI+)"); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_RD_RB_mRI) + { + if (example) + sprintf (p, "R%d, (R%d, -R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07); + else + strcpy (p, "RD, (RB, -RI)"); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_R_IMM8) + { + if (example) + sprintf (p, "R%d, #0x%x", rand () & 0x07, rand () & 0xff); + else + strcpy (p, "RD, #imm8"); + p = &p[strlen (p)]; + } + else if (format & M68XG_OP_R_IMM16) + { + if (example) + sprintf (p, "R%d, #0x%x", rand () & 0x07, rand () & 0xffff); + else + strcpy (p, "RD, #imm16"); + p = &p[strlen (p)]; + } } - - if (format & M6811_OP_IX) + else { - if (example) - sprintf (p, "%d,X", rand () & 0x0FF); - else - strcpy (p, _("<imm8>,X")); - p = &p[strlen (p)]; - } - if (format & M6811_OP_IY) - { - if (example) - sprintf (p, "%d,X", rand () & 0x0FF); - else - strcpy (p, _("<imm8>,X")); - p = &p[strlen (p)]; - } + if (format & M6811_OP_IMM8) + { + if (example) + sprintf (p, "#%d", rand () & 0x0FF); + else + strcpy (p, _("#<imm8>")); + p = &p[strlen (p)]; + } - if (format & M6812_OP_IDX) - { - if (example) - sprintf (p, "%d,X", rand () & 0x0FF); - else - strcpy (p, "n,r"); - p = &p[strlen (p)]; - } + if (format & M6811_OP_IMM16) + { + if (example) + sprintf (p, "#%d", rand () & 0x0FFFF); + else + strcpy (p, _("#<imm16>")); + p = &p[strlen (p)]; + } - if (format & M6812_OP_PAGE) - { - if (example) - sprintf (p, ", %d", rand () & 0x0FF); - else - strcpy (p, ", <page>"); - p = &p[strlen (p)]; - } + if (format & M6811_OP_IX) + { + if (example) + sprintf (p, "%d,X", rand () & 0x0FF); + else + strcpy (p, _("<imm8>,X")); + p = &p[strlen (p)]; + } - if (format & M6811_OP_DIRECT) - { - if (example) - sprintf (p, "*Z%d", rand () & 0x0FF); - else - strcpy (p, _("*<abs8>")); - p = &p[strlen (p)]; - } + if (format & M6811_OP_IY) + { + if (example) + sprintf (p, "%d,X", rand () & 0x0FF); + else + strcpy (p, _("<imm8>,X")); + p = &p[strlen (p)]; + } - if (format & M6811_OP_BITMASK) - { - if (buf[0]) - *p++ = ' '; + if (format & M6812_OP_IDX) + { + if (example) + sprintf (p, "%d,X", rand () & 0x0FF); + else + strcpy (p, "n,r"); + p = &p[strlen (p)]; + } - if (example) - sprintf (p, "#$%02x", rand () & 0x0FF); - else - strcpy (p, _("#<mask>")); + if (format & M6812_OP_PAGE) + { + if (example) + sprintf (p, ", %d", rand () & 0x0FF); + else + strcpy (p, ", <page>"); + p = &p[strlen (p)]; + } - p = &p[strlen (p)]; - if (format & M6811_OP_JUMP_REL) - *p++ = ' '; - } + if (format & M6811_OP_DIRECT) + { + if (example) + sprintf (p, "*Z%d", rand () & 0x0FF); + else + strcpy (p, _("*<abs8>")); + p = &p[strlen (p)]; + } - if (format & M6811_OP_IND16) - { - if (example) - sprintf (p, _("symbol%d"), rand () & 0x0FF); - else - strcpy (p, _("<abs>")); + if (format & M6811_OP_BITMASK) + { + if (buf[0]) + *p++ = ' '; - p = &p[strlen (p)]; - } + if (example) + sprintf (p, "#$%02x", rand () & 0x0FF); + else + strcpy (p, _("#<mask>")); - if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) - { - if (example) + p = &p[strlen (p)]; + if (format & M6811_OP_JUMP_REL) + *p++ = ' '; + } + + if (format & M6811_OP_IND16) { - if (format & M6811_OP_BITMASK) - { - sprintf (p, ".+%d", rand () & 0x7F); - } + if (example) + sprintf (p, _("symbol%d"), rand () & 0x0FF); else + strcpy (p, _("<abs>")); + + p = &p[strlen (p)]; + } + + if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) + { + if (example) { - sprintf (p, "L%d", rand () & 0x0FF); + if (format & M6811_OP_BITMASK) + { + sprintf (p, ".+%d", rand () & 0x7F); + } + else + { + sprintf (p, "L%d", rand () & 0x0FF); + } } + else + strcpy (p, _("<label>")); } - else - strcpy (p, _("<label>")); } - return buf; } @@ -870,7 +1054,29 @@ reg_name_search (char *name) return REG_PC; if (strcasecmp (name, "ccr") == 0) return REG_CCR; - +/* XGATE */ + if (strcasecmp (name, "r0") == 0) + return REG_R0; + if (strcasecmp (name, "r1") == 0) + return REG_R1; + if (strcasecmp (name, "r2") == 0) + return REG_R2; + if (strcasecmp (name, "r3") == 0) + return REG_R3; + if (strcasecmp (name, "r4") == 0) + return REG_R4; + if (strcasecmp (name, "r5") == 0) + return REG_R5; + if (strcasecmp (name, "r6") == 0) + return REG_R6; + if (strcasecmp (name, "r7") == 0) + return REG_R7; + if (strcasecmp (name, "sp") == 0) + return REG_SP_XG; + if (strcasecmp (name, "pc") == 0) + return REG_PC_XG; + if (strcasecmp (name, "ccr") == 0) + return REG_CCR_XG; return REG_NONE; } @@ -1271,51 +1477,83 @@ get_operand (operand *oper, int which, long opmode) static int check_range (long num, int mode) { - /* Auto increment and decrement are ok for [-8..8] without 0. */ - if (mode & M6812_AUTO_INC_DEC) - return (num != 0 && num <= 8 && num >= -8); + if (current_architecture == cpuxgate) + { + switch (mode) + { + case M68XG_OP_IMM3: + return (num >= 0 && num <= 7) ? 1 : 0; - /* The 68HC12 supports 5, 9 and 16-bit offsets. */ - if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX)) - mode = M6811_OP_IND16; + case M68XG_OP_R_IMM4: + return (num >= 0 && num <= 15) ? 1 : 0; - if (mode & M6812_OP_JUMP_REL16) - mode = M6811_OP_IND16; + case M68XG_OP_R_R_OFFS5: + return (num >= 0 && num <= 31) ? 1 : 0; - mode &= ~M6811_OP_BRANCH; - switch (mode) - { - case M6811_OP_IX: - case M6811_OP_IY: - case M6811_OP_DIRECT: - return (num >= 0 && num <= 255) ? 1 : 0; + case M68XG_OP_R_IMM8: + return (num >= 0 && num <= 255) ? 1 : 0; - case M6811_OP_BITMASK: - case M6811_OP_IMM8: - case M6812_OP_PAGE: - return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00)) - ? 1 : 0; + case M68XG_OP_R_IMM16: + return (num >= 0 && num <= 65535) ? 1 : 0; - case M6811_OP_JUMP_REL: - return (num >= -128 && num <= 127) ? 1 : 0; + case M68XG_OP_B_MARKER: + return (num >= -512 && num <= 511) ? 1 : 0; - case M6811_OP_IND16: - case M6811_OP_IND16 | M6812_OP_PAGE: - case M6811_OP_IMM16: - return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000)) - ? 1 : 0; + case M68XG_OP_BRA_MARKER: + return (num >= -1024 && num <= 1023) ? 1 : 0; - case M6812_OP_IBCC_MARKER: - case M6812_OP_TBCC_MARKER: - case M6812_OP_DBCC_MARKER: - return (num >= -256 && num <= 255) ? 1 : 0; + default: + return 0; + } + } + else + { + /* Auto increment and decrement are ok for [-8..8] without 0. */ + if (mode & M6812_AUTO_INC_DEC) + return (num != 0 && num <= 8 && num >= -8); - case M6812_OP_TRAP_ID: - return ((num >= 0x30 && num <= 0x39) - || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0; + /* The 68HC12 supports 5, 9 and 16-bit offsets. */ + if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX)) + mode = M6811_OP_IND16; - default: - return 0; + if (mode & M6812_OP_JUMP_REL16) + mode = M6811_OP_IND16; + + mode &= ~M6811_OP_BRANCH; + switch (mode) + { + case M6811_OP_IX: + case M6811_OP_IY: + case M6811_OP_DIRECT: + return (num >= 0 && num <= 255) ? 1 : 0; + + case M6811_OP_BITMASK: + case M6811_OP_IMM8: + case M6812_OP_PAGE: + return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00)) + ? 1 : 0; + + case M6811_OP_JUMP_REL: + return (num >= -128 && num <= 127) ? 1 : 0; + + case M6811_OP_IND16: + case M6811_OP_IND16 | M6812_OP_PAGE: + case M6811_OP_IMM16: + return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000)) + ? 1 : 0; + + case M6812_OP_IBCC_MARKER: + case M6812_OP_TBCC_MARKER: + case M6812_OP_DBCC_MARKER: + return (num >= -256 && num <= 255) ? 1 : 0; + + case M6812_OP_TRAP_ID: + return ((num >= 0x30 && num <= 0x39) + || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0; + + default: + return 0; + } } } @@ -1473,10 +1711,92 @@ fixup24 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED) as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op); } } + +/* XGATE Put a 1 byte expression described by 'oper'. If this expression + containts unresolved symbols, generate an 8-bit fixup. */ +static void +fixup8_xg (expressionS *oper, int mode, int opmode) +{ + char *f; + + f = frag_more (1); + + if (oper->X_op == O_constant) + { + fixS *fixp; + int reloc; + + if ((opmode & M6811_OP_HIGH_ADDR) || (opmode & M6811_OP_LOW_ADDR)) + { + if (opmode & M6811_OP_HIGH_ADDR) + reloc = BFD_RELOC_M68HC11_HI8; + else + reloc = BFD_RELOC_M68HC11_LO8; + + fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, + oper, FALSE, reloc); + fixp->fx_no_overflow = 1; + number_to_chars_bigendian (f, 0, 1); + } + else + { + if (!(check_range (oper->X_add_number, mode))) + as_bad (_("Operand out of 8-bit range: `%ld'."), + oper->X_add_number); + number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1); + } + } + else if (oper->X_op != O_register) + { + if (mode == M68XG_OP_REL9) + { + fixS *fixp; + + /* Future improvement: + This fixup/reloc isn't adding on constants to symbols. */ + fixp = fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2, + oper, TRUE, BFD_RELOC_M68HC12_9_PCREL); + fixp->fx_pcrel_adjust = 1; + } + else if (mode == M68XG_OP_REL10) + { + fixS *fixp; + + /* Future improvement: + This fixup/reloc isn't adding on constants to symbols. */ + fixp = fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2, + oper, TRUE, BFD_RELOC_M68HC12_10_PCREL); + fixp->fx_pcrel_adjust = 1; + } + else + { + fixS *fixp; + int reloc; + + /* Now create an 8-bit fixup. If there was some %hi, %lo + modifier, generate the reloc accordingly. */ + if (opmode & M6811_OP_HIGH_ADDR) + reloc = BFD_RELOC_M68HC11_HI8; + else if (opmode & M6811_OP_LOW_ADDR) + reloc = BFD_RELOC_M68HC11_LO8; + else + reloc = BFD_RELOC_8; + + fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, + oper, FALSE, reloc); + if (reloc != BFD_RELOC_8) + fixp->fx_no_overflow = 1; + } + number_to_chars_bigendian (f, 0, 1); + } + else + as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op); +} /* 68HC11 and 68HC12 code generation. */ /* Translate the short branch/bsr instruction into a long branch. */ + static unsigned char convert_branch (unsigned char code) { @@ -1741,6 +2061,7 @@ build_dbranch_insn (struct m68hc11_opcode *opcode, operand operands[], #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4) /* Assemble the post index byte for 68HC12 extended addressing modes. */ + static int build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) { @@ -1760,15 +2081,15 @@ build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) if (op->exp.X_op == O_constant) { if (!check_range (val, mode)) - { - as_bad (_("Increment/decrement value is out of range: `%ld'."), - val); - } + as_bad (_("Increment/decrement value is out of range: `%ld'."), + val); + if (mode & (M6812_POST_INC | M6812_PRE_INC)) byte |= (val - 1) & 0x07; else byte |= (8 - ((val) & 7)) | 0x8; } + switch (op->reg1) { case REG_NONE: @@ -1820,14 +2141,15 @@ build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) as_bad (_("Invalid register.")); break; } + if (op->exp.X_op == O_constant) { if (!check_range (val, M6812_OP_IDX)) - { - as_bad (_("Offset out of 16-bit range: %ld."), val); - } + as_bad (_("Offset out of 16-bit range: %ld."), val); - if (move_insn && !(val >= -16 && val <= 15)) + if (move_insn && !(val >= -16 && val <= 15) + && ((!(mode & M6812_OP_IDX) && !(mode & M6812_OP_D_IDX_2)) + || !(current_architecture & cpu9s12x))) { as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."), val); @@ -1867,6 +2189,7 @@ build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) return 3; } } + if (mode & M6812_OP_D_IDX_2) { byte = (byte << 3) | 0xe3; @@ -1889,14 +2212,31 @@ build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) sym = make_expr_symbol (&op->exp); off = 0; } + /* movb/movw cannot be relaxed. */ if (move_insn) { - byte <<= 6; - number_to_chars_bigendian (f, byte, 1); - fix_new (frag_now, f - frag_now->fr_literal, 1, - sym, off, 0, BFD_RELOC_M68HC12_5B); - return 1; + if ((mode & M6812_OP_IDX) && (current_architecture & cpu9s12x)) + { + /* Must treat as a 16bit relocate as size of final result is unknown. */ + + byte <<= 3; + byte |= 0b11100010; + number_to_chars_bigendian (f, byte, 1); + fix_new (frag_now, f - frag_now->fr_literal, 2, + sym, off, 0, BFD_RELOC_M68HC12_16B); + f = frag_more (2); + return 1; + } + else + { + /* Non-S12X will fail at relocate stage if offset out of range. */ + byte <<= 6; + number_to_chars_bigendian (f, byte, 1); + fix_new (frag_now, f - frag_now->fr_literal, 1, + sym, off, 0, BFD_RELOC_M68HC12_5B); + return 1; + } } else { @@ -1909,6 +2249,7 @@ build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) else { f = frag_more (1); + /* movb/movw cannot be relaxed. */ if (move_insn) { @@ -1936,7 +2277,7 @@ build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) { if (op->reg1 != REG_D) as_bad (_("Expecting register D for indexed indirect mode.")); - if (move_insn) + if ((move_insn) && (!(current_architecture & cpu9s12x))) as_bad (_("Indexed indirect mode is not allowed for movb/movw.")); byte = 0xE7; @@ -1987,6 +2328,8 @@ build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) return 1; } + fprintf (stderr, "mode = 0x%x\nop->reg1 = 0x%x\nop->reg2 = 0x%x\n", + mode, op->reg1, op->reg2); as_fatal (_("Addressing mode not implemented yet.")); return 0; } @@ -1998,8 +2341,9 @@ build_reg_mode (operand *op, int format) unsigned char byte; char *f; - if (format & M6812_OP_SEX_MARKER - && op->reg1 != REG_A && op->reg1 != REG_B && op->reg1 != REG_CCR) + if ((format & M6812_OP_SEX_MARKER) + && (op->reg1 != REG_A) && (op->reg1 != REG_B) && (op->reg1 != REG_CCR) + && (!(current_architecture & cpu9s12x))) as_bad (_("Invalid source register for this instruction, use 'tfr'.")); else if (op->reg1 == REG_NONE || op->reg1 == REG_PC) as_bad (_("Invalid source register.")); @@ -2015,17 +2359,96 @@ build_reg_mode (operand *op, int format) if (format & M6812_OP_EXG_MARKER) byte |= 0x80; + if ((format & M6812_OP_SEX_MARKER) + && (op->reg1 == REG_D) && (current_architecture & cpu9s12x)) + byte |= 0x08; + f = frag_more (1); number_to_chars_bigendian (f, byte, 1); return 1; } +/* build_insn_xg takes a pointer to the opcode entry in the opcode table, + the array of operand expressions and builds the corresponding instruction. */ + +static void +build_insn_xg (struct m68hc11_opcode *opcode, + operand operands[], + int nb_operands ATTRIBUTE_UNUSED) +{ + char *f; + long format; + + /* Put the page code instruction if there is one. */ + format = opcode->format; + + if (!(operands[0].mode & (M6811_OP_LOW_ADDR | M6811_OP_HIGH_ADDR))) + /* Need to retain those two modes, but clear for others. */ + operands[0].mode = 0; + + if (format & M68XG_OP_R_IMM8) + { + /* These opcodes are byte followed by imm8. */ + f = m68hc11_new_insn (1); + number_to_chars_bigendian (f, opcode->opcode >> 8, 1); + fixup8_xg (&operands[0].exp, format, operands[0].mode); + } + else if (format & M68XG_OP_R_IMM16) + { + fixS *fixp; + /* These opcodes expand into two imm8 instructions. + Emit as low:high as per the Freescale datasheet. + The linker requires them to be adjacent to handle the upper byte. */ + + /* Build low byte. */ + f = m68hc11_new_insn (1); + number_to_chars_bigendian (f, opcode->opcode >> 8, 1); + operands[0].mode = M6811_OP_LOW_ADDR; + f = frag_more (1); + fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, + &operands[0].exp, FALSE, BFD_RELOC_M68HC12_LO8XG); + fixp->fx_no_overflow = 1; + number_to_chars_bigendian (f, 0, 1); + + /* Build high byte. */ + f = m68hc11_new_insn (1); + number_to_chars_bigendian (f, (opcode->opcode >> 8) | 0x08, 1); + operands[0].mode = M6811_OP_HIGH_ADDR; + f = frag_more (1); + fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, + &operands[0].exp, FALSE, BFD_RELOC_M68HC12_HI8XG); + fixp->fx_no_overflow = 1; + number_to_chars_bigendian (f, 0, 1); + + } + else if (format & M68XG_OP_REL9) + { + f = m68hc11_new_insn (1); + number_to_chars_bigendian (f, opcode->opcode >> 8, 1); /* High byte. */ + fixup8_xg (&operands[0].exp, format, M68XG_OP_REL9); + } + else if (format & M68XG_OP_REL10) + { + f = m68hc11_new_insn (1); + number_to_chars_bigendian (f, opcode->opcode >> 8, 1); /* High byte. */ + fixup8_xg (&operands[0].exp, format, M68XG_OP_REL10); + } + else + { + f = m68hc11_new_insn (2); + number_to_chars_bigendian (f, opcode->opcode, 2); + } + return; +} + /* build_insn takes a pointer to the opcode entry in the opcode table, the array of operand expressions and builds the corresponding instruction. This operation only deals with non relative jumps insn (need special handling). */ + static void -build_insn (struct m68hc11_opcode *opcode, operand operands[], +build_insn (struct m68hc11_opcode *opcode, + operand operands[], int nb_operands ATTRIBUTE_UNUSED) { int i; @@ -2159,6 +2582,21 @@ find (struct m68hc11_opcode_def *opc, operand operands[], int nb_operands) opcode = opc->opcode; /* Now search the opcode table table for one with operands + that matches what we've got. */ + + if (current_architecture & cpuxgate) + { + /* Many XGATE insns are simple enough that we get an exact match. */ + for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++) + if (opcode->format == operands[nb_operands-1].mode) + return opcode; + + return 0; + } + + /* Non XGATE */ + + /* Now search the opcode table table for one with operands that matches what we've got. We're only done if the operands matched so far AND there are no more to check. */ for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++) @@ -2260,7 +2698,7 @@ find (struct m68hc11_opcode_def *opc, operand operands[], int nb_operands) || operands[i].reg1 == REG_SP || operands[i].reg1 == REG_PC)) continue; - if (i == 1 && format & M6812_OP_IDX_P2) + if (i == 1 && (format & M6812_OP_IDX_P2)) continue; } if (mode & format & (M6812_OP_D_IDX | M6812_OP_D_IDX_2)) @@ -2301,12 +2739,7 @@ find (struct m68hc11_opcode_def *opc, operand operands[], int nb_operands) match = 1; } - if (!match) - { - return (0); - } - - return opcode; + return match ? opcode : 0; } /* Find the real opcode and its associated operands. We use a progressive @@ -2387,6 +2820,7 @@ md_assemble (char *str) struct m68hc11_opcode_def *opc; struct m68hc11_opcode *opcode; + struct m68hc11_opcode opcode_local; unsigned char *op_start, *op_end; char *save; char name[20]; @@ -2419,6 +2853,629 @@ md_assemble (char *str) return; } + if (current_architecture == cpuxgate) + { + /* Find the opcode definition given its name. */ + opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); + if (opc == NULL) + { + as_bad (_("Opcode `%s' is not recognized."), name); + return; + } + + /* Grab a local copy. */ + opcode_local.name = opc->opcode->name; + /* These will be incomplete where multiple variants exist. */ + opcode_local.opcode = opc->opcode->opcode; + opcode_local.format = opc->opcode->format; + + save = input_line_pointer; + input_line_pointer = (char *) op_end; + + if (opc->format == M68XG_OP_NONE) + { + /* No special handling required. */ + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (opc->opcode, operands, 0); + return; + } + + /* Special handling of TFR. */ + if (strncmp (opc->opcode->name, "tfr",3) == 0) + { + /* There must be two operands with a comma. */ + input_line_pointer = skip_whites (input_line_pointer); + operands[0].reg1 = register_name (); + if (operands[0].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + input_line_pointer = skip_whites (input_line_pointer); + if (*input_line_pointer != ',') + { + as_bad ("Missing comma.\n"); + return; + } + input_line_pointer++; + input_line_pointer = skip_whites (input_line_pointer); + operands[1].reg1 = register_name (); + if (operands[1].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + input_line_pointer = skip_whites (input_line_pointer); + if (*input_line_pointer != '\n' && *input_line_pointer) + { + as_bad (_("Garbage at end of instruction: `%s'."), + input_line_pointer); + return; + } + if (operands[1].reg1 == REG_CCR) /* ,CCR */ + opc->opcode->opcode = 0x00f8 | ( operands[0].reg1 << 8); + else if (operands[0].reg1 == REG_CCR) /* CCR, */ + opc->opcode->opcode = 0x00f9 | ( operands[1].reg1 << 8); + else if (operands[1].reg1 == REG_PC) /* ,PC */ + opc->opcode->opcode = 0x00fa | ( operands[0].reg1 << 8); + else + { + as_bad ("Invalid operand to TFR\n"); + return; + } + /* no special handling required */ + opcode_local.format = M68XG_OP_NONE; + opcode_local.opcode = opc->opcode->opcode; + build_insn_xg (&opcode_local, operands, 0); + return; + } + + /* CSEM, SSEM */ + if (opc->format & M68XG_OP_IMM3) + { + /* Either IMM3 or R */ + input_line_pointer = skip_whites (input_line_pointer); + if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) + { + operands[0].reg1 = register_name (); + if (operands[0].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + operands[0].mode = M68XG_OP_R; + /* One opcode has multiple modes, so find right one. */ + opcode = find (opc, operands, 1); + if (opcode) + { + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8); + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (&opcode_local, operands, 1); + } + else + as_bad ("No opcode found\n"); + + return; + } + else + { + if (*input_line_pointer == '#') + input_line_pointer++; + + expression (&operands[0].exp); + if (operands[0].exp.X_op == O_illegal) + { + as_bad (_("Illegal operand.")); + return; + } + else if (operands[0].exp.X_op == O_absent) + { + as_bad (_("Missing operand.")); + return; + } + + if (check_range (operands[0].exp.X_add_number,M68XG_OP_IMM3)) + { + opcode_local.opcode |= (operands[0].exp.X_add_number); + operands[0].mode = M68XG_OP_IMM3; + + opcode = find (opc, operands, 1); + if (opcode) + { + opcode_local.opcode = opcode->opcode; + opcode_local.opcode + |= (operands[0].exp.X_add_number) << 8; + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (&opcode_local, operands, 1); + } + else + as_bad ("No opcode found\n"); + + return; + } + else + { + as_bad ("Number out of range for IMM3\n"); + return; + } + } + } + + /* Special handling of SIF. */ + if (strncmp (opc->opcode->name, "sif",3) == 0) + { + /* Either OP_NONE or OP_RS. */ + if (*input_line_pointer != '\n') + input_line_pointer = skip_whites (input_line_pointer); + + if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') + || (*input_line_pointer == '\0')) + opc->opcode->opcode = 0x0300; + else + { + operands[0].reg1 = register_name (); + if (operands[0].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + opcode_local.opcode = 0x00f7 | (operands[0].reg1 << 8); + } + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (&opcode_local, operands, 0); + return; + } + + /* SEX, PAR, JAL plus aliases NEG, TST, COM */ + if (opc->format & M68XG_OP_R) + { + input_line_pointer = skip_whites (input_line_pointer); + operands[0].reg1 = register_name (); + if (operands[0].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') + || (*input_line_pointer == '\0')) + { + /* Likely to be OP R. */ + if (opc->format & M68XG_OP_R) + { + operands[0].mode = M68XG_OP_R; + + opcode = find (opc, operands, 1); + if (opcode) + { + if ((strncmp (opc->opcode->name, "com",3) == 0) + || (strncmp (opc->opcode->name, "neg",3) == 0)) + /* Special case for com RD as alias for sub RD,R0,RS */ + /* Special case for neg RD as alias for sub RD,R0,RS */ + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8) | (operands[0].reg1 << 2); + else if (strncmp (opc->opcode->name, "tst",3) == 0) + /* Special case for tst RS alias for sub R0, RS, R0 */ + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 5); + else + opcode_local.opcode |= (operands[0].reg1 << 8); + } + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (&opcode_local, operands, 0); + } + else + as_bad ("No valid mode found\n"); + + return; + } + } + + if (opc->format & (M68XG_OP_REL9 | M68XG_OP_REL10)) + { + opcode_local.format = opc->format; + input_line_pointer = skip_whites (input_line_pointer); + expression (&operands[0].exp); + if (operands[0].exp.X_op == O_illegal) + { + as_bad (_("Illegal operand.")); + return; + } + else if (operands[0].exp.X_op == O_absent) + { + as_bad (_("Missing operand.")); + return; + } + opcode_local.opcode = opc->opcode->opcode; + build_insn_xg (&opcode_local, operands, 1); + return; + } + + + /* For other command formats, parse input line and determine the mode + we are using as we go. */ + + input_line_pointer = skip_whites (input_line_pointer); + if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') + || (*input_line_pointer == '\0')) + return; /* nothing left */ + + if (*input_line_pointer == '#') + { + as_bad ("No register specified before hash\n"); + return; + } + + /* first operand is expected to be a register */ + if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) + { + operands[0].reg1 = register_name (); + if (operands[0].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + } + + input_line_pointer = skip_whites (input_line_pointer); + if (*input_line_pointer != ',') + { + as_bad ("Missing operand\n"); + return; + } + input_line_pointer++; + input_line_pointer = skip_whites (input_line_pointer); + + if (*input_line_pointer == '#') + { + /* Some kind of immediate mode, check if this is possible. */ + if (!(opc->format + & (M68XG_OP_R_IMM8 | M68XG_OP_R_IMM16 | M68XG_OP_R_IMM4))) + as_bad ("Invalid immediate mode for `%s'", opc->opcode->name); + else + { + input_line_pointer++; + input_line_pointer = skip_whites (input_line_pointer); + if (strncmp (input_line_pointer, "%hi", 3) == 0) + { + input_line_pointer += 3; + operands[0].mode = M6811_OP_HIGH_ADDR; + } + else if (strncmp (input_line_pointer, "%lo", 3) == 0) + { + input_line_pointer += 3; + operands[0].mode = M6811_OP_LOW_ADDR; + } + else + operands[0].mode = 0; + + expression (&operands[0].exp); + if (operands[0].exp.X_op == O_illegal) + { + as_bad (_("Illegal operand.")); + return; + } + else if (operands[0].exp.X_op == O_absent) + { + as_bad (_("Missing operand.")); + return; + } + /* ok so far, can only be one mode */ + opcode_local.format = opc->format + & (M68XG_OP_R_IMM8 | M68XG_OP_R_IMM16 | M68XG_OP_R_IMM4); + if (opcode_local.format & M68XG_OP_R_IMM4) + { + operands[0].mode = M68XG_OP_R_IMM4; + /* same opcodes have multiple modes, so find right one */ + opcode = find (opc, operands, 1); + if (opcode) + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8); + + if (operands[0].exp.X_op != O_constant) + as_bad ("Only constants supported at for IMM4 mode\n"); + else + { + if (check_range + (operands[0].exp.X_add_number,M68XG_OP_R_IMM4)) + opcode_local.opcode + |= (operands[0].exp.X_add_number << 4); + else + as_bad ("Number out of range for IMM4\n"); + } + opcode_local.format = M68XG_OP_NONE; + } + else if (opcode_local.format & M68XG_OP_R_IMM16) + { + operands[0].mode = M68XG_OP_R_IMM16; + + opcode = find (opc, operands, 1); + if (opcode) + { + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8); + } + } + else + { + opcode_local.opcode = opc->opcode->opcode + | (operands[0].reg1 << 8); + } + build_insn_xg (&opcode_local, operands, 1); + } + } + else if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) + { + /* we've got as far as OP R, R */ + operands[1].reg1 = register_name (); + if (operands[1].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') + || (*input_line_pointer == '\0')) + { + /* looks like OP_R_R */ + if (opc->format & M68XG_OP_R_R) + { + operands[0].mode = M68XG_OP_R_R; + /* same opcodes have multiple modes, so find right one */ + opcode = find (opc, operands, 1); + if (opcode) + { + if ((strncmp (opc->opcode->name, "com",3) == 0) + || (strncmp (opc->opcode->name, "mov",3) == 0) + || (strncmp (opc->opcode->name, "neg",3) == 0)) + { + /* Special cases for: + com RD, RS alias for xnor RD,R0,RS + mov RD, RS alias for or RD, R0, RS + neg RD, RS alias for sub RD, R0, RS */ + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8) | (operands[1].reg1 << 2); + } + else if ((strncmp (opc->opcode->name, "cmp",3) == 0) + || (strncmp (opc->opcode->name, "cpc",3) == 0)) + { + /* special cases for: + cmp RS1, RS2 alias for sub R0, RS1, RS2 + cpc RS1, RS2 alias for sbc R0, RS1, RS2 */ + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 5) | (operands[1].reg1 << 2); + } + else + { + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8) | (operands[1].reg1 << 5); + } + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (&opcode_local, operands, 1); + } + } + else + { + as_bad ("No valid mode found\n"); + } + } + else + { + /* more data */ + if (*input_line_pointer != ',') + { + as_bad (_("Missing operand.")); + return; + } + input_line_pointer++; + input_line_pointer = skip_whites (input_line_pointer); + if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) + { + operands[2].reg1 = register_name (); + if (operands[2].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + if (opc->format & M68XG_OP_R_R_R) + { + operands[0].mode = M68XG_OP_R_R_R; + + opcode = find (opc, operands, 1); + if (opcode) + { + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8) | (operands[1].reg1 << 5) + | (operands[2].reg1 << 2); + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (&opcode_local, operands, 1); + } + } + else + { + as_bad ("No valid mode found\n"); + } + } + } + } + else if (*input_line_pointer == '(') /* Indexed modes */ + { + input_line_pointer++; + input_line_pointer = skip_whites (input_line_pointer); + if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) + { + /* we've got as far as OP R, (R */ + operands[1].reg1 = register_name (); + if (operands[1].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + + if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') + || (*input_line_pointer == '\0')) + { + /* Looks like OP_R_R. */ + as_bad (_("Missing operand.")); + return; + } + + input_line_pointer = skip_whites (input_line_pointer); + + if (*input_line_pointer != ',') + { + as_bad (_("Missing operand.")); + return; + } + input_line_pointer++; + input_line_pointer = skip_whites (input_line_pointer); + + if (*input_line_pointer == '#') + { + input_line_pointer++; + input_line_pointer = skip_whites (input_line_pointer); + expression (&operands[0].exp); + if (operands[0].exp.X_op == O_illegal) + { + as_bad (_("Illegal operand.")); + return; + } + else if (operands[0].exp.X_op == O_absent) + { + as_bad (_("Missing operand.")); + return; + } + + input_line_pointer = skip_whites (input_line_pointer); + if (*input_line_pointer != ')') + { + as_bad ("Missing `)' to close register indirect operand."); + return; + } + else + { + input_line_pointer++; + } + + /* Ok so far, can only be one mode. */ + opcode_local.format = M68XG_OP_R_R_OFFS5; + operands[0].mode = M68XG_OP_R_R_OFFS5; + + opcode = find (opc, operands, 1); + if (opcode) + { + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8) | (operands[1].reg1 << 5); + if (operands[0].exp.X_op != O_constant) + { + as_bad + ("Only constants supported for indexed OFFS5 mode\n"); + } + else + { + if (check_range (operands[0].exp.X_add_number, + M68XG_OP_R_R_OFFS5)) + { + opcode_local.opcode + |= (operands[0].exp.X_add_number); + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (&opcode_local, operands, 1); + } + else + { + as_bad ("Number out of range for OFFS5\n"); + } + } + } + } + else + { + operands[0].mode = M68XG_OP_RD_RB_RI; + + if (*input_line_pointer == '-') + { + operands[0].mode = M68XG_OP_RD_RB_mRI; + input_line_pointer++; + } + operands[2].reg1 = register_name (); + if (operands[2].reg1 == REG_NONE) + { + as_bad ("Invalid register\n"); + return; + } + + if (*input_line_pointer == '+') + { + if (opcode_local.format == M68XG_OP_RD_RB_mRI) + { + as_bad (_("Illegal operand.")); + return; + } + operands[0].mode = M68XG_OP_RD_RB_RIp; + input_line_pointer++; + } + + input_line_pointer = skip_whites (input_line_pointer); + if (*input_line_pointer != ')') + { + as_bad + ("Missing `)' to close register indirect operand."); + return; + } + else + { + input_line_pointer++; + } + + opcode = find (opc, operands, 1); + if (opcode) + { + opcode_local.opcode = opcode->opcode + | (operands[0].reg1 << 8) | (operands[1].reg1 << 5) + | (operands[2].reg1 << 2); + opcode_local.format = M68XG_OP_NONE; + build_insn_xg (&opcode_local, operands, 1); + } + else + { + as_bad ("Failed to find opcode for %s %s\n", + opc->opcode->name, (char *)op_end); + } + } + } + } + else + { + as_bad (_("Failed to find a valid mode for `%s'."), + opc->opcode->name); + } + + if (opc->opcode && !flag_mri) + { + char *p = input_line_pointer; + + while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r') + p++; + + if (*p != '\n' && *p) + as_bad (_("Garbage at end of instruction: `%s'."), p); + } + + input_line_pointer = save; + + /* Opcode is known but does not have valid operands. Print out the + syntax for this opcode. */ + if (opc->opcode == 0) + { + if (flag_print_insn_syntax) + print_insn_format (name); + + as_bad (_("Invalid operand for `%s'"), name); + return; + } + + return; + } + /* Find the opcode definition given its name. */ opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); @@ -2437,7 +3494,7 @@ md_assemble (char *str) branch_optimize = 1; } - /* The following test should probably be removed. This is not conform + /* The following test should probably be removed. This does not conform to Motorola assembler specs. */ if (opc == NULL && flag_mri) { @@ -2525,8 +3582,120 @@ md_assemble (char *str) if (flag_print_insn_syntax) print_insn_format (name); - as_bad (_("Invalid operand for `%s'"), name); - return; + if (((strcmp (name, "movb") == 0) || (strcmp (name, "movw") == 0)) + && (current_architecture & cpu9s12x)) + { + char *f; + int movb; + if (strcmp (name, "movb") == 0) + movb = 8; + else + movb = 0; + + /* The existing operand extract code fell over if these additional modes + were enabled in m68hc11-opc.c. So they are commented there and + decoded here instead. */ + + if (operands[1].mode & (M6812_OP_IDX | M6812_OP_IDX_1 + | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2 | M6812_PRE_INC + | M6812_PRE_DEC | M6812_POST_INC | M6812_POST_DEC )) + { + /* first check if valid mode then start building it up */ + if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16 + | M6811_OP_IND16 | M6812_OP_IDX | M6812_OP_IDX_1 + | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) + { + int opr16a; + if (operands[1].mode & (M6811_OP_IND16)) + opr16a = 3; + else + opr16a = 0; + + f = m68hc11_new_insn (2); + + if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16)) + { + number_to_chars_bigendian (f, 0x1800 + movb + opr16a, 2); + build_indexed_byte (&operands[1], operands[1].mode, 1); + if (movb) + fixup8 (&operands[0].exp, M6811_OP_IMM8, + operands[0].mode); + else + fixup16 (&operands[0].exp, M6811_OP_IMM16, + operands[0].mode); + + return; + } + else if (operands[0].mode & M6811_OP_IND16) + { + number_to_chars_bigendian (f, 0x1801 + movb + opr16a, 2); + build_indexed_byte (&operands[1], operands[1].mode, 1); + fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); + return; + } + else + { + number_to_chars_bigendian (f, 0x1802 + movb + opr16a, 2); + build_indexed_byte (&operands[0], operands[0].mode, 1); + build_indexed_byte (&operands[1], operands[1].mode, 1); + return; + } + } + } + else if (operands[1].mode & M6811_OP_IND16) + { + /* First check if this is valid mode, then start building it up. */ + if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16 + | M6811_OP_IND16 | M6812_OP_IDX | M6812_OP_IDX_1 + | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) + { + int opr16a; + if (operands[1].mode & (M6811_OP_IND16)) + opr16a = 3; + else + opr16a = 0; + + f = m68hc11_new_insn (2); + + /* The first two cases here should actually be covered by the + normal operand code. */ + if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16)) + { + number_to_chars_bigendian (f, 0x1800 + movb + opr16a, 2); + if (movb) + fixup8 (&operands[0].exp, M6811_OP_IMM8, operands[0].mode); + else + fixup16 (&operands[0].exp, M6811_OP_IMM16, operands[0].mode); + + fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); + return; + } + else if (operands[0].mode & M6811_OP_IND16) + { + number_to_chars_bigendian (f, 0x1801 + movb + opr16a, 2); + build_indexed_byte (&operands[1], operands[1].mode, 1); + fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); + return; + } + else + { + number_to_chars_bigendian (f, 0x1802 + movb + opr16a, 2); + build_indexed_byte (&operands[0], operands[0].mode, 1); + fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode); + return; + } + } + } + + as_bad (_("Invalid operand for `%s'"), name); + return; + + } + else + { + as_bad (_("Invalid operand for `%s'"), name); + return; + } } /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is @@ -3210,9 +4379,13 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) break; case BFD_RELOC_M68HC11_HI8: + /* Caution, %hi(<symbol>+%ld) will generate incorrect code if %lo + causes a carry. */ + case BFD_RELOC_M68HC12_HI8XG: value = value >> 8; /* Fall through. */ + case BFD_RELOC_M68HC12_LO8XG: case BFD_RELOC_M68HC11_LO8: case BFD_RELOC_8: case BFD_RELOC_M68HC11_PAGE: @@ -3228,6 +4401,26 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) value); break; + /* These next two are for XGATE. */ + case BFD_RELOC_M68HC12_9_PCREL: + ((bfd_byte *) where)[0] |= (bfd_byte) ((value >>9) & 0x01); + ((bfd_byte *) where)[1] = (bfd_byte) ((value>>1) & 0xff); + if (value < -512 || value > 511) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("Value %ld too large for 9-bit PC-relative branch."), + value); + break; + + case BFD_RELOC_M68HC12_10_PCREL: + ((bfd_byte *) where)[0] |= (bfd_byte) ((value >>9) & 0x03); + ((bfd_byte *) where)[1] = (bfd_byte) ((value>>1) & 0xff); + if (value < -1024 || value > 1023) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("Value %ld too large for 10-bit PC-relative branch."), + value); + + break; + case BFD_RELOC_M68HC11_3B: if (value <= 0 || value > 8) as_bad_where (fixP->fx_file, fixP->fx_line, @@ -3252,6 +4445,30 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) where[0] |= (0x10 | (16 + value)); break; + case BFD_RELOC_M68HC12_9B: + if (value < -256 || value > 255) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("Offset out of 9-bit range for movw/movb insn: %ld"), + value); + /* sign bit already in xb postbyte */ + if (value >= 0) + where[1] = value; + else + where[1] = (256 + value); + break; + + case BFD_RELOC_M68HC12_16B: + if (value < -32768 || value > 32767) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("Offset out of 16-bit range for movw/movb insn: %ld"), + value); + if (value < 0) + value += 65536; + + where[1] = (value >> 8); + where[2] = (value & 0xff); + break; + case BFD_RELOC_M68HC11_RL_JUMP: case BFD_RELOC_M68HC11_RL_GROUP: case BFD_RELOC_VTABLE_INHERIT: diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 034cc92..694c806 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -369,7 +369,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @ifset M68HC11 @emph{Target M68HC11 options:} - [@b{-m68hc11}|@b{-m68hc12}|@b{-m68hcs12}] + [@b{-m68hc11}|@b{-m68hc12}|@b{-m68hcs12}|@b{-mm9s12x}|@b{-mm9s12xg}] [@b{-mshort}|@b{-mlong}] [@b{-mshort-double}|@b{-mlong-double}] [@b{--force-long-branches}] [@b{--short-branches}] @@ -1050,10 +1050,14 @@ Motorola 68HC11 or 68HC12 series. @table @gcctabopt -@item -m68hc11 | -m68hc12 | -m68hcs12 +@item -m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg Specify what processor is the target. The default is defined by the configuration option when building the assembler. +@item --xgate-ramoffset +Instruct the linker to offset RAM addresses from S12X address space into +XGATE address space. + @item -mshort Specify to use the 16-bit integer ABI. @@ -1083,10 +1087,10 @@ when the instruction does not support direct addressing mode. Print the syntax of instruction in case of error. @item --print-opcodes -print the list of instructions with syntax and then exit. +Print the list of instructions with syntax and then exit. @item --generate-example -print an example of instruction for each possible instruction and then exit. +Print an example of instruction for each possible instruction and then exit. This option is only useful for testing @command{@value{AS}}. @end table diff --git a/gas/doc/c-m68hc11.texi b/gas/doc/c-m68hc11.texi index bebc53e..3d69396 100644 --- a/gas/doc/c-m68hc11.texi +++ b/gas/doc/c-m68hc11.texi @@ -1,5 +1,5 @@ @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003, -@c 2006, 2011 +@c 2006, 2011, 2012 @c Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -35,24 +35,40 @@ dependent options. @cindex @samp{-m68hc11} @item -m68hc11 -This option switches the assembler in the M68HC11 mode. In this mode, +This option switches the assembler into the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11. @cindex @samp{-m68hc12} @item -m68hc12 -This option switches the assembler in the M68HC12 mode. In this mode, +This option switches the assembler into the M68HC12 mode. In this mode, the assembler also accepts 68HC12 operands and mnemonics. It produces code for the 68HC12. A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications. @cindex @samp{-m68hcs12} @item -m68hcs12 -This option switches the assembler in the M68HCS12 mode. This mode is +This option switches the assembler into the M68HCS12 mode. This mode is similar to @samp{-m68hc12} but specifies to assemble for the 68HCS12 series. The only difference is on the assembling of the @samp{movb} and @samp{movw} instruction when a PC-relative operand is used. +@cindex @samp{-mm9s12x} +@item -mm9s12x +This option switches the assembler into the M9S12X mode. This mode is +similar to @samp{-m68hc12} but specifies to assemble for the S12X +series which is a superset of the HCS12. + +@cindex @samp{-mm9s12xg} +@item -mm9s12xg +This option switches the assembler into the XGATE mode for the RISC +co-processor featured on some S12X-family chips. + +@cindex @samp{--xgate-ramoffset} +@item --xgate-ramoffset +This option instructs the linker to offset RAM addresses from S12X address +space into XGATE address space. + @cindex @samp{-mshort} @item -mshort This option controls the ABI and indicates to use a 16-bit integer ABI. diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 251e7d6..fdf52be 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,20 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + + * gas/m68hc11/insns9s12x.s: New + * gas/m68hc11/insns9s12x.d: New + * gas/m68hc11/hexprefix.s: New + * gas/m68hc11/hexprefix.d: New + * gas/m68hc11/9s12x-exg-sex-tfr.s: New + * gas/m68hc11/9s12x-exg-sex-tfr.d: New + * gas/m68hc11/insns9s12xg.s: New + * gas/m68hc11/insns9s12xg.d: New + * gas/m68hc11/9s12x-mov.s: New + * gas/m68hc11/9s12x-mov.d: New + * gas/m68hc11/m68hc11.exp: Updated + * gas/m68hc11/*.d: Brought in line with changed objdump output. + * gas/all/gas.exp: XFAIL all hc11/12 targets for redef2,3. + * gas/elf/elf.exp: XFAIL all hc11/12 targets for redef. + 2012-05-14 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Rhonda Wittels <rhonda@codesourcery.com> diff --git a/gas/testsuite/gas/elf/dwarf2-1.d b/gas/testsuite/gas/elf/dwarf2-1.d index 8decc1c..b691bfd 100644 --- a/gas/testsuite/gas/elf/dwarf2-1.d +++ b/gas/testsuite/gas/elf/dwarf2-1.d @@ -1,7 +1,7 @@ #as: --compress-debug-sections #readelf: -w #name: DWARF2 1 -#not-target: ia64-*-* +#not-target: ia64-*-* m68hc1*-*-* m681*-*-* Contents of the .[z]?debug_info section: diff --git a/gas/testsuite/gas/elf/dwarf2-2.d b/gas/testsuite/gas/elf/dwarf2-2.d index 030adb8..3b3a341 100644 --- a/gas/testsuite/gas/elf/dwarf2-2.d +++ b/gas/testsuite/gas/elf/dwarf2-2.d @@ -1,7 +1,7 @@ #as: --compress-debug-sections #readelf: -w #name: DWARF2 2 -#not-target: ia64-*-* +#not-target: ia64-*-* m68hc1*-*-* m681*-*-* Contents of the .[z]?debug_info section: diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index 15d4407..736eec9 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -126,6 +126,7 @@ if { [is_elf_format] } then { # against ordinary symbols into relocations against section symbols. # This is usually revealed by the error message: # symbol `sym' required but not present + setup_xfail "m681*-*-*" "m68hc*-*-*" run_dump_test redef run_dump_test equ-reloc } diff --git a/gas/testsuite/gas/m68hc11/9s12x-exg-sex-tfr.d b/gas/testsuite/gas/m68hc11/9s12x-exg-sex-tfr.d new file mode 100644 index 0000000..dafd7fe --- /dev/null +++ b/gas/testsuite/gas/m68hc11/9s12x-exg-sex-tfr.d @@ -0,0 +1,65 @@ +#objdump: -d -mm9s12x --prefix-addresses --reloc +#as: -mm9s12x +#name: s12x extended forms of exg,tfr,sex + +dump.o: file format elf32-m68hc12 + + +Disassembly of section .text: +0x00000000 exg A,A +0x00000002 exg B,A +0x00000004 exg D,A +0x00000006 exg A,B +0x00000008 exg B,B +0x0000000a exg D,B +0x0000000c exg CCR,CCR +0x0000000e exg D,CCR +0x00000010 exg X,CCR +0x00000012 exg Y,CCR +0x00000014 exg SP,CCR +0x00000016 exg A,D +0x00000018 exg B,D +0x0000001a exg CCR,D +0x0000001c exg D,D +0x0000001e exg X,D +0x00000020 exg Y,D +0x00000022 exg SP,D +0x00000024 exg CCR,X +0x00000026 xgdx +0x00000028 exg X,X +0x0000002a exg Y,X +0x0000002c exg SP,X +0x0000002e exg CCR,Y +0x00000030 xgdy +0x00000032 exg X,Y +0x00000034 exg Y,Y +0x00000036 exg SP,Y +0x00000038 exg CCR,SP +0x0000003a exg D,SP +0x0000003c exg X,SP +0x0000003e exg Y,SP +0x00000040 exg SP,SP +0x00000042 sex A,D +0x00000044 sex B,D +0x00000046 sex D,X +0x00000048 sex D,Y +0x0000004a tfr A,A +0x0000004c tfr B,A +0x0000004e tfr D,A +0x00000050 tfr A,B +0x00000052 tfr B,B +0x00000054 tfr D,B +0x00000056 tfr D,D +0x00000058 tfr X,D +0x0000005a tfr Y,D +0x0000005c tfr SP,D +0x0000005e tfr X,X +0x00000060 tfr Y,X +0x00000062 tsx +0x00000064 tfr X,Y +0x00000066 tfr Y,Y +0x00000068 tsy +0x0000006a tfr D,SP +0x0000006c txs +0x0000006e tys +0x00000070 tfr SP,SP diff --git a/gas/testsuite/gas/m68hc11/9s12x-exg-sex-tfr.s b/gas/testsuite/gas/m68hc11/9s12x-exg-sex-tfr.s new file mode 100644 index 0000000..efe5a9a --- /dev/null +++ b/gas/testsuite/gas/m68hc11/9s12x-exg-sex-tfr.s @@ -0,0 +1,145 @@ +# Test for correct generation of 9s12x specific insns. + + .sect .text +;; +;; Test all s12x extended forms of exg,tfr,sex where supported +;; +;; presently tmp register and h/l forms not supported in gas +;exg +;; none of shaded area is actually supported + exg a,a + exg b,a +; exg ccrh,a +; exg tmp3h,a + exg d,a +; exg xh,a +; exg yh,a +; exg sph,a + exg a,b + exg b,b +; exg ccrl,b +; exg tmp3l,b + exg d,b +; exg xl,b +; exg yl,b +; exg spl,b +; exg a,ccrh +; exg b,ccrl + exg ccr,ccr +; exg tmp3,ccr + exg d,ccr + exg x,ccr + exg y,ccr + exg sp,ccr +; exg a,tmp2h +; exg b,tmp2l +; exg ccr,tmp2 +; exg tmp3,tmp2 +; exg d,tmp1 +; exg x,tmp2 +; exg y,tmp2 +; exg sp,tmp2 + exg a,d + exg b,d + exg ccr,d +; exg tmp1,d + exg d,d + exg x,d + exg y,d + exg sp,d +; exg a,xh +; exg b,xl + exg ccr,x +; exg tmp3,x + exg d,x + exg x,x + exg y,x + exg sp,x +; exg a,yh +; exg b,yl + exg ccr,y +; exg tmp3,y + exg d,y + exg x,y + exg y,y + exg sp,y +; exg a,sph +; exg b,spl + exg ccr,sp +; exg tmp3,sp + exg d,sp + exg x,sp + exg y,sp + exg sp,sp + +;sex + sex a,d + sex b,d + sex d,x ; new + sex d,y ; new + +;tfr + tfr a,a + tfr b,a +; tfr tmp3h,a + tfr d,a +; tfr xh,a +; tfr yh,a +; tfr sph,a + tfr a,b + tfr b,b +; tfr ccrl,b +; tfr tmp3l,b + tfr d,b +; tfr xl,b +; tfr yl,b +; tfr spl,b +; tfr a,ccrh +; tfr b,ccrl +; tfr ccrw,ccrw +; tfr tmp3,ccrw +; tfr d,ccrw +; tfr x,ccrw +; tfr y,ccrw +; tfr sp,ccrw +; tfr a,tmp2h +; tfr b,tmp2l +; tfr ccrw,tmp +; tfr tmp3,tmp2 +; tfr d,tmp1 +; tfr x,tmp2 +; tfr y,tmp2 +; tfr sp,tmp2 +;sex +;sex +; tfr ccrw,d +; tfr tmp1,d + tfr d,d + tfr x,d + tfr y,d + tfr sp,d +; tfr a,xh +; tfr b,xl +; tfr ccrw,x +; tfr tmp3,x +;sex + tfr x,x + tfr y,x + tfr sp,x +; tfr a,yh +; tfr b,yl +; tfr ccrw,y +; tfr tmp3,y +;sex + tfr x,y + tfr y,y + tfr sp,y +; tfr a,sph +; tfr b,spl +; tfr ccrw,xp +; tfr tmp3,sp + tfr d,sp + tfr x,sp + tfr y,sp + tfr sp,sp + diff --git a/gas/testsuite/gas/m68hc11/9s12x-mov.d b/gas/testsuite/gas/m68hc11/9s12x-mov.d new file mode 100644 index 0000000..dac7f75 --- /dev/null +++ b/gas/testsuite/gas/m68hc11/9s12x-mov.d @@ -0,0 +1,68 @@ +#objdump: -d -mm9s12x --prefix-addresses --reloc +#as: -mm9s12x +#name: s12x extended forms of movb,movw + +dump.o: file format elf32-m68hc12 + + +Disassembly of section .text: +00000000 <.text> movb #0x4, 0x00001234 <a1> +00000005 <.text\+0x5> movb #0x44, 0x0,X +00000009 <.text\+0x9> movb #0x58, 0xff02,Y +0000000e <.text\+0xe> movb #0x89, 0x1234,SP +00000014 <.text\+0x14> movb #0xfe, \[D,X\] +00000018 <.text\+0x18> movb #0x80, \[0x3456,SP\] +0000001e <.text\+0x1e> movb 0x00001234 <a1>, 0x00003456 <a2> +00000024 <.text\+0x24> movb 0x00003456 <a2>, 0x1,X +00000029 <.text\+0x29> movb 0x00008123 <a3>, 0xff,Y +0000002f <.text\+0x2f> movb 0x0000c567 <a4>, 0x1234,SP +00000036 <.text\+0x36> movb 0x00002987 <a5>, \[D,Y\] +0000003b <.text\+0x3b> movb 0x00001009 <a6>, \[0x8123,SP\] +00000042 <.text\+0x42> movb 1,X\+, 0x00001234 <a1> +00000047 <.text\+0x47> movb 2,-X, 0xf,X +0000004b <.text\+0x4b> movb 7,SP\+, 0xfd,Y +00000050 <.text\+0x50> movb 6,-SP, 0x3456,SP +00000056 <.text\+0x56> movb 0xfff1,Y, \[D,X\] +0000005a <.text\+0x5a> movb 0xd,SP, \[0x2987,SP\] +00000060 <.text\+0x60> movb \[D,X\], 0x00001234 <a1> +00000065 <.text\+0x65> movb \[D,Y\], 0xe,X +00000069 <.text\+0x69> movb \[D,SP\], 0xfd,Y +0000006e <.text\+0x6e> movb \[D,PC\], 0x3456,SP +00000074 <.text\+0x74> movb \[D,X\], \[D,X\] +00000078 <.text\+0x78> movb \[D,Y\], \[0x2987,SP\] +0000007e <.text\+0x7e> movb \[0x1234,X\], 0x00003456 <a2> +00000085 <.text\+0x85> movb \[0x3456,Y\], 0xd,X +0000008b <.text\+0x8b> movb \[0x8123,SP\], 0xfb,Y +00000092 <.text\+0x92> movb \[0xc567,PC\], 0x8123,SP +0000009a <.text\+0x9a> movb \[0x2987,X\], \[D,PC\] +000000a0 <.text\+0xa0> movb \[0x1009,Y\], \[0x2987,SP\] +000000a8 <.text\+0xa8> movw #0x00001234 <a1>, 0x00001234 <a1> +000000ae <.text\+0xae> movw #0x00003456 <a2>, 0x0,X +000000b3 <.text\+0xb3> movw #0x00008123 <a3>, 0xff02,Y +000000b9 <.text\+0xb9> movw #0x0000c567 <a4>, 0x1234,SP +000000c0 <.text\+0xc0> movw #0x00002987 <a5>, \[D,X\] +000000c5 <.text\+0xc5> movw #0x00001009 <a6>, \[0x3456,SP\] +000000cc <.text\+0xcc> movw 0x00001234 <a1>, 0x00003456 <a2> +000000d2 <.text\+0xd2> movw 0x00003456 <a2>, 0x1,X +000000d7 <.text\+0xd7> movw 0x00008123 <a3>, 0xff,Y +000000dd <.text\+0xdd> movw 0x0000c567 <a4>, 0x1234,SP +000000e4 <.text\+0xe4> movw 0x00002987 <a5>, \[D,Y\] +000000e9 <.text\+0xe9> movw 0x00001009 <a6>, \[0x8123,SP\] +000000f0 <.text\+0xf0> movw 1,X\+, 0x00001234 <a1> +000000f5 <.text\+0xf5> movw 2,-X, 0xf,X +000000f9 <.text\+0xf9> movw 7,SP\+, 0xfd,Y +000000fe <.text\+0xfe> movw 6,-SP, 0x3456,SP +00000104 <.text\+0x104> movw 0xfff1,Y, \[D,X\] +00000108 <.text\+0x108> movw 0xd,SP, \[0x2987,SP\] +0000010e <.text\+0x10e> movw \[D,X\], 0x00001234 <a1> +00000113 <.text\+0x113> movw \[D,Y\], 0xe,X +00000117 <.text\+0x117> movw \[D,SP\], 0xfd,Y +0000011c <.text\+0x11c> movw \[D,PC\], 0x3456,SP +00000122 <.text\+0x122> movw \[D,X\], \[D,X\] +00000126 <.text\+0x126> movw \[D,Y\], \[0x2987,SP\] +0000012c <.text\+0x12c> movw \[0x1234,X\], 0x00003456 <a2> +00000133 <.text\+0x133> movw \[0x3456,Y\], 0xd,X +00000139 <.text\+0x139> movw \[0x8123,SP\], 0xfb,Y +00000140 <.text\+0x140> movw \[0xc567,PC\], 0x8123,SP +00000148 <.text\+0x148> movw \[0x2987,X\], \[D,PC\] +0000014e <.text\+0x14e> movw \[0x1009,Y\], \[0x2987,SP\] diff --git a/gas/testsuite/gas/m68hc11/9s12x-mov.s b/gas/testsuite/gas/m68hc11/9s12x-mov.s new file mode 100644 index 0000000..553b4c7 --- /dev/null +++ b/gas/testsuite/gas/m68hc11/9s12x-mov.s @@ -0,0 +1,91 @@ +# Test for correct generation of 9s12x specific moves + + .sect .text +;; +;; Test all s12x extended forms of movb, movw +;; page 273 et seq in S12XCPUV2 +;; +v1=4 +v2=68 +v3=88 +v4=0x89 +v5=0xfe +v6=0x80 +a1=0x1234 +a2=0x3456 +a3=0x8123 +a4=0xc567 +a5=0x2987 +a6=0x1009 + +;movb + movb #v1, a1 + movb #v2, 0,x + movb #v3, -254,y + movb #v4, a1,sp + movb #v5, [d,x] + movb #v6, [a2,sp] + + movb a1, a2 + movb a2, 1,x + movb a3, 255,y + movb a4, a1,sp + movb a5, [d,y] + movb a6, [a3,sp] + + movb 1,x+, a1 + movb 2,-x, 15,x + movb 7,sp+, 253,y + movb 6,-sp, a2,sp + movb -15,y, [d,x] + movb 13,sp, [a5,sp] + + movb [d,x], a1 + movb [d,y], 14,x + movb [d,sp], 253,y + movb [d,pc], a2,sp + movb [d,x], [d,x] + movb [d,y], [a5,sp] + + movb [a1,x], a2 + movb [a2,y], 13,x + movb [a3,sp], 251,y + movb [a4,pc], a3,sp + movb [a5,x], [d,pc] + movb [a6,y], [a5,sp] + +;movw + movw #a1, a1 + movw #a2, 0,x + movw #a3, -254,y + movw #a4, a1,sp + movw #a5, [d,x] + movw #a6, [a2,sp] + + movw a1, a2 + movw a2, 1,x + movw a3, 255,y + movw a4, a1,sp + movw a5, [d,y] + movw a6, [a3,sp] + + movw 1,x+, a1 + movw 2,-x, 15,x + movw 7,sp+, 253,y + movw 6,-sp, a2,sp + movw -15,y, [d,x] + movw 13,sp, [a5,sp] + + movw [d,x], a1 + movw [d,y], 14,x + movw [d,sp], 253,y + movw [d,pc], a2,sp + movw [d,x], [d,x] + movw [d,y], [a5,sp] + + movw [a1,x], a2 + movw [a2,y], 13,x + movw [a3,sp], 251,y + movw [a4,pc], a3,sp + movw [a5,x], [d,pc] + movw [a6,y], [a5,sp] diff --git a/gas/testsuite/gas/m68hc11/all_insns.d b/gas/testsuite/gas/m68hc11/all_insns.d index 3531b3a..55dd534 100644 --- a/gas/testsuite/gas/m68hc11/all_insns.d +++ b/gas/testsuite/gas/m68hc11/all_insns.d @@ -10,377 +10,377 @@ Disassembly of section .text: 0+0+ <L0> aba 0+0001 <L1> abx 0+0002 <L2> aby -0+0004 <L3> adca #103 -0+0006 <L4> adca \*0+0+ <L0> +0+0004 <L3> adca #0x67 +0+0006 <L4> adca \*0x0+0+ <L0> 7: R_M68HC11_8 Z198 -0+0008 <L5> adca 105,x -0+000a <L6> adca 0+0+ <L0> +0+0008 <L5> adca 0x69,x +0+000a <L6> adca 0x0+0+ <L0> b: R_M68HC11_16 symbol115 -0+000d <L7> adca 81,x -0+000f <L8> adcb #255 -0+0011 <L9> adcb \*0+0+ <L0> +0+000d <L7> adca 0x51,x +0+000f <L8> adcb #0xff +0+0011 <L9> adcb \*0x0+0+ <L0> 12: R_M68HC11_8 Z74 -0+0013 <L10> adcb 236,x -0+0015 <L11> adcb 0+0+ <L0> +0+0013 <L10> adcb 0xec,x +0+0015 <L11> adcb 0x0+0+ <L0> 16: R_M68HC11_16 symbol41 -0+0018 <L12> adcb 205,x -0+001a <L13> adda #186 -0+001c <L14> adda \*0+0+ <L0> +0+0018 <L12> adcb 0xcd,x +0+001a <L13> adda #0xba +0+001c <L14> adda \*0x0+0+ <L0> 1d: R_M68HC11_8 Z171 -0+001e <L15> adda 242,x -0+0020 <L16> adda 0+0+ <L0> +0+001e <L15> adda 0xf2,x +0+0020 <L16> adda 0x0+0+ <L0> 21: R_M68HC11_16 symbol251 -0+0023 <L17> adda 227,x -0+0025 <L18> addb #70 -0+0027 <L19> addb \*0+0+ <L0> +0+0023 <L17> adda 0xe3,x +0+0025 <L18> addb #0x46 +0+0027 <L19> addb \*0x0+0+ <L0> 28: R_M68HC11_8 Z124 -0+0029 <L20> addb 194,x -0+002b <L21> addb 0+0+ <L0> +0+0029 <L20> addb 0xc2,x +0+002b <L21> addb 0x0+0+ <L0> 2c: R_M68HC11_16 symbol84 -0+002e <L22> addb 248,x -0+0030 <L23> addd #0+231b <L330\+0x2034> -0+0033 <L24> addd \*0+0+ <L0> +0+002e <L22> addb 0xf8,x +0+0030 <L23> addd #0x0+231b <L330\+0x2034> +0+0033 <L24> addd \*0x0+0+ <L0> 34: R_M68HC11_8 Z232 -0+0035 <L25> addd 231,x -0+0037 <L26> addd 0+0+ <L0> +0+0035 <L25> addd 0xe7,x +0+0037 <L26> addd 0x0+0+ <L0> 38: R_M68HC11_16 symbol141 -0+003a <L27> addd 118,x -0+003c <L28> anda #90 -0+003e <L29> anda \*0+0+ <L0> +0+003a <L27> addd 0x76,x +0+003c <L28> anda #0x5a +0+003e <L29> anda \*0x0+0+ <L0> 3f: R_M68HC11_8 Z46 -0+0040 <L30> anda 99,x -0+0042 <L31> anda 0+0+ <L0> +0+0040 <L30> anda 0x63,x +0+0042 <L31> anda 0x0+0+ <L0> 43: R_M68HC11_16 symbol51 -0+0045 <L32> anda 159,x -0+0047 <L33> andb #201 -0+0049 <L34> andb \*0+0+ <L0> +0+0045 <L32> anda 0x9f,x +0+0047 <L33> andb #0xc9 +0+0049 <L34> andb \*0x0+0+ <L0> 4a: R_M68HC11_8 Z154 -0+004b <L35> andb 102,x -0+004d <L36> andb 0+0+ <L0> +0+004b <L35> andb 0x66,x +0+004d <L36> andb 0x0+0+ <L0> 4e: R_M68HC11_16 symbol50 -0+0050 <L37> andb 13,x -0+0052 <L38> asl 183,x -0+0054 <L39> asl 0+0+ <L0> +0+0050 <L37> andb 0xd,x +0+0052 <L38> asl 0xb7,x +0+0054 <L39> asl 0x0+0+ <L0> 55: R_M68HC11_16 symbol49 -0+0057 <L40> asl 88,x +0+0057 <L40> asl 0x58,x 0+0059 <L41> asla 0+005a <L42> aslb 0+005b <L43> asld -0+005c <L44> asr 163,x -0+005e <L45> asr 0+0+ <L0> +0+005c <L44> asr 0xa3,x +0+005e <L45> asr 0x0+0+ <L0> 5f: R_M68HC11_16 symbol90 -0+0061 <L46> asr 37,x +0+0061 <L46> asr 0x25,x 0+0063 <L47> asra 0+0064 <L48> asrb -0+0065 <L49> bcs 0+006a <L50> +0+0065 <L49> bcs 0x0+006a <L50> 65: R_M68HC11_RL_JUMP \*ABS\* -0+0067 <L49\+0x2> jmp 0+0+ <L0> +0+0067 <L49\+0x2> jmp 0x0+0+ <L0> 68: R_M68HC11_16 L93 -0+006a <L50> bclr \*0+0+ <L0> #\$00 +0+006a <L50> bclr \*0x0+0+ <L0>, #0x00 6b: R_M68HC11_8 Z5 6c: R_M68HC11_8 \$17 -0+006d <L51> bclr 88,x #\$00 +0+006d <L51> bclr 0x58,x, #0x00 6f: R_M68HC11_8 \$e9 -0+0070 <L52> bclr 94,x #\$00 +0+0070 <L52> bclr 0x5e,x, #0x00 72: R_M68HC11_8 \$d4 -0+0073 <L53> bcc 0+0078 <L54> +0+0073 <L53> bcc 0x0+0078 <L54> 73: R_M68HC11_RL_JUMP \*ABS\* -0+0075 <L53\+0x2> jmp 0+0+ <L0> +0+0075 <L53\+0x2> jmp 0x0+0+ <L0> 76: R_M68HC11_16 L171 -0+0078 <L54> bne 0+007d <L55> +0+0078 <L54> bne 0x0+007d <L55> 78: R_M68HC11_RL_JUMP \*ABS\* -0+007a <L54\+0x2> jmp 0+0+ <L0> +0+007a <L54\+0x2> jmp 0x0+0+ <L0> 7b: R_M68HC11_16 L178 -0+007d <L55> blt 0+0082 <L56> +0+007d <L55> blt 0x0+0082 <L56> 7d: R_M68HC11_RL_JUMP \*ABS\* -0+007f <L55\+0x2> jmp 0+0+ <L0> +0+007f <L55\+0x2> jmp 0x0+0+ <L0> 80: R_M68HC11_16 L205 -0+0082 <L56> ble 0+0087 <L57> +0+0082 <L56> ble 0x0+0087 <L57> 82: R_M68HC11_RL_JUMP \*ABS\* -0+0084 <L56\+0x2> jmp 0+0+ <L0> +0+0084 <L56\+0x2> jmp 0x0+0+ <L0> 85: R_M68HC11_16 L198 -0+0087 <L57> bls 0+008c <L58> +0+0087 <L57> bls 0x0+008c <L58> 87: R_M68HC11_RL_JUMP \*ABS\* -0+0089 <L57\+0x2> jmp 0+0+ <L0> +0+0089 <L57\+0x2> jmp 0x0+0+ <L0> 8a: R_M68HC11_16 L155 -0+008c <L58> bcs 0+0091 <L59> +0+008c <L58> bcs 0x0+0091 <L59> 8c: R_M68HC11_RL_JUMP \*ABS\* -0+008e <L58\+0x2> jmp 0+0+ <L0> +0+008e <L58\+0x2> jmp 0x0+0+ <L0> 8f: R_M68HC11_16 L180 -0+0091 <L59> bita #84 -0+0093 <L60> bita \*0+0+ <L0> +0+0091 <L59> bita #0x54 +0+0093 <L60> bita \*0x0+0+ <L0> 94: R_M68HC11_8 Z17 -0+0095 <L61> bita 14,x -0+0097 <L62> bita 0+0+ <L0> +0+0095 <L61> bita 0xe,x +0+0097 <L62> bita 0x0+0+ <L0> 98: R_M68HC11_16 symbol130 -0+009a <L63> bita 116,x -0+009c <L64> bitb #65 -0+009e <L65> bitb \*0+0+ <L0> +0+009a <L63> bita 0x74,x +0+009c <L64> bitb #0x41 +0+009e <L65> bitb \*0x0+0+ <L0> 9f: R_M68HC11_8 Z33 -0+00a0 <L66> bitb 61,x -0+00a2 <L67> bitb 0+0+ <L0> +0+00a0 <L66> bitb 0x3d,x +0+00a2 <L67> bitb 0x0+0+ <L0> a3: R_M68HC11_16 symbol220 -0+00a5 <L68> bitb 135,x -0+00a7 <L69> ble 0+011d <L112> +0+00a5 <L68> bitb 0x87,x +0+00a7 <L69> ble 0x0+011d <L112> a7: R_M68HC11_RL_JUMP \*ABS\* -0+00a9 <L70> bcc 0+00ae <L71> +0+00a9 <L70> bcc 0x0+00ae <L71> a9: R_M68HC11_RL_JUMP \*ABS\* -0+00ab <L70\+0x2> jmp 0+0+ <L0> +0+00ab <L70\+0x2> jmp 0x0+0+ <L0> ac: R_M68HC11_16 L233 -0+00ae <L71> bls 0+0097 <L62> +0+00ae <L71> bls 0x0+0097 <L62> ae: R_M68HC11_RL_JUMP \*ABS\* -0+00b0 <L72> bge 0+00b5 <L73> +0+00b0 <L72> bge 0x0+00b5 <L73> b0: R_M68HC11_RL_JUMP \*ABS\* -0+00b2 <L72\+0x2> jmp 0+0+ <L0> +0+00b2 <L72\+0x2> jmp 0x0+0+ <L0> b3: R_M68HC11_16 L161 -0+00b5 <L73> bmi 0+009e <L65> +0+00b5 <L73> bmi 0x0+009e <L65> b5: R_M68HC11_RL_JUMP \*ABS\* -0+00b7 <L74> beq 0+00bc <L75> +0+00b7 <L74> beq 0x0+00bc <L75> b7: R_M68HC11_RL_JUMP \*ABS\* -0+00b9 <L74\+0x2> jmp 0+0+ <L0> +0+00b9 <L74\+0x2> jmp 0x0+0+ <L0> ba: R_M68HC11_16 L225 -0+00bc <L75> bmi 0+00c1 <L76> +0+00bc <L75> bmi 0x0+00c1 <L76> bc: R_M68HC11_RL_JUMP \*ABS\* -0+00be <L75\+0x2> jmp 0+0+ <L0> +0+00be <L75\+0x2> jmp 0x0+0+ <L0> bf: R_M68HC11_16 L252 -0+00c1 <L76> bra 0+0106 <L103> +0+00c1 <L76> bra 0x0+0106 <L103> c1: R_M68HC11_RL_JUMP \*ABS\* -0+00c3 <L77> brclr \*0+0+ <L0> #\$00 0+0145 <L125\+0x2> +0+00c3 <L77> brclr \*0x0+0+ <L0>, #0x00, 0x0+0145 <L125\+0x2> c3: R_M68HC11_RL_JUMP \*ABS\* c4: R_M68HC11_8 Z62 c5: R_M68HC11_8 \$01 -0+00c7 <L78> brclr 151,x #\$00 0+0127 <L115> +0+00c7 <L78> brclr 0x97,x, #0x00, 0x0+0127 <L115> c7: R_M68HC11_RL_JUMP \*ABS\* c9: R_M68HC11_8 \$ea -0+00cb <L79> brclr 107,x #\$00 0+00de <L84\+0x1> +0+00cb <L79> brclr 0x6b,x, #0x00, 0x0+00de <L84\+0x1> cb: R_M68HC11_RL_JUMP \*ABS\* cd: R_M68HC11_8 \$96 -0+00cf <L80> brn 0+0082 <L56> +0+00cf <L80> brn 0x0+0082 <L56> cf: R_M68HC11_RL_JUMP \*ABS\* -0+00d1 <L81> brset \*0+0+ <L0> #\$00 0+0141 <L124> +0+00d1 <L81> brset \*0x0+0+ <L0>, #0x00, 0x0+0141 <L124> d1: R_M68HC11_RL_JUMP \*ABS\* d2: R_M68HC11_8 Z92 d3: R_M68HC11_8 \$2a -0+00d5 <L82> brset 176,x #\$00 0+0154 <L132> +0+00d5 <L82> brset 0xb0,x, #0x00, 0x0+0154 <L132> d5: R_M68HC11_RL_JUMP \*ABS\* d7: R_M68HC11_8 \$3b -0+00d9 <L83> brset 50,x #\$00 0+0119 <L110\+0x2> +0+00d9 <L83> brset 0x32,x, #0x00, 0x0+0119 <L110\+0x2> d9: R_M68HC11_RL_JUMP \*ABS\* db: R_M68HC11_8 \$af -0+00dd <L84> bset \*0+0+ <L0> #\$00 +0+00dd <L84> bset \*0x0+0+ <L0>, #0x00 de: R_M68HC11_8 Z84 df: R_M68HC11_8 \$ec -0+00e0 <L85> bset 24,x #\$00 +0+00e0 <L85> bset 0x18,x, #0x00 e2: R_M68HC11_8 \$db -0+00e3 <L86> bset 92,x #\$00 +0+00e3 <L86> bset 0x5c,x, #0x00 e5: R_M68HC11_8 \$02 -0+00e6 <L87> jsr 0+0+ <L0> +0+00e6 <L87> jsr 0x0+0+ <L0> e6: R_M68HC11_RL_JUMP \*ABS\* e7: R_M68HC11_16 L26 -0+00e9 <L88> bvs 0+00ee <L89> +0+00e9 <L88> bvs 0x0+00ee <L89> e9: R_M68HC11_RL_JUMP \*ABS\* -0+00eb <L88\+0x2> jmp 0+0+ <L0> +0+00eb <L88\+0x2> jmp 0x0+0+ <L0> ec: R_M68HC11_16 L254 -0+00ee <L89> bvs 0+00a2 <L67> +0+00ee <L89> bvs 0x0+00a2 <L67> ee: R_M68HC11_RL_JUMP \*ABS\* 0+00f0 <L90> cba 0+00f1 <L91> clc 0+00f2 <L92> cli -0+00f3 <L93> clr 251,x -0+00f5 <L94> clr 0+0+ <L0> +0+00f3 <L93> clr 0xfb,x +0+00f5 <L94> clr 0x0+0+ <L0> f6: R_M68HC11_16 symbol250 -0+00f8 <L95> clr 170,x +0+00f8 <L95> clr 0xaa,x 0+00fa <L96> clra 0+00fb <L97> clrb 0+00fc <L98> clv -0+00fd <L99> cmpa #58 -0+00ff <L100> cmpa \*0+0+ <L0> +0+00fd <L99> cmpa #0x3a +0+00ff <L100> cmpa \*0x0+0+ <L0> 100: R_M68HC11_8 Z251 -0+0101 <L101> cmpa 41,x -0+0103 <L102> cmpa 0+0+ <L0> +0+0101 <L101> cmpa 0x29,x +0+0103 <L102> cmpa 0x0+0+ <L0> 104: R_M68HC11_16 symbol209 -0+0106 <L103> cmpa 230,x -0+0108 <L104> cmpb #5 -0+010a <L105> cmpb \*0+0+ <L0> +0+0106 <L103> cmpa 0xe6,x +0+0108 <L104> cmpb #0x5 +0+010a <L105> cmpb \*0x0+0+ <L0> 10b: R_M68HC11_8 Z60 -0+010c <L106> cmpb 124,x -0+010e <L107> cmpb 0+0+ <L0> +0+010c <L106> cmpb 0x7c,x +0+010e <L107> cmpb 0x0+0+ <L0> 10f: R_M68HC11_16 symbol148 -0+0111 <L108> cmpb 117,x -0+0113 <L109> cpd #0+0fd8 <L330\+0xcf1> -0+0117 <L110> cpd \*0+0+ <L0> +0+0111 <L108> cmpb 0x75,x +0+0113 <L109> cpd #0x0+0fd8 <L330\+0xcf1> +0+0117 <L110> cpd \*0x0+0+ <L0> 119: R_M68HC11_8 Z190 -0+011a <L111> cpd 97,x -0+011d <L112> cpd 0+0+ <L0> +0+011a <L111> cpd 0x61,x +0+011d <L112> cpd 0x0+0+ <L0> 11f: R_M68HC11_16 symbol137 -0+0121 <L113> cpd 249,x -0+0124 <L114> cpx #0+af5c <L330\+0xac75> -0+0127 <L115> cpx \*0+0+ <L0> +0+0121 <L113> cpd 0xf9,x +0+0124 <L114> cpx #0x0+af5c <L330\+0xac75> +0+0127 <L115> cpx \*0x0+0+ <L0> 128: R_M68HC11_8 Z187 -0+0129 <L116> cpx 168,x -0+012b <L117> cpx 0+0+ <L0> +0+0129 <L116> cpx 0xa8,x +0+012b <L117> cpx 0x0+0+ <L0> 12c: R_M68HC11_16 symbol153 -0+012e <L118> cpx 15,x -0+0130 <L119> cpy #0+4095 <L330\+0x3dae> -0+0134 <L120> cpy \*0+0+ <L0> +0+012e <L118> cpx 0xf,x +0+0130 <L119> cpy #0x0+4095 <L330\+0x3dae> +0+0134 <L120> cpy \*0x0+0+ <L0> 136: R_M68HC11_8 Z177 -0+0137 <L121> cpy 235,x -0+013a <L122> cpy 0+0+ <L0> +0+0137 <L121> cpy 0xeb,x +0+013a <L122> cpy 0x0+0+ <L0> 13c: R_M68HC11_16 symbol241 -0+013e <L123> cpy 179,x -0+0141 <L124> com 5,x -0+0143 <L125> com 0+0+ <L0> +0+013e <L123> cpy 0xb3,x +0+0141 <L124> com 0x5,x +0+0143 <L125> com 0x0+0+ <L0> 144: R_M68HC11_16 symbol239 -0+0146 <L126> com 247,x +0+0146 <L126> com 0xf7,x 0+0148 <L127> coma 0+0149 <L128> comb -0+014a <L129> cpd #0+bf00 <L330\+0xbc19> -0+014e <L130> cpd \*0+0+ <L0> +0+014a <L129> cpd #0x0+bf00 <L330\+0xbc19> +0+014e <L130> cpd \*0x0+0+ <L0> 150: R_M68HC11_8 Z233 -0+0151 <L131> cpd 161,x -0+0154 <L132> cpd 0+0+ <L0> +0+0151 <L131> cpd 0xa1,x +0+0154 <L132> cpd 0x0+0+ <L0> 156: R_M68HC11_16 symbol58 -0+0158 <L133> cpd 229,x -0+015b <L134> cpx #0+8fca <L330\+0x8ce3> -0+015e <L135> cpx \*0+0+ <L0> +0+0158 <L133> cpd 0xe5,x +0+015b <L134> cpx #0x0+8fca <L330\+0x8ce3> +0+015e <L135> cpx \*0x0+0+ <L0> 15f: R_M68HC11_8 Z11 -0+0160 <L136> cpx 203,x -0+0162 <L137> cpx 0+0+ <L0> +0+0160 <L136> cpx 0xcb,x +0+0162 <L137> cpx 0x0+0+ <L0> 163: R_M68HC11_16 symbol208 -0+0165 <L138> cpx 72,x -0+0167 <L139> cpy #0+0247 <L248> -0+016b <L140> cpy \*0+0+ <L0> +0+0165 <L138> cpx 0x48,x +0+0167 <L139> cpy #0x0+0247 <L248> +0+016b <L140> cpy \*0x0+0+ <L0> 16d: R_M68HC11_8 Z100 -0+016e <L141> cpy 189,x -0+0171 <L142> cpy 0+0+ <L0> +0+016e <L141> cpy 0xbd,x +0+0171 <L142> cpy 0x0+0+ <L0> 173: R_M68HC11_16 symbol31 -0+0175 <L143> cpy 35,x +0+0175 <L143> cpy 0x23,x 0+0178 <L144> daa -0+0179 <L145> dec 30,x -0+017b <L146> dec 0+0+ <L0> +0+0179 <L145> dec 0x1e,x +0+017b <L146> dec 0x0+0+ <L0> 17c: R_M68HC11_16 symbol168 -0+017e <L147> dec 28,x +0+017e <L147> dec 0x1c,x 0+0180 <L148> deca 0+0181 <L149> decb 0+0182 <L150> des 0+0183 <L151> dex 0+0184 <L152> dey -0+0186 <L153> eora #123 -0+0188 <L154> eora \*0+0+ <L0> +0+0186 <L153> eora #0x7b +0+0188 <L154> eora \*0x0+0+ <L0> 189: R_M68HC11_8 Z100 -0+018a <L155> eora 197,x -0+018c <L156> eora 0+0+ <L0> +0+018a <L155> eora 0xc5,x +0+018c <L156> eora 0x0+0+ <L0> 18d: R_M68HC11_16 symbol20 -0+018f <L157> eora 115,x -0+0191 <L158> eorb #90 -0+0193 <L159> eorb \*0+0+ <L0> +0+018f <L157> eora 0x73,x +0+0191 <L158> eorb #0x5a +0+0193 <L159> eorb \*0x0+0+ <L0> 194: R_M68HC11_8 Z197 -0+0195 <L160> eorb 94,x -0+0197 <L161> eorb 0+0+ <L0> +0+0195 <L160> eorb 0x5e,x +0+0197 <L161> eorb 0x0+0+ <L0> 198: R_M68HC11_16 symbol75 -0+019a <L162> eorb 121,x +0+019a <L162> eorb 0x79,x 0+019c <L163> fdiv 0+019d <L164> idiv -0+019e <L165> inc 99,x -0+01a0 <L166> inc 0+0+ <L0> +0+019e <L165> inc 0x63,x +0+01a0 <L166> inc 0x0+0+ <L0> 1a1: R_M68HC11_16 symbol59 -0+01a3 <L167> inc 112,x +0+01a3 <L167> inc 0x70,x 0+01a5 <L168> inca 0+01a6 <L169> incb 0+01a7 <L170> ins 0+01a8 <L171> inx 0+01a9 <L172> iny -0+01ab <L173> jmp 100,x -0+01ad <L174> jmp 0+0+ <L0> +0+01ab <L173> jmp 0x64,x +0+01ad <L174> jmp 0x0+0+ <L0> 1ad: R_M68HC11_RL_JUMP \*ABS\* 1ae: R_M68HC11_16 symbol36 -0+01b0 <L175> jmp 17,x -0+01b2 <L176> jsr \*0+0+ <L0> +0+01b0 <L175> jmp 0x11,x +0+01b2 <L176> jsr \*0x0+0+ <L0> 1b2: R_M68HC11_RL_JUMP \*ABS\* 1b3: R_M68HC11_8 Z158 -0+01b4 <L177> jsr 9,x -0+01b6 <L178> jsr 0+0+ <L0> +0+01b4 <L177> jsr 0x9,x +0+01b6 <L178> jsr 0x0+0+ <L0> 1b6: R_M68HC11_RL_JUMP \*ABS\* 1b7: R_M68HC11_16 symbol220 -0+01b9 <L179> jsr 170,x -0+01bb <L180> ldaa #212 -0+01bd <L181> ldaa \*0+0+ <L0> +0+01b9 <L179> jsr 0xaa,x +0+01bb <L180> ldaa #0xd4 +0+01bd <L181> ldaa \*0x0+0+ <L0> 1be: R_M68HC11_8 Z172 -0+01bf <L182> ldaa 242,x -0+01c1 <L183> ldaa 0+0+ <L0> +0+01bf <L182> ldaa 0xf2,x +0+01c1 <L183> ldaa 0x0+0+ <L0> 1c2: R_M68HC11_16 symbol27 -0+01c4 <L184> ldaa 16,x -0+01c6 <L185> ldab #175 -0+01c8 <L186> ldab \*0+0+ <L0> +0+01c4 <L184> ldaa 0x10,x +0+01c6 <L185> ldab #0xaf +0+01c8 <L186> ldab \*0x0+0+ <L0> 1c9: R_M68HC11_8 Z59 -0+01ca <L187> ldab 51,x -0+01cc <L188> ldab 0+0+ <L0> +0+01ca <L187> ldab 0x33,x +0+01cc <L188> ldab 0x0+0+ <L0> 1cd: R_M68HC11_16 symbol205 -0+01cf <L189> ldab 227,x -0+01d1 <L190> ldd #0+c550 <L330\+0xc269> -0+01d4 <L191> ldd \*0+0+ <L0> +0+01cf <L189> ldab 0xe3,x +0+01d1 <L190> ldd #0x0+c550 <L330\+0xc269> +0+01d4 <L191> ldd \*0x0+0+ <L0> 1d5: R_M68HC11_8 Z72 -0+01d6 <L192> ldd 71,x -0+01d8 <L193> ldd 0+0+ <L0> +0+01d6 <L192> ldd 0x47,x +0+01d8 <L193> ldd 0x0+0+ <L0> 1d9: R_M68HC11_16 symbol21 -0+01db <L194> ldd 92,x -0+01dd <L195> lds #0+4fbb <L330\+0x4cd4> -0+01e0 <L196> lds \*0+0+ <L0> +0+01db <L194> ldd 0x5c,x +0+01dd <L195> lds #0x0+4fbb <L330\+0x4cd4> +0+01e0 <L196> lds \*0x0+0+ <L0> 1e1: R_M68HC11_8 Z111 -0+01e2 <L197> lds 34,x -0+01e4 <L198> lds 0+0+ <L0> +0+01e2 <L197> lds 0x22,x +0+01e4 <L198> lds 0x0+0+ <L0> 1e5: R_M68HC11_16 symbol25 -0+01e7 <L199> lds 186,x -0+01e9 <L200> ldx #0+579b <L330\+0x54b4> -0+01ec <L201> ldx \*0+0+ <L0> +0+01e7 <L199> lds 0xba,x +0+01e9 <L200> ldx #0x0+579b <L330\+0x54b4> +0+01ec <L201> ldx \*0x0+0+ <L0> 1ed: R_M68HC11_8 Z125 -0+01ee <L202> ldx 245,x -0+01f0 <L203> ldx 0+0+ <L0> +0+01ee <L202> ldx 0xf5,x +0+01f0 <L203> ldx 0x0+0+ <L0> 1f1: R_M68HC11_16 symbol11 -0+01f3 <L204> ldx 225,x -0+01f5 <L205> ldy #0+ac1a <L330\+0xa933> -0+01f9 <L206> ldy \*0+0+ <L0> +0+01f3 <L204> ldx 0xe1,x +0+01f5 <L205> ldy #0x0+ac1a <L330\+0xa933> +0+01f9 <L206> ldy \*0x0+0+ <L0> 1fb: R_M68HC11_8 Z28 -0+01fc <L207> ldy 127,x -0+01ff <L208> ldy 0+0+ <L0> +0+01fc <L207> ldy 0x7f,x +0+01ff <L208> ldy 0x0+0+ <L0> 201: R_M68HC11_16 symbol35 -0+0203 <L209> ldy 248,x -0+0206 <L210> asl 41,x -0+0208 <L211> asl 0+0+ <L0> +0+0203 <L209> ldy 0xf8,x +0+0206 <L210> asl 0x29,x +0+0208 <L211> asl 0x0+0+ <L0> 209: R_M68HC11_16 symbol248 -0+020b <L212> asl 164,x +0+020b <L212> asl 0xa4,x 0+020d <L213> asla 0+020e <L214> aslb 0+020f <L215> asld -0+0210 <L216> lsr 27,x -0+0212 <L217> lsr 0+0+ <L0> +0+0210 <L216> lsr 0x1b,x +0+0212 <L217> lsr 0x0+0+ <L0> 213: R_M68HC11_16 symbol19 -0+0215 <L218> lsr 181,x +0+0215 <L218> lsr 0xb5,x 0+0217 <L219> lsra 0+0218 <L220> lsrb 0+0219 <L221> lsrd 0+021a <L222> mul -0+021b <L223> neg 202,x -0+021d <L224> neg 0+0+ <L0> +0+021b <L223> neg 0xca,x +0+021d <L224> neg 0x0+0+ <L0> 21e: R_M68HC11_16 symbol78 -0+0220 <L225> neg 232,x +0+0220 <L225> neg 0xe8,x 0+0222 <L226> nega 0+0223 <L227> negb 0+0224 <L228> nop -0+0225 <L229> oraa #152 -0+0227 <L230> oraa \*0+0+ <L0> +0+0225 <L229> oraa #0x98 +0+0227 <L230> oraa \*0x0+0+ <L0> 228: R_M68HC11_8 Z50 -0+0229 <L231> oraa 56,x -0+022b <L232> oraa 0+0+ <L0> +0+0229 <L231> oraa 0x38,x +0+022b <L232> oraa 0x0+0+ <L0> 22c: R_M68HC11_16 symbol224 -0+022e <L233> oraa 121,x -0+0230 <L234> orab #77 -0+0232 <L235> orab \*0+0+ <L0> +0+022e <L233> oraa 0x79,x +0+0230 <L234> orab #0x4d +0+0232 <L235> orab \*0x0+0+ <L0> 233: R_M68HC11_8 Z61 -0+0234 <L236> orab 52,x -0+0236 <L237> orab 0+0+ <L0> +0+0234 <L236> orab 0x34,x +0+0236 <L237> orab 0x0+0+ <L0> 237: R_M68HC11_16 symbol188 -0+0239 <L238> orab 95,x +0+0239 <L238> orab 0x5f,x 0+023b <L239> psha 0+023c <L240> pshb 0+023d <L241> pshx @@ -389,106 +389,106 @@ Disassembly of section .text: 0+0241 <L244> pulb 0+0242 <L245> pulx 0+0243 <L246> puly -0+0245 <L247> rol 78,x -0+0247 <L248> rol 0+0+ <L0> +0+0245 <L247> rol 0x4e,x +0+0247 <L248> rol 0x0+0+ <L0> 248: R_M68HC11_16 symbol119 -0+024a <L249> rol 250,x +0+024a <L249> rol 0xfa,x 0+024c <L250> rola 0+024d <L251> rolb -0+024e <L252> ror 203,x -0+0250 <L253> ror 0+0+ <L0> +0+024e <L252> ror 0xcb,x +0+0250 <L253> ror 0x0+0+ <L0> 251: R_M68HC11_16 symbol108 -0+0253 <L254> ror 5,x +0+0253 <L254> ror 0x5,x 0+0255 <L255> rora 0+0256 <L256> rorb 0+0257 <L257> rti 0+0258 <L258> rts 0+0259 <L259> sba -0+025a <L260> sbca #172 -0+025c <L261> sbca \*0+0+ <L0> +0+025a <L260> sbca #0xac +0+025c <L261> sbca \*0x0+0+ <L0> 25d: R_M68HC11_8 Z134 -0+025e <L262> sbca 33,x -0+0260 <L263> sbca 0+0+ <L0> +0+025e <L262> sbca 0x21,x +0+0260 <L263> sbca 0x0+0+ <L0> 261: R_M68HC11_16 symbol43 -0+0263 <L264> sbca 170,x -0+0265 <L265> sbcb #26 -0+0267 <L266> sbcb \*0+0+ <L0> +0+0263 <L264> sbca 0xaa,x +0+0265 <L265> sbcb #0x1a +0+0267 <L266> sbcb \*0x0+0+ <L0> 268: R_M68HC11_8 Z85 -0+0269 <L267> sbcb 162,x -0+026b <L268> sbcb 0+0+ <L0> +0+0269 <L267> sbcb 0xa2,x +0+026b <L268> sbcb 0x0+0+ <L0> 26c: R_M68HC11_16 symbol190 -0+026e <L269> sbcb 112,x +0+026e <L269> sbcb 0x70,x 0+0270 <L270> sec 0+0271 <L271> sei 0+0272 <L272> sev -0+0273 <L273> staa \*0+0+ <L0> +0+0273 <L273> staa \*0x0+0+ <L0> 274: R_M68HC11_8 Z181 -0+0275 <L274> staa 115,x -0+0277 <L275> staa 0+0+ <L0> +0+0275 <L274> staa 0x73,x +0+0277 <L275> staa 0x0+0+ <L0> 278: R_M68HC11_16 symbol59 -0+027a <L276> staa 4,x -0+027c <L277> stab \*0+0+ <L0> +0+027a <L276> staa 0x4,x +0+027c <L277> stab \*0x0+0+ <L0> 27d: R_M68HC11_8 Z92 -0+027e <L278> stab 211,x -0+0280 <L279> stab 0+0+ <L0> +0+027e <L278> stab 0xd3,x +0+0280 <L279> stab 0x0+0+ <L0> 281: R_M68HC11_16 symbol54 -0+0283 <L280> stab 148,x -0+0285 <L281> std \*0+0+ <L0> +0+0283 <L280> stab 0x94,x +0+0285 <L281> std \*0x0+0+ <L0> 286: R_M68HC11_8 Z179 -0+0287 <L282> std 175,x -0+0289 <L283> std 0+0+ <L0> +0+0287 <L282> std 0xaf,x +0+0289 <L283> std 0x0+0+ <L0> 28a: R_M68HC11_16 symbol226 -0+028c <L284> std 240,x +0+028c <L284> std 0xf0,x 0+028e <L285> stop -0+028f <L286> sts \*0+0+ <L0> +0+028f <L286> sts \*0x0+0+ <L0> 290: R_M68HC11_8 Z228 -0+0291 <L287> sts 158,x -0+0293 <L288> sts 0+0+ <L0> +0+0291 <L287> sts 0x9e,x +0+0293 <L288> sts 0x0+0+ <L0> 294: R_M68HC11_16 symbol79 -0+0296 <L289> sts 50,x -0+0298 <L290> stx \*0+0+ <L0> +0+0296 <L289> sts 0x32,x +0+0298 <L290> stx \*0x0+0+ <L0> 299: R_M68HC11_8 Z21 -0+029a <L291> stx 73,x -0+029c <L292> stx 0+0+ <L0> +0+029a <L291> stx 0x49,x +0+029c <L292> stx 0x0+0+ <L0> 29d: R_M68HC11_16 symbol253 -0+029f <L293> stx 130,x -0+02a1 <L294> sty \*0+0+ <L0> +0+029f <L293> stx 0x82,x +0+02a1 <L294> sty \*0x0+0+ <L0> 2a3: R_M68HC11_8 Z78 -0+02a4 <L295> sty 169,x -0+02a7 <L296> sty 0+0+ <L0> +0+02a4 <L295> sty 0xa9,x +0+02a7 <L296> sty 0x0+0+ <L0> 2a9: R_M68HC11_16 symbol8 -0+02ab <L297> sty 112,x -0+02ae <L298> suba #212 -0+02b0 <L299> suba \*0+0+ <L0> +0+02ab <L297> sty 0x70,x +0+02ae <L298> suba #0xd4 +0+02b0 <L299> suba \*0x0+0+ <L0> 2b1: R_M68HC11_8 Z178 -0+02b2 <L300> suba 138,x -0+02b4 <L301> suba 0+0+ <L0> +0+02b2 <L300> suba 0x8a,x +0+02b4 <L301> suba 0x0+0+ <L0> 2b5: R_M68HC11_16 symbol41 -0+02b7 <L302> suba 84,x -0+02b9 <L303> subb #72 -0+02bb <L304> subb \*0+0+ <L0> +0+02b7 <L302> suba 0x54,x +0+02b9 <L303> subb #0x48 +0+02bb <L304> subb \*0x0+0+ <L0> 2bc: R_M68HC11_8 Z154 -0+02bd <L305> subb 10,x -0+02bf <L306> subb 0+0+ <L0> +0+02bd <L305> subb 0xa,x +0+02bf <L306> subb 0x0+0+ <L0> 2c0: R_M68HC11_16 symbol188 -0+02c2 <L307> subb 213,x -0+02c4 <L308> subd #0+f10e <L330\+0xee27> -0+02c7 <L309> subd \*0+0+ <L0> +0+02c2 <L307> subb 0xd5,x +0+02c4 <L308> subd #0x0+f10e <L330\+0xee27> +0+02c7 <L309> subd \*0x0+0+ <L0> 2c8: R_M68HC11_8 Z24 -0+02c9 <L310> subd 168,x -0+02cb <L311> subd 0+0+ <L0> +0+02c9 <L310> subd 0xa8,x +0+02cb <L311> subd 0x0+0+ <L0> 2cc: R_M68HC11_16 symbol68 -0+02ce <L312> subd 172,x +0+02ce <L312> subd 0xac,x 0+02d0 <L313> swi 0+02d1 <L314> tab 0+02d2 <L315> tap 0+02d3 <L316> tba ... 0+02d5 <L318> tpa -0+02d6 <L319> tst 91,x -0+02d8 <L320> tst 0+0+ <L0> +0+02d6 <L319> tst 0x5b,x +0+02d8 <L320> tst 0x0+0+ <L0> 2d9: R_M68HC11_16 symbol243 -0+02db <L321> tst 142,x +0+02db <L321> tst 0x8e,x 0+02dd <L322> tsta 0+02de <L323> tstb 0+02df <L324> tsx diff --git a/gas/testsuite/gas/m68hc11/branchs12.d b/gas/testsuite/gas/m68hc11/branchs12.d index 682b1cc..47d3598 100644 --- a/gas/testsuite/gas/m68hc11/branchs12.d +++ b/gas/testsuite/gas/m68hc11/branchs12.d @@ -5,220 +5,220 @@ .*: +file format elf32\-m68hc12 Disassembly of section .text: -0+00 <start> bgt 0+48 <L1> +0+00 <start> bgt 0x0+48 <L1> [ ]+0: R_M68HC12_RL_JUMP \*ABS\* -0+02 <start\+0x2> bge 0+48 <L1> +0+02 <start\+0x2> bge 0x0+48 <L1> [ ]+2: R_M68HC12_RL_JUMP \*ABS\* -0+04 <start\+0x4> ble 0+48 <L1> +0+04 <start\+0x4> ble 0x0+48 <L1> [ ]+4: R_M68HC12_RL_JUMP \*ABS\* -0+06 <start\+0x6> blt 0+48 <L1> +0+06 <start\+0x6> blt 0x0+48 <L1> [ ]+6: R_M68HC12_RL_JUMP \*ABS\* -0+08 <start\+0x8> bhi 0+48 <L1> +0+08 <start\+0x8> bhi 0x0+48 <L1> [ ]+8: R_M68HC12_RL_JUMP \*ABS\* -0+0a <start\+0xa> bcc 0+48 <L1> +0+0a <start\+0xa> bcc 0x0+48 <L1> [ ]+a: R_M68HC12_RL_JUMP \*ABS\* -0+0c <start\+0xc> bcc 0+48 <L1> +0+0c <start\+0xc> bcc 0x0+48 <L1> [ ]+c: R_M68HC12_RL_JUMP \*ABS\* -0+0e <start\+0xe> beq 0+48 <L1> +0+0e <start\+0xe> beq 0x0+48 <L1> [ ]+e: R_M68HC12_RL_JUMP \*ABS\* -0+10 <start\+0x10> bls 0+48 <L1> +0+10 <start\+0x10> bls 0x0+48 <L1> [ ]+10: R_M68HC12_RL_JUMP \*ABS\* -0+12 <start\+0x12> bcs 0+48 <L1> +0+12 <start\+0x12> bcs 0x0+48 <L1> [ ]+12: R_M68HC12_RL_JUMP \*ABS\* -0+14 <start\+0x14> bcs 0+48 <L1> +0+14 <start\+0x14> bcs 0x0+48 <L1> [ ]+14: R_M68HC12_RL_JUMP \*ABS\* -0+16 <start\+0x16> bmi 0+48 <L1> +0+16 <start\+0x16> bmi 0x0+48 <L1> [ ]+16: R_M68HC12_RL_JUMP \*ABS\* -0+18 <start\+0x18> bvs 0+48 <L1> +0+18 <start\+0x18> bvs 0x0+48 <L1> [ ]+18: R_M68HC12_RL_JUMP \*ABS\* -0+1a <start\+0x1a> bra 0+48 <L1> +0+1a <start\+0x1a> bra 0x0+48 <L1> [ ]+1a: R_M68HC12_RL_JUMP \*ABS\* -0+1c <start\+0x1c> bvc 0+48 <L1> +0+1c <start\+0x1c> bvc 0x0+48 <L1> [ ]+1c: R_M68HC12_RL_JUMP \*ABS\* -0+1e <start\+0x1e> bne 0+48 <L1> +0+1e <start\+0x1e> bne 0x0+48 <L1> [ ]+1e: R_M68HC12_RL_JUMP \*ABS\* -0+20 <start\+0x20> bpl 0+48 <L1> +0+20 <start\+0x20> bpl 0x0+48 <L1> [ ]+20: R_M68HC12_RL_JUMP \*ABS\* -0+22 <start\+0x22> brn 0+48 <L1> +0+22 <start\+0x22> brn 0x0+48 <L1> [ ]+22: R_M68HC12_RL_JUMP \*ABS\* -0+24 <start\+0x24> bgt 0+00 <start> +0+24 <start\+0x24> bgt 0x0+00 <start> [ ]+24: R_M68HC12_RL_JUMP \*ABS\* -0+26 <start\+0x26> bge 0+00 <start> +0+26 <start\+0x26> bge 0x0+00 <start> [ ]+26: R_M68HC12_RL_JUMP \*ABS\* -0+28 <start\+0x28> ble 0+00 <start> +0+28 <start\+0x28> ble 0x0+00 <start> [ ]+28: R_M68HC12_RL_JUMP \*ABS\* -0+2a <start\+0x2a> blt 0+00 <start> +0+2a <start\+0x2a> blt 0x0+00 <start> [ ]+2a: R_M68HC12_RL_JUMP \*ABS\* -0+2c <start\+0x2c> bhi 0+00 <start> +0+2c <start\+0x2c> bhi 0x0+00 <start> [ ]+2c: R_M68HC12_RL_JUMP \*ABS\* -0+2e <start\+0x2e> bcc 0+00 <start> +0+2e <start\+0x2e> bcc 0x0+00 <start> [ ]+2e: R_M68HC12_RL_JUMP \*ABS\* -0+30 <start\+0x30> bcc 0+00 <start> +0+30 <start\+0x30> bcc 0x0+00 <start> [ ]+30: R_M68HC12_RL_JUMP \*ABS\* -0+32 <start\+0x32> beq 0+00 <start> +0+32 <start\+0x32> beq 0x0+00 <start> [ ]+32: R_M68HC12_RL_JUMP \*ABS\* -0+34 <start\+0x34> bls 0+00 <start> +0+34 <start\+0x34> bls 0x0+00 <start> [ ]+34: R_M68HC12_RL_JUMP \*ABS\* -0+36 <start\+0x36> bcs 0+00 <start> +0+36 <start\+0x36> bcs 0x0+00 <start> [ ]+36: R_M68HC12_RL_JUMP \*ABS\* -0+38 <start\+0x38> bcs 0+00 <start> +0+38 <start\+0x38> bcs 0x0+00 <start> [ ]+38: R_M68HC12_RL_JUMP \*ABS\* -0+3a <start\+0x3a> bmi 0+00 <start> +0+3a <start\+0x3a> bmi 0x0+00 <start> [ ]+3a: R_M68HC12_RL_JUMP \*ABS\* -0+3c <start\+0x3c> bvs 0+00 <start> +0+3c <start\+0x3c> bvs 0x0+00 <start> [ ]+3c: R_M68HC12_RL_JUMP \*ABS\* -0+3e <start\+0x3e> bra 0+00 <start> +0+3e <start\+0x3e> bra 0x0+00 <start> [ ]+3e: R_M68HC12_RL_JUMP \*ABS\* -0+40 <start\+0x40> bvc 0+00 <start> +0+40 <start\+0x40> bvc 0x0+00 <start> [ ]+40: R_M68HC12_RL_JUMP \*ABS\* -0+42 <start\+0x42> bne 0+00 <start> +0+42 <start\+0x42> bne 0x0+00 <start> [ ]+42: R_M68HC12_RL_JUMP \*ABS\* -0+44 <start\+0x44> bpl 0+00 <start> +0+44 <start\+0x44> bpl 0x0+00 <start> [ ]+44: R_M68HC12_RL_JUMP \*ABS\* -0+46 <start\+0x46> brn 0+00 <start> +0+46 <start\+0x46> brn 0x0+00 <start> [ ]+46: R_M68HC12_RL_JUMP \*ABS\* -0+48 <L1> lbgt 0+1e7 <L2> +0+48 <L1> lbgt 0x0+1e7 <L2> [ ]+48: R_M68HC12_RL_JUMP \*ABS\* -0+4c <L1\+0x4> lbge 0+1e7 <L2> +0+4c <L1\+0x4> lbge 0x0+1e7 <L2> [ ]+4c: R_M68HC12_RL_JUMP \*ABS\* -0+50 <L1\+0x8> lble 0+1e7 <L2> +0+50 <L1\+0x8> lble 0x0+1e7 <L2> [ ]+50: R_M68HC12_RL_JUMP \*ABS\* -0+54 <L1\+0xc> lblt 0+1e7 <L2> +0+54 <L1\+0xc> lblt 0x0+1e7 <L2> [ ]+54: R_M68HC12_RL_JUMP \*ABS\* -0+58 <L1\+0x10> lbhi 0+1e7 <L2> +0+58 <L1\+0x10> lbhi 0x0+1e7 <L2> [ ]+58: R_M68HC12_RL_JUMP \*ABS\* -0+5c <L1\+0x14> lbcc 0+1e7 <L2> +0+5c <L1\+0x14> lbcc 0x0+1e7 <L2> [ ]+5c: R_M68HC12_RL_JUMP \*ABS\* -0+60 <L1\+0x18> lbcc 0+1e7 <L2> +0+60 <L1\+0x18> lbcc 0x0+1e7 <L2> [ ]+60: R_M68HC12_RL_JUMP \*ABS\* -0+64 <L1\+0x1c> lbeq 0+1e7 <L2> +0+64 <L1\+0x1c> lbeq 0x0+1e7 <L2> [ ]+64: R_M68HC12_RL_JUMP \*ABS\* -0+68 <L1\+0x20> lbls 0+1e7 <L2> +0+68 <L1\+0x20> lbls 0x0+1e7 <L2> [ ]+68: R_M68HC12_RL_JUMP \*ABS\* -0+6c <L1\+0x24> lbcs 0+1e7 <L2> +0+6c <L1\+0x24> lbcs 0x0+1e7 <L2> [ ]+6c: R_M68HC12_RL_JUMP \*ABS\* -0+70 <L1\+0x28> lbcs 0+1e7 <L2> +0+70 <L1\+0x28> lbcs 0x0+1e7 <L2> [ ]+70: R_M68HC12_RL_JUMP \*ABS\* -0+74 <L1\+0x2c> lbmi 0+1e7 <L2> +0+74 <L1\+0x2c> lbmi 0x0+1e7 <L2> [ ]+74: R_M68HC12_RL_JUMP \*ABS\* -0+78 <L1\+0x30> lbvs 0+1e7 <L2> +0+78 <L1\+0x30> lbvs 0x0+1e7 <L2> [ ]+78: R_M68HC12_RL_JUMP \*ABS\* -0+7c <L1\+0x34> lbra 0+1e7 <L2> +0+7c <L1\+0x34> lbra 0x0+1e7 <L2> [ ]+7c: R_M68HC12_RL_JUMP \*ABS\* -0+80 <L1\+0x38> lbvc 0+1e7 <L2> +0+80 <L1\+0x38> lbvc 0x0+1e7 <L2> [ ]+80: R_M68HC12_RL_JUMP \*ABS\* -0+84 <L1\+0x3c> lbne 0+1e7 <L2> +0+84 <L1\+0x3c> lbne 0x0+1e7 <L2> [ ]+84: R_M68HC12_RL_JUMP \*ABS\* -0+88 <L1\+0x40> lbpl 0+1e7 <L2> +0+88 <L1\+0x40> lbpl 0x0+1e7 <L2> [ ]+88: R_M68HC12_RL_JUMP \*ABS\* -0+8c <L1\+0x44> lbrn 0+1e7 <L2> +0+8c <L1\+0x44> lbrn 0x0+1e7 <L2> [ ]+8c: R_M68HC12_RL_JUMP \*ABS\* -0+90 <L1\+0x48> lbgt 0+00 <start> +0+90 <L1\+0x48> lbgt 0x0+00 <start> [ ]+90: R_M68HC12_RL_JUMP \*ABS\* [ ]+92: R_M68HC12_PCREL_16 undefined -0+94 <L1\+0x4c> lbge 0+00 <start> +0+94 <L1\+0x4c> lbge 0x0+00 <start> [ ]+94: R_M68HC12_RL_JUMP \*ABS\* [ ]+96: R_M68HC12_PCREL_16 undefined -0+98 <L1\+0x50> lble 0+00 <start> +0+98 <L1\+0x50> lble 0x0+00 <start> [ ]+98: R_M68HC12_RL_JUMP \*ABS\* [ ]+9a: R_M68HC12_PCREL_16 undefined -0+9c <L1\+0x54> lblt 0+00 <start> +0+9c <L1\+0x54> lblt 0x0+00 <start> [ ]+9c: R_M68HC12_RL_JUMP \*ABS\* [ ]+9e: R_M68HC12_PCREL_16 undefined -0+a0 <L1\+0x58> lbhi 0+00 <start> +0+a0 <L1\+0x58> lbhi 0x0+00 <start> [ ]+a0: R_M68HC12_RL_JUMP \*ABS\* [ ]+a2: R_M68HC12_PCREL_16 undefined -0+a4 <L1\+0x5c> lbcc 0+00 <start> +0+a4 <L1\+0x5c> lbcc 0x0+00 <start> [ ]+a4: R_M68HC12_RL_JUMP \*ABS\* [ ]+a6: R_M68HC12_PCREL_16 undefined -0+a8 <L1\+0x60> lbcc 0+00 <start> +0+a8 <L1\+0x60> lbcc 0x0+00 <start> [ ]+a8: R_M68HC12_RL_JUMP \*ABS\* [ ]+aa: R_M68HC12_PCREL_16 undefined -0+ac <L1\+0x64> lbeq 0+00 <start> +0+ac <L1\+0x64> lbeq 0x0+00 <start> [ ]+ac: R_M68HC12_RL_JUMP \*ABS\* [ ]+ae: R_M68HC12_PCREL_16 undefined -0+b0 <L1\+0x68> lbls 0+00 <start> +0+b0 <L1\+0x68> lbls 0x0+00 <start> [ ]+b0: R_M68HC12_RL_JUMP \*ABS\* [ ]+b2: R_M68HC12_PCREL_16 undefined -0+b4 <L1\+0x6c> lbcs 0+00 <start> +0+b4 <L1\+0x6c> lbcs 0x0+00 <start> [ ]+b4: R_M68HC12_RL_JUMP \*ABS\* [ ]+b6: R_M68HC12_PCREL_16 undefined -0+b8 <L1\+0x70> lbcs 0+00 <start> +0+b8 <L1\+0x70> lbcs 0x0+00 <start> [ ]+b8: R_M68HC12_RL_JUMP \*ABS\* [ ]+ba: R_M68HC12_PCREL_16 undefined -0+bc <L1\+0x74> lbmi 0+00 <start> +0+bc <L1\+0x74> lbmi 0x0+00 <start> [ ]+bc: R_M68HC12_RL_JUMP \*ABS\* [ ]+be: R_M68HC12_PCREL_16 undefined -0+c0 <L1\+0x78> lbvs 0+00 <start> +0+c0 <L1\+0x78> lbvs 0x0+00 <start> [ ]+c0: R_M68HC12_RL_JUMP \*ABS\* [ ]+c2: R_M68HC12_PCREL_16 undefined -0+c4 <L1\+0x7c> jmp 0+00 <start> +0+c4 <L1\+0x7c> jmp 0x0+00 <start> [ ]+c4: R_M68HC12_RL_JUMP \*ABS\* [ ]+c5: R_M68HC12_16 undefined -0+c7 <L1\+0x7f> lbvc 0+00 <start> +0+c7 <L1\+0x7f> lbvc 0x0+00 <start> [ ]+c7: R_M68HC12_RL_JUMP \*ABS\* [ ]+c9: R_M68HC12_PCREL_16 undefined -0+cb <L1\+0x83> lbne 0+00 <start> +0+cb <L1\+0x83> lbne 0x0+00 <start> [ ]+cb: R_M68HC12_RL_JUMP \*ABS\* [ ]+cd: R_M68HC12_PCREL_16 undefined -0+cf <L1\+0x87> lbpl 0+00 <start> +0+cf <L1\+0x87> lbpl 0x0+00 <start> [ ]+cf: R_M68HC12_RL_JUMP \*ABS\* [ ]+d1: R_M68HC12_PCREL_16 undefined -0+d3 <L1\+0x8b> lbrn 0+00 <start> +0+d3 <L1\+0x8b> lbrn 0x0+00 <start> [ ]+d3: R_M68HC12_RL_JUMP \*ABS\* [ ]+d5: R_M68HC12_PCREL_16 undefined -0+d7 <L1\+0x8f> lbgt 0+10 <start\+0x10> +0+d7 <L1\+0x8f> lbgt 0x0+10 <start\+0x10> [ ]+d7: R_M68HC12_RL_JUMP \*ABS\* [ ]+d9: R_M68HC12_PCREL_16 undefined -0+db <L1\+0x93> lbge 0+10 <start\+0x10> +0+db <L1\+0x93> lbge 0x0+10 <start\+0x10> [ ]+db: R_M68HC12_RL_JUMP \*ABS\* [ ]+dd: R_M68HC12_PCREL_16 undefined -0+df <L1\+0x97> lble 0+10 <start\+0x10> +0+df <L1\+0x97> lble 0x0+10 <start\+0x10> [ ]+df: R_M68HC12_RL_JUMP \*ABS\* [ ]+e1: R_M68HC12_PCREL_16 undefined -0+e3 <L1\+0x9b> lblt 0+10 <start\+0x10> +0+e3 <L1\+0x9b> lblt 0x0+10 <start\+0x10> [ ]+e3: R_M68HC12_RL_JUMP \*ABS\* [ ]+e5: R_M68HC12_PCREL_16 undefined -0+e7 <L1\+0x9f> lbhi 0+10 <start\+0x10> +0+e7 <L1\+0x9f> lbhi 0x0+10 <start\+0x10> [ ]+e7: R_M68HC12_RL_JUMP \*ABS\* [ ]+e9: R_M68HC12_PCREL_16 undefined -0+eb <L1\+0xa3> lbcc 0+10 <start\+0x10> +0+eb <L1\+0xa3> lbcc 0x0+10 <start\+0x10> [ ]+eb: R_M68HC12_RL_JUMP \*ABS\* [ ]+ed: R_M68HC12_PCREL_16 undefined -0+ef <L1\+0xa7> lbcc 0+10 <start\+0x10> +0+ef <L1\+0xa7> lbcc 0x0+10 <start\+0x10> [ ]+ef: R_M68HC12_RL_JUMP \*ABS\* [ ]+f1: R_M68HC12_PCREL_16 undefined -0+f3 <L1\+0xab> lbeq 0+10 <start\+0x10> +0+f3 <L1\+0xab> lbeq 0x0+10 <start\+0x10> [ ]+f3: R_M68HC12_RL_JUMP \*ABS\* [ ]+f5: R_M68HC12_PCREL_16 undefined -0+f7 <L1\+0xaf> lbls 0+10 <start\+0x10> +0+f7 <L1\+0xaf> lbls 0x0+10 <start\+0x10> [ ]+f7: R_M68HC12_RL_JUMP \*ABS\* [ ]+f9: R_M68HC12_PCREL_16 undefined -0+fb <L1\+0xb3> lbcs 0+10 <start\+0x10> +0+fb <L1\+0xb3> lbcs 0x0+10 <start\+0x10> [ ]+fb: R_M68HC12_RL_JUMP \*ABS\* [ ]+fd: R_M68HC12_PCREL_16 undefined -0+ff <L1\+0xb7> lbcs 0+10 <start\+0x10> +0+ff <L1\+0xb7> lbcs 0x0+10 <start\+0x10> [ ]+ff: R_M68HC12_RL_JUMP \*ABS\* [ ]+101: R_M68HC12_PCREL_16 undefined -0+103 <L1\+0xbb> lbmi 0+10 <start\+0x10> +0+103 <L1\+0xbb> lbmi 0x0+10 <start\+0x10> [ ]+103: R_M68HC12_RL_JUMP \*ABS\* [ ]+105: R_M68HC12_PCREL_16 undefined -0+107 <L1\+0xbf> lbvs 0+10 <start\+0x10> +0+107 <L1\+0xbf> lbvs 0x0+10 <start\+0x10> [ ]+107: R_M68HC12_RL_JUMP \*ABS\* [ ]+109: R_M68HC12_PCREL_16 undefined -0+10b <L1\+0xc3> lbra 0+10 <start\+0x10> +0+10b <L1\+0xc3> lbra 0x0+10 <start\+0x10> [ ]+10b: R_M68HC12_RL_JUMP \*ABS\* [ ]+10d: R_M68HC12_PCREL_16 undefined -0+10f <L1\+0xc7> lbvc 0+10 <start\+0x10> +0+10f <L1\+0xc7> lbvc 0x0+10 <start\+0x10> [ ]+10f: R_M68HC12_RL_JUMP \*ABS\* [ ]+111: R_M68HC12_PCREL_16 undefined -0+113 <L1\+0xcb> lbne 0+10 <start\+0x10> +0+113 <L1\+0xcb> lbne 0x0+10 <start\+0x10> [ ]+113: R_M68HC12_RL_JUMP \*ABS\* [ ]+115: R_M68HC12_PCREL_16 undefined -0+117 <L1\+0xcf> lbpl 0+10 <start\+0x10> +0+117 <L1\+0xcf> lbpl 0x0+10 <start\+0x10> [ ]+117: R_M68HC12_RL_JUMP \*ABS\* [ ]+119: R_M68HC12_PCREL_16 undefined -0+11b <L1\+0xd3> lbrn 0+10 <start\+0x10> +0+11b <L1\+0xd3> lbrn 0x0+10 <start\+0x10> [ ]+11b: R_M68HC12_RL_JUMP \*ABS\* [ ]+11d: R_M68HC12_PCREL_16 undefined ... diff --git a/gas/testsuite/gas/m68hc11/bug-1825.d b/gas/testsuite/gas/m68hc11/bug-1825.d index 0f134fc..055d82d 100644 --- a/gas/testsuite/gas/m68hc11/bug-1825.d +++ b/gas/testsuite/gas/m68hc11/bug-1825.d @@ -15,9 +15,9 @@ _main: nop 0: a7 nop ldx L1,pc ; Assemble to 5\-bit > 0 offset - 1: ee c2 ldx 2,PC \{5 <L1>\} + 1: ee c2 ldx 0x2,PC \{0x5 <L1>\} bra L2 - 3: 20 02 bra 7 <L2> + 3: 20 02 bra 0x7 <L2> 3: R_M68HC12_RL_JUMP \*ABS\* 0+5 <L1>: @@ -28,7 +28,7 @@ L1: .dc.w 0xaabb L2: subd L1,pc ; Assemble to 5\-bit < 0 offset - 7: a3 dc subd \-4,PC \{5 <L1>\} + 7: a3 dc subd 0xfffc,PC \{0x5 <L1>\} 0+9 <L3>: 9: a7 nop @@ -48,9 +48,9 @@ L2: L3: .ds.b 14, 0xA7 ldab L3,pc ; 5\-bit < 0 offset - 17: e6 d0 ldab \-16,PC \{9 <L3>\} + 17: e6 d0 ldab 0xfff0,PC \{0x9 <L3>\} ldab L4,pc ; 5\-bit > 0 offset - 19: e6 cf ldab 15,PC \{2a <L4>\} + 19: e6 cf ldab 0xf,PC \{0x2a <L4>\} ... 0+2a <L4>: @@ -59,9 +59,9 @@ L3: L4: .skip 128 subd L4,pc ; 9\-bit < 0 offset - aa: a3 f9 7d subd \-131,PC \{2a <L4>\} + aa: a3 f9 7d subd 0xff7d,PC \{0x2a <L4>\} addd L5,pc ; 9\-bit > 0 offset - ad: e3 f8 80 addd 128,PC \{130 <L5>\} + ad: e3 f8 80 addd 0x80,PC \{0x130 <L5>\} ... 0+130 <L5>: @@ -71,9 +71,9 @@ L4: L5: .skip 256\-3 orab L5,pc ; 9 bit < 0 offset \(min value\) - 22d: ea f9 00 orab \-256,PC \{130 <L5>\} + 22d: ea f9 00 orab 0xff00,PC \{0x130 <L5>\} oraa L6,pc ; 9 bit > 0 offset \(max value\) - 230: aa f8 ff oraa 255,PC \{332 <L6>\} + 230: aa f8 ff oraa 0xff,PC \{0x332 <L6>\} ... 0+332 <L6>: @@ -84,31 +84,31 @@ L5: L6: .skip 256\-2 orab L6,pc ; 16 bit < 0 offset - 430: ea fa fe fe orab \-258,PC \{332 <L6>\} + 430: ea fa fe fe orab 0xfefe,PC \{0x332 <L6>\} anda _main,pc ; 16 bit < 0 offset - 434: a4 fa fb c8 anda \-1080,PC \{0 <_main>\} + 434: a4 fa fb c8 anda 0xfbc8,PC \{0x0 <_main>\} andb L7,pc - 438: e4 fa 01 00 andb 256,PC \{53c <L7>\} + 438: e4 fa 01 00 andb 0x100,PC \{0x53c <L7>\} ... 0+53c <L7>: .skip 256 L7: stab external,pc ; External 16\-bit PCREL - 53c: 6b fa fa c0 stab \-1344,PC \{0 <_main>\} + 53c: 6b fa fa c0 stab 0xfac0,PC \{0x0 <_main>\} 53e: R_M68HC12_PCREL_16 external ldd _table,pc - 540: ec cf ldd 15,PC \{551 <_table>\} + 540: ec cf ldd 0xf,PC \{0x551 <_table>\} addd _table\+2,pc - 542: e3 cf addd 15,PC \{553 <_table\+0x2>\} + 542: e3 cf addd 0xf,PC \{0x553 <_table\+0x2>\} subd _table\+4,pc - 544: a3 cf subd 15,PC \{555 <_table\+0x4>\} + 544: a3 cf subd 0xf,PC \{0x555 <_table\+0x4>\} addd _table\+8,pc - 546: e3 f8 10 addd 16,PC \{559 <_table\+0x8>\} + 546: e3 f8 10 addd 0x10,PC \{0x559 <_table\+0x8>\} addd _table\+12,pc - 549: e3 f8 11 addd 17,PC \{55d <_table\+0xc>\} + 549: e3 f8 11 addd 0x11,PC \{0x55d <_table\+0xc>\} addd _table\+16,pc - 54c: e3 f8 12 addd 18,PC \{561 <_table\+0x10>\} + 54c: e3 f8 12 addd 0x12,PC \{0x561 <_table\+0x10>\} rts 54f: 3d rts nop @@ -119,11 +119,11 @@ L7: _table: .ds.b 16,0 leax _table,sp ; 16\-bit absolute reloc - 561: 1a f2 00 00 leax 0,SP + 561: 1a f2 00 00 leax 0x0,SP 563: R_M68HC12_16 _table leay _table,x - 565: 19 e2 00 00 leay 0,X + 565: 19 e2 00 00 leay 0x0,X 567: R_M68HC12_16 _table leax _table,y - 569: 1a ea 00 00 leax 0,Y + 569: 1a ea 00 00 leax 0x0,Y 56b: R_M68HC12_16 _table diff --git a/gas/testsuite/gas/m68hc11/hexprefix.d b/gas/testsuite/gas/m68hc11/hexprefix.d new file mode 100644 index 0000000..f6c9dd7 --- /dev/null +++ b/gas/testsuite/gas/m68hc11/hexprefix.d @@ -0,0 +1,19 @@ +#objdump: -d -mm9s12x --prefix-addresses --reloc +#as: -mm9s12x +#name: verify hex prefixes present and not duplicated (hexprefix) + +dump.o: file format elf32-m68hc12 + + +Disassembly of section .text: +0x00000000 ldaa 0x00001234 +0x00000003 ldab #0x12 +0x00000005 ldd \*0x00000023 +0x00000007 ldx #0x00001234 +0x0000000a movw 0x00001234, 0x00002345 +0x00000010 movb 0x00003456, 0x00004567 +0x00000016 orx 0x00008765 +0x0000001a call 0x00104007 \{0x00008007, 0x3d\} + 1a: R_M68HC12_RL_JUMP \*ABS\* +0x0000001e movw #0x00001234, 0x00002345 +0x00000024 movb #0x23, 0x00003456 diff --git a/gas/testsuite/gas/m68hc11/hexprefix.s b/gas/testsuite/gas/m68hc11/hexprefix.s new file mode 100644 index 0000000..18647f2 --- /dev/null +++ b/gas/testsuite/gas/m68hc11/hexprefix.s @@ -0,0 +1,14 @@ +# Test for correct generation of hex prefixes. + + .sect .text + + ldaa 0x1234 + ldab #0x12 + ldd *0x23 + ldx #0x1234 + movw 0x1234, 0x2345 + movb 0x3456, 0x4567 + orx 0x8765 + call 0x8007, 0x3d + movw #0x1234, 0x2345 + movb #0x23, 0x3456 diff --git a/gas/testsuite/gas/m68hc11/indexed12.d b/gas/testsuite/gas/m68hc11/indexed12.d index 360d87b..1862b6a 100644 --- a/gas/testsuite/gas/m68hc11/indexed12.d +++ b/gas/testsuite/gas/m68hc11/indexed12.d @@ -17,122 +17,122 @@ _main: 0: a7 nop ;;; Global check \(1st\) ldab L1\-_main,x ; Offset/const of these 2 insns must be - 1: e6 e0 93 ldab 147,X + 1: e6 e0 93 ldab 0x93,X ldaa #L1\-_main ; identical \(likewise for 2nd global check\) - 4: 86 93 ldaa #147 + 4: 86 93 ldaa #0x93 ;;; Test gas relax with difference of symbols \(same section\) ldaa L2\-L1,x ; \-> ldaa 2,x \(5\-bit offset\), text seg - 6: a6 02 ldaa 2,X + 6: a6 02 ldaa 0x2,X adda L1\-L2,y ; \-> adda \-2,y \(5\-bit offset\), text seg - 8: ab 5e adda \-2,Y + 8: ab 5e adda 0xfffe,Y orab L7\-L6,sp ; \-> orab 8,sp \(5\-bit offset\), text seg - a: ea 88 orab 8,SP + a: ea 88 orab 0x8,SP anda L8\-L7,sp ; \-> anda 15,sp \(5\-bit offset\), text seg - c: a4 8f anda 15,SP + c: a4 8f anda 0xf,SP eora L7\-L8,sp ; \-> eora \-15,sp \(5\-bit offset\), text seg - e: a8 91 eora \-15,SP + e: a8 91 eora 0xfff1,SP eorb L7\-L9,sp ; \-> eorb \-16,sp \(5\-bit offset\), text seg - 10: e8 90 eorb \-16,SP + 10: e8 90 eorb 0xfff0,SP andb L9\-L7,sp ; \-> andb 16,sp \(9\-bit offset\), text seg - 12: e4 f0 10 andb 16,SP + 12: e4 f0 10 andb 0x10,SP staa L7\-L10,x ; \-> staa \-17,x \(9\-bit offset\), text seg - 15: 6a e1 ef staa \-17,X + 15: 6a e1 ef staa 0xffef,X stab L11\-L10,y ; \-> stab 128,y \(9\-bit offset\), text seg - 18: 6b e8 80 stab 128,Y + 18: 6b e8 80 stab 0x80,Y stab L10\-L11,y ; \-> stab \-128,y \(9\-bit offset\), text seg - 1b: 6b e9 80 stab \-128,Y + 1b: 6b e9 80 stab 0xff80,Y stab L11\-L10\+1,y ; \-> stab 129,y \(9\-bit offset\), text seg - 1e: 6b e8 81 stab 129,Y + 1e: 6b e8 81 stab 0x81,Y stab L10\-L11\-1,y ; \-> stab \-129,y \(9\-bit offset\), text seg - 21: 6b e9 7f stab \-129,Y + 21: 6b e9 7f stab 0xff7f,Y stab L11\-1\-L10,y ; \-> stab 127,y \(9\-bit offset\), text seg - 24: 6b e8 7f stab 127,Y + 24: 6b e8 7f stab 0x7f,Y stab L10\-1\-L11,y ; \-> stab \-129,y \(9\-bit offset\), text seg - 27: 6b e9 7f stab \-129,Y + 27: 6b e9 7f stab 0xff7f,Y tst L12\-L10,x ; \-> tst 255,x \(9\-bit offset\), text seg - 2a: e7 e0 ff tst 255,X + 2a: e7 e0 ff tst 0xff,X tst L10\-L12,x ; \-> tst \-255,x \(9\-bit offset\), text seg - 2d: e7 e1 01 tst \-255,X + 2d: e7 e1 01 tst 0xff01,X tst L12\-L10\+1,x ; \-> tst 256,x \(16\-bit offset\), text seg - 30: e7 e2 01 00 tst 256,X + 30: e7 e2 01 00 tst 0x100,X mina L13\-L10,x ; \-> mina 256,x \(16\-bit offset\) - 34: 18 19 e2 01 mina 256,X + 34: 18 19 e2 01 mina 0x100,X 38: 00 mina L10\-L13,x ; \-> mina \-256,x \(9\-bit offset\) - 39: 18 19 e1 00 mina \-256,X + 39: 18 19 e1 00 mina 0xff00,X maxa L14\-L10,x ; \-> maxa 257,x \(16\-bit offset\) - 3d: 18 18 e2 01 maxa 257,X + 3d: 18 18 e2 01 maxa 0x101,X 41: 01 maxa L10\-L14,x ; \-> maxa \-257,x \(16\-bit offset\) - 42: 18 18 e2 fe maxa \-257,X + 42: 18 18 e2 fe maxa 0xfeff,X 46: ff ;;; Test gas relax with difference of symbols \(different section\) ldaa D2\-D1,x ; \-> ldaa 2,x \(5\-bit offset\), data seg - 47: a6 02 ldaa 2,X + 47: a6 02 ldaa 0x2,X adda D1\-D2,y ; \-> adda \-2,y \(5\-bit offset\), data seg - 49: ab 5e adda \-2,Y + 49: ab 5e adda 0xfffe,Y orab D7\-D6,sp ; \-> orab 8,sp \(5\-bit offset\), data seg - 4b: ea 88 orab 8,SP + 4b: ea 88 orab 0x8,SP anda D8\-D7,sp ; \-> anda 15,sp \(5\-bit offset\), data seg - 4d: a4 8f anda 15,SP + 4d: a4 8f anda 0xf,SP eora D7\-D8,sp ; \-> eora \-15,sp \(5\-bit offset\), data seg - 4f: a8 91 eora \-15,SP + 4f: a8 91 eora 0xfff1,SP eorb D7\-D9,sp ; \-> eorb \-16,sp \(5\-bit offset\), data seg - 51: e8 90 eorb \-16,SP + 51: e8 90 eorb 0xfff0,SP andb D9\-D7,sp ; \-> andb 16,sp \(9\-bit offset\), data seg - 53: e4 f0 10 andb 16,SP + 53: e4 f0 10 andb 0x10,SP staa D7\-D10,x ; \-> staa \-17,x \(9\-bit offset\), data seg - 56: 6a e1 ef staa \-17,X + 56: 6a e1 ef staa 0xffef,X stab D11\-D10,y ; \-> stab 128,y \(9\-bit offset\), data seg - 59: 6b e8 80 stab 128,Y + 59: 6b e8 80 stab 0x80,Y stab D10\-D11,y ; \-> stab \-128,y \(9\-bit offset\), data seg - 5c: 6b e9 80 stab \-128,Y + 5c: 6b e9 80 stab 0xff80,Y stab D11\-D10\+1,y ; \-> stab 129,y \(9\-bit offset\), data seg - 5f: 6b e8 81 stab 129,Y + 5f: 6b e8 81 stab 0x81,Y stab D10\-D11\+1,y ; \-> stab \-127,y \(9\-bit offset\), data seg - 62: 6b e9 81 stab \-127,Y + 62: 6b e9 81 stab 0xff81,Y stab D11\-1\-D10,y ; \-> stab 127,y \(9\-bit offset\), data seg - 65: 6b e8 7f stab 127,Y + 65: 6b e8 7f stab 0x7f,Y stab D10\-1\-D11,y ; \-> stab \-129,y \(9\-bit offset\), data seg - 68: 6b e9 7f stab \-129,Y + 68: 6b e9 7f stab 0xff7f,Y tst D12\-D10,x ; \-> tst 255,x \(9\-bit offset\), data seg - 6b: e7 e0 ff tst 255,X + 6b: e7 e0 ff tst 0xff,X tst D10\-D12,x ; \-> tst \-255,x \(9\-bit offset\), data seg - 6e: e7 e1 01 tst \-255,X + 6e: e7 e1 01 tst 0xff01,X tst D12\-D10\+1,x ; \-> tst 256,x \(16\-bit offset\), data seg - 71: e7 e2 01 00 tst 256,X + 71: e7 e2 01 00 tst 0x100,X mina D13\-D10,x ; \-> mina 256,x \(16\-bit offset\) - 75: 18 19 e2 01 mina 256,X + 75: 18 19 e2 01 mina 0x100,X 79: 00 mina D10\-D13,x ; \-> mina \-256,x \(9\-bit offset\) - 7a: 18 19 e1 00 mina \-256,X + 7a: 18 19 e1 00 mina 0xff00,X maxa D14\-D10,x ; \-> maxa 257,x \(16\-bit offset\) - 7e: 18 18 e2 01 maxa 257,X + 7e: 18 18 e2 01 maxa 0x101,X 82: 01 maxa D10\-D14,x ; \-> maxa \-257,x \(16\-bit offset\) - 83: 18 18 e2 fe maxa \-257,X + 83: 18 18 e2 fe maxa 0xfeff,X 87: ff ;;; Global check \(2nd\) ldab L1\-_main,x - 88: e6 e0 93 ldab 147,X + 88: e6 e0 93 ldab 0x93,X ldaa #L1\-_main - 8b: 86 93 ldaa #147 + 8b: 86 93 ldaa #0x93 ;;; Indexed addressing with external symbol ldab _external\+128,x - 8d: e6 e2 00 80 ldab 128,X + 8d: e6 e2 00 80 ldab 0x80,X bra L2 - 91: 20 02 bra 95 <L2> + 91: 20 02 bra 0x95 <L2> 0+93 <L1>: 93: aa bb oraa 5,SP\- diff --git a/gas/testsuite/gas/m68hc11/insns-dwarf2.d b/gas/testsuite/gas/m68hc11/insns-dwarf2.d index 5b05bb7..706a04e 100644 --- a/gas/testsuite/gas/m68hc11/insns-dwarf2.d +++ b/gas/testsuite/gas/m68hc11/insns-dwarf2.d @@ -16,18 +16,18 @@ Disassembly of section .text: _start: lds #stack\+1024 - 0: 8e 04 00 lds #400 <stack_end> + 0: 8e 04 00 lds #0x400 <stack_end> ldx #1 - 3: ce 00 01 ldx #1 <_start\+0x1> + 3: ce 00 01 ldx #0x1 <_start\+0x1> 0+06 <Loop>: Loop: jsr test - 6: bd 00 00 jsr 0 <_start> + 6: bd 00 00 jsr 0x0 <_start> dex 9: 09 dex bne Loop - a: 26 fa bne 6 <Loop> + a: 26 fa bne 0x6 <Loop> 0000000c <Stop>: c: cd 03 .byte 0xcd, 0x03 @@ -36,15 +36,15 @@ Stop: .byte 0xcd .byte 3 bra _start - e: 20 f0 bra 0 <_start> + e: 20 f0 bra 0x0 <_start> 00000010 <test>: test: ldd #2 - 10: cc 00 02 ldd #2 <_start\+0x2> + 10: cc 00 02 ldd #0x2 <_start\+0x2> jsr test2 - 13: bd 00 00 jsr 0 <_start> + 13: bd 00 00 jsr 0x0 <_start> rts 16: 39 rts @@ -56,59 +56,59 @@ value = 23 .globl test2 test2: ldx value,y - 17: cd ee 17 ldx 23,y + 17: cd ee 17 ldx 0x17,y std value,x - 1a: ed 17 std 23,x + 1a: ed 17 std 0x17,x ldd ,x - 1c: ec 00 ldd 0,x + 1c: ec 00 ldd 0x0,x sty ,y - 1e: 18 ef 00 sty 0,y + 1e: 18 ef 00 sty 0x0,y stx ,y - 21: cd ef 00 stx 0,y + 21: cd ef 00 stx 0x0,y brclr 6,x,#4,test2 - 24: 1f 06 04 ef brclr 6,x #\$04 17 <test2> + 24: 1f 06 04 ef brclr 0x6,x, #0x04, 0x17 <test2> brclr 12,x #8 test2 - 28: 1f 0c 08 eb brclr 12,x #\$08 17 <test2> + 28: 1f 0c 08 eb brclr 0xc,x, #0x08, 0x17 <test2> ldd \*ZD1 - 2c: dc 00 ldd \*0 <_start> + 2c: dc 00 ldd \*0x0 <_start> ldx \*ZD1\+2 - 2e: de 02 ldx \*2 <_start\+0x2> + 2e: de 02 ldx \*0x2 <_start\+0x2> clr \*ZD2 - 30: 7f 00 00 clr 0 <_start> + 30: 7f 00 00 clr 0x0 <_start> clr \*ZD2\+1 - 33: 7f 00 01 clr 1 <_start\+0x1> + 33: 7f 00 01 clr 0x1 <_start\+0x1> bne .-4 - 36: 26 fc bne 34 <test2\+0x1d> + 36: 26 fc bne 0x34 <test2\+0x1d> beq .\+2 - 38: 27 02 beq 3c <test2\+0x25> + 38: 27 02 beq 0x3c <test2\+0x25> bclr \*ZD1\+1, #32 - 3a: 15 01 20 bclr \*1 <_start\+0x1> #\$20 + 3a: 15 01 20 bclr \*0x1 <_start\+0x1>, #0x20 brclr \*ZD2\+2, #40, test2 - 3d: 13 02 28 d6 brclr \*2 <_start\+0x2> #\$28 17 <test2> + 3d: 13 02 28 d6 brclr \*0x2 <_start\+0x2>, #0x28, 0x17 <test2> ldy #24\+_start-44 - 41: 18 ce ff ec ldy #ffec <stack_end\+0xfbec> + 41: 18 ce ff ec ldy #0xffec <stack_end\+0xfbec> ldd B_low,y - 45: 18 ec 0c ldd 12,y + 45: 18 ec 0c ldd 0xc,y addd A_low,y - 48: 18 e3 2c addd 44,y + 48: 18 e3 2c addd 0x2c,y addd D_low,y - 4b: 18 e3 32 addd 50,y + 4b: 18 e3 32 addd 0x32,y subd A_low - 4e: b3 00 2c subd 2c <test2\+0x15> + 4e: b3 00 2c subd 0x2c <test2\+0x15> subd #A_low - 51: 83 00 2c subd #2c <test2\+0x15> + 51: 83 00 2c subd #0x2c <test2\+0x15> jmp Stop - 54: 7e 00 00 jmp 0 <_start> + 54: 7e 00 00 jmp 0x0 <_start> 00000057 <L1>: L1: anda #%lo\(test2\) - 57: 84 17 anda #23 + 57: 84 17 anda #0x17 andb #%hi\(test2\) - 59: c4 00 andb #0 + 59: c4 00 andb #0x0 ldab #%page\(test2\) ; Check that the relocs are against symbol - 5b: c6 00 ldab #0 + 5b: c6 00 ldab #0x0 ldy #%addr\(test2\) ; otherwise linker relaxation fails - 5d: 18 ce 00 00 ldy #0 <_start> + 5d: 18 ce 00 00 ldy #0x0 <_start> rts 61: 39 rts diff --git a/gas/testsuite/gas/m68hc11/insns.d b/gas/testsuite/gas/m68hc11/insns.d index 41cb4b0..a90620f 100644 --- a/gas/testsuite/gas/m68hc11/insns.d +++ b/gas/testsuite/gas/m68hc11/insns.d @@ -7,63 +7,63 @@ .*: +file format elf32\-m68hc11 Disassembly of section .text: -0+0+ <_start> lds #0+0400 <stack_end> +0+0+ <_start> lds #0x0+0400 <stack_end> [ ]+1: R_M68HC11_16 stack -0+0003 <_start\+0x3> ldx #0+0001 <_start\+0x1> -0+0006 <Loop> jsr 0+0+ <_start> +0+0003 <_start\+0x3> ldx #0x0+0001 <_start\+0x1> +0+0006 <Loop> jsr 0x0+0+ <_start> [ ]+6: R_M68HC11_RL_JUMP \*ABS\* [ ]+7: R_M68HC11_16 test 0+0009 <Loop\+0x3> dex -0+000a <Loop\+0x4> bne 0+0006 <Loop> +0+000a <Loop\+0x4> bne 0x0+0006 <Loop> [ ]+a: R_M68HC11_RL_JUMP \*ABS\* 0+000c <Stop> .byte 0xcd, 0x03 -0+000e <Stop\+0x2> bra 0+0+ <_start> +0+000e <Stop\+0x2> bra 0x0+0+ <_start> [ ]+e: R_M68HC11_RL_JUMP \*ABS\* -0+0010 <test> ldd #0+0002 <_start\+0x2> -0+0013 <test\+0x3> jsr 0+0+ <_start> +0+0010 <test> ldd #0x0+0002 <_start\+0x2> +0+0013 <test\+0x3> jsr 0x0+0+ <_start> [ ]+13: R_M68HC11_RL_JUMP \*ABS\* [ ]+14: R_M68HC11_16 test2 0+0016 <test\+0x6> rts -0+0017 <test2> ldx 23,y -0+001a <test2\+0x3> std 23,x -0+001c <test2\+0x5> ldd 0,x -0+001e <test2\+0x7> sty 0,y -0+0021 <test2\+0xa> stx 0,y -0+0024 <test2\+0xd> brclr 6,x #\$04 0+0017 <test2> +0+0017 <test2> ldx 0x17,y +0+001a <test2\+0x3> std 0x17,x +0+001c <test2\+0x5> ldd 0x0,x +0+001e <test2\+0x7> sty 0x0,y +0+0021 <test2\+0xa> stx 0x0,y +0+0024 <test2\+0xd> brclr 0x6,x, #0x04, 0x0+0017 <test2> [ ]+24: R_M68HC11_RL_JUMP \*ABS\* -0+0028 <test2\+0x11> brclr 12,x #\$08 0+0017 <test2> +0+0028 <test2\+0x11> brclr 0xc,x, #0x08, 0x0+0017 <test2> [ ]+28: R_M68HC11_RL_JUMP \*ABS\* -0+002c <test2\+0x15> ldd \*0+0+ <_start> +0+002c <test2\+0x15> ldd \*0x0+0+ <_start> [ ]+2d: R_M68HC11_8 ZD1 -0+002e <test2\+0x17> ldx \*0+0002 <_start\+0x2> +0+002e <test2\+0x17> ldx \*0x0+0002 <_start\+0x2> [ ]+2f: R_M68HC11_8 ZD1 -0+0030 <test2\+0x19> clr 0+0+ <_start> +0+0030 <test2\+0x19> clr 0x0+0+ <_start> [ ]+31: R_M68HC11_16 ZD2 -0+0033 <test2\+0x1c> clr 0+0001 <_start\+0x1> +0+0033 <test2\+0x1c> clr 0x0+0001 <_start\+0x1> [ ]+34: R_M68HC11_16 ZD2 -0+0036 <test2\+0x1f> bne 0+0034 <test2\+0x1d> -0+0038 <test2\+0x21> beq 0+003c <test2\+0x25> -0+003a <test2\+0x23> bclr \*0+0001 <_start\+0x1> #\$20 +0+0036 <test2\+0x1f> bne 0x0+0034 <test2\+0x1d> +0+0038 <test2\+0x21> beq 0x0+003c <test2\+0x25> +0+003a <test2\+0x23> bclr \*0x0+0001 <_start\+0x1>, #0x20 [ ]+3b: R_M68HC11_8 ZD1 -0+003d <test2\+0x26> brclr \*0+0002 <_start\+0x2> #\$28 0+0017 <test2> +0+003d <test2\+0x26> brclr \*0x0+0002 <_start\+0x2>, #0x28, 0x0+0017 <test2> [ ]+3d: R_M68HC11_RL_JUMP \*ABS\* [ ]+3e: R_M68HC11_8 ZD2 -0+0041 <test2\+0x2a> ldy #0+ffec <stack_end\+0xfbec> +0+0041 <test2\+0x2a> ldy #0x0+ffec <stack_end\+0xfbec> [ ]+43: R_M68HC11_16 _start -0+0045 <test2\+0x2e> ldd 12,y -0+0048 <test2\+0x31> addd 44,y -0+004b <test2\+0x34> addd 50,y -0+004e <test2\+0x37> subd 0+002c <test2\+0x15> -0+0051 <test2\+0x3a> subd #0+002c <test2\+0x15> -0+0054 <test2\+0x3d> jmp 0+0+ <_start> +0+0045 <test2\+0x2e> ldd 0xc,y +0+0048 <test2\+0x31> addd 0x2c,y +0+004b <test2\+0x34> addd 0x32,y +0+004e <test2\+0x37> subd 0x0+002c <test2\+0x15> +0+0051 <test2\+0x3a> subd #0x0+002c <test2\+0x15> +0+0054 <test2\+0x3d> jmp 0x0+0+ <_start> [ ]+54: R_M68HC11_RL_JUMP \*ABS\* [ ]+55: R_M68HC11_16 Stop -0+0057 <L1> anda #23 +0+0057 <L1> anda #0x17 [ ]+58: R_M68HC11_LO8 \.text -0+0059 <L1\+0x2> andb #0 +0+0059 <L1\+0x2> andb #0x0 [ ]+5a: R_M68HC11_HI8 \.text -0+5b <L1\+0x4> ldab #0 +0+5b <L1\+0x4> ldab #0x0 [ ]+5c: R_M68HC11_PAGE test2 -0+5d <L1\+0x6> ldy #0+ <_start> +0+5d <L1\+0x6> ldy #0x0+ <_start> [ ]+5f: R_M68HC11_LO16 test2 0+61 <L1\+0xa> rts diff --git a/gas/testsuite/gas/m68hc11/insns12.d b/gas/testsuite/gas/m68hc11/insns12.d index c42cfcc..3abc5a9 100644 --- a/gas/testsuite/gas/m68hc11/insns12.d +++ b/gas/testsuite/gas/m68hc11/insns12.d @@ -5,81 +5,81 @@ .*: +file format elf32-m68hc12 Disassembly of section .text: -0+ <call_test> call 0+ <call_test> \{0+ <call_test>, 0\} +0+ <call_test> call 0x0+ <call_test> \{0x0+ <call_test>, 0x0\} 0: R_M68HC12_RL_JUMP \*ABS\* 1: R_M68HC12_24 _foo -0+4 <call_test\+0x4> call 0+ <call_test> \{0+ <call_test>, 1\} +0+4 <call_test\+0x4> call 0x0+ <call_test> \{0x0+ <call_test>, 0x1\} 4: R_M68HC12_RL_JUMP \*ABS\* 5: R_M68HC12_LO16 _foo -0+8 <call_test\+0x8> call 0+ <call_test> \{0+ <call_test>, 0\} +0+8 <call_test\+0x8> call 0x0+ <call_test> \{0x0+ <call_test>, 0x0\} 8: R_M68HC12_RL_JUMP \*ABS\* 9: R_M68HC12_LO16 _foo b: R_M68HC12_PAGE foo_page -0+c <call_test\+0xc> call 0,X, 3 +0+c <call_test\+0xc> call 0x0,X, 0x3 c: R_M68HC12_RL_JUMP \*ABS\* -0+f <call_test\+0xf> call 4,Y, 12 +0+f <call_test\+0xf> call 0x4,Y, 0xc f: R_M68HC12_RL_JUMP \*ABS\* -0+12 <call_test\+0x12> call 7,SP, 13 +0+12 <call_test\+0x12> call 0x7,SP, 0xd 12: R_M68HC12_RL_JUMP \*ABS\* -0+15 <call_test\+0x15> call 12,X, 0 +0+15 <call_test\+0x15> call 0xc,X, 0x0 15: R_M68HC12_RL_JUMP \*ABS\* 17: R_M68HC12_PAGE foo_page -0+18 <call_test\+0x18> call 4,Y, 0 +0+18 <call_test\+0x18> call 0x4,Y, 0x0 18: R_M68HC12_RL_JUMP \*ABS\* 1a: R_M68HC12_PAGE foo_page -0+1b <call_test\+0x1b> call 7,SP, 0 +0+1b <call_test\+0x1b> call 0x7,SP, 0x0 1b: R_M68HC12_RL_JUMP \*ABS\* 1d: R_M68HC12_PAGE foo_page 0+1e <call_test\+0x1e> call \[D,X\] 1e: R_M68HC12_RL_JUMP \*ABS\* -0+20 <call_test\+0x20> ldab \[32767,SP\] -0+24 <call_test\+0x24> call \[2048,SP\] +0+20 <call_test\+0x20> ldab \[0x7fff,SP\] +0+24 <call_test\+0x24> call \[0x800,SP\] 24: R_M68HC12_RL_JUMP \*ABS\* -0+28 <call_test\+0x28> call \[0,X\] +0+28 <call_test\+0x28> call \[0x0,X\] 28: R_M68HC12_RL_JUMP \*ABS\* 2a: R_M68HC12_16 _foo 0+2c <call_test\+0x2c> rtc -0+2d <special_test> emacs 0+ <call_test> +0+2d <special_test> emacs 0x0+ <call_test> 2f: R_M68HC12_16 _foo -0+31 <special_test\+0x4> maxa 0,X -0+34 <special_test\+0x7> maxa 819,Y +0+31 <special_test\+0x4> maxa 0x0,X +0+34 <special_test\+0x7> maxa 0x333,Y 0+39 <special_test\+0xc> maxa \[D,X\] -0+3c <special_test\+0xf> maxa \[0,X\] +0+3c <special_test\+0xf> maxa \[0x0,X\] 3f: R_M68HC12_16 _foo -0+41 <special_test\+0x14> maxm 0,X -0+44 <special_test\+0x17> maxm 819,Y +0+41 <special_test\+0x14> maxm 0x0,X +0+44 <special_test\+0x17> maxm 0x333,Y 0+49 <special_test\+0x1c> maxm \[D,X\] -0+4c <special_test\+0x1f> maxm \[0,X\] +0+4c <special_test\+0x1f> maxm \[0x0,X\] 4f: R_M68HC12_16 _foo -0+51 <special_test\+0x24> emaxd 0,X -0+54 <special_test\+0x27> emaxd 819,Y +0+51 <special_test\+0x24> emaxd 0x0,X +0+54 <special_test\+0x27> emaxd 0x333,Y 0+59 <special_test\+0x2c> emaxd \[D,X\] -0+5c <special_test\+0x2f> emaxd \[0,X\] +0+5c <special_test\+0x2f> emaxd \[0x0,X\] 5f: R_M68HC12_16 _foo -0+61 <special_test\+0x34> emaxm 0,X -0+64 <special_test\+0x37> emaxm 819,Y +0+61 <special_test\+0x34> emaxm 0x0,X +0+64 <special_test\+0x37> emaxm 0x333,Y 0+69 <special_test\+0x3c> emaxm \[D,X\] -0+6c <special_test\+0x3f> emaxm \[0,X\] +0+6c <special_test\+0x3f> emaxm \[0x0,X\] 6f: R_M68HC12_16 _foo -0+71 <special_test\+0x44> mina 0,X -0+74 <special_test\+0x47> mina 819,Y +0+71 <special_test\+0x44> mina 0x0,X +0+74 <special_test\+0x47> mina 0x333,Y 0+79 <special_test\+0x4c> mina \[D,X\] -0+7c <special_test\+0x4f> mina \[0,X\] +0+7c <special_test\+0x4f> mina \[0x0,X\] 7f: R_M68HC12_16 _foo -0+81 <special_test\+0x54> minm 0,X -0+84 <special_test\+0x57> minm 819,Y +0+81 <special_test\+0x54> minm 0x0,X +0+84 <special_test\+0x57> minm 0x333,Y 0+89 <special_test\+0x5c> minm \[D,X\] -0+8c <special_test\+0x5f> minm \[0,X\] +0+8c <special_test\+0x5f> minm \[0x0,X\] 8f: R_M68HC12_16 _foo -0+91 <special_test\+0x64> emind 0,X -0+94 <special_test\+0x67> emind 819,Y +0+91 <special_test\+0x64> emind 0x0,X +0+94 <special_test\+0x67> emind 0x333,Y 0+99 <special_test\+0x6c> emind \[D,X\] -0+9c <special_test\+0x6f> emind \[0,X\] +0+9c <special_test\+0x6f> emind \[0x0,X\] 9f: R_M68HC12_16 _foo 0+a1 <special_test\+0x74> emul 0+a2 <special_test\+0x75> emuls -0+a4 <special_test\+0x77> etbl 3,X -0+a7 <special_test\+0x7a> etbl 4,PC \{0+ae <special_test\+0x81>\} +0+a4 <special_test\+0x77> etbl 0x3,X +0+a7 <special_test\+0x7a> etbl 0x4,PC \{0x0+ae <special_test\+0x81>\} 0+aa <special_test\+0x7d> rev 0+ac <special_test\+0x7f> revw 0+ae <special_test\+0x81> wav diff --git a/gas/testsuite/gas/m68hc11/insns9s12x.d b/gas/testsuite/gas/m68hc11/insns9s12x.d new file mode 100644 index 0000000..650015f --- /dev/null +++ b/gas/testsuite/gas/m68hc11/insns9s12x.d @@ -0,0 +1,82 @@ +#objdump: -d -mm9s12x --prefix-addresses --reloc +#as: -mm9s12x +#name: 9s12x specific instructions (insns9s12x) + +dump.o: file format elf32-m68hc12 + + +Disassembly of section .text: +0x00000000 addx #0x00005678 +0x00000004 addy 2,X\+ +0x00000007 aded 0x0,X +0x0000000a adex 2,-Y +0x0000000d adey \[D,X\] +0x00000010 andx #0x00009988 +0x00000014 andy 0x000055aa +0x00000018 aslw 0x00002004 +0x0000001c aslx +0x0000001e asly +0x00000020 asrw 0x3000,Y +0x00000025 asrx +0x00000027 asry +0x00000029 bitx \[0x3456,SP\] +0x0000002e bity \[D,SP\] +0x00000031 btas 0x00002345, #0x04 +0x00000036 clrw 0x2008,Y +0x0000003b clrx +0x0000003d clry +0x0000003f comw 0x0,X +0x00000042 comx +0x00000044 comy +0x00000046 cped #0x0000fdeb +0x0000004a cpes 0x0000fedc +0x0000004e cpex 0x2,SP +0x00000051 cpey 2,SP\+ +0x00000054 decw 0x0,X +0x00000057 decx +0x00000059 decy +0x0000005b eorx 0x00000034 +0x0000005f eory 0x00001234 +0x00000063 gldaa 0x00005678 +0x00000067 gldab 0x0,X +0x0000006a gldd 2,Y\+ +0x0000006d glds 0x0,Y +0x00000070 gldx \[D,Y\] +0x00000073 gldy \[D,X\] +0x00000076 gstaa 0x00005001 +0x0000007a gstab 0x00005189 +0x0000007e gstd 0x5000,X +0x00000083 gsts 0x00007008 +0x00000087 gstx 0x6001,Y +0x0000008c gsty \[D,X\] +0x0000008f incw \[0x100,SP\] +0x00000094 incx +0x00000096 incy +0x00000098 aslw 0x00003005 +0x0000009c aslx +0x0000009e asly +0x000000a0 lsrw 0x00003890 +0x000000a4 lsrx +0x000000a6 lsry +0x000000a8 negw 2,-Y +0x000000ab negx +0x000000ad negy +0x000000af orx #0x00009876 +0x000000b3 ory 0x00009876 +0x000000b7 pshcw +0x000000b9 pulcw +0x000000bb rolw 0x00005544 +0x000000bf rolx +0x000000c1 roly +0x000000c3 rorw 0x0,X +0x000000c6 rorx +0x000000c8 rory +0x000000ca sbed 0x2,Y +0x000000cd sbex 0x00003458 +0x000000d1 sbey 0x00008543 +0x000000d5 subx \[D,Y\] +0x000000d8 suby \[D,X\] +0x000000db sys +0x000000dd tstw 0x3,X +0x000000e0 tstx +0x000000e2 tsty diff --git a/gas/testsuite/gas/m68hc11/insns9s12x.s b/gas/testsuite/gas/m68hc11/insns9s12x.s new file mode 100644 index 0000000..74af484 --- /dev/null +++ b/gas/testsuite/gas/m68hc11/insns9s12x.s @@ -0,0 +1,83 @@ +# Test for correct generation of 9s12x specific insns. + + .sect .text + + addx #0x5678 + addy 2,x+ + aded 0,x + adex 2,-y + adey [d,x] + andx #0x9988 + andy 0x55aa + aslw 0x2004 + aslx + asly + asrw 0x3000,y + asrx + asry + bitx [0x3456,sp] + bity [d,sp] + btas 0x2345, #0x04 + clrw 0x2008,y + clrx + clry + comw 0,x + comx + comy + cped #0xfdeb + cpes 0xfedc + cpex 2,sp + cpey 2,sp+ + decw 0,x + decx + decy + eorx 0x34 + eory 0x1234 +; exg in own test + gldaa 0x5678 + gldab 0,x + gldd 2,y+ + glds 0,y + gldx [d,y] + gldy [d,x] + gstaa 0x5001 + gstab 0x5189 + gstd 0x5000,x + gsts 0x7008 + gstx 0x6001,y + gsty [d,x] + incw [0x100,sp] + incx + incy + lslw 0x3005 + lslx + lsly + lsrw 0x3890 + lsrx + lsry +; mov in own test + negw 2,-y + negx + negy + orx #0x9876 + ory 0x9876 + pshcw + pulcw + rolw 0x5544 + rolx + roly + rorw 0,x + rorx + rory + sbed 2,y + sbex 0x3458 + sbey 0x8543 +;sex with exg + subx [d,y] + suby [d,x] + sys +;tfr with exg + tstw 3,x + tstx + tsty + diff --git a/gas/testsuite/gas/m68hc11/insns9s12xg.d b/gas/testsuite/gas/m68hc11/insns9s12xg.d new file mode 100644 index 0000000..7b41620 --- /dev/null +++ b/gas/testsuite/gas/m68hc11/insns9s12xg.d @@ -0,0 +1,120 @@ +#objdump: -d -mm9s12xg --prefix-addresses --reloc +#as: -mm9s12xg +#name: XGATE instruction set and all modes + +dump.o: file format elf32-m68hc12 + + +Disassembly of section .text: +00000000 <label1> adc R1, R2, R3 +00000002 <label2> add R4, R6, R1 +00000004 <label3> addl R7, #0x34 +00000006 <label3\+0x2> addh R7, #0x12 +00000008 <label3\+0x4> addl R4, #0xa5 +0000000a <label3\+0x6> addh R4, #0x32 +0000000c <label3\+0x8> and R7, R6, R5 +0000000e <label3\+0xa> andl R2, #0x32 +00000010 <label3\+0xc> andh R2, #0x54 +00000012 <label3\+0xe> andl R1, #0xa5 +00000014 <label3\+0x10> andh R1, #0x32 +00000016 <label3\+0x12> asr R2, #0x3 +00000018 <label3\+0x14> asr R3, R4 +0000001a <label3\+0x16> bcc 0x00000000 <label1> +0000001c <label3\+0x18> bcs 0x00000002 <label2> +0000001e <label3\+0x1a> beq 0x00000004 <label3> +00000020 <label3\+0x1c> bfext R1, R2, R3 +00000022 <label3\+0x1e> bffo R4, R5 +00000024 <label3\+0x20> bfins R6, R7, R1 +00000026 <label3\+0x22> bfinsi R2, R4, R6 +00000028 <label3\+0x24> bfinsx R3, R5, R7 +0000002a <label3\+0x26> bge 0x00000000 <label1> +0000002c <label3\+0x28> bgt 0x00000002 <label2> +0000002e <label3\+0x2a> bhi 0x00000004 <label3> +00000030 <label3\+0x2c> bcc 0x00000000 <label1> +00000032 <label3\+0x2e> bith R2, #0x55 +00000034 <label3\+0x30> bitl R3, #0xaa +00000036 <label3\+0x32> ble 0x00000002 <label2> +00000038 <label3\+0x34> bcs 0x00000004 <label3> +0000003a <label3\+0x36> bls 0x00000000 <label1> +0000003c <label3\+0x38> blt 0x00000002 <label2> +0000003e <label3\+0x3a> bmi 0x00000004 <label3> +00000040 <label3\+0x3c> bne 0x00000000 <label1> +00000042 <label3\+0x3e> bpl 0x00000002 <label2> +00000044 <label3\+0x40> bra 0x00000004 <label3> +00000046 <label3\+0x42> brk +00000048 <label3\+0x44> bvc 0x00000000 <label1> +0000004a <label3\+0x46> bvs 0x00000002 <label2> +0000004c <label3\+0x48> sub R0, R1, R2 +0000004e <label3\+0x4a> cmpl R3, #0x34 +00000050 <label3\+0x4c> cpch R3, #0x12 +00000052 <label3\+0x4e> cmpl R4, #0x32 +00000054 <label3\+0x50> xnor R4, R0, R5 +00000056 <label3\+0x52> xnor R6, R0, R6 +00000058 <label3\+0x54> sbc R0, R7, R5 +0000005a <label3\+0x56> cpch R6, #0xa5 +0000005c <label3\+0x58> csem #0x2 +0000005e <label3\+0x5a> csem R1 +00000060 <label3\+0x5c> csl R2, #0x1 +00000062 <label3\+0x5e> csl R3, R4 +00000064 <label3\+0x60> csr R5, #0x4 +00000066 <label3\+0x62> csr R6, R7 +00000068 <label3\+0x64> jal R1 +0000006a <label3\+0x66> ldb R2, \(R3, #0x4\) +0000006c <label3\+0x68> ldb R3, \(R0, R2\) +0000006e <label3\+0x6a> ldb R4, \(R5, R6\+\) +00000070 <label3\+0x6c> ldb R5, \(R6, -R7\) +00000072 <label3\+0x6e> ldh R6, #0x35 +00000074 <label3\+0x70> ldl R7, #0x46 +00000076 <label3\+0x72> ldw R1, \(R2, #0x1d\) +00000078 <label3\+0x74> ldw R2, \(R3, R0\) +0000007a <label3\+0x76> ldw R3, \(R4, R5\+\) +0000007c <label3\+0x78> ldw R4, \(R5, -R6\) +0000007e <label3\+0x7a> ldl R6, #0x34 +00000080 <label3\+0x7c> ldh R6, #0x12 +00000082 <label3\+0x7e> lsl R7, #0x2 +00000084 <label3\+0x80> lsl R2, R1 +00000086 <label3\+0x82> lsr R5, #0x3 +00000088 <label3\+0x84> lsl R6, R3 +0000008a <label3\+0x86> or R7, R0, R6 +0000008c <label3\+0x88> sub R2, R0, R3 +0000008e <label3\+0x8a> sub R4, R0, R4 +00000090 <label3\+0x8c> nop +00000092 <label3\+0x8e> or R2, R3, R4 +00000094 <label3\+0x90> orl R5, #0x56 +00000096 <label3\+0x92> orh R5, #0x12 +00000098 <label3\+0x94> orh R6, #0x08 +0000009a <label3\+0x96> orl R4, #0xf0 +0000009c <label3\+0x98> par R1 +0000009e <label3\+0x9a> rol R2, #0x5 +000000a0 <label3\+0x9c> rol R3, R4 +000000a2 <label3\+0x9e> ror R3, #0x6 +000000a4 <label3\+0xa0> ror R5, R4 +000000a6 <label3\+0xa2> rts +000000a8 <label3\+0xa4> sbc R7, R1, R2 +000000aa <label3\+0xa6> sex R1 +000000ac <label3\+0xa8> sif +000000ae <label3\+0xaa> sif R2 +000000b0 <label3\+0xac> ssem #0x5 +000000b2 <label3\+0xae> ssem R3 +000000b4 <label3\+0xb0> stb R2, \(R4, #0xf\) +000000b6 <label3\+0xb2> stb R3, \(R5, R6\) +000000b8 <label3\+0xb4> stb R0, \(R7, R1\+\) +000000ba <label3\+0xb6> stb R1, \(R2, -R3\) +000000bc <label3\+0xb8> stw R7, \(R6, #0x1e\) +000000be <label3\+0xba> stw R6, \(R5, R0\) +000000c0 <label3\+0xbc> stw R5, \(R4, R3\+\) +000000c2 <label3\+0xbe> stw R4, \(R3, -R2\) +000000c4 <label3\+0xc0> sub R7, R6, R5 +000000c6 <label3\+0xc2> subl R4, #0x34 +000000c8 <label3\+0xc4> subh R4, #0x12 +000000ca <label3\+0xc6> subh R5, #0x44 +000000cc <label3\+0xc8> subl R4, #0x55 +000000ce <label3\+0xca> tfr R2, CCR +000000d0 <label3\+0xcc> tfr CCR, R3 +000000d2 <label3\+0xce> tfr R5, PC +000000d4 <label3\+0xd0> sub R0, R2, R0 +000000d6 <label3\+0xd2> xnor R4, R6, R2 +000000d8 <label3\+0xd4> xnorl R3, #0x32 +000000da <label3\+0xd6> xnorh R3, #0x54 +000000dc <label3\+0xd8> xnorh R2, #0x32 +000000de <label3\+0xda> xnorl R1, #0x54 diff --git a/gas/testsuite/gas/m68hc11/insns9s12xg.s b/gas/testsuite/gas/m68hc11/insns9s12xg.s new file mode 100644 index 0000000..fc4c0cd --- /dev/null +++ b/gas/testsuite/gas/m68hc11/insns9s12xg.s @@ -0,0 +1,118 @@ +# XGATE instruction set and all modes + + .sect .text + +val1 = 0x1234 +val2 = 0x5432 +u08_1 = 0x32 +u08_2 = 0xa5 + +label1: + adc r1,r2,r3 +label2: + add r4,r6,r1 +label3: + add r7,#val1 ;splits out to addh, addl + addl r4,#u08_2 + addh r4,#u08_1 + and r7,r6,r5 + and r2,#val2 + andl r1, #u08_2 + andh r1, #u08_1 + asr r2,#3 + asr r3,r4 + bcc label1 + bcs label2 + beq label3 + bfext r1,r2,r3 + bffo r4,r5 + bfins r6,r7,r1 + bfinsi r2,r4,r6 + bfinsx r3,r5,r7 + bge label1 + bgt label2 + bhi label3 + bhs label1 + bith r2,#0x55 + bitl r3,#0xaa + ble label2 + blo label3 + bls label1 + blt label2 + bmi label3 + bne label1 + bpl label2 + bra label3 + brk + bvc label1 + bvs label2 + cmp r1,r2 + cmp r3,#val1 + cmpl r4,#u08_1 + com r4,r5 + com r6 + cpc r7,r5 + cpch r6,#u08_2 + csem #2 + csem r1 + csl r2,#1 + csl r3,r4 + csr r5,#4 + csr r6,r7 + jal r1 + ldb r2,(r3,#4) + ldb r3,(r0,r2) + ldb r4,(r5,r6+) + ldb r5,(r6,-r7) + ldh r6,#0x35 + ldl r7,#0x46 + ldw r1,(r2,#29) + ldw r2,(r3,r0) + ldw r3,(r4,r5+) + ldw r4,(r5,-r6) + ldw r6,#0x1234 + lsl r7,#2 + lsl r2,r1 + lsr r5,#3 + lsl r6,r3 + mov r7,r6 + neg r2,r3 + neg r4 + nop + or r2,r3,r4 + or r5,#0x1256 + orh r6,#0x08 + orl r4,#0xf0 + par r1 ; comma on datasheet a typo? + rol r2,#5 + rol r3,r4 + ror r3,#6 + ror r5,r4 + rts + sbc r7,r1,r2 + sex r1 + sif + sif r2 + ssem #5 + ssem r3 + stb r2,(r4,#15) + stb r3,(r5,r6) + stb r0,(r7,r1+) + stb r1,(r2,-r3) + stw r7,(r6,#30) + stw r6,(r5,r0) + stw r5,(r4,r3+) + stw r4,(r3,-r2) + sub r7,r6,r5 + sub r4,#val1 + subh r5,#0x44 + subl r4,#0x55 + tfr r2,ccr + tfr ccr,r3 + tfr r5,pc + tst r2 + xnor r4,r6,r2 + xnor r3,#val2 + xnorh r2,#0x32 + xnorl r1,#0x54 + diff --git a/gas/testsuite/gas/m68hc11/lbranch-dwarf2.d b/gas/testsuite/gas/m68hc11/lbranch-dwarf2.d index 14798e9..6aaeae6 100644 --- a/gas/testsuite/gas/m68hc11/lbranch-dwarf2.d +++ b/gas/testsuite/gas/m68hc11/lbranch-dwarf2.d @@ -16,67 +16,67 @@ Disassembly of section .text: _start: _rcall: ldaa #0x10 ;86 10 - 0: 86 10 ldaa #16 + 0: 86 10 ldaa #0x10 jbra Lend ; Must be switched to a jmp - 2: 7e 00 00 jmp 0 <_rcall> + 2: 7e 00 00 jmp 0x0 <_rcall> jbsr toto ; -> to a jsr - 5: bd 00 00 jsr 0 <_rcall> + 5: bd 00 00 jsr 0x0 <_rcall> jbne toto ; -> to a beq\+jmp - 8: 27 03 beq d <_rcall\+0xd> - a: 7e 00 00 jmp 0 <_rcall> + 8: 27 03 beq 0xd <_rcall\+0xd> + a: 7e 00 00 jmp 0x0 <_rcall> jbeq toto ; -> to a bne\+jmp - d: 26 03 bne 12 <_rcall\+0x12> - f: 7e 00 00 jmp 0 <_rcall> + d: 26 03 bne 0x12 <_rcall\+0x12> + f: 7e 00 00 jmp 0x0 <_rcall> jbcs toto ; -> to a bcc\+jmp - 12: 24 03 bcc 17 <_rcall\+0x17> - 14: 7e 00 00 jmp 0 <_rcall> + 12: 24 03 bcc 0x17 <_rcall\+0x17> + 14: 7e 00 00 jmp 0x0 <_rcall> jbcc toto ; -> to a bcs\+jmp - 17: 25 03 bcs 1c <_rcall\+0x1c> - 19: 7e 00 00 jmp 0 <_rcall> + 17: 25 03 bcs 0x1c <_rcall\+0x1c> + 19: 7e 00 00 jmp 0x0 <_rcall> xgdx 1c: 8f xgdx xgdx 1d: 8f xgdx beq bidule ; -> to a bne\+jmp - 1e: 26 03 bne 23 <_rcall\+0x23> - 20: 7e 00 00 jmp 0 <_rcall> + 1e: 26 03 bne 0x23 <_rcall\+0x23> + 20: 7e 00 00 jmp 0x0 <_rcall> bcs bidule ; -> to a bcc\+jmp - 23: 24 03 bcc 28 <_rcall\+0x28> - 25: 7e 00 00 jmp 0 <_rcall> + 23: 24 03 bcc 0x28 <_rcall\+0x28> + 25: 7e 00 00 jmp 0x0 <_rcall> bcc bidule ; -> to a bcs\+jmp - 28: 25 03 bcs 2d <_rcall\+0x2d> - 2a: 7e 00 00 jmp 0 <_rcall> + 28: 25 03 bcs 0x2d <_rcall\+0x2d> + 2a: 7e 00 00 jmp 0x0 <_rcall> xgdx 2d: 8f xgdx jbra 200 - 2e: 7e 00 c8 jmp c8 <_rcall\+0xc8> + 2e: 7e 00 c8 jmp 0xc8 <_rcall\+0xc8> jbsr 1923 - 31: bd 07 83 jsr 783 <L0\+0x602> + 31: bd 07 83 jsr 0x783 <L0\+0x602> bne Lend ; -> to a beq\+jmp - 34: 27 03 beq 39 <_rcall\+0x39> - 36: 7e 00 00 jmp 0 <_rcall> + 34: 27 03 beq 0x39 <_rcall\+0x39> + 36: 7e 00 00 jmp 0x0 <_rcall> jbsr toto - 39: bd 00 00 jsr 0 <_rcall> + 39: bd 00 00 jsr 0x0 <_rcall> jbeq toto - 3c: 26 03 bne 41 <_rcall\+0x41> - 3e: 7e 00 00 jmp 0 <_rcall> + 3c: 26 03 bne 0x41 <_rcall\+0x41> + 3e: 7e 00 00 jmp 0x0 <_rcall> ... .skip 200 ldaa \*dir ;96 33 - 109: 96 00 ldaa \*0 <_rcall> + 109: 96 00 ldaa \*0x0 <_rcall> 0000010b <Lend>: Lend: bhi external_op - 10b: 23 03 bls 110 <Lend\+0x5> - 10d: 7e 00 00 jmp 0 <_rcall> + 10b: 23 03 bls 0x110 <Lend\+0x5> + 10d: 7e 00 00 jmp 0x0 <_rcall> bls external_op - 110: 22 03 bhi 115 <Lend\+0xa> - 112: 7e 00 00 jmp 0 <_rcall> + 110: 22 03 bhi 0x115 <Lend\+0xa> + 112: 7e 00 00 jmp 0x0 <_rcall> bsr out - 115: bd 00 00 jsr 0 <_rcall> + 115: bd 00 00 jsr 0x0 <_rcall> ldx #12 - 118: ce 00 0c ldx #c <_rcall\+0xc> + 118: ce 00 0c ldx #0xc <_rcall\+0xc> 0000011b <toto>: toto: diff --git a/gas/testsuite/gas/m68hc11/lbranch.d b/gas/testsuite/gas/m68hc11/lbranch.d index 4770a4a..07a559d 100644 --- a/gas/testsuite/gas/m68hc11/lbranch.d +++ b/gas/testsuite/gas/m68hc11/lbranch.d @@ -7,74 +7,74 @@ .*: +file format elf32\-m68hc11 Disassembly of section .text: -0+0+ <_rcall> ldaa #16 -0+0002 <_rcall\+0x2> jmp 0+0+ <_rcall> +0+0+ <_rcall> ldaa #0x10 +0+0002 <_rcall\+0x2> jmp 0x0+0+ <_rcall> [ ]+2: R_M68HC11_RL_JUMP \*ABS\* [ ]+3: R_M68HC11_16 Lend -0+0005 <_rcall\+0x5> jsr 0+0+ <_rcall> +0+0005 <_rcall\+0x5> jsr 0x0+0+ <_rcall> [ ]+5: R_M68HC11_RL_JUMP \*ABS\* [ ]+6: R_M68HC11_16 toto -0+0008 <_rcall\+0x8> beq 0+000d <_rcall\+0xd> +0+0008 <_rcall\+0x8> beq 0x0+000d <_rcall\+0xd> [ ]+8: R_M68HC11_RL_JUMP \*ABS\* -0+000a <_rcall\+0xa> jmp 0+0+ <_rcall> +0+000a <_rcall\+0xa> jmp 0x0+0+ <_rcall> [ ]+b: R_M68HC11_16 toto -0+000d <_rcall\+0xd> bne 0+0012 <_rcall\+0x12> +0+000d <_rcall\+0xd> bne 0x0+0012 <_rcall\+0x12> [ ]+d: R_M68HC11_RL_JUMP \*ABS\* -0+000f <_rcall\+0xf> jmp 0+0+ <_rcall> +0+000f <_rcall\+0xf> jmp 0x0+0+ <_rcall> [ ]+10: R_M68HC11_16 toto -0+0012 <_rcall\+0x12> bcc 0+0017 <_rcall\+0x17> +0+0012 <_rcall\+0x12> bcc 0x0+0017 <_rcall\+0x17> [ ]+12: R_M68HC11_RL_JUMP \*ABS\* -0+0014 <_rcall\+0x14> jmp 0+0+ <_rcall> +0+0014 <_rcall\+0x14> jmp 0x0+0+ <_rcall> [ ]+15: R_M68HC11_16 toto -0+0017 <_rcall\+0x17> bcs 0+001c <_rcall\+0x1c> +0+0017 <_rcall\+0x17> bcs 0x0+001c <_rcall\+0x1c> [ ]+17: R_M68HC11_RL_JUMP \*ABS\* -0+0019 <_rcall\+0x19> jmp 0+0+ <_rcall> +0+0019 <_rcall\+0x19> jmp 0x0+0+ <_rcall> [ ]+1a: R_M68HC11_16 toto 0+001c <_rcall\+0x1c> xgdx 0+001d <_rcall\+0x1d> xgdx -0+001e <_rcall\+0x1e> bne 0+0023 <_rcall\+0x23> +0+001e <_rcall\+0x1e> bne 0x0+0023 <_rcall\+0x23> [ ]+1e: R_M68HC11_RL_JUMP \*ABS\* -0+0020 <_rcall\+0x20> jmp 0+0+ <_rcall> +0+0020 <_rcall\+0x20> jmp 0x0+0+ <_rcall> [ ]+21: R_M68HC11_16 bidule -0+0023 <_rcall\+0x23> bcc 0+0028 <_rcall\+0x28> +0+0023 <_rcall\+0x23> bcc 0x0+0028 <_rcall\+0x28> [ ]+23: R_M68HC11_RL_JUMP \*ABS\* -0+0025 <_rcall\+0x25> jmp 0+0+ <_rcall> +0+0025 <_rcall\+0x25> jmp 0x0+0+ <_rcall> [ ]+26: R_M68HC11_16 bidule -0+0028 <_rcall\+0x28> bcs 0+002d <_rcall\+0x2d> +0+0028 <_rcall\+0x28> bcs 0x0+002d <_rcall\+0x2d> [ ]+28: R_M68HC11_RL_JUMP \*ABS\* -0+002a <_rcall\+0x2a> jmp 0+0+ <_rcall> +0+002a <_rcall\+0x2a> jmp 0x0+0+ <_rcall> [ ]+2b: R_M68HC11_16 bidule 0+002d <_rcall\+0x2d> xgdx -0+002e <_rcall\+0x2e> jmp 0+00c8 <_rcall\+0xc8> +0+002e <_rcall\+0x2e> jmp 0x0+00c8 <_rcall\+0xc8> [ ]+2e: R_M68HC11_RL_JUMP \*ABS\* -0+0031 <_rcall\+0x31> jsr 0+0783 <bidule\+0x603> +0+0031 <_rcall\+0x31> jsr 0x0+0783 <bidule\+0x603> [ ]+31: R_M68HC11_RL_JUMP \*ABS\* -0+0034 <_rcall\+0x34> beq 0+0039 <_rcall\+0x39> +0+0034 <_rcall\+0x34> beq 0x0+0039 <_rcall\+0x39> [ ]+34: R_M68HC11_RL_JUMP \*ABS\* -0+0036 <_rcall\+0x36> jmp 0+0+ <_rcall> +0+0036 <_rcall\+0x36> jmp 0x0+0+ <_rcall> [ ]+37: R_M68HC11_16 Lend -0+0039 <_rcall\+0x39> jsr 0+0+ <_rcall> +0+0039 <_rcall\+0x39> jsr 0x0+0+ <_rcall> [ ]+39: R_M68HC11_RL_JUMP \*ABS\* [ ]+3a: R_M68HC11_16 toto -0+003c <_rcall\+0x3c> bne 0+0041 <_rcall\+0x41> +0+003c <_rcall\+0x3c> bne 0x0+0041 <_rcall\+0x41> [ ]+3c: R_M68HC11_RL_JUMP \*ABS\* -0+003e <_rcall\+0x3e> jmp 0+0+ <_rcall> +0+003e <_rcall\+0x3e> jmp 0x0+0+ <_rcall> [ ]+3f: R_M68HC11_16 toto ... -0+0109 <_rcall\+0x109> ldaa \*0+0+ <_rcall> +0+0109 <_rcall\+0x109> ldaa \*0x0+0+ <_rcall> [ ]+10a: R_M68HC11_8 .page0 -0+010b <Lend> bls 0+0110 <Lend\+0x5> +0+010b <Lend> bls 0x0+0110 <Lend\+0x5> [ ]+10b: R_M68HC11_RL_JUMP \*ABS\* -0+010d <Lend\+0x2> jmp 0+0+ <_rcall> +0+010d <Lend\+0x2> jmp 0x0+0+ <_rcall> [ ]+10e: R_M68HC11_16 external_op -0+0110 <Lend\+0x5> bhi 0+0115 <Lend\+0xa> +0+0110 <Lend\+0x5> bhi 0x0+0115 <Lend\+0xa> [ ]+110: R_M68HC11_RL_JUMP \*ABS\* -0+0112 <Lend\+0x7> jmp 0+0+ <_rcall> +0+0112 <Lend\+0x7> jmp 0x0+0+ <_rcall> [ ]+113: R_M68HC11_16 external_op -0+0115 <Lend\+0xa> jsr 0+0+ <_rcall> +0+0115 <Lend\+0xa> jsr 0x0+0+ <_rcall> [ ]+115: R_M68HC11_RL_JUMP \*ABS\* [ ]+116: R_M68HC11_16 out -0+0118 <Lend\+0xd> ldx #0+000c <_rcall\+0xc> +0+0118 <Lend\+0xd> ldx #0x0+000c <_rcall\+0xc> 0+011b <toto> rts ... 0+0180 <bidule> rts diff --git a/gas/testsuite/gas/m68hc11/m68hc11.exp b/gas/testsuite/gas/m68hc11/m68hc11.exp index 84dc83d..a4f908b 100644 --- a/gas/testsuite/gas/m68hc11/m68hc11.exp +++ b/gas/testsuite/gas/m68hc11/m68hc11.exp @@ -29,6 +29,8 @@ proc gas_m68hc11_opcode_list { flags expect_count } { gas_m68hc11_opcode_list "-m68hc11" 149 gas_m68hc11_opcode_list "-m68hc12" 192 gas_m68hc11_opcode_list "-m68hcs12" 192 +gas_m68hc11_opcode_list "-mm9s12x" 266 +gas_m68hc11_opcode_list "-mm9s12xg" 74 # Test for a message produced when assembling a file @@ -97,6 +99,9 @@ gas_m68hc11_error "--short-branchs" "bne 200\n" \ gas_m68hc11_error "" "bar\n" "Opcode .bar. is not recognized." gas_m68hc11_error "--print-insn-syntax" "bne\n" \ "Instruction formats for .bne..*" +#Check that 9s12x opcodes are rejected +gas_m68hc11_error "-m68hc11" "subx\n" "Opcode .subx. is not recognized" +gas_m68hc11_error "-m68hc11" "roly\n" "Opcode .roly. is not recognized" # ------------------ # 68HC12 error tests @@ -148,14 +153,28 @@ gas_m68hc11_error "-m68hc12" "movb 2,x,bar,pc\nbar=300\n" \ "Offset out of 5-bit range for movw/movb insn: 300" gas_m68hc11_error "-m68hc12" "movb bar,pc,2,x\nbar=300\n" \ "Offset out of 5-bit range for movw/movb insn: 300" +#check the 9s12x opcodes not supported +gas_m68hc11_error "-m68hc12" "subx\n" "Opcode .subx. is not recognized" +gas_m68hc11_error "-m68hc12" "roly\n" "Opcode .roly. is not recognized" +gas_m68hc11_error "-m68hc12" "sex d,x\n" \ + "Invalid source register for this instruction, use .tfr." +gas_m68hc11_error "-m68hc12" "sex d,y\n" \ + "Invalid source register for this instruction, use .tfr." + +#m9s12x tests +gas_m68hc11_error "-mm9s12x" "par r3\n" "Opcode .par. is not recognized" +gas_m68hc11_error "-mm9s12x" "csem #1\n" "Opcode .csem. is not recognized" + +#m9s12xg tests +gas_m68hc11_error "-mm9s12xg" "roly\n" "Opcode .roly. is not recognized" +gas_m68hc11_error "-mm9s12xg" "ldab #1\n" "Opcode .ldab. is not recognized" # ------------------ # Specific commands -gas_m68hc11_warning "" ".mode \"bar\"\n" "Invalid mode: .bar." -gas_m68hc11_error "" ".relax 23\n" "bad .relax format" -gas_m68hc11_error "" ".relax bar-23\n" "bad .relax format" -gas_m68hc11_error "" ".far bar bar\n" "junk at end of line" - +gas_m68hc11_warning "-m68hc11" ".mode \"bar\"\n" "Invalid mode: .bar." +gas_m68hc11_error "-m68hc11" ".relax 23\n" "bad .relax format" +gas_m68hc11_error "-m68hc11" ".relax bar-23\n" "bad .relax format" +gas_m68hc11_error "-m68hc11" ".far bar bar\n" "junk at end of line" run_dump_test insns run_dump_test lbranch @@ -177,3 +196,15 @@ run_dump_test insns12 run_dump_test indexed12 run_dump_test bug-1825 run_dump_test movb + +# Some m9s12x tests +run_dump_test insns9s12x +run_dump_test 9s12x-exg-sex-tfr +run_dump_test 9s12x-mov + +# Some m9s12xg tests +run_dump_test insns9s12xg + +# Confirm hex prefixes +run_dump_test hexprefix + diff --git a/gas/testsuite/gas/m68hc11/malis.d b/gas/testsuite/gas/m68hc11/malis.d index 8f5ad40..7a4c852 100644 --- a/gas/testsuite/gas/m68hc11/malis.d +++ b/gas/testsuite/gas/m68hc11/malis.d @@ -7,31 +7,31 @@ .*: +file format elf32\-m68hc11 Disassembly of section .text: -0+000 <L0> ldaa 1,x -0+002 <L1> ldaa #44 -0+004 <L_txt2> ldx #0+000 <L0> -0+007 <L_constant> ldaa #123 -0+009 <L_constant\+0x2> ldaa #233 -0+00b <L_constant\+0x4> ldab #138 -0+00d <L_constant\+0x6> ldab #7 -0+00f <L_constant\+0x8> ldaa #60 -0+011 <L_constant\+0xa> ldaa #255 -0+013 <L12> ldaa #174 -0+015 <L13> ldaa #178 -0+017 <L11> ldx #0+0af <entry\+0x6c> -0+01a <L11\+0x3> ldx #0+001 <L0\+0x1> -0+01d <L11\+0x6> ldx #0+001 <L0\+0x1> -0+020 <L11\+0x9> ldx #0+000 <L0> -0+023 <L11\+0xc> ldab #210 -0+025 <L_if> ldx #0+001 <L0\+0x1> -0+028 <L_if\+0x3> ldaa #31 -0+02a <L_if\+0x5> ldaa #4 -0+02c <L_if\+0x7> ldx #0+017 <L11> -0+02f <L_if\+0xa> ldx #0+004 <L_txt2> -0+032 <L_if\+0xd> ldy #0+001 <L0\+0x1> -0+036 <L_if\+0x11> ldy #0+001 <L0\+0x1> -0+03a <L_if\+0x15> ldaa #23 -0+03c <L_if\+0x17> staa 0+018 <L11\+0x1> +0+000 <L0> ldaa 0x1,x +0+002 <L1> ldaa #0x2c +0+004 <L_txt2> ldx #0x0+000 <L0> +0+007 <L_constant> ldaa #0x7b +0+009 <L_constant\+0x2> ldaa #0xe9 +0+00b <L_constant\+0x4> ldab #0x8a +0+00d <L_constant\+0x6> ldab #0x7 +0+00f <L_constant\+0x8> ldaa #0x3c +0+011 <L_constant\+0xa> ldaa #0xff +0+013 <L12> ldaa #0xae +0+015 <L13> ldaa #0xb2 +0+017 <L11> ldx #0x0+0af <entry\+0x6c> +0+01a <L11\+0x3> ldx #0x0+001 <L0\+0x1> +0+01d <L11\+0x6> ldx #0x0+001 <L0\+0x1> +0+020 <L11\+0x9> ldx #0x0+000 <L0> +0+023 <L11\+0xc> ldab #0xd2 +0+025 <L_if> ldx #0x0+001 <L0\+0x1> +0+028 <L_if\+0x3> ldaa #0x1f +0+02a <L_if\+0x5> ldaa #0x4 +0+02c <L_if\+0x7> ldx #0x0+017 <L11> +0+02f <L_if\+0xa> ldx #0x0+004 <L_txt2> +0+032 <L_if\+0xd> ldy #0x0+001 <L0\+0x1> +0+036 <L_if\+0x11> ldy #0x0+001 <L0\+0x1> +0+03a <L_if\+0x15> ldaa #0x17 +0+03c <L_if\+0x17> staa 0x0+018 <L11\+0x1> 0+03f <L_if\+0x1a> rts -0+040 <L_if\+0x1b> ldaa 0+017 <L11> +0+040 <L_if\+0x1b> ldaa 0x0+017 <L11> 0+043 <entry> rts diff --git a/gas/testsuite/gas/m68hc11/movb.d b/gas/testsuite/gas/m68hc11/movb.d index 4ef5e81..b3501ef 100644 --- a/gas/testsuite/gas/m68hc11/movb.d +++ b/gas/testsuite/gas/m68hc11/movb.d @@ -7,445 +7,445 @@ Disassembly of section .text: 0+00 <\.text>: -[ ]+ 0: 86 00[ ]+ ldaa #0 -[ ]+ 2: 18 0a 0f 0f movb 15,X, 15,X -[ ]+ 6: 18 0a 0f 0f movb 15,X, 15,X -[ ]+ a: 18 0a 0f 0f movb 15,X, 15,X -[ ]+ e: 86 01[ ]+ ldaa #1 -[ ]+10: 18 0a 0f 0f movb 15,X, 15,X -[ ]+14: 18 0a 0f 0f movb 15,X, 15,X -[ ]+18: 18 0a 0f 0f movb 15,X, 15,X -[ ]+1c: 86 02[ ]+ ldaa #2 -[ ]+1e: 18 0a 0f 10 movb 15,X, \-16,X -[ ]+22: 18 0a 0f 10 movb 15,X, \-16,X -[ ]+26: 18 0a 0f 10 movb 15,X, \-16,X -[ ]+2a: 86 03[ ]+ ldaa #3 -[ ]+2c: 18 0a 10 0f movb \-16,X, 15,X -[ ]+30: 18 0a 10 0f movb \-16,X, 15,X -[ ]+34: 18 0a 10 0f movb \-16,X, 15,X -[ ]+38: 86 04[ ]+ ldaa #4 -[ ]+3a: 18 02 0f 0f movw 15,X, 15,X -[ ]+3e: 18 02 0f 0f movw 15,X, 15,X -[ ]+42: 18 02 0f 0f movw 15,X, 15,X -[ ]+46: 86 05[ ]+ ldaa #5 -[ ]+48: 18 02 0f 0f movw 15,X, 15,X -[ ]+4c: 18 02 0f 0f movw 15,X, 15,X -[ ]+50: 18 02 0f 0f movw 15,X, 15,X -[ ]+54: 86 06[ ]+ ldaa #6 -[ ]+56: 18 02 0f 10 movw 15,X, \-16,X -[ ]+5a: 18 02 0f 10 movw 15,X, \-16,X -[ ]+5e: 18 02 0f 10 movw 15,X, \-16,X -[ ]+62: 86 07[ ]+ ldaa #7 -[ ]+64: 18 02 10 0f movw \-16,X, 15,X -[ ]+68: 18 02 10 0f movw \-16,X, 15,X -[ ]+6c: 18 02 10 0f movw \-16,X, 15,X -[ ]+70: 86 08[ ]+ ldaa #8 -[ ]+72: 18 0a 4f 4f movb 15,Y, 15,Y -[ ]+76: 18 0a 4f 4f movb 15,Y, 15,Y -[ ]+7a: 18 0a 4f 4f movb 15,Y, 15,Y -[ ]+7e: 86 09[ ]+ ldaa #9 -[ ]+80: 18 0a 4f 4f movb 15,Y, 15,Y -[ ]+84: 18 0a 4f 4f movb 15,Y, 15,Y -[ ]+88: 18 0a 4f 4f movb 15,Y, 15,Y -[ ]+8c: 86 0a[ ]+ ldaa #10 -[ ]+8e: 18 0a 4f 50 movb 15,Y, \-16,Y -[ ]+92: 18 0a 4f 50 movb 15,Y, \-16,Y -[ ]+96: 18 0a 4f 50 movb 15,Y, \-16,Y -[ ]+9a: 86 0b[ ]+ ldaa #11 -[ ]+9c: 18 0a 50 4f movb \-16,Y, 15,Y -[ ]+a0: 18 0a 50 4f movb \-16,Y, 15,Y -[ ]+a4: 18 0a 50 4f movb \-16,Y, 15,Y -[ ]+a8: 86 0c[ ]+ ldaa #12 -[ ]+aa: 18 02 4f 4f movw 15,Y, 15,Y -[ ]+ae: 18 02 4f 4f movw 15,Y, 15,Y -[ ]+b2: 18 02 4f 4f movw 15,Y, 15,Y -[ ]+b6: 86 0d[ ]+ ldaa #13 -[ ]+b8: 18 02 4f 4f movw 15,Y, 15,Y -[ ]+bc: 18 02 4f 4f movw 15,Y, 15,Y -[ ]+c0: 18 02 4f 4f movw 15,Y, 15,Y -[ ]+c4: 86 0e[ ]+ ldaa #14 -[ ]+c6: 18 02 4f 50 movw 15,Y, \-16,Y -[ ]+ca: 18 02 4f 50 movw 15,Y, \-16,Y -[ ]+ce: 18 02 4f 50 movw 15,Y, \-16,Y -[ ]+d2: 86 0f[ ]+ ldaa #15 -[ ]+d4: 18 02 50 4f movw \-16,Y, 15,Y -[ ]+d8: 18 02 50 4f movw \-16,Y, 15,Y -[ ]+dc: 18 02 50 4f movw \-16,Y, 15,Y -[ ]+e0: 86 10[ ]+ ldaa #16 -[ ]+e2: 18 0a 4f cf movb 15,Y, 15,PC \{f5 <cat2\+0xe6>\} -[ ]+e6: 18 0a 4f cf movb 15,Y, 15,PC \{f9 <cat2\+0xea>\} -[ ]+ea: 18 0a 4f cf movb 15,Y, 15,PC \{fd <cat2\+0xee>\} -[ ]+ee: 86 11[ ]+ ldaa #17 -[ ]+f0: 18 0a 4f cf movb 15,Y, 15,PC \{103 <cat2\+0xf4>\} -[ ]+f4: 18 0a 4f cf movb 15,Y, 15,PC \{107 <cat2\+0xf8>\} -[ ]+f8: 18 0a 4f cf movb 15,Y, 15,PC \{10b <cat2\+0xfc>\} -[ ]+fc: 86 12[ ]+ ldaa #18 -[ ]+fe: 18 0a 4f d0 movb 15,Y, \-16,PC \{f2 <cat2\+0xe3>\} - 102: 18 0a 4f d0 movb 15,Y, \-16,PC \{f6 <cat2\+0xe7>\} - 106: 18 0a 4f d0 movb 15,Y, \-16,PC \{fa <cat2\+0xeb>\} - 10a: 86 13[ ]+ ldaa #19 - 10c: 18 0a 50 cf movb \-16,Y, 15,PC \{11f <cat2\+0x110>\} - 110: 18 0a 50 cf movb \-16,Y, 15,PC \{123 <cat2\+0x114>\} - 114: 18 0a 50 cf movb \-16,Y, 15,PC \{127 <cat2\+0x118>\} - 118: 86 14[ ]+ ldaa #20 - 11a: 18 02 4f cf movw 15,Y, 15,PC \{12d <cat2\+0x11e>\} - 11e: 18 02 4f cf movw 15,Y, 15,PC \{131 <cat2\+0x122>\} - 122: 18 02 4f cf movw 15,Y, 15,PC \{135 <cat2\+0x126>\} - 126: 86 15[ ]+ ldaa #21 - 128: 18 02 4f cf movw 15,Y, 15,PC \{13b <cat2\+0x12c>\} - 12c: 18 02 4f cf movw 15,Y, 15,PC \{13f <cat2\+0x130>\} - 130: 18 02 4f cf movw 15,Y, 15,PC \{143 <cat2\+0x134>\} - 134: 86 16[ ]+ ldaa #22 - 136: 18 02 4f d0 movw 15,Y, \-16,PC \{12a <cat2\+0x11b>\} - 13a: 18 02 4f d0 movw 15,Y, \-16,PC \{12e <cat2\+0x11f>\} - 13e: 18 02 4f d0 movw 15,Y, \-16,PC \{132 <cat2\+0x123>\} - 142: 86 17[ ]+ ldaa #23 - 144: 18 02 50 cf movw \-16,Y, 15,PC \{157 <cat2\+0x148>\} - 148: 18 02 50 cf movw \-16,Y, 15,PC \{15b <cat2\+0x14c>\} - 14c: 18 02 50 cf movw \-16,Y, 15,PC \{15f <cat2\+0x150>\} - 150: 86 18[ ]+ ldaa #24 - 152: 18 0a 8f cf movb 15,SP, 15,PC \{165 <cat2\+0x156>\} - 156: 18 0a 8f cf movb 15,SP, 15,PC \{169 <cat2\+0x15a>\} - 15a: 18 0a 8f cf movb 15,SP, 15,PC \{16d <cat2\+0x15e>\} - 15e: 86 19[ ]+ ldaa #25 - 160: 18 0a 8f cf movb 15,SP, 15,PC \{173 <cat2\+0x164>\} - 164: 18 0a 8f cf movb 15,SP, 15,PC \{177 <cat2\+0x168>\} - 168: 18 0a 8f cf movb 15,SP, 15,PC \{17b <cat2\+0x16c>\} - 16c: 86 1a[ ]+ ldaa #26 - 16e: 18 0a 8f d0 movb 15,SP, \-16,PC \{162 <cat2\+0x153>\} - 172: 18 0a 8f d0 movb 15,SP, \-16,PC \{166 <cat2\+0x157>\} - 176: 18 0a 8f d0 movb 15,SP, \-16,PC \{16a <cat2\+0x15b>\} - 17a: 86 1b[ ]+ ldaa #27 - 17c: 18 0a 90 cf movb \-16,SP, 15,PC \{18f <cat2\+0x180>\} - 180: 18 0a 90 cf movb \-16,SP, 15,PC \{193 <cat2\+0x184>\} - 184: 18 0a 90 cf movb \-16,SP, 15,PC \{197 <cat2\+0x188>\} - 188: 86 1c[ ]+ ldaa #28 - 18a: 18 02 8f cf movw 15,SP, 15,PC \{19d <cat2\+0x18e>\} - 18e: 18 02 8f cf movw 15,SP, 15,PC \{1a1 <cat2\+0x192>\} - 192: 18 02 8f cf movw 15,SP, 15,PC \{1a5 <cat2\+0x196>\} - 196: 86 1d[ ]+ ldaa #29 - 198: 18 02 8f cf movw 15,SP, 15,PC \{1ab <cat2\+0x19c>\} - 19c: 18 02 8f cf movw 15,SP, 15,PC \{1af <cat2\+0x1a0>\} - 1a0: 18 02 8f cf movw 15,SP, 15,PC \{1b3 <cat2\+0x1a4>\} - 1a4: 86 1e[ ]+ ldaa #30 - 1a6: 18 02 8f d0 movw 15,SP, \-16,PC \{19a <cat2\+0x18b>\} - 1aa: 18 02 8f d0 movw 15,SP, \-16,PC \{19e <cat2\+0x18f>\} - 1ae: 18 02 8f d0 movw 15,SP, \-16,PC \{1a2 <cat2\+0x193>\} - 1b2: 86 1f[ ]+ ldaa #31 - 1b4: 18 02 90 cf movw \-16,SP, 15,PC \{1c7 <cat2\+0x1b8>\} - 1b8: 18 02 90 cf movw \-16,SP, 15,PC \{1cb <cat2\+0x1bc>\} - 1bc: 18 02 90 cf movw \-16,SP, 15,PC \{1cf <cat2\+0x1c0>\} - 1c0: 86 20[ ]+ ldaa #32 - 1c2: 18 09 0f 10 movb 1000 <cat2\+0xff1>, 15,X +[ ]+ 0: 86 00[ ]+ ldaa #0x0 +[ ]+ 2: 18 0a 0f 0f movb 0xf,X, 0xf,X +[ ]+ 6: 18 0a 0f 0f movb 0xf,X, 0xf,X +[ ]+ a: 18 0a 0f 0f movb 0xf,X, 0xf,X +[ ]+ e: 86 01[ ]+ ldaa #0x1 +[ ]+10: 18 0a 0f 0f movb 0xf,X, 0xf,X +[ ]+14: 18 0a 0f 0f movb 0xf,X, 0xf,X +[ ]+18: 18 0a 0f 0f movb 0xf,X, 0xf,X +[ ]+1c: 86 02[ ]+ ldaa #0x2 +[ ]+1e: 18 0a 0f 10 movb 0xf,X, 0xfff0,X +[ ]+22: 18 0a 0f 10 movb 0xf,X, 0xfff0,X +[ ]+26: 18 0a 0f 10 movb 0xf,X, 0xfff0,X +[ ]+2a: 86 03[ ]+ ldaa #0x3 +[ ]+2c: 18 0a 10 0f movb 0xfff0,X, 0xf,X +[ ]+30: 18 0a 10 0f movb 0xfff0,X, 0xf,X +[ ]+34: 18 0a 10 0f movb 0xfff0,X, 0xf,X +[ ]+38: 86 04[ ]+ ldaa #0x4 +[ ]+3a: 18 02 0f 0f movw 0xf,X, 0xf,X +[ ]+3e: 18 02 0f 0f movw 0xf,X, 0xf,X +[ ]+42: 18 02 0f 0f movw 0xf,X, 0xf,X +[ ]+46: 86 05[ ]+ ldaa #0x5 +[ ]+48: 18 02 0f 0f movw 0xf,X, 0xf,X +[ ]+4c: 18 02 0f 0f movw 0xf,X, 0xf,X +[ ]+50: 18 02 0f 0f movw 0xf,X, 0xf,X +[ ]+54: 86 06[ ]+ ldaa #0x6 +[ ]+56: 18 02 0f 10 movw 0xf,X, 0xfff0,X +[ ]+5a: 18 02 0f 10 movw 0xf,X, 0xfff0,X +[ ]+5e: 18 02 0f 10 movw 0xf,X, 0xfff0,X +[ ]+62: 86 07[ ]+ ldaa #0x7 +[ ]+64: 18 02 10 0f movw 0xfff0,X, 0xf,X +[ ]+68: 18 02 10 0f movw 0xfff0,X, 0xf,X +[ ]+6c: 18 02 10 0f movw 0xfff0,X, 0xf,X +[ ]+70: 86 08[ ]+ ldaa #0x8 +[ ]+72: 18 0a 4f 4f movb 0xf,Y, 0xf,Y +[ ]+76: 18 0a 4f 4f movb 0xf,Y, 0xf,Y +[ ]+7a: 18 0a 4f 4f movb 0xf,Y, 0xf,Y +[ ]+7e: 86 09[ ]+ ldaa #0x9 +[ ]+80: 18 0a 4f 4f movb 0xf,Y, 0xf,Y +[ ]+84: 18 0a 4f 4f movb 0xf,Y, 0xf,Y +[ ]+88: 18 0a 4f 4f movb 0xf,Y, 0xf,Y +[ ]+8c: 86 0a[ ]+ ldaa #0xa +[ ]+8e: 18 0a 4f 50 movb 0xf,Y, 0xfff0,Y +[ ]+92: 18 0a 4f 50 movb 0xf,Y, 0xfff0,Y +[ ]+96: 18 0a 4f 50 movb 0xf,Y, 0xfff0,Y +[ ]+9a: 86 0b[ ]+ ldaa #0xb +[ ]+9c: 18 0a 50 4f movb 0xfff0,Y, 0xf,Y +[ ]+a0: 18 0a 50 4f movb 0xfff0,Y, 0xf,Y +[ ]+a4: 18 0a 50 4f movb 0xfff0,Y, 0xf,Y +[ ]+a8: 86 0c[ ]+ ldaa #0xc +[ ]+aa: 18 02 4f 4f movw 0xf,Y, 0xf,Y +[ ]+ae: 18 02 4f 4f movw 0xf,Y, 0xf,Y +[ ]+b2: 18 02 4f 4f movw 0xf,Y, 0xf,Y +[ ]+b6: 86 0d[ ]+ ldaa #0xd +[ ]+b8: 18 02 4f 4f movw 0xf,Y, 0xf,Y +[ ]+bc: 18 02 4f 4f movw 0xf,Y, 0xf,Y +[ ]+c0: 18 02 4f 4f movw 0xf,Y, 0xf,Y +[ ]+c4: 86 0e[ ]+ ldaa #0xe +[ ]+c6: 18 02 4f 50 movw 0xf,Y, 0xfff0,Y +[ ]+ca: 18 02 4f 50 movw 0xf,Y, 0xfff0,Y +[ ]+ce: 18 02 4f 50 movw 0xf,Y, 0xfff0,Y +[ ]+d2: 86 0f[ ]+ ldaa #0xf +[ ]+d4: 18 02 50 4f movw 0xfff0,Y, 0xf,Y +[ ]+d8: 18 02 50 4f movw 0xfff0,Y, 0xf,Y +[ ]+dc: 18 02 50 4f movw 0xfff0,Y, 0xf,Y +[ ]+e0: 86 10[ ]+ ldaa #0x10 +[ ]+e2: 18 0a 4f cf movb 0xf,Y, 0xf,PC \{0xf5 <cat2\+0xe6>\} +[ ]+e6: 18 0a 4f cf movb 0xf,Y, 0xf,PC \{0xf9 <cat2\+0xea>\} +[ ]+ea: 18 0a 4f cf movb 0xf,Y, 0xf,PC \{0xfd <cat2\+0xee>\} +[ ]+ee: 86 11[ ]+ ldaa #0x11 +[ ]+f0: 18 0a 4f cf movb 0xf,Y, 0xf,PC \{0x103 <cat2\+0xf4>\} +[ ]+f4: 18 0a 4f cf movb 0xf,Y, 0xf,PC \{0x107 <cat2\+0xf8>\} +[ ]+f8: 18 0a 4f cf movb 0xf,Y, 0xf,PC \{0x10b <cat2\+0xfc>\} +[ ]+fc: 86 12[ ]+ ldaa #0x12 +[ ]+fe: 18 0a 4f d0 movb 0xf,Y, 0xfff0,PC \{0xf2 <cat2\+0xe3>\} + 102: 18 0a 4f d0 movb 0xf,Y, 0xfff0,PC \{0xf6 <cat2\+0xe7>\} + 106: 18 0a 4f d0 movb 0xf,Y, 0xfff0,PC \{0xfa <cat2\+0xeb>\} + 10a: 86 13[ ]+ ldaa #0x13 + 10c: 18 0a 50 cf movb 0xfff0,Y, 0xf,PC \{0x11f <cat2\+0x110>\} + 110: 18 0a 50 cf movb 0xfff0,Y, 0xf,PC \{0x123 <cat2\+0x114>\} + 114: 18 0a 50 cf movb 0xfff0,Y, 0xf,PC \{0x127 <cat2\+0x118>\} + 118: 86 14[ ]+ ldaa #0x14 + 11a: 18 02 4f cf movw 0xf,Y, 0xf,PC \{0x12d <cat2\+0x11e>\} + 11e: 18 02 4f cf movw 0xf,Y, 0xf,PC \{0x131 <cat2\+0x122>\} + 122: 18 02 4f cf movw 0xf,Y, 0xf,PC \{0x135 <cat2\+0x126>\} + 126: 86 15[ ]+ ldaa #0x15 + 128: 18 02 4f cf movw 0xf,Y, 0xf,PC \{0x13b <cat2\+0x12c>\} + 12c: 18 02 4f cf movw 0xf,Y, 0xf,PC \{0x13f <cat2\+0x130>\} + 130: 18 02 4f cf movw 0xf,Y, 0xf,PC \{0x143 <cat2\+0x134>\} + 134: 86 16[ ]+ ldaa #0x16 + 136: 18 02 4f d0 movw 0xf,Y, 0xfff0,PC \{0x12a <cat2\+0x11b>\} + 13a: 18 02 4f d0 movw 0xf,Y, 0xfff0,PC \{0x12e <cat2\+0x11f>\} + 13e: 18 02 4f d0 movw 0xf,Y, 0xfff0,PC \{0x132 <cat2\+0x123>\} + 142: 86 17[ ]+ ldaa #0x17 + 144: 18 02 50 cf movw 0xfff0,Y, 0xf,PC \{0x157 <cat2\+0x148>\} + 148: 18 02 50 cf movw 0xfff0,Y, 0xf,PC \{0x15b <cat2\+0x14c>\} + 14c: 18 02 50 cf movw 0xfff0,Y, 0xf,PC \{0x15f <cat2\+0x150>\} + 150: 86 18[ ]+ ldaa #0x18 + 152: 18 0a 8f cf movb 0xf,SP, 0xf,PC \{0x165 <cat2\+0x156>\} + 156: 18 0a 8f cf movb 0xf,SP, 0xf,PC \{0x169 <cat2\+0x15a>\} + 15a: 18 0a 8f cf movb 0xf,SP, 0xf,PC \{0x16d <cat2\+0x15e>\} + 15e: 86 19[ ]+ ldaa #0x19 + 160: 18 0a 8f cf movb 0xf,SP, 0xf,PC \{0x173 <cat2\+0x164>\} + 164: 18 0a 8f cf movb 0xf,SP, 0xf,PC \{0x177 <cat2\+0x168>\} + 168: 18 0a 8f cf movb 0xf,SP, 0xf,PC \{0x17b <cat2\+0x16c>\} + 16c: 86 1a[ ]+ ldaa #0x1a + 16e: 18 0a 8f d0 movb 0xf,SP, 0xfff0,PC \{0x162 <cat2\+0x153>\} + 172: 18 0a 8f d0 movb 0xf,SP, 0xfff0,PC \{0x166 <cat2\+0x157>\} + 176: 18 0a 8f d0 movb 0xf,SP, 0xfff0,PC \{0x16a <cat2\+0x15b>\} + 17a: 86 1b[ ]+ ldaa #0x1b + 17c: 18 0a 90 cf movb 0xfff0,SP, 0xf,PC \{0x18f <cat2\+0x180>\} + 180: 18 0a 90 cf movb 0xfff0,SP, 0xf,PC \{0x193 <cat2\+0x184>\} + 184: 18 0a 90 cf movb 0xfff0,SP, 0xf,PC \{0x197 <cat2\+0x188>\} + 188: 86 1c[ ]+ ldaa #0x1c + 18a: 18 02 8f cf movw 0xf,SP, 0xf,PC \{0x19d <cat2\+0x18e>\} + 18e: 18 02 8f cf movw 0xf,SP, 0xf,PC \{0x1a1 <cat2\+0x192>\} + 192: 18 02 8f cf movw 0xf,SP, 0xf,PC \{0x1a5 <cat2\+0x196>\} + 196: 86 1d[ ]+ ldaa #0x1d + 198: 18 02 8f cf movw 0xf,SP, 0xf,PC \{0x1ab <cat2\+0x19c>\} + 19c: 18 02 8f cf movw 0xf,SP, 0xf,PC \{0x1af <cat2\+0x1a0>\} + 1a0: 18 02 8f cf movw 0xf,SP, 0xf,PC \{0x1b3 <cat2\+0x1a4>\} + 1a4: 86 1e[ ]+ ldaa #0x1e + 1a6: 18 02 8f d0 movw 0xf,SP, 0xfff0,PC \{0x19a <cat2\+0x18b>\} + 1aa: 18 02 8f d0 movw 0xf,SP, 0xfff0,PC \{0x19e <cat2\+0x18f>\} + 1ae: 18 02 8f d0 movw 0xf,SP, 0xfff0,PC \{0x1a2 <cat2\+0x193>\} + 1b2: 86 1f[ ]+ ldaa #0x1f + 1b4: 18 02 90 cf movw 0xfff0,SP, 0xf,PC \{0x1c7 <cat2\+0x1b8>\} + 1b8: 18 02 90 cf movw 0xfff0,SP, 0xf,PC \{0x1cb <cat2\+0x1bc>\} + 1bc: 18 02 90 cf movw 0xfff0,SP, 0xf,PC \{0x1cf <cat2\+0x1c0>\} + 1c0: 86 20[ ]+ ldaa #0x20 + 1c2: 18 09 0f 10 movb 0x1000 <cat2\+0xff1>, 0xf,X 1c6: 00 - 1c7: 18 09 0f 10 movb 1000 <cat2\+0xff1>, 15,X + 1c7: 18 09 0f 10 movb 0x1000 <cat2\+0xff1>, 0xf,X 1cb: 00 - 1cc: 18 09 0f 10 movb 1000 <cat2\+0xff1>, 15,X + 1cc: 18 09 0f 10 movb 0x1000 <cat2\+0xff1>, 0xf,X 1d0: 00 - 1d1: 86 21[ ]+ ldaa #33 - 1d3: 18 0d 0f 10 movb 15,X, 1000 <cat2\+0xff1> + 1d1: 86 21[ ]+ ldaa #0x21 + 1d3: 18 0d 0f 10 movb 0xf,X, 0x1000 <cat2\+0xff1> 1d7: 00 - 1d8: 18 0d 0f 10 movb 15,X, 1000 <cat2\+0xff1> + 1d8: 18 0d 0f 10 movb 0xf,X, 0x1000 <cat2\+0xff1> 1dc: 00 - 1dd: 18 0d 0f 10 movb 15,X, 1000 <cat2\+0xff1> + 1dd: 18 0d 0f 10 movb 0xf,X, 0x1000 <cat2\+0xff1> 1e1: 00 - 1e2: 86 22[ ]+ ldaa #34 - 1e4: 18 09 10 10 movb 1000 <cat2\+0xff1>, \-16,X + 1e2: 86 22[ ]+ ldaa #0x22 + 1e4: 18 09 10 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,X 1e8: 00 - 1e9: 18 09 10 10 movb 1000 <cat2\+0xff1>, \-16,X + 1e9: 18 09 10 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,X 1ed: 00 - 1ee: 18 09 10 10 movb 1000 <cat2\+0xff1>, \-16,X + 1ee: 18 09 10 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,X 1f2: 00 - 1f3: 86 23[ ]+ ldaa #35 - 1f5: 18 0d 10 10 movb \-16,X, 1000 <cat2\+0xff1> + 1f3: 86 23[ ]+ ldaa #0x23 + 1f5: 18 0d 10 10 movb 0xfff0,X, 0x1000 <cat2\+0xff1> 1f9: 00 - 1fa: 18 0d 10 10 movb \-16,X, 1000 <cat2\+0xff1> + 1fa: 18 0d 10 10 movb 0xfff0,X, 0x1000 <cat2\+0xff1> 1fe: 00 - 1ff: 18 0d 10 10 movb \-16,X, 1000 <cat2\+0xff1> + 1ff: 18 0d 10 10 movb 0xfff0,X, 0x1000 <cat2\+0xff1> 203: 00 - 204: 86 24[ ]+ ldaa #36 - 206: 18 01 0f 10 movw 1002 <cat2\+0xff3>, 15,X + 204: 86 24[ ]+ ldaa #0x24 + 206: 18 01 0f 10 movw 0x1002 <cat2\+0xff3>, 0xf,X 20a: 02 - 20b: 18 01 0f 10 movw 1002 <cat2\+0xff3>, 15,X + 20b: 18 01 0f 10 movw 0x1002 <cat2\+0xff3>, 0xf,X 20f: 02 - 210: 18 01 0f 10 movw 1002 <cat2\+0xff3>, 15,X + 210: 18 01 0f 10 movw 0x1002 <cat2\+0xff3>, 0xf,X 214: 02 - 215: 86 25[ ]+ ldaa #37 - 217: 18 05 0f 10 movw 15,X, 1002 <cat2\+0xff3> + 215: 86 25[ ]+ ldaa #0x25 + 217: 18 05 0f 10 movw 0xf,X, 0x1002 <cat2\+0xff3> 21b: 02 - 21c: 18 05 0f 10 movw 15,X, 1002 <cat2\+0xff3> + 21c: 18 05 0f 10 movw 0xf,X, 0x1002 <cat2\+0xff3> 220: 02 - 221: 18 05 0f 10 movw 15,X, 1002 <cat2\+0xff3> + 221: 18 05 0f 10 movw 0xf,X, 0x1002 <cat2\+0xff3> 225: 02 - 226: 86 26[ ]+ ldaa #38 - 228: 18 01 10 10 movw 1002 <cat2\+0xff3>, \-16,X + 226: 86 26[ ]+ ldaa #0x26 + 228: 18 01 10 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,X 22c: 02 - 22d: 18 01 10 10 movw 1002 <cat2\+0xff3>, \-16,X + 22d: 18 01 10 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,X 231: 02 - 232: 18 01 10 10 movw 1002 <cat2\+0xff3>, \-16,X + 232: 18 01 10 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,X 236: 02 - 237: 86 27[ ]+ ldaa #39 - 239: 18 05 10 10 movw \-16,X, 1002 <cat2\+0xff3> + 237: 86 27[ ]+ ldaa #0x27 + 239: 18 05 10 10 movw 0xfff0,X, 0x1002 <cat2\+0xff3> 23d: 02 - 23e: 18 05 10 10 movw \-16,X, 1002 <cat2\+0xff3> + 23e: 18 05 10 10 movw 0xfff0,X, 0x1002 <cat2\+0xff3> 242: 02 - 243: 18 05 10 10 movw \-16,X, 1002 <cat2\+0xff3> + 243: 18 05 10 10 movw 0xfff0,X, 0x1002 <cat2\+0xff3> 247: 02 - 248: 86 28[ ]+ ldaa #40 - 24a: 18 09 4f 10 movb 1000 <cat2\+0xff1>, 15,Y + 248: 86 28[ ]+ ldaa #0x28 + 24a: 18 09 4f 10 movb 0x1000 <cat2\+0xff1>, 0xf,Y 24e: 00 - 24f: 18 09 4f 10 movb 1000 <cat2\+0xff1>, 15,Y + 24f: 18 09 4f 10 movb 0x1000 <cat2\+0xff1>, 0xf,Y 253: 00 - 254: 18 09 4f 10 movb 1000 <cat2\+0xff1>, 15,Y + 254: 18 09 4f 10 movb 0x1000 <cat2\+0xff1>, 0xf,Y 258: 00 - 259: 86 29[ ]+ ldaa #41 - 25b: 18 0d 4f 10 movb 15,Y, 1000 <cat2\+0xff1> + 259: 86 29[ ]+ ldaa #0x29 + 25b: 18 0d 4f 10 movb 0xf,Y, 0x1000 <cat2\+0xff1> 25f: 00 - 260: 18 0d 4f 10 movb 15,Y, 1000 <cat2\+0xff1> + 260: 18 0d 4f 10 movb 0xf,Y, 0x1000 <cat2\+0xff1> 264: 00 - 265: 18 0d 4f 10 movb 15,Y, 1000 <cat2\+0xff1> + 265: 18 0d 4f 10 movb 0xf,Y, 0x1000 <cat2\+0xff1> 269: 00 - 26a: 86 2a[ ]+ ldaa #42 - 26c: 18 09 50 10 movb 1000 <cat2\+0xff1>, \-16,Y + 26a: 86 2a[ ]+ ldaa #0x2a + 26c: 18 09 50 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,Y 270: 00 - 271: 18 09 50 10 movb 1000 <cat2\+0xff1>, \-16,Y + 271: 18 09 50 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,Y 275: 00 - 276: 18 09 50 10 movb 1000 <cat2\+0xff1>, \-16,Y + 276: 18 09 50 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,Y 27a: 00 - 27b: 86 2b[ ]+ ldaa #43 - 27d: 18 0d 50 10 movb \-16,Y, 1000 <cat2\+0xff1> + 27b: 86 2b[ ]+ ldaa #0x2b + 27d: 18 0d 50 10 movb 0xfff0,Y, 0x1000 <cat2\+0xff1> 281: 00 - 282: 18 0d 50 10 movb \-16,Y, 1000 <cat2\+0xff1> + 282: 18 0d 50 10 movb 0xfff0,Y, 0x1000 <cat2\+0xff1> 286: 00 - 287: 18 0d 50 10 movb \-16,Y, 1000 <cat2\+0xff1> + 287: 18 0d 50 10 movb 0xfff0,Y, 0x1000 <cat2\+0xff1> 28b: 00 - 28c: 86 2c[ ]+ ldaa #44 - 28e: 18 01 4f 10 movw 1002 <cat2\+0xff3>, 15,Y + 28c: 86 2c[ ]+ ldaa #0x2c + 28e: 18 01 4f 10 movw 0x1002 <cat2\+0xff3>, 0xf,Y 292: 02 - 293: 18 01 4f 10 movw 1002 <cat2\+0xff3>, 15,Y + 293: 18 01 4f 10 movw 0x1002 <cat2\+0xff3>, 0xf,Y 297: 02 - 298: 18 01 4f 10 movw 1002 <cat2\+0xff3>, 15,Y + 298: 18 01 4f 10 movw 0x1002 <cat2\+0xff3>, 0xf,Y 29c: 02 - 29d: 86 2d[ ]+ ldaa #45 - 29f: 18 05 4f 10 movw 15,Y, 1002 <cat2\+0xff3> + 29d: 86 2d[ ]+ ldaa #0x2d + 29f: 18 05 4f 10 movw 0xf,Y, 0x1002 <cat2\+0xff3> 2a3: 02 - 2a4: 18 05 4f 10 movw 15,Y, 1002 <cat2\+0xff3> + 2a4: 18 05 4f 10 movw 0xf,Y, 0x1002 <cat2\+0xff3> 2a8: 02 - 2a9: 18 05 4f 10 movw 15,Y, 1002 <cat2\+0xff3> + 2a9: 18 05 4f 10 movw 0xf,Y, 0x1002 <cat2\+0xff3> 2ad: 02 - 2ae: 86 2e[ ]+ ldaa #46 - 2b0: 18 01 50 10 movw 1002 <cat2\+0xff3>, \-16,Y + 2ae: 86 2e[ ]+ ldaa #0x2e + 2b0: 18 01 50 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,Y 2b4: 02 - 2b5: 18 01 50 10 movw 1002 <cat2\+0xff3>, \-16,Y + 2b5: 18 01 50 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,Y 2b9: 02 - 2ba: 18 01 50 10 movw 1002 <cat2\+0xff3>, \-16,Y + 2ba: 18 01 50 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,Y 2be: 02 - 2bf: 86 2f[ ]+ ldaa #47 - 2c1: 18 05 50 10 movw \-16,Y, 1002 <cat2\+0xff3> + 2bf: 86 2f[ ]+ ldaa #0x2f + 2c1: 18 05 50 10 movw 0xfff0,Y, 0x1002 <cat2\+0xff3> 2c5: 02 - 2c6: 18 05 50 10 movw \-16,Y, 1002 <cat2\+0xff3> + 2c6: 18 05 50 10 movw 0xfff0,Y, 0x1002 <cat2\+0xff3> 2ca: 02 - 2cb: 18 05 50 10 movw \-16,Y, 1002 <cat2\+0xff3> + 2cb: 18 05 50 10 movw 0xfff0,Y, 0x1002 <cat2\+0xff3> 2cf: 02 - 2d0: 86 30[ ]+ ldaa #48 - 2d2: 18 09 cf 10 movb 1000 <cat2\+0xff1>, 15,PC \{2e4 <cat2\+0x2d5>\} + 2d0: 86 30[ ]+ ldaa #0x30 + 2d2: 18 09 cf 10 movb 0x1000 <cat2\+0xff1>, 0xf,PC \{0x2e4 <cat2\+0x2d5>\} 2d6: 00 - 2d7: 18 09 cf 10 movb 1000 <cat2\+0xff1>, 15,PC \{2e9 <cat2\+0x2da>\} + 2d7: 18 09 cf 10 movb 0x1000 <cat2\+0xff1>, 0xf,PC \{0x2e9 <cat2\+0x2da>\} 2db: 00 - 2dc: 18 09 cf 10 movb 1000 <cat2\+0xff1>, 15,PC \{2ee <cat2\+0x2df>\} + 2dc: 18 09 cf 10 movb 0x1000 <cat2\+0xff1>, 0xf,PC \{0x2ee <cat2\+0x2df>\} 2e0: 00 - 2e1: 86 31[ ]+ ldaa #49 - 2e3: 18 0d cf 10 movb 15,PC \{2f5 <cat2\+0x2e6>\}, 1000 <cat2\+0xff1> + 2e1: 86 31[ ]+ ldaa #0x31 + 2e3: 18 0d cf 10 movb 0xf,PC \{0x2f5 <cat2\+0x2e6>\}, 0x1000 <cat2\+0xff1> 2e7: 00 - 2e8: 18 0d cf 10 movb 15,PC \{2fa <cat2\+0x2eb>\}, 1000 <cat2\+0xff1> + 2e8: 18 0d cf 10 movb 0xf,PC \{0x2fa <cat2\+0x2eb>\}, 0x1000 <cat2\+0xff1> 2ec: 00 - 2ed: 18 0d cf 10 movb 15,PC \{2ff <cat2\+0x2f0>\}, 1000 <cat2\+0xff1> + 2ed: 18 0d cf 10 movb 0xf,PC \{0x2ff <cat2\+0x2f0>\}, 0x1000 <cat2\+0xff1> 2f1: 00 - 2f2: 86 32[ ]+ ldaa #50 - 2f4: 18 09 d0 10 movb 1000 <cat2\+0xff1>, \-16,PC \{2e7 <cat2\+0x2d8>\} + 2f2: 86 32[ ]+ ldaa #0x32 + 2f4: 18 09 d0 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,PC \{0x2e7 <cat2\+0x2d8>\} 2f8: 00 - 2f9: 18 09 d0 10 movb 1000 <cat2\+0xff1>, \-16,PC \{2ec <cat2\+0x2dd>\} + 2f9: 18 09 d0 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,PC \{0x2ec <cat2\+0x2dd>\} 2fd: 00 - 2fe: 18 09 d0 10 movb 1000 <cat2\+0xff1>, \-16,PC \{2f1 <cat2\+0x2e2>\} + 2fe: 18 09 d0 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,PC \{0x2f1 <cat2\+0x2e2>\} 302: 00 - 303: 86 33[ ]+ ldaa #51 - 305: 18 0d d0 10 movb \-16,PC \{2f8 <cat2\+0x2e9>\}, 1000 <cat2\+0xff1> + 303: 86 33[ ]+ ldaa #0x33 + 305: 18 0d d0 10 movb 0xfff0,PC \{0x2f8 <cat2\+0x2e9>\}, 0x1000 <cat2\+0xff1> 309: 00 - 30a: 18 0d d0 10 movb \-16,PC \{2fd <cat2\+0x2ee>\}, 1000 <cat2\+0xff1> + 30a: 18 0d d0 10 movb 0xfff0,PC \{0x2fd <cat2\+0x2ee>\}, 0x1000 <cat2\+0xff1> 30e: 00 - 30f: 18 0d d0 10 movb \-16,PC \{302 <cat2\+0x2f3>\}, 1000 <cat2\+0xff1> + 30f: 18 0d d0 10 movb 0xfff0,PC \{0x302 <cat2\+0x2f3>\}, 0x1000 <cat2\+0xff1> 313: 00 - 314: 86 34[ ]+ ldaa #52 - 316: 18 01 cf 10 movw 1002 <cat2\+0xff3>, 15,PC \{328 <cat2\+0x319>\} + 314: 86 34[ ]+ ldaa #0x34 + 316: 18 01 cf 10 movw 0x1002 <cat2\+0xff3>, 0xf,PC \{0x328 <cat2\+0x319>\} 31a: 02 - 31b: 18 01 cf 10 movw 1002 <cat2\+0xff3>, 15,PC \{32d <cat2\+0x31e>\} + 31b: 18 01 cf 10 movw 0x1002 <cat2\+0xff3>, 0xf,PC \{0x32d <cat2\+0x31e>\} 31f: 02 - 320: 18 01 cf 10 movw 1002 <cat2\+0xff3>, 15,PC \{332 <cat2\+0x323>\} + 320: 18 01 cf 10 movw 0x1002 <cat2\+0xff3>, 0xf,PC \{0x332 <cat2\+0x323>\} 324: 02 - 325: 86 35[ ]+ ldaa #53 - 327: 18 05 cf 10 movw 15,PC \{339 <cat2\+0x32a>\}, 1002 <cat2\+0xff3> + 325: 86 35[ ]+ ldaa #0x35 + 327: 18 05 cf 10 movw 0xf,PC \{0x339 <cat2\+0x32a>\}, 0x1002 <cat2\+0xff3> 32b: 02 - 32c: 18 05 cf 10 movw 15,PC \{33e <cat2\+0x32f>\}, 1002 <cat2\+0xff3> + 32c: 18 05 cf 10 movw 0xf,PC \{0x33e <cat2\+0x32f>\}, 0x1002 <cat2\+0xff3> 330: 02 - 331: 18 05 cf 10 movw 15,PC \{343 <cat2\+0x334>\}, 1002 <cat2\+0xff3> + 331: 18 05 cf 10 movw 0xf,PC \{0x343 <cat2\+0x334>\}, 0x1002 <cat2\+0xff3> 335: 02 - 336: 86 36[ ]+ ldaa #54 - 338: 18 01 d0 10 movw 1002 <cat2\+0xff3>, \-16,PC \{32b <cat2\+0x31c>\} + 336: 86 36[ ]+ ldaa #0x36 + 338: 18 01 d0 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,PC \{0x32b <cat2\+0x31c>\} 33c: 02 - 33d: 18 01 d0 10 movw 1002 <cat2\+0xff3>, \-16,PC \{330 <cat2\+0x321>\} + 33d: 18 01 d0 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,PC \{0x330 <cat2\+0x321>\} 341: 02 - 342: 18 01 d0 10 movw 1002 <cat2\+0xff3>, \-16,PC \{335 <cat2\+0x326>\} + 342: 18 01 d0 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,PC \{0x335 <cat2\+0x326>\} 346: 02 - 347: 86 37[ ]+ ldaa #55 - 349: 18 05 d0 10 movw \-16,PC \{33c <cat2\+0x32d>\}, 1002 <cat2\+0xff3> + 347: 86 37[ ]+ ldaa #0x37 + 349: 18 05 d0 10 movw 0xfff0,PC \{0x33c <cat2\+0x32d>\}, 0x1002 <cat2\+0xff3> 34d: 02 - 34e: 18 05 d0 10 movw \-16,PC \{341 <cat2\+0x332>\}, 1002 <cat2\+0xff3> + 34e: 18 05 d0 10 movw 0xfff0,PC \{0x341 <cat2\+0x332>\}, 0x1002 <cat2\+0xff3> 352: 02 - 353: 18 05 d0 10 movw \-16,PC \{346 <cat2\+0x337>\}, 1002 <cat2\+0xff3> + 353: 18 05 d0 10 movw 0xfff0,PC \{0x346 <cat2\+0x337>\}, 0x1002 <cat2\+0xff3> 357: 02 - 358: 86 38[ ]+ ldaa #56 - 35a: 18 09 8f 10 movb 1000 <cat2\+0xff1>, 15,SP + 358: 86 38[ ]+ ldaa #0x38 + 35a: 18 09 8f 10 movb 0x1000 <cat2\+0xff1>, 0xf,SP 35e: 00 - 35f: 18 09 8f 10 movb 1000 <cat2\+0xff1>, 15,SP + 35f: 18 09 8f 10 movb 0x1000 <cat2\+0xff1>, 0xf,SP 363: 00 - 364: 18 09 8f 10 movb 1000 <cat2\+0xff1>, 15,SP + 364: 18 09 8f 10 movb 0x1000 <cat2\+0xff1>, 0xf,SP 368: 00 - 369: 86 39[ ]+ ldaa #57 - 36b: 18 0d 8f 10 movb 15,SP, 1000 <cat2\+0xff1> + 369: 86 39[ ]+ ldaa #0x39 + 36b: 18 0d 8f 10 movb 0xf,SP, 0x1000 <cat2\+0xff1> 36f: 00 - 370: 18 0d 8f 10 movb 15,SP, 1000 <cat2\+0xff1> + 370: 18 0d 8f 10 movb 0xf,SP, 0x1000 <cat2\+0xff1> 374: 00 - 375: 18 0d 8f 10 movb 15,SP, 1000 <cat2\+0xff1> + 375: 18 0d 8f 10 movb 0xf,SP, 0x1000 <cat2\+0xff1> 379: 00 - 37a: 86 3a[ ]+ ldaa #58 - 37c: 18 09 90 10 movb 1000 <cat2\+0xff1>, \-16,SP + 37a: 86 3a[ ]+ ldaa #0x3a + 37c: 18 09 90 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,SP 380: 00 - 381: 18 09 90 10 movb 1000 <cat2\+0xff1>, \-16,SP + 381: 18 09 90 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,SP 385: 00 - 386: 18 09 90 10 movb 1000 <cat2\+0xff1>, \-16,SP + 386: 18 09 90 10 movb 0x1000 <cat2\+0xff1>, 0xfff0,SP 38a: 00 - 38b: 86 3b[ ]+ ldaa #59 - 38d: 18 0d 90 10 movb \-16,SP, 1000 <cat2\+0xff1> + 38b: 86 3b[ ]+ ldaa #0x3b + 38d: 18 0d 90 10 movb 0xfff0,SP, 0x1000 <cat2\+0xff1> 391: 00 - 392: 18 0d 90 10 movb \-16,SP, 1000 <cat2\+0xff1> + 392: 18 0d 90 10 movb 0xfff0,SP, 0x1000 <cat2\+0xff1> 396: 00 - 397: 18 0d 90 10 movb \-16,SP, 1000 <cat2\+0xff1> + 397: 18 0d 90 10 movb 0xfff0,SP, 0x1000 <cat2\+0xff1> 39b: 00 - 39c: 86 3c[ ]+ ldaa #60 - 39e: 18 01 8f 10 movw 1002 <cat2\+0xff3>, 15,SP + 39c: 86 3c[ ]+ ldaa #0x3c + 39e: 18 01 8f 10 movw 0x1002 <cat2\+0xff3>, 0xf,SP 3a2: 02 - 3a3: 18 01 8f 10 movw 1002 <cat2\+0xff3>, 15,SP + 3a3: 18 01 8f 10 movw 0x1002 <cat2\+0xff3>, 0xf,SP 3a7: 02 - 3a8: 18 01 8f 10 movw 1002 <cat2\+0xff3>, 15,SP + 3a8: 18 01 8f 10 movw 0x1002 <cat2\+0xff3>, 0xf,SP 3ac: 02 - 3ad: 86 3d[ ]+ ldaa #61 - 3af: 18 05 8f 10 movw 15,SP, 1002 <cat2\+0xff3> + 3ad: 86 3d[ ]+ ldaa #0x3d + 3af: 18 05 8f 10 movw 0xf,SP, 0x1002 <cat2\+0xff3> 3b3: 02 - 3b4: 18 05 8f 10 movw 15,SP, 1002 <cat2\+0xff3> + 3b4: 18 05 8f 10 movw 0xf,SP, 0x1002 <cat2\+0xff3> 3b8: 02 - 3b9: 18 05 8f 10 movw 15,SP, 1002 <cat2\+0xff3> + 3b9: 18 05 8f 10 movw 0xf,SP, 0x1002 <cat2\+0xff3> 3bd: 02 - 3be: 86 3e[ ]+ ldaa #62 - 3c0: 18 01 90 10 movw 1002 <cat2\+0xff3>, \-16,SP + 3be: 86 3e[ ]+ ldaa #0x3e + 3c0: 18 01 90 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,SP 3c4: 02 - 3c5: 18 01 90 10 movw 1002 <cat2\+0xff3>, \-16,SP + 3c5: 18 01 90 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,SP 3c9: 02 - 3ca: 18 01 90 10 movw 1002 <cat2\+0xff3>, \-16,SP + 3ca: 18 01 90 10 movw 0x1002 <cat2\+0xff3>, 0xfff0,SP 3ce: 02 - 3cf: 86 3f[ ]+ ldaa #63 - 3d1: 18 05 90 10 movw \-16,SP, 1002 <cat2\+0xff3> + 3cf: 86 3f[ ]+ ldaa #0x3f + 3d1: 18 05 90 10 movw 0xfff0,SP, 0x1002 <cat2\+0xff3> 3d5: 02 - 3d6: 18 05 90 10 movw \-16,SP, 1002 <cat2\+0xff3> + 3d6: 18 05 90 10 movw 0xfff0,SP, 0x1002 <cat2\+0xff3> 3da: 02 - 3db: 18 05 90 10 movw \-16,SP, 1002 <cat2\+0xff3> + 3db: 18 05 90 10 movw 0xfff0,SP, 0x1002 <cat2\+0xff3> 3df: 02 - 3e0: 86 40[ ]+ ldaa #64 - 3e2: 18 08 07 aa movb #170, 7,X - 3e6: 18 08 07 aa movb #170, 7,X - 3ea: 18 08 07 aa movb #170, 7,X - 3ee: 86 41[ ]+ ldaa #65 - 3f0: 18 08 18 aa movb #170, \-8,X - 3f4: 18 08 18 aa movb #170, \-8,X - 3f8: 18 08 18 aa movb #170, \-8,X - 3fc: 86 42[ ]+ ldaa #66 - 3fe: 18 00 07 00 movw #44 <cat2\+0x35>, 7,X + 3e0: 86 40[ ]+ ldaa #0x40 + 3e2: 18 08 07 aa movb #0xaa, 0x7,X + 3e6: 18 08 07 aa movb #0xaa, 0x7,X + 3ea: 18 08 07 aa movb #0xaa, 0x7,X + 3ee: 86 41[ ]+ ldaa #0x41 + 3f0: 18 08 18 aa movb #0xaa, 0xfff8,X + 3f4: 18 08 18 aa movb #0xaa, 0xfff8,X + 3f8: 18 08 18 aa movb #0xaa, 0xfff8,X + 3fc: 86 42[ ]+ ldaa #0x42 + 3fe: 18 00 07 00 movw #0x44 <cat2\+0x35>, 0x7,X 402: 44 - 403: 18 00 07 00 movw #44 <cat2\+0x35>, 7,X + 403: 18 00 07 00 movw #0x44 <cat2\+0x35>, 0x7,X 407: 44 - 408: 18 00 07 00 movw #44 <cat2\+0x35>, 7,X + 408: 18 00 07 00 movw #0x44 <cat2\+0x35>, 0x7,X 40c: 44 - 40d: 86 43[ ]+ ldaa #67 - 40f: 18 00 18 00 movw #44 <cat2\+0x35>, \-8,X + 40d: 86 43[ ]+ ldaa #0x43 + 40f: 18 00 18 00 movw #0x44 <cat2\+0x35>, 0xfff8,X 413: 44 - 414: 18 00 18 00 movw #44 <cat2\+0x35>, \-8,X + 414: 18 00 18 00 movw #0x44 <cat2\+0x35>, 0xfff8,X 418: 44 - 419: 18 00 18 00 movw #44 <cat2\+0x35>, \-8,X + 419: 18 00 18 00 movw #0x44 <cat2\+0x35>, 0xfff8,X 41d: 44 - 41e: 86 44[ ]+ ldaa #68 - 420: 18 08 47 aa movb #170, 7,Y - 424: 18 08 47 aa movb #170, 7,Y - 428: 18 08 47 aa movb #170, 7,Y - 42c: 86 45[ ]+ ldaa #69 - 42e: 18 08 58 aa movb #170, \-8,Y - 432: 18 08 58 aa movb #170, \-8,Y - 436: 18 08 58 aa movb #170, \-8,Y - 43a: 86 46[ ]+ ldaa #70 - 43c: 18 00 47 00 movw #44 <cat2\+0x35>, 7,Y + 41e: 86 44[ ]+ ldaa #0x44 + 420: 18 08 47 aa movb #0xaa, 0x7,Y + 424: 18 08 47 aa movb #0xaa, 0x7,Y + 428: 18 08 47 aa movb #0xaa, 0x7,Y + 42c: 86 45[ ]+ ldaa #0x45 + 42e: 18 08 58 aa movb #0xaa, 0xfff8,Y + 432: 18 08 58 aa movb #0xaa, 0xfff8,Y + 436: 18 08 58 aa movb #0xaa, 0xfff8,Y + 43a: 86 46[ ]+ ldaa #0x46 + 43c: 18 00 47 00 movw #0x44 <cat2\+0x35>, 0x7,Y 440: 44 - 441: 18 00 47 00 movw #44 <cat2\+0x35>, 7,Y + 441: 18 00 47 00 movw #0x44 <cat2\+0x35>, 0x7,Y 445: 44 - 446: 18 00 47 00 movw #44 <cat2\+0x35>, 7,Y + 446: 18 00 47 00 movw #0x44 <cat2\+0x35>, 0x7,Y 44a: 44 - 44b: 86 47[ ]+ ldaa #71 - 44d: 18 00 58 00 movw #44 <cat2\+0x35>, \-8,Y + 44b: 86 47[ ]+ ldaa #0x47 + 44d: 18 00 58 00 movw #0x44 <cat2\+0x35>, 0xfff8,Y 451: 44 - 452: 18 00 58 00 movw #44 <cat2\+0x35>, \-8,Y + 452: 18 00 58 00 movw #0x44 <cat2\+0x35>, 0xfff8,Y 456: 44 - 457: 18 00 58 00 movw #44 <cat2\+0x35>, \-8,Y + 457: 18 00 58 00 movw #0x44 <cat2\+0x35>, 0xfff8,Y 45b: 44 - 45c: 86 48[ ]+ ldaa #72 - 45e: 18 08 c7 aa movb #170, 7,PC \{468 <cat2\+0x459>\} - 462: 18 08 c7 aa movb #170, 7,PC \{46c <cat2\+0x45d>\} - 466: 18 08 c7 aa movb #170, 7,PC \{470 <cat2\+0x461>\} - 46a: 86 49[ ]+ ldaa #73 - 46c: 18 08 d8 aa movb #170, \-8,PC \{467 <cat2\+0x458>\} - 470: 18 08 d8 aa movb #170, \-8,PC \{46b <cat2\+0x45c>\} - 474: 18 08 d8 aa movb #170, \-8,PC \{46f <cat2\+0x460>\} - 478: 86 4a[ ]+ ldaa #74 - 47a: 18 00 c7 00 movw #44 <cat2\+0x35>, 7,PC \{484 <cat2\+0x475>\} + 45c: 86 48[ ]+ ldaa #0x48 + 45e: 18 08 c7 aa movb #0xaa, 0x7,PC \{0x468 <cat2\+0x459>\} + 462: 18 08 c7 aa movb #0xaa, 0x7,PC \{0x46c <cat2\+0x45d>\} + 466: 18 08 c7 aa movb #0xaa, 0x7,PC \{0x470 <cat2\+0x461>\} + 46a: 86 49[ ]+ ldaa #0x49 + 46c: 18 08 d8 aa movb #0xaa, 0xfff8,PC \{0x467 <cat2\+0x458>\} + 470: 18 08 d8 aa movb #0xaa, 0xfff8,PC \{0x46b <cat2\+0x45c>\} + 474: 18 08 d8 aa movb #0xaa, 0xfff8,PC \{0x46f <cat2\+0x460>\} + 478: 86 4a[ ]+ ldaa #0x4a + 47a: 18 00 c7 00 movw #0x44 <cat2\+0x35>, 0x7,PC \{0x484 <cat2\+0x475>\} 47e: 44 - 47f: 18 00 c7 00 movw #44 <cat2\+0x35>, 7,PC \{489 <cat2\+0x47a>\} + 47f: 18 00 c7 00 movw #0x44 <cat2\+0x35>, 0x7,PC \{0x489 <cat2\+0x47a>\} 483: 44 - 484: 18 00 c7 00 movw #44 <cat2\+0x35>, 7,PC \{48e <cat2\+0x47f>\} + 484: 18 00 c7 00 movw #0x44 <cat2\+0x35>, 0x7,PC \{0x48e <cat2\+0x47f>\} 488: 44 - 489: 86 4b[ ]+ ldaa #75 - 48b: 18 00 d8 00 movw #44 <cat2\+0x35>, \-8,PC \{486 <cat2\+0x477>\} + 489: 86 4b[ ]+ ldaa #0x4b + 48b: 18 00 d8 00 movw #0x44 <cat2\+0x35>, 0xfff8,PC \{0x486 <cat2\+0x477>\} 48f: 44 - 490: 18 00 d8 00 movw #44 <cat2\+0x35>, \-8,PC \{48b <cat2\+0x47c>\} + 490: 18 00 d8 00 movw #0x44 <cat2\+0x35>, 0xfff8,PC \{0x48b <cat2\+0x47c>\} 494: 44 - 495: 18 00 d8 00 movw #44 <cat2\+0x35>, \-8,PC \{490 <cat2\+0x481>\} + 495: 18 00 d8 00 movw #0x44 <cat2\+0x35>, 0xfff8,PC \{0x490 <cat2\+0x481>\} 499: 44 - 49a: 86 4c[ ]+ ldaa #76 - 49c: 18 08 87 aa movb #170, 7,SP - 4a0: 18 08 87 aa movb #170, 7,SP - 4a4: 18 08 87 aa movb #170, 7,SP - 4a8: 86 4d[ ]+ ldaa #77 - 4aa: 18 08 98 aa movb #170, \-8,SP - 4ae: 18 08 98 aa movb #170, \-8,SP - 4b2: 18 08 98 aa movb #170, \-8,SP - 4b6: 86 4e[ ]+ ldaa #78 - 4b8: 18 00 87 00 movw #44 <cat2\+0x35>, 7,SP + 49a: 86 4c[ ]+ ldaa #0x4c + 49c: 18 08 87 aa movb #0xaa, 0x7,SP + 4a0: 18 08 87 aa movb #0xaa, 0x7,SP + 4a4: 18 08 87 aa movb #0xaa, 0x7,SP + 4a8: 86 4d[ ]+ ldaa #0x4d + 4aa: 18 08 98 aa movb #0xaa, 0xfff8,SP + 4ae: 18 08 98 aa movb #0xaa, 0xfff8,SP + 4b2: 18 08 98 aa movb #0xaa, 0xfff8,SP + 4b6: 86 4e[ ]+ ldaa #0x4e + 4b8: 18 00 87 00 movw #0x44 <cat2\+0x35>, 0x7,SP 4bc: 44 - 4bd: 18 00 87 00 movw #44 <cat2\+0x35>, 7,SP + 4bd: 18 00 87 00 movw #0x44 <cat2\+0x35>, 0x7,SP 4c1: 44 - 4c2: 18 00 87 00 movw #44 <cat2\+0x35>, 7,SP + 4c2: 18 00 87 00 movw #0x44 <cat2\+0x35>, 0x7,SP 4c6: 44 - 4c7: 86 4f[ ]+ ldaa #79 - 4c9: 18 00 98 00 movw #44 <cat2\+0x35>, \-8,SP + 4c7: 86 4f[ ]+ ldaa #0x4f + 4c9: 18 00 98 00 movw #0x44 <cat2\+0x35>, 0xfff8,SP 4cd: 44 - 4ce: 18 00 98 00 movw #44 <cat2\+0x35>, \-8,SP + 4ce: 18 00 98 00 movw #0x44 <cat2\+0x35>, 0xfff8,SP 4d2: 44 - 4d3: 18 00 98 00 movw #44 <cat2\+0x35>, \-8,SP + 4d3: 18 00 98 00 movw #0x44 <cat2\+0x35>, 0xfff8,SP 4d7: 44 - 4d8: 86 50[ ]+ ldaa #80 + 4d8: 86 50[ ]+ ldaa #0x50 diff --git a/gas/testsuite/gas/m68hc11/opers12-dwarf2.d b/gas/testsuite/gas/m68hc11/opers12-dwarf2.d index 9542460..8faaf4c 100644 --- a/gas/testsuite/gas/m68hc11/opers12-dwarf2.d +++ b/gas/testsuite/gas/m68hc11/opers12-dwarf2.d @@ -14,49 +14,49 @@ Disassembly of section .text: start: anda \[12,x\] ; Indexed indirect - 0: a4 e3 00 0c anda \[12,X\] + 0: a4 e3 00 0c anda \[0xc,X\] ldaa #10 - 4: 86 0a ldaa #10 + 4: 86 0a ldaa #0xa ldx L1 - 6: fe 00 00 ldx 0 <start> + 6: fe 00 00 ldx 0x0 <start> 0+09 <L1>: L1: ldy ,x - 9: ed 00 ldy 0,X + 9: ed 00 ldy 0x0,X addd 1,y ; Offset from register - b: e3 41 addd 1,Y + b: e3 41 addd 0x1,Y subd \-1,y - d: a3 5f subd \-1,Y + d: a3 5f subd 0xffff,Y eora 15,y - f: a8 4f eora 15,Y + f: a8 4f eora 0xf,Y eora \-16,y - 11: a8 50 eora \-16,Y + 11: a8 50 eora 0xfff0,Y eorb 16,y - 13: e8 e8 10 eorb 16,Y + 13: e8 e8 10 eorb 0x10,Y eorb \-17,y - 16: e8 e9 ef eorb \-17,Y + 16: e8 e9 ef eorb 0xffef,Y oraa 128,sp - 19: aa f0 80 oraa 128,SP + 19: aa f0 80 oraa 0x80,SP orab \-128,sp - 1c: ea f1 80 orab \-128,SP + 1c: ea f1 80 orab 0xff80,SP orab 255,x - 1f: ea e0 ff orab 255,X + 1f: ea e0 ff orab 0xff,X orab \-256,x - 22: ea e1 00 orab \-256,X + 22: ea e1 00 orab 0xff00,X anda 256,x - 25: a4 e2 01 00 anda 256,X + 25: a4 e2 01 00 anda 0x100,X andb \-257,x - 29: e4 e2 fe ff andb \-257,X + 29: e4 e2 fe ff andb 0xfeff,X anda \[12,x\] ; Indexed indirect \(16\-bit offset\) - 2d: a4 e3 00 0c anda \[12,X\] + 2d: a4 e3 00 0c anda \[0xc,X\] ldaa \[257,y\] - 31: a6 eb 01 01 ldaa \[257,Y\] + 31: a6 eb 01 01 ldaa \[0x101,Y\] ldab \[32767,sp\] - 35: e6 f3 7f ff ldab \[32767,SP\] + 35: e6 f3 7f ff ldab \[0x7fff,SP\] ldd \[32768,pc\] - 39: ec fb 80 00 ldd \[32768,PC\] + 39: ec fb 80 00 ldd \[0x8000,PC\] ldd L1,pc - 3d: ec f9 c9 ldd -55,PC \{9 <L1>\} + 3d: ec f9 c9 ldd 0xffc9,PC \{0x9 <L1>\} std a,x ; Two\-reg index 40: 6c e4 std A,X ldx b,x @@ -96,92 +96,92 @@ L1: ldy ,x std \[d,pc\] 64: 6c ff std \[D,PC\] beq L1 - 66: 27 a1 beq 9 <L1> + 66: 27 a1 beq 0x9 <L1> lbeq start - 68: 18 27 ff 94 lbeq 0 <start> + 68: 18 27 ff 94 lbeq 0x0 <start> lbcc L2 - 6c: 18 24 00 4c lbcc bc <L2> + 6c: 18 24 00 4c lbcc 0xbc <L2> ;; ;; Move insn with various operands ;; movb start, 1,x - 70: 18 09 01 00 movb 0 <start>, 1,X + 70: 18 09 01 00 movb 0x0 <start>, 0x1,X 74: 00 movw 1,x, start - 75: 18 05 01 00 movw 1,X, 0 <start> + 75: 18 05 01 00 movw 0x1,X, 0x0 <start> 79: 00 movb start, 1,\+x - 7a: 18 09 20 00 movb 0 <start>, 1,\+X + 7a: 18 09 20 00 movb 0x0 <start>, 1,\+X 7e: 00 movb start, 1,\-x - 7f: 18 09 2f 00 movb 0 <start>, 1,\-X + 7f: 18 09 2f 00 movb 0x0 <start>, 1,\-X 83: 00 movb #23, 1,\-sp - 84: 18 08 af 17 movb #23, 1,\-SP + 84: 18 08 af 17 movb #0x17, 1,\-SP movb L1, L2 - 88: 18 0c 00 00 movb 0 <start>, 0 <start> + 88: 18 0c 00 00 movb 0x0 <start>, 0x0 <start> 8c: 00 00 movb L1, a,x - 8e: 18 09 e4 00 movb 0 <start>, A,X + 8e: 18 09 e4 00 movb 0x0 <start>, A,X 92: 00 movw L1, b,x - 93: 18 01 e5 00 movw 0 <start>, B,X + 93: 18 01 e5 00 movw 0x0 <start>, B,X 97: 00 movw L1, d,x - 98: 18 01 e6 00 movw 0 <start>, D,X + 98: 18 01 e6 00 movw 0x0 <start>, D,X 9c: 00 movw d,x, a,x 9d: 18 02 e6 e4 movw D,X, A,X movw b,sp, d,pc a1: 18 02 f5 fe movw B,SP, D,PC movw b,sp, L1 - a5: 18 05 f5 00 movw B,SP, 0 <start> + a5: 18 05 f5 00 movw B,SP, 0x0 <start> a9: 00 movw b,sp, 1,x - aa: 18 02 f5 01 movw B,SP, 1,X + aa: 18 02 f5 01 movw B,SP, 0x1,X movw d,x, a,y ae: 18 02 e6 ec movw D,X, A,Y trap #0x30 - b2: 18 30 trap #48 + b2: 18 30 trap #0x30 trap #0x39 - b4: 18 39 trap #57 + b4: 18 39 trap #0x39 trap #0x40 - b6: 18 40 trap #64 + b6: 18 40 trap #0x40 trap #0x80 - b8: 18 80 trap #128 + b8: 18 80 trap #0x80 trap #255 - ba: 18 ff trap #255 + ba: 18 ff trap #0xff 0+bc <L2>: L2: movw 1,x,2,x - bc: 18 02 01 02 movw 1,X, 2,X + bc: 18 02 01 02 movw 0x1,X, 0x2,X movw \-1,\-1 - c0: 18 04 ff ff movw ffff <bb\+0xd7ff>, ffff <bb\+0xd7ff> + c0: 18 04 ff ff movw 0xffff <bb\+0xd7ff>, 0xffff <bb\+0xd7ff> c4: ff ff movw \-1,1,x - c6: 18 01 01 ff movw ffff <bb\+0xd7ff>, 1,X + c6: 18 01 01 ff movw 0xffff <bb\+0xd7ff>, 0x1,X ca: ff movw #\-1,1,x - cb: 18 00 01 ff movw #ffff <bb\+0xd7ff>, 1,X + cb: 18 00 01 ff movw #0xffff <bb\+0xd7ff>, 0x1,X cf: ff movw 3,8 - d0: 18 04 00 03 movw 3 <start\+0x3>, 8 <start\+0x8> + d0: 18 04 00 03 movw 0x3 <start\+0x3>, 0x8 <start\+0x8> d4: 00 08 movw #3,3 - d6: 18 03 00 03 movw #3 <start\+0x3>, 3 <start\+0x3> + d6: 18 03 00 03 movw #0x3 <start\+0x3>, 0x3 <start\+0x3> da: 00 03 movw #3,1,x - dc: 18 00 01 00 movw #3 <start\+0x3>, 1,X + dc: 18 00 01 00 movw #0x3 <start\+0x3>, 0x1,X e0: 03 movw 3,1,x - e1: 18 01 01 00 movw 3 <start\+0x3>, 1,X + e1: 18 01 01 00 movw 0x3 <start\+0x3>, 0x1,X e5: 03 movw 3,\+2,x - e6: 18 01 02 00 movw 3 <start\+0x3>, 2,X + e6: 18 01 02 00 movw 0x3 <start\+0x3>, 0x2,X ea: 03 movw 4,\-2,x - eb: 18 01 1e 00 movw 4 <start\+0x4>, \-2,X + eb: 18 01 1e 00 movw 0x4 <start\+0x4>, 0xfffe,X ef: 04 rts f0: 3d rts @@ -193,50 +193,50 @@ L2: post_indexed_pb: t1: leas abort,x - f1: 1b e2 00 00 leas 0,X + f1: 1b e2 00 00 leas 0x0,X 0+f5 <t2>: t2: leax t2\-t1,y - f5: 1a 44 leax 4,Y + f5: 1a 44 leax 0x4,Y leax toto,x - f7: 1a e0 64 leax 100,X + f7: 1a e0 64 leax 0x64,X leas toto\+titi,sp - fa: 1b f0 6e leas 110,SP + fa: 1b f0 6e leas 0x6e,SP leay titi,x - fd: 19 0a leay 10,X + fd: 19 0a leay 0xa,X leas bb,y - ff: 1b ea 28 00 leas 10240,Y + ff: 1b ea 28 00 leas 0x2800,Y leas min5b,pc - 103: 1b d0 leas -16,PC \{f5 <t2>\} + 103: 1b d0 leas 0xfff0,PC \{0xf5 <t2>\} leas max5b,pc - 105: 1b cf leas 15,PC \{116 <t2\+0x21>\} + 105: 1b cf leas 0xf,PC \{0x116 <t2\+0x21>\} leas min9b,pc - 107: 1b fa ff 00 leas -256,PC \{b <L1\+0x2>\} + 107: 1b fa ff 00 leas 0xff00,PC \{0xb <L1\+0x2>\} leas max9b,pc - 10b: 1b f8 ff leas 255,PC \{20d <L0\+0xd9>\} + 10b: 1b f8 ff leas 0xff,PC \{0x20d <L0\+0xd9>\} ;; ;; Disassembler bug with movb ;; movb #23,0x2345 - 10e: 18 0b 17 23 movb #23, 2345 <L0\+0x2211> + 10e: 18 0b 17 23 movb #0x17, 0x2345 <L0\+0x2211> 112: 45 movb #40,12,sp - 113: 18 08 8c 28 movb #40, 12,SP + 113: 18 08 8c 28 movb #0x28, 0xc,SP movb #39,3,\+sp - 117: 18 08 a2 27 movb #39, 3,\+SP + 117: 18 08 a2 27 movb #0x27, 3,\+SP movb #20,14,sp - 11b: 18 08 8e 14 movb #20, 14,SP + 11b: 18 08 8e 14 movb #0x14, 0xe,SP movw #0x3210,0x3456 - 11f: 18 03 32 10 movw #3210 <bb\+0xa10>, 3456 <bb\+0xc56> + 11f: 18 03 32 10 movw #0x3210 <bb\+0xa10>, 0x3456 <bb\+0xc56> 123: 34 56 movw #0x4040,12,sp - 125: 18 00 8c 40 movw #4040 <bb\+0x1840>, 12,SP + 125: 18 00 8c 40 movw #0x4040 <bb\+0x1840>, 0xc,SP 129: 40 movw #0x3900,3,\+sp - 12a: 18 00 a2 39 movw #3900 <bb\+0x1100>, 3,\+SP + 12a: 18 00 a2 39 movw #0x3900 <bb\+0x1100>, 3,\+SP 12e: 00 movw #0x2000,14,sp - 12f: 18 00 8e 20 movw #2000 <L0\+0x1ecc>, 14,SP + 12f: 18 00 8e 20 movw #0x2000 <L0\+0x1ecc>, 0xe,SP 133: 00 diff --git a/gas/testsuite/gas/m68hc11/opers12.d b/gas/testsuite/gas/m68hc11/opers12.d index 8f6de24..9f31bda 100644 --- a/gas/testsuite/gas/m68hc11/opers12.d +++ b/gas/testsuite/gas/m68hc11/opers12.d @@ -5,28 +5,28 @@ .*: +file format elf32\-m68hc12 Disassembly of section .text: -0+0+ <start> anda \[12,X\] -0+0004 <start\+0x4> ldaa #10 -0+0006 <start\+0x6> ldx 0+0+ <start> +0+0+ <start> anda \[0xc,X\] +0+0004 <start\+0x4> ldaa #0xa +0+0006 <start\+0x6> ldx 0x0+0+ <start> [ ]+7: R_M68HC12_16 L1 -0+0009 <L1> ldy 0,X -0+000b <L1\+0x2> addd 1,Y -0+000d <L1\+0x4> subd \-1,Y -0+000f <L1\+0x6> eora 15,Y -0+0011 <L1\+0x8> eora \-16,Y -0+0013 <L1\+0xa> eorb 16,Y -0+0016 <L1\+0xd> eorb \-17,Y -0+0019 <L1\+0x10> oraa 128,SP -0+001c <L1\+0x13> orab \-128,SP -0+001f <L1\+0x16> orab 255,X -0+0022 <L1\+0x19> orab \-256,X -0+0025 <L1\+0x1c> anda 256,X -0+0029 <L1\+0x20> andb \-257,X -0+002d <L1\+0x24> anda \[12,X\] -0+0031 <L1\+0x28> ldaa \[257,Y\] -0+0035 <L1\+0x2c> ldab \[32767,SP\] -0+0039 <L1\+0x30> ldd \[32768,PC\] -0+003d <L1\+0x34> ldd \-55,PC \{0+9 <L1>\} +0+0009 <L1> ldy 0x0,X +0+000b <L1\+0x2> addd 0x1,Y +0+000d <L1\+0x4> subd 0xffff,Y +0+000f <L1\+0x6> eora 0xf,Y +0+0011 <L1\+0x8> eora 0xfff0,Y +0+0013 <L1\+0xa> eorb 0x10,Y +0+0016 <L1\+0xd> eorb 0xffef,Y +0+0019 <L1\+0x10> oraa 0x80,SP +0+001c <L1\+0x13> orab 0xff80,SP +0+001f <L1\+0x16> orab 0xff,X +0+0022 <L1\+0x19> orab 0xff00,X +0+0025 <L1\+0x1c> anda 0x100,X +0+0029 <L1\+0x20> andb 0xfeff,X +0+002d <L1\+0x24> anda \[0xc,X\] +0+0031 <L1\+0x28> ldaa \[0x101,Y\] +0+0035 <L1\+0x2c> ldab \[0x7fff,SP\] +0+0039 <L1\+0x30> ldd \[0x8000,PC\] +0+003d <L1\+0x34> ldd 0xffc9,PC \{0x0+9 <L1>\} 0+0040 <L1\+0x37> std A,X 0+0042 <L1\+0x39> ldx B,X 0+0044 <L1\+0x3b> stx D,Y @@ -46,68 +46,68 @@ Disassembly of section .text: 0+0060 <L1\+0x57> std \[D,Y\] 0+0062 <L1\+0x59> std \[D,SP\] 0+0064 <L1\+0x5b> std \[D,PC\] -0+0066 <L1\+0x5d> beq 0+0009 <L1> +0+0066 <L1\+0x5d> beq 0x0+0009 <L1> [ ]+66: R_M68HC12_RL_JUMP \*ABS\* -0+0068 <L1\+0x5f> lbeq 0+0+ <start> +0+0068 <L1\+0x5f> lbeq 0x0+0 <start> [ ]+68: R_M68HC12_RL_JUMP \*ABS\* -0+006c <L1\+0x63> lbcc 0+00bc <L2> +0+006c <L1\+0x63> lbcc 0x0+00bc <L2> [ ]+6c: R_M68HC12_RL_JUMP \*ABS\* -0+0070 <L1\+0x67> movb 0+0+ <start>, 1,X +0+0070 <L1\+0x67> movb 0x0+0+ <start>, 0x1,X [ ]+73: R_M68HC12_16 start -0+0075 <L1\+0x6c> movw 1,X, 0+0+ <start> +0+0075 <L1\+0x6c> movw 0x1,X, 0x0+0+ <start> [ ]+78: R_M68HC12_16 start -0+007a <L1\+0x71> movb 0+0+ <start>, 1,\+X +0+007a <L1\+0x71> movb 0x0+0+ <start>, 1,\+X [ ]+7d: R_M68HC12_16 start -0+007f <L1\+0x76> movb 0+0+ <start>, 1,\-X +0+007f <L1\+0x76> movb 0x0+0+ <start>, 1,\-X [ ]+82: R_M68HC12_16 start -0+0084 <L1\+0x7b> movb #23, 1,\-SP -0+0088 <L1\+0x7f> movb 0+0+ <start>, 0+0+ <start> +0+0084 <L1\+0x7b> movb #0x17, 1,\-SP +0+0088 <L1\+0x7f> movb 0x0+0+ <start>, 0x0+0+ <start> [ ]+8a: R_M68HC12_16 L1 [ ]+8c: R_M68HC12_16 L2 -0+008e <L1\+0x85> movb 0+0+ <start>, A,X +0+008e <L1\+0x85> movb 0x0+0+ <start>, A,X [ ]+91: R_M68HC12_16 L1 -0+0093 <L1\+0x8a> movw 0+0+ <start>, B,X +0+0093 <L1\+0x8a> movw 0x0+0+ <start>, B,X [ ]+96: R_M68HC12_16 L1 -0+0098 <L1\+0x8f> movw 0+0+ <start>, D,X +0+0098 <L1\+0x8f> movw 0x0+0+ <start>, D,X [ ]+9b: R_M68HC12_16 L1 0+009d <L1\+0x94> movw D,X, A,X 0+00a1 <L1\+0x98> movw B,SP, D,PC -0+00a5 <L1\+0x9c> movw B,SP, 0+0+ <start> +0+00a5 <L1\+0x9c> movw B,SP, 0x0+0+ <start> [ ]+a8: R_M68HC12_16 L1 -0+00aa <L1\+0xa1> movw B,SP, 1,X +0+00aa <L1\+0xa1> movw B,SP, 0x1,X 0+00ae <L1\+0xa5> movw D,X, A,Y -0+00b2 <L1\+0xa9> trap #48 -0+00b4 <L1\+0xab> trap #57 -0+00b6 <L1\+0xad> trap #64 -0+00b8 <L1\+0xaf> trap #128 -0+00ba <L1\+0xb1> trap #255 -0+00bc <L2> movw 1,X, 2,X -0+00c0 <L2\+0x4> movw 0+ffff <bb\+0xd7ff>, 0+ffff <bb\+0xd7ff> -0+00c6 <L2\+0xa> movw 0+ffff <bb\+0xd7ff>, 1,X -0+00cb <L2\+0xf> movw #0+ffff <bb\+0xd7ff>, 1,X -0+00d0 <L2\+0x14> movw 0+0003 <start\+0x3>, 0+0008 <start\+0x8> -0+00d6 <L2\+0x1a> movw #0+0003 <start\+0x3>, 0+0003 <start\+0x3> -0+00dc <L2\+0x20> movw #0+0003 <start\+0x3>, 1,X -0+00e1 <L2\+0x25> movw 0+0003 <start\+0x3>, 1,X -0+00e6 <L2\+0x2a> movw 0+0003 <start\+0x3>, 2,X -0+00eb <L2\+0x2f> movw 0+0004 <start\+0x4>, \-2,X +0+00b2 <L1\+0xa9> trap #0x30 +0+00b4 <L1\+0xab> trap #0x39 +0+00b6 <L1\+0xad> trap #0x40 +0+00b8 <L1\+0xaf> trap #0x80 +0+00ba <L1\+0xb1> trap #0xff +0+00bc <L2> movw 0x1,X, 0x2,X +0+00c0 <L2\+0x4> movw 0x0+ffff <bb\+0xd7ff>, 0x0+ffff <bb\+0xd7ff> +0+00c6 <L2\+0xa> movw 0x0+ffff <bb\+0xd7ff>, 0x1,X +0+00cb <L2\+0xf> movw #0x0+ffff <bb\+0xd7ff>, 0x1,X +0+00d0 <L2\+0x14> movw 0x0+0003 <start\+0x3>, 0x0+0008 <start\+0x8> +0+00d6 <L2\+0x1a> movw #0x0+0003 <start\+0x3>, 0x0+0003 <start\+0x3> +0+00dc <L2\+0x20> movw #0x0+0003 <start\+0x3>, 0x1,X +0+00e1 <L2\+0x25> movw 0x0+0003 <start\+0x3>, 0x1,X +0+00e6 <L2\+0x2a> movw 0x0+0003 <start\+0x3>, 0x2,X +0+00eb <L2\+0x2f> movw 0x0+0004 <start\+0x4>, 0xfffe,X 0+00f0 <L2\+0x34> rts -0+00f1 <post_indexed_pb> leas 0,X +0+00f1 <post_indexed_pb> leas 0x0,X [ ]+f3: R_M68HC12_16 abort -0+00f5 <t2> leax 4,Y -0+00f7 <t2\+0x2> leax 100,X -0+00fa <t2\+0x5> leas 110,SP -0+00fd <t2\+0x8> leay 10,X -0+00ff <t2\+0xa> leas 10240,Y -0+0103 <t2\+0xe> leas -16,PC \{0+f5 <t2>\} -0+0105 <t2\+0x10> leas 15,PC \{0+116 <t2\+0x21>\} -0+0107 <t2\+0x12> leas -256,PC \{0+b <L1\+0x2>\} -0+010b <t2\+0x16> leas 255,PC \{0+20d <max9b\+0x10e>\} -0+010e <t2\+0x19> movb #23, 0+2345 <max9b\+0x2246> -0+0113 <t2\+0x1e> movb #40, 12,SP -0+0117 <t2\+0x22> movb #39, 3,\+SP -0+011b <t2\+0x26> movb #20, 14,SP -0+011f <t2\+0x2a> movw #0+3210 <bb\+0xa10>, 0+3456 <bb\+0xc56> -0+0125 <t2\+0x30> movw #0+4040 <bb\+0x1840>, 12,SP -0+012a <t2\+0x35> movw #0+3900 <bb\+0x1100>, 3,\+SP -0+012f <t2\+0x3a> movw #0+2000 <max9b\+0x1f01>, 14,SP +0+00f5 <t2> leax 0x4,Y +0+00f7 <t2\+0x2> leax 0x64,X +0+00fa <t2\+0x5> leas 0x6e,SP +0+00fd <t2\+0x8> leay 0xa,X +0+00ff <t2\+0xa> leas 0x2800,Y +0+0103 <t2\+0xe> leas 0xfff0,PC \{0x0+f5 <t2>\} +0+0105 <t2\+0x10> leas 0xf,PC \{0x0+116 <t2\+0x21>\} +0+0107 <t2\+0x12> leas 0xff00,PC \{0x0+b <L1\+0x2>\} +0+010b <t2\+0x16> leas 0xff,PC \{0x0+20d <max9b\+0x10e>\} +0+010e <t2\+0x19> movb #0x17, 0x0+2345 <max9b\+0x2246> +0+0113 <t2\+0x1e> movb #0x28, 0xc,SP +0+0117 <t2\+0x22> movb #0x27, 3,\+SP +0+011b <t2\+0x26> movb #0x14, 0xe,SP +0+011f <t2\+0x2a> movw #0x0+3210 <bb\+0xa10>, 0x0+3456 <bb\+0xc56> +0+0125 <t2\+0x30> movw #0x0+4040 <bb\+0x1840>, 0xc,SP +0+012a <t2\+0x35> movw #0x0+3900 <bb\+0x1100>, 3,\+SP +0+012f <t2\+0x3a> movw #0x0+2000 <max9b\+0x1f01>, 0xe,SP diff --git a/include/ChangeLog b/include/ChangeLog index 7a747a7..8853386 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + + * dis-asm.h (print_insn_m9s12x): Prototype. + (print_insn_m9s12xg): Prototype. + 2012-05-03 Sean Keys <skeys@ipdatasys.com> * dis-asm.h (print_insn_xgate): Define. diff --git a/include/dis-asm.h b/include/dis-asm.h index 203b113..f9c8ae9 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -260,6 +260,8 @@ extern int print_insn_m32c (bfd_vma, disassemble_info *); extern int print_insn_m32r (bfd_vma, disassemble_info *); extern int print_insn_m68hc11 (bfd_vma, disassemble_info *); extern int print_insn_m68hc12 (bfd_vma, disassemble_info *); +extern int print_insn_m9s12x (bfd_vma, disassemble_info *); +extern int print_insn_m9s12xg (bfd_vma, disassemble_info *); extern int print_insn_m68k (bfd_vma, disassemble_info *); extern int print_insn_m88k (bfd_vma, disassemble_info *); extern int print_insn_mcore (bfd_vma, disassemble_info *); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 81ae20d..8e476b7 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,9 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + + * m68hc11.h (R_M68HC12_16B, R_M68HC12_PCREL_9, R_M68HC12_PCREL_10) + R_M68HC12_HI8XG, R_M68HC12_LO8XG): New relocations. + (E_M68HC11_XGATE_RAMOFFSET): Define. + 2012-05-14 James Lemke <jwlemke@codesourcery.com> * ppc.h (SEC_PPC_VLE): Remove. diff --git a/include/elf/m68hc11.h b/include/elf/m68hc11.h index ca325d9..9a37a44 100644 --- a/include/elf/m68hc11.h +++ b/include/elf/m68hc11.h @@ -1,5 +1,5 @@ /* m68hc11 & m68hc12 ELF support for BFD. - Copyright 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001, 2002, 2010, 2012 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -42,6 +42,12 @@ START_RELOC_NUMBERS (elf_m68hc11_reloc_type) RELOC_NUMBER (R_M68HC11_LO16, 12) RELOC_NUMBER (R_M68HC11_PAGE, 13) + RELOC_NUMBER (R_M68HC12_16B, 15) + RELOC_NUMBER (R_M68HC12_PCREL_9, 16) + RELOC_NUMBER (R_M68HC12_PCREL_10, 17) + RELOC_NUMBER (R_M68HC12_HI8XG, 18) + RELOC_NUMBER (R_M68HC12_LO8XG, 19) + /* GNU extension for linker relaxation. Mark beginning of a jump instruction (any form). */ RELOC_NUMBER (R_M68HC11_RL_JUMP, 20) @@ -64,6 +70,9 @@ END_RELOC_NUMBERS (R_M68HC11_max) /* Uses 68HC12 memory banks. */ #define E_M68HC12_BANKS 0x000000004 +/* XGATE ram offsetting. */ +#define E_M68HC11_XGATE_RAMOFFSET 0x000000100 + #define EF_M68HC11_MACH_MASK 0xF0 #define EF_M68HC11_GENERIC 0x00 /* Generic 68HC12/backward compatibility. */ #define EF_M68HC12_MACH 0x10 /* 68HC12 microcontroller. */ @@ -86,10 +95,10 @@ END_RELOC_NUMBERS (R_M68HC11_max) /* Special values for the st_other field in the symbol table. These are used for 68HC12 to identify far functions (must be called with 'call' and returns with 'rtc'). */ -#define STO_M68HC12_FAR 0x80 +#define STO_M68HC12_FAR 0x80 /* Identify interrupt handlers. This is used by the debugger to correctly compute the stack frame. */ -#define STO_M68HC12_INTERRUPT 0x40 +#define STO_M68HC12_INTERRUPT 0x40 #endif diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 7160f10..209a472 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,8 +1,13 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + + * m68hc11.h: Add XGate definitions. + (struct m68hc11_opcode): Add xg_mask field. + 2012-05-14 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Rhonda Wittels <rhonda@codesourcery.com> - * ppc.h (PPC_OPCODE_VLE): New definition. + * ppc.h (PPC_OPCODE_VLE): New definition. (PPC_OP_SA): New macro. (PPC_OP_SE_VLE): New macro. (PPC_OP): Use a variable shift amount. diff --git a/include/opcode/m68hc11.h b/include/opcode/m68hc11.h index 83f5a9a..1a00200 100644 --- a/include/opcode/m68hc11.h +++ b/include/opcode/m68hc11.h @@ -1,5 +1,6 @@ /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table - Copyright 1999, 2000, 2002, 2003, 2010 Free Software Foundation, Inc. + Copyright 1999, 2000, 2002, 2003, 2010, 2012 + Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. @@ -37,8 +38,7 @@ of the M6811_INIT register. At init time, the I/O registers are mapped at 0x1000. Address of registers is then: - 0x1000 + M6811_xxx -*/ + 0x1000 + M6811_xxx. */ #define M6811_PORTA 0x00 /* Port A register */ #define M6811__RES1 0x01 /* Unused/Reserved */ #define M6811_PIOC 0x02 /* Parallel I/O Control register */ @@ -364,6 +364,26 @@ #define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ #define M6812_OP_IDX_P2 0x40000000 +/* XGATE defines. + These overlap with HC11/12 as above but not used at the same time. */ +#define M68XG_OP_NONE 0x0001 +#define M68XG_OP_IMM3 0x0002 +#define M68XG_OP_R 0x0004 +#define M68XG_OP_R_R 0x0008 +#define M68XG_OP_R_IMM4 0x0010 +#define M68XG_OP_R_R_R 0x0020 +#define M68XG_OP_REL9 0x0040 +#define M68XG_OP_REL10 0x0080 +#define M68XG_OP_R_R_OFFS5 0x0100 +#define M68XG_OP_RD_RB_RI 0x0200 +#define M68XG_OP_RD_RB_RIp 0x0400 +#define M68XG_OP_RD_RB_mRI 0x0800 +#define M68XG_OP_R_IMM8 0x1000 +#define M68XG_OP_R_IMM16 0x2000 +#define M68XG_OP_REG 0x4000 /* Register operand 1. */ +#define M68XG_OP_REG_2 0x8000 /* Register operand 2. */ +#define M68XG_MAX_OPERANDS 3 /* Max operands of triadic r1, r2, r3. */ + /* Markers to identify some instructions. */ #define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ #define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ @@ -374,35 +394,43 @@ #define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ #define M6812_OP_TBCC_MARKER 0x01000000 +/* XGATE markers. */ +#define M68XG_OP_B_MARKER 0x04000000 /* bXX rel9 */ +#define M68XG_OP_BRA_MARKER 0x02000000 /* bra rel10 */ + #define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ #define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ #define M6811_OP_LOW_ADDR 0x02000000 -#define M68HC12_BANK_VIRT 0x010000 -#define M68HC12_BANK_MASK 0x00003fff -#define M68HC12_BANK_BASE 0x00008000 -#define M68HC12_BANK_SHIFT 14 -#define M68HC12_BANK_PAGE_MASK 0x0ff +#define M68HC12_BANK_VIRT 0x010000 +#define M68HC12_BANK_MASK 0x00003fff +#define M68HC12_BANK_BASE 0x00008000 +#define M68HC12_BANK_SHIFT 14 +#define M68HC12_BANK_PAGE_MASK 0x0ff /* CPU identification. */ #define cpu6811 0x01 #define cpu6812 0x02 #define cpu6812s 0x04 +#define cpu9s12x 0x08 /* 9S12X main cpu. */ +#define cpuxgate 0x10 /* The XGATE module itself. */ /* The opcode table is an array of struct m68hc11_opcode. */ -struct m68hc11_opcode { - const char* name; /* Op-code name */ +struct m68hc11_opcode +{ + const char * name; /* Op-code name. */ long format; unsigned char size; - unsigned char opcode; + unsigned int opcode; unsigned char cycles_low; unsigned char cycles_high; unsigned char set_flags_mask; unsigned char clr_flags_mask; unsigned char chg_flags_mask; unsigned char arch; + unsigned int xg_mask; /* Mask with zero in register place for xgate. */ }; /* Alias definition for 68HC12. */ diff --git a/ld/ChangeLog b/ld/ChangeLog index b93216c..eff6cf3 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,7 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + + * NEWS: Mention the support for S12X processors. + 2012-05-14 James Lemke <jwlemke@codesourcery.com> * ldlang.c (walk_wild_consider_section): Don't copy section_flag_list. @@ -1,5 +1,7 @@ -*- text -*- +* Add support for S12X processor. + * Add support for the VLE extension to the PowerPC architecture. * Add support for the Freescale XGATE architecture. diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 050115a..610d75a 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,18 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + + * ld-m68hc11/xgate-link.s: New. + * ld-m68hc11/xgate-link.d: New. + * ld-m68hc11/xgate-offset.s: New. + * ld-m68hc11/xgate-offset.d: New. + * ld-m68hc11/xgate1.s: New. + * ld-m68hc11/xgate1.d: New. + * ld-m68hc11/xgate2.s: New. + * ld-m68hc11/m68hc11.exp: Updated. + * ld-m68hc11/*.d: Brought in line with changed objdump output. + * ld-gc/gc.exp: Update CFLAGS for m68hc11. + * ld-plugin/plugin.exp: Likewise. + * ld-srec/srec.exp: XFAIL for m68hc11 and m68hc12. + 2012-05-14 David S. Miller <davem@davemloft.net> * ld-sparc/tlssunbin32.rd: Update. diff --git a/ld/testsuite/ld-gc/gc.exp b/ld/testsuite/ld-gc/gc.exp index 996eac4..7a59ad3 100644 --- a/ld/testsuite/ld-gc/gc.exp +++ b/ld/testsuite/ld-gc/gc.exp @@ -32,6 +32,11 @@ if [istarget powerpc64*-*-*] { set cflags "$cflags -mminimal-toc" } +if { [istarget m681*-*-*] || [istarget m68hc1*-*-*] } { + # Otherwise tests FAIL due to _.frame + set cflags "$cflags -fomit-frame-pointer -mshort" +} + if { [is_remote host] || [which $CC] != 0 } { ld_compile "$CC -c $CFLAGS $cflags" $srcdir/$subdir/gc.c $objfile } diff --git a/ld/testsuite/ld-m68hc11/adj-brset.d b/ld/testsuite/ld-m68hc11/adj-brset.d index a6306cf..fbda304 100644 --- a/ld/testsuite/ld-m68hc11/adj-brset.d +++ b/ld/testsuite/ld-m68hc11/adj-brset.d @@ -6,26 +6,26 @@ .*: +file format elf32\-m68hc11 Disassembly of section .text: -0+8000 <_start> brclr 140,x \#\$c8 0+804a <L8> -0+8004 <L1> addd \*0+4 <_toto> -0+8006 <L1\+0x2> brclr 20,x \#\$03 0+8004 <L1> -0+800a <L1\+0x6> brclr 90,x \#\$63 0+801a <L3> -0+800e <L2> addd \*0+4 <_toto> -0+8010 <L2\+0x2> brclr 19,y \#\$04 0+800e <L2> -0+8015 <L2\+0x7> brclr 91,y \#\$62 0+8024 <L4> -0+801a <L3> addd \*0+4 <_toto> -0+801c <L3\+0x2> brset 18,x \#\$05 0+801a <L3> -0+8020 <L3\+0x6> brset 92,x \#\$61 0+8030 <L5> -0+8024 <L4> addd \*0+4 <_toto> -0+8026 <L4\+0x2> brset 17,y \#\$06 0+8024 <L4> -0+802b <L4\+0x7> brset 93,y \#\$60 0+8030 <L5> -0+8030 <L5> addd \*0+4 <_toto> -0+8032 <L5\+0x2> brset \*0+32 <_table> \#\$07 0+8030 <L5> -0+8036 <L5\+0x6> brset \*0+3c <_table\+0xa> \#\$5f 0+8044 <L7> -0+803a <L6> addd \*0+4 <_toto> -0+803c <L6\+0x2> brclr \*0+33 <_table\+0x1> \#\$08 0+803a <L6> -0+8040 <L6\+0x6> brset \*0+3d <_table\+0xb> \#\$5e 0+804a <L8> -0+8044 <L7> addd \*0+4 <_toto> -0+8046 <L7\+0x2> brclr \*0+33 <_table\+0x1> \#\$08 0+803a <L6> -0+804a <L8> brclr 140,x \#\$c8 0+8000 <_start> +0+8000 <_start> brclr 0x8c,x, #0xc8, 0x0+804a <L8> +0+8004 <L1> addd \*0x0+4 <_toto> +0+8006 <L1\+0x2> brclr 0x14,x, \#0x03, 0x0+8004 <L1> +0+800a <L1\+0x6> brclr 0x5a,x, \#0x63, 0x0+801a <L3> +0+800e <L2> addd \*0x0+4 <_toto> +0+8010 <L2\+0x2> brclr 0x13,y, \#0x04, 0x0+800e <L2> +0+8015 <L2\+0x7> brclr 0x5b,y, \#0x62, 0x0+8024 <L4> +0+801a <L3> addd \*0x0+4 <_toto> +0+801c <L3\+0x2> brset 0x12,x, \#0x05, 0x0+801a <L3> +0+8020 <L3\+0x6> brset 0x5c,x, \#0x61, 0x0+8030 <L5> +0+8024 <L4> addd \*0x0+4 <_toto> +0+8026 <L4\+0x2> brset 0x11,y, \#0x06, 0x0+8024 <L4> +0+802b <L4\+0x7> brset 0x5d,y, \#0x60, 0x0+8030 <L5> +0+8030 <L5> addd \*0x0+4 <_toto> +0+8032 <L5\+0x2> brset \*0x0+32 <_table>, \#0x07, 0x0+8030 <L5> +0+8036 <L5\+0x6> brset \*0x0+3c <_table\+0xa>, \#0x5f, 0x0+8044 <L7> +0+803a <L6> addd \*0x0+4 <_toto> +0+803c <L6\+0x2> brclr \*0x0+33 <_table\+0x1>, \#0x08, 0x0+803a <L6> +0+8040 <L6\+0x6> brset \*0x0+3d <_table\+0xb>, \#0x5e, 0x0+804a <L8> +0+8044 <L7> addd \*0x0+4 <_toto> +0+8046 <L7\+0x2> brclr \*0x0+33 <_table\+0x1>, \#0x08, 0x0+803a <L6> +0+804a <L8> brclr 0x8c,x, \#0xc8, 0x0+8000 <_start> 0+804e <L8\+0x4> rts diff --git a/ld/testsuite/ld-m68hc11/adj-jump.d b/ld/testsuite/ld-m68hc11/adj-jump.d index da181bd..cca407f 100644 --- a/ld/testsuite/ld-m68hc11/adj-jump.d +++ b/ld/testsuite/ld-m68hc11/adj-jump.d @@ -6,54 +6,54 @@ .*: +file format elf32\-m68hc11 Disassembly of section .text: -0+8000 <_start> bra 0+8074 <L3> +0+8000 <_start> bra 0x0+8074 <L3> ... -0+8016 <_start\+0x16> bra 0+8074 <L3> -0+8018 <L1> addd 0,x -0+801a <L1\+0x2> bne 0+8018 <L1> -0+801c <L1\+0x4> addd \*0+4 <_toto> -0+801e <L1\+0x6> beq 0+8018 <L1> -0+8020 <L1\+0x8> addd \*0+5 <_toto\+0x1> -0+8022 <L1\+0xa> bne 0+8018 <L1> -0+8024 <L1\+0xc> bgt 0+8018 <L1> -0+8026 <L1\+0xe> bge 0+8018 <L1> -0+8028 <L1\+0x10> beq 0+8018 <L1> -0+802a <L1\+0x12> ble 0+8018 <L1> -0+802c <L1\+0x14> blt 0+8018 <L1> -0+802e <L1\+0x16> bhi 0+8018 <L1> -0+8030 <L1\+0x18> bcc 0+8018 <L1> -0+8032 <L1\+0x1a> beq 0+8018 <L1> -0+8034 <L1\+0x1c> bls 0+8018 <L1> -0+8036 <L1\+0x1e> bcs 0+8018 <L1> -0+8038 <L1\+0x20> bcs 0+8018 <L1> -0+803a <L1\+0x22> bmi 0+8018 <L1> -0+803c <L1\+0x24> bvs 0+8018 <L1> -0+803e <L1\+0x26> bcc 0+8018 <L1> -0+8040 <L1\+0x28> bpl 0+8018 <L1> -0+8042 <L1\+0x2a> bvc 0+8018 <L1> -0+8044 <L1\+0x2c> bne 0+8018 <L1> -0+8046 <L1\+0x2e> brn 0+8018 <L1> -0+8048 <L1\+0x30> bra 0+8018 <L1> -0+804a <L1\+0x32> addd \*0+4 <_toto> -0+804c <L1\+0x34> addd \*0+4 <_toto> -0+804e <L1\+0x36> addd \*0+4 <_toto> -0+8050 <L1\+0x38> addd \*0+4 <_toto> -0+8052 <L1\+0x3a> addd \*0+4 <_toto> -0+8054 <L1\+0x3c> addd \*0+4 <_toto> -0+8056 <L1\+0x3e> addd \*0+4 <_toto> -0+8058 <L1\+0x40> addd \*0+4 <_toto> -0+805a <L1\+0x42> addd \*0+4 <_toto> -0+805c <L1\+0x44> addd \*0+4 <_toto> -0+805e <L1\+0x46> addd \*0+4 <_toto> -0+8060 <L1\+0x48> addd \*0+4 <_toto> -0+8062 <L1\+0x4a> addd \*0+4 <_toto> -0+8064 <L1\+0x4c> addd \*0+4 <_toto> -0+8066 <L1\+0x4e> addd \*0+4 <_toto> -0+8068 <L2> bra 0+8000 <_start> -0+806a <L2\+0x2> bne 0+8068 <L2> -0+806c <L2\+0x4> beq 0+8074 <L3> -0+806e <L2\+0x6> addd \*0+4 <_toto> -0+8070 <L2\+0x8> beq 0+8074 <L3> -0+8072 <L2\+0xa> addd \*0+4 <_toto> -0+8074 <L3> addd \*0+4 <_toto> +0+8016 <_start\+0x16> bra 0x0+8074 <L3> +0+8018 <L1> addd 0x0,x +0+801a <L1\+0x2> bne 0x0+8018 <L1> +0+801c <L1\+0x4> addd \*0x0+4 <_toto> +0+801e <L1\+0x6> beq 0x0+8018 <L1> +0+8020 <L1\+0x8> addd \*0x0+5 <_toto\+0x1> +0+8022 <L1\+0xa> bne 0x0+8018 <L1> +0+8024 <L1\+0xc> bgt 0x0+8018 <L1> +0+8026 <L1\+0xe> bge 0x0+8018 <L1> +0+8028 <L1\+0x10> beq 0x0+8018 <L1> +0+802a <L1\+0x12> ble 0x0+8018 <L1> +0+802c <L1\+0x14> blt 0x0+8018 <L1> +0+802e <L1\+0x16> bhi 0x0+8018 <L1> +0+8030 <L1\+0x18> bcc 0x0+8018 <L1> +0+8032 <L1\+0x1a> beq 0x0+8018 <L1> +0+8034 <L1\+0x1c> bls 0x0+8018 <L1> +0+8036 <L1\+0x1e> bcs 0x0+8018 <L1> +0+8038 <L1\+0x20> bcs 0x0+8018 <L1> +0+803a <L1\+0x22> bmi 0x0+8018 <L1> +0+803c <L1\+0x24> bvs 0x0+8018 <L1> +0+803e <L1\+0x26> bcc 0x0+8018 <L1> +0+8040 <L1\+0x28> bpl 0x0+8018 <L1> +0+8042 <L1\+0x2a> bvc 0x0+8018 <L1> +0+8044 <L1\+0x2c> bne 0x0+8018 <L1> +0+8046 <L1\+0x2e> brn 0x0+8018 <L1> +0+8048 <L1\+0x30> bra 0x0+8018 <L1> +0+804a <L1\+0x32> addd \*0x0+4 <_toto> +0+804c <L1\+0x34> addd \*0x0+4 <_toto> +0+804e <L1\+0x36> addd \*0x0+4 <_toto> +0+8050 <L1\+0x38> addd \*0x0+4 <_toto> +0+8052 <L1\+0x3a> addd \*0x0+4 <_toto> +0+8054 <L1\+0x3c> addd \*0x0+4 <_toto> +0+8056 <L1\+0x3e> addd \*0x0+4 <_toto> +0+8058 <L1\+0x40> addd \*0x0+4 <_toto> +0+805a <L1\+0x42> addd \*0x0+4 <_toto> +0+805c <L1\+0x44> addd \*0x0+4 <_toto> +0+805e <L1\+0x46> addd \*0x0+4 <_toto> +0+8060 <L1\+0x48> addd \*0x0+4 <_toto> +0+8062 <L1\+0x4a> addd \*0x0+4 <_toto> +0+8064 <L1\+0x4c> addd \*0x0+4 <_toto> +0+8066 <L1\+0x4e> addd \*0x0+4 <_toto> +0+8068 <L2> bra 0x0+8000 <_start> +0+806a <L2\+0x2> bne 0x0+8068 <L2> +0+806c <L2\+0x4> beq 0x0+8074 <L3> +0+806e <L2\+0x6> addd \*0x0+4 <_toto> +0+8070 <L2\+0x8> beq 0x0+8074 <L3> +0+8072 <L2\+0xa> addd \*0x0+4 <_toto> +0+8074 <L3> addd \*0x0+4 <_toto> 0+8076 <L3\+0x2> rts diff --git a/ld/testsuite/ld-m68hc11/bug-1403.d b/ld/testsuite/ld-m68hc11/bug-1403.d index dfd69b0..16f6e19 100644 --- a/ld/testsuite/ld-m68hc11/bug-1403.d +++ b/ld/testsuite/ld-m68hc11/bug-1403.d @@ -6,6 +6,6 @@ .*: +file format elf32-m68hc11 Disassembly of section .text: -0+8000 <_start> bset \*0+ <__bss_size> \#\$04 -0+8003 <L1> bra 0+8005 <toto> +0+8000 <_start> bset \*0x0+ <__bss_size>, \#0x04 +0+8003 <L1> bra 0x0+8005 <toto> 0+8005 <toto> rts diff --git a/ld/testsuite/ld-m68hc11/bug-1417.d b/ld/testsuite/ld-m68hc11/bug-1417.d index 1947506..942ba63 100644 --- a/ld/testsuite/ld-m68hc11/bug-1417.d +++ b/ld/testsuite/ld-m68hc11/bug-1417.d @@ -6,9 +6,9 @@ .*: +file format elf32-m68hc11 Disassembly of section .text: -0+8000 <_start> tst 0+ <__bss_size> -0+8003 <_start\+0x3> bne 0+8007 <L1> -0+8005 <_start\+0x5> bsr 0+800b <foo> -0+8007 <L1> bset \*0+ <__bss_size> \#\$04 +0+8000 <_start> tst 0x0+ <__bss_size> +0+8003 <_start\+0x3> bne 0x0+8007 <L1> +0+8005 <_start\+0x5> bsr 0x0+800b <foo> +0+8007 <L1> bset \*0x0+ <__bss_size>, \#0x04 0+800a <L2> rts 0+800b <foo> rts diff --git a/ld/testsuite/ld-m68hc11/bug-3331.d b/ld/testsuite/ld-m68hc11/bug-3331.d index cee93ab..6f72313 100644 --- a/ld/testsuite/ld-m68hc11/bug-3331.d +++ b/ld/testsuite/ld-m68hc11/bug-3331.d @@ -6,8 +6,8 @@ .*: +file format elf32-m68hc11 Disassembly of section .text: -0+8000 <_start> ldx #0+1100 <__data_section_start> -0+8003 <_start\+0x3> bset 0,x \#\$04 -0+8006 <L1> ldd \#0+2 <__bss_size\+0x2> -0+8009 <L1\+0x3> std \*0+ <__bss_size> +0+8000 <_start> ldx #0x0+1100 <__data_section_start> +0+8003 <_start\+0x3> bset 0x0,x, \#0x04 +0+8006 <L1> ldd \#0x0+2 <__bss_size\+0x2> +0+8009 <L1\+0x3> std \*0x0+ <__bss_size> 0+800b <L1\+0x5> rts diff --git a/ld/testsuite/ld-m68hc11/far-hc11.d b/ld/testsuite/ld-m68hc11/far-hc11.d index d563356..b93bb63 100644 --- a/ld/testsuite/ld-m68hc11/far-hc11.d +++ b/ld/testsuite/ld-m68hc11/far-hc11.d @@ -7,66 +7,66 @@ Disassembly of section .text: 0+8000 <tramp._far_foo> pshb -0+8001 <tramp._far_foo\+0x1> ldab \#0 -0+8003 <tramp._far_foo\+0x3> ldy \#0+8072 <_far_foo> -0+8007 <tramp._far_foo\+0x7> jmp 0+8056 <__far_trampoline> +0+8001 <tramp._far_foo\+0x1> ldab \#0x0 +0+8003 <tramp._far_foo\+0x3> ldy \#0x0+8072 <_far_foo> +0+8007 <tramp._far_foo\+0x7> jmp 0x0+8056 <__far_trampoline> 0+800a <tramp._far_bar> pshb -0+800b <tramp._far_bar\+0x1> ldab \#0 -0+800d <tramp._far_bar\+0x3> ldy \#0+806a .* -0+8011 <tramp._far_bar\+0x7> jmp 0+8056 <__far_trampoline> -0+8014 <_start> lds \#0+64 <stack> -0+8017 <_start\+0x3> ldx \#0+abcd .* +0+800b <tramp._far_bar\+0x1> ldab \#0x0 +0+800d <tramp._far_bar\+0x3> ldy \#0x0+806a .* +0+8011 <tramp._far_bar\+0x7> jmp 0x0+8056 <__far_trampoline> +0+8014 <_start> lds \#0x0+64 <stack> +0+8017 <_start\+0x3> ldx \#0x0+abcd .* 0+801a <_start\+0x6> pshx -0+801b <_start\+0x7> ldd \#0+1234 .* -0+801e <_start\+0xa> ldx \#0+5678 .* -0+8021 <_start\+0xd> jsr 0+800a <tramp._far_bar> -0+8024 <_start\+0x10> cpx \#0+1234 .* -0+8027 <_start\+0x13> bne 0+804e <fail> -0+8029 <_start\+0x15> cpd \#0+5678 .* -0+802d <_start\+0x19> bne 0+804e <fail> +0+801b <_start\+0x7> ldd \#0x0+1234 .* +0+801e <_start\+0xa> ldx \#0x0+5678 .* +0+8021 <_start\+0xd> jsr 0x0+800a <tramp._far_bar> +0+8024 <_start\+0x10> cpx \#0x0+1234 .* +0+8027 <_start\+0x13> bne 0x0+804e <fail> +0+8029 <_start\+0x15> cpd \#0x0+5678 .* +0+802d <_start\+0x19> bne 0x0+804e <fail> 0+802f <_start\+0x1b> pulx -0+8030 <_start\+0x1c> cpx \#0+abcd .* -0+8033 <_start\+0x1f> bne 0+804e <fail> -0+8035 <_start\+0x21> ldd \#0+8000 <tramp._far_foo> +0+8030 <_start\+0x1c> cpx \#0x0+abcd .* +0+8033 <_start\+0x1f> bne 0x0+804e <fail> +0+8035 <_start\+0x21> ldd \#0x0+8000 <tramp._far_foo> 0+8038 <_start\+0x24> xgdx -0+8039 <_start\+0x25> jsr 0,x -0+803b <_start\+0x27> ldd \#0+800a <tramp._far_bar> +0+8039 <_start\+0x25> jsr 0x0,x +0+803b <_start\+0x27> ldd \#0x0+800a <tramp._far_bar> 0+803e <_start\+0x2a> xgdy -0+8040 <_start\+0x2c> jsr 0,y -0+8043 <_start\+0x2f> ldaa \#0 -0+8045 <_start\+0x31> ldy \#0+8079 <_far_no_tramp> -0+8049 <_start\+0x35> bsr 0+8066 <__call_a16> +0+8040 <_start\+0x2c> jsr 0x0,y +0+8043 <_start\+0x2f> ldaa \#0x0 +0+8045 <_start\+0x31> ldy \#0x0+8079 <_far_no_tramp> +0+8049 <_start\+0x35> bsr 0x0+8066 <__call_a16> 0+804b <_start\+0x37> clra 0+804c <_start\+0x38> clrb 0+804d <_start\+0x39> wai -0+804e <fail> ldd \#0+1 <__bss_size\+0x1> +0+804e <fail> ldd \#0x0+1 <__bss_size\+0x1> 0+8051 <fail\+0x3> wai -0+8052 <fail\+0x4> bra 0+8014 <_start> +0+8052 <fail\+0x4> bra 0x0+8014 <_start> 0+8054 <__return> ins 0+8055 <__return\+0x1> rts 0+8056 <__far_trampoline> psha 0+8057 <__far_trampoline\+0x1> psha 0+8058 <__far_trampoline\+0x2> pshx 0+8059 <__far_trampoline\+0x3> tsx -0+805a <__far_trampoline\+0x4> ldab 4,x -0+805c <__far_trampoline\+0x6> ldaa 2,x -0+805e <__far_trampoline\+0x8> staa 4,x +0+805a <__far_trampoline\+0x4> ldab 0x4,x +0+805c <__far_trampoline\+0x6> ldaa 0x2,x +0+805e <__far_trampoline\+0x8> staa 0x4,x 0+8060 <__far_trampoline\+0xa> pulx 0+8061 <__far_trampoline\+0xb> pula 0+8062 <__far_trampoline\+0xc> pula -0+8063 <__far_trampoline\+0xd> jmp 0,y +0+8063 <__far_trampoline\+0xd> jmp 0x0,y 0+8066 <__call_a16> psha -0+8067 <__call_a16\+0x1> jmp 0,y +0+8067 <__call_a16\+0x1> jmp 0x0,y Disassembly of section .bank1: -0+806a <_far_bar> jsr 0+8071 <local_bank1> +0+806a <_far_bar> jsr 0x0+8071 <local_bank1> 0+806d <_far_bar\+0x3> xgdx -0+806e <_far_bar\+0x4> jmp 0+8054 <__return> +0+806e <_far_bar\+0x4> jmp 0x0+8054 <__return> 0+8071 <local_bank1> rts Disassembly of section .bank2: -0+8072 <_far_foo> jsr 0+8078 <local_bank2> -0+8075 <_far_foo\+0x3> jmp 0+8054 <__return> +0+8072 <_far_foo> jsr 0x0+8078 <local_bank2> +0+8075 <_far_foo\+0x3> jmp 0x0+8054 <__return> 0+8078 <local_bank2> rts Disassembly of section .bank3: -0+8079 <_far_no_tramp> jsr 0+807f <local_bank3> -0+807c <_far_no_tramp\+0x3> jmp 0+8054 <__return> +0+8079 <_far_no_tramp> jsr 0x0+807f <local_bank3> +0+807c <_far_no_tramp\+0x3> jmp 0x0+8054 <__return> 0+807f <local_bank3> rts diff --git a/ld/testsuite/ld-m68hc11/far-hc12.d b/ld/testsuite/ld-m68hc11/far-hc12.d index 09b3fec..7d99089 100644 --- a/ld/testsuite/ld-m68hc11/far-hc12.d +++ b/ld/testsuite/ld-m68hc11/far-hc12.d @@ -6,49 +6,49 @@ .*: file format elf32\-m68hc12 Disassembly of section .text: -0+c000 <tramp\._far_foo> ldy \#0+8000 <__bank_start> -0+c003 <tramp\._far_foo\+0x3> call 0+c049 <__far_trampoline> \{0+c049 <__far_trampoline>, 1\} -0+c007 <tramp\._far_bar> ldy \#0+8000 <__bank_start> -0+c00a <tramp\._far_bar\+0x3> call 0+c049 <__far_trampoline> \{0+c049 <__far_trampoline>, 0\} -0+c00e <_start> lds \#0+2063 <stack-0x1> -0+c011 <_start\+0x3> ldx \#0+abcd <__bank_start\+0x2bcd> +0+c000 <tramp\._far_foo> ldy \#0x0+8000 <__bank_start> +0+c003 <tramp\._far_foo\+0x3> call 0x0+c049 <__far_trampoline> \{0x0+c049 <__far_trampoline>, 0x1\} +0+c007 <tramp\._far_bar> ldy \#0x0+8000 <__bank_start> +0+c00a <tramp\._far_bar\+0x3> call 0x0+c049 <__far_trampoline> \{0x0+c049 <__far_trampoline>, 0x0\} +0+c00e <_start> lds \#0x0+2063 <stack-0x1> +0+c011 <_start\+0x3> ldx \#0x0+abcd <__bank_start\+0x2bcd> 0+c014 <_start\+0x6> pshx -0+c015 <_start\+0x7> ldd \#0+1234 <stack\-0xe30> -0+c018 <_start\+0xa> ldx \#0+5678 <__bank_size\+0x1678> -0+c01b <_start\+0xd> jsr 0+c007 <tramp._far_bar> -0+c01e <_start\+0x10> cpx \#0+1234 <stack\-0xe30> -0+c021 <_start\+0x13> bne 0+c043 <fail> -0+c023 <_start\+0x15> cpd \#0+5678 <__bank_size\+0x1678> -0+c026 <_start\+0x18> bne 0+c043 <fail> +0+c015 <_start\+0x7> ldd \#0x0+1234 <stack\-0xe30> +0+c018 <_start\+0xa> ldx \#0x0+5678 <__bank_size\+0x1678> +0+c01b <_start\+0xd> jsr 0x0+c007 <tramp._far_bar> +0+c01e <_start\+0x10> cpx \#0x0+1234 <stack\-0xe30> +0+c021 <_start\+0x13> bne 0x0+c043 <fail> +0+c023 <_start\+0x15> cpd \#0x0+5678 <__bank_size\+0x1678> +0+c026 <_start\+0x18> bne 0x0+c043 <fail> 0+c028 <_start\+0x1a> pulx -0+c029 <_start\+0x1b> cpx \#0+abcd <__bank_start\+0x2bcd> -0+c02c <_start\+0x1e> bne 0+c043 <fail> -0+c02e <_start\+0x20> ldd \#0+c000 <tramp._far_foo> +0+c029 <_start\+0x1b> cpx \#0x0+abcd <__bank_start\+0x2bcd> +0+c02c <_start\+0x1e> bne 0x0+c043 <fail> +0+c02e <_start\+0x20> ldd \#0x0+c000 <tramp._far_foo> 0+c031 <_start\+0x23> xgdx -0+c033 <_start\+0x25> jsr 0,X -0+c035 <_start\+0x27> ldd \#0+c007 <tramp._far_bar> +0+c033 <_start\+0x25> jsr 0x0,X +0+c035 <_start\+0x27> ldd \#0x0+c007 <tramp._far_bar> 0+c038 <_start\+0x2a> xgdy -0+c03a <_start\+0x2c> jsr 0,Y -0+c03c <_start\+0x2e> call 0+18000 <_far_no_tramp> \{0+8000 <__bank_start>, 2\} +0+c03a <_start\+0x2c> jsr 0x0,Y +0+c03c <_start\+0x2e> call 0x0+18000 <_far_no_tramp> \{0x0+8000 <__bank_start>, 0x2\} 0+c040 <_start\+0x32> clra 0+c041 <_start\+0x33> clrb 0+c042 <_start\+0x34> wai -0+c043 <fail> ldd \#0+1 <stack\-0x2063> +0+c043 <fail> ldd \#0x0+1 <stack\-0x2063> 0+c046 <fail\+0x3> wai -0+c047 <fail\+0x4> bra 0+c00e <_start> -0+c049 <__far_trampoline> movb 0,SP, 2,SP -0+c04d <__far_trampoline\+0x4> leas 2,SP -0+c04f <__far_trampoline\+0x6> jmp 0,Y +0+c047 <fail\+0x4> bra 0x0+c00e <_start> +0+c049 <__far_trampoline> movb 0x0,SP, 0x2,SP +0+c04d <__far_trampoline\+0x4> leas 0x2,SP +0+c04f <__far_trampoline\+0x6> jmp 0x0,Y Disassembly of section .bank1: -0+10+ <_far_bar> jsr 0+10006 <local_bank1> +0+10+ <_far_bar> jsr 0x0+10006 <local_bank1> 0+10003 <_far_bar\+0x3> xgdx 0+10005 <_far_bar\+0x5> rtc 0+10006 <local_bank1> rts Disassembly of section .bank2: -0+14000 <_far_foo> jsr 0+14004 <local_bank2> +0+14000 <_far_foo> jsr 0x0+14004 <local_bank2> 0+14003 <_far_foo\+0x3> rtc 0+14004 <local_bank2> rts Disassembly of section .bank3: -0+18000 <_far_no_tramp> jsr 0+18004 <local_bank3> +0+18000 <_far_no_tramp> jsr 0x0+18004 <local_bank3> 0+18003 <_far_no_tramp\+0x3> rtc 0+18004 <local_bank3> rts diff --git a/ld/testsuite/ld-m68hc11/link-hcs12.d b/ld/testsuite/ld-m68hc11/link-hcs12.d index d90fcf6..5fd5fae 100644 --- a/ld/testsuite/ld-m68hc11/link-hcs12.d +++ b/ld/testsuite/ld-m68hc11/link-hcs12.d @@ -1,19 +1,19 @@ #source: link-hcs12.s -m68hcs12 #source: link-hc12.s -m68hc12 #as: -mshort -#ld: -m m68hc12elf +#ld: -m m68hc12elf --script $srcdir/$subdir/far-hc12.ld #objdump: -p -d --prefix-addresses -r .*: file format elf32\-m68hc12 Program Header: - LOAD off 0x0+1000 vaddr 0x0+8000 paddr 0x0+8000 align 2\*\*12 + LOAD off 0x0+1000 vaddr 0x0+c000 paddr 0x0+c000 align 2\*\*12 filesz 0x0+6 memsz 0x0+6 flags r-x private flags = 22:\[abi=16\-bit int, 64\-bit double, cpu=HCS12\] \[memory=flat\] Disassembly of section .text: -0+8000 <_start> jsr 0+8005 <main> -0+8003 <_start\+0x3> bra 0+8000 <_start> -0+8005 <main> rts +0+c000 <_start> jsr 0x0+c005 <main> +0+c003 <_start\+0x3> bra 0x0+c000 <_start> +0+c005 <main> rts diff --git a/ld/testsuite/ld-m68hc11/relax-direct.d b/ld/testsuite/ld-m68hc11/relax-direct.d index 3de3d9a..519c074 100644 --- a/ld/testsuite/ld-m68hc11/relax-direct.d +++ b/ld/testsuite/ld-m68hc11/relax-direct.d @@ -6,57 +6,57 @@ .*: +file format elf32-m68hc11 Disassembly of section .text: -0+8000 <_start> lds \*0+28 <stack> -0+8002 <_start\+0x2> ldd \*0+ <__bss_size> -0+8004 <_start\+0x4> beq 0+800f <F1> -0+8006 <_start\+0x6> bne 0+800b <_start\+0xb> -0+8008 <_start\+0x8> jmp 0+8138 <F2> -0+800b <_start\+0xb> std \*0+ <__bss_size> -0+800d <_start\+0xd> jsr \*0+ <__bss_size> -0+800f <F1> addd \*0+4 <_toto> -0+8011 <F1\+0x2> bne 0+8000 <_start> -0+8013 <F1\+0x4> addd \*0+cc <_table\+0x9a> -0+8015 <F1\+0x6> addd 0+114 <_stack_top\+0x1a> -0+8018 <F1\+0x9> adca \*0+34 <_table\+0x2> -0+801a <F1\+0xb> adcb \*0+35 <_table\+0x3> -0+801c <F1\+0xd> adda \*0+36 <_table\+0x4> -0+801e <F1\+0xf> addb \*0+37 <_table\+0x5> -0+8020 <F1\+0x11> addd \*0+38 <_table\+0x6> -0+8022 <F1\+0x13> anda \*0+39 <_table\+0x7> -0+8024 <F1\+0x15> andb \*0+3a <_table\+0x8> -0+8026 <F1\+0x17> cmpa \*0+3b <_table\+0x9> -0+8028 <F1\+0x19> cmpb \*0+3c <_table\+0xa> -0+802a <F1\+0x1b> cpd \*0+3d <_table\+0xb> -0+802d <F1\+0x1e> cpx \*0+3e <_table\+0xc> -0+802f <F1\+0x20> cpy \*0+3f <_table\+0xd> -0+8032 <F1\+0x23> eora \*0+40 <_table\+0xe> -0+8034 <F1\+0x25> eorb \*0+41 <_table\+0xf> -0+8036 <F1\+0x27> jsr \*0+42 <_table\+0x10> -0+8038 <F1\+0x29> ldaa \*0+43 <_table\+0x11> -0+803a <F1\+0x2b> ldab \*0+44 <_table\+0x12> -0+803c <F1\+0x2d> ldd \*0+45 <_table\+0x13> -0+803e <F1\+0x2f> lds \*0+46 <_table\+0x14> -0+8040 <F1\+0x31> ldx \*0+47 <_table\+0x15> -0+8042 <F1\+0x33> ldy \*0+48 <_table\+0x16> -0+8045 <F1\+0x36> oraa \*0+49 <_table\+0x17> -0+8047 <F1\+0x38> orab \*0+4a <_table\+0x18> -0+8049 <F1\+0x3a> sbcb \*0+4b <_table\+0x19> -0+804b <F1\+0x3c> sbca \*0+4c <_table\+0x1a> -0+804d <F1\+0x3e> staa \*0+4d <_table\+0x1b> -0+804f <F1\+0x40> stab \*0+4e <_table\+0x1c> -0+8051 <F1\+0x42> std \*0+4f <_table\+0x1d> -0+8053 <F1\+0x44> sts \*0+50 <_table\+0x1e> -0+8055 <F1\+0x46> stx \*0+51 <_table\+0x1f> -0+8057 <F1\+0x48> sty \*0+52 <_table\+0x20> -0+805a <F1\+0x4b> suba \*0+53 <_table\+0x21> -0+805c <F1\+0x4d> subb \*0+54 <_table\+0x22> -0+805e <F1\+0x4f> subd \*0+55 <_table\+0x23> -0+8060 <F1\+0x51> bne 0+8000 <_start> -0+8062 <F1\+0x53> bra 0+800f <F1> +0+8000 <_start> lds \*0x0+28 <stack> +0+8002 <_start\+0x2> ldd \*0x0+ <__bss_size> +0+8004 <_start\+0x4> beq 0x0+800f <F1> +0+8006 <_start\+0x6> bne 0x0+800b <_start\+0xb> +0+8008 <_start\+0x8> jmp 0x0+8138 <F2> +0+800b <_start\+0xb> std \*0x0+ <__bss_size> +0+800d <_start\+0xd> jsr \*0x0+ <__bss_size> +0+800f <F1> addd \*0x0+4 <_toto> +0+8011 <F1\+0x2> bne 0x0+8000 <_start> +0+8013 <F1\+0x4> addd \*0x0+cc <_table\+0x9a> +0+8015 <F1\+0x6> addd 0x0+114 <_stack_top\+0x1a> +0+8018 <F1\+0x9> adca \*0x0+34 <_table\+0x2> +0+801a <F1\+0xb> adcb \*0x0+35 <_table\+0x3> +0+801c <F1\+0xd> adda \*0x0+36 <_table\+0x4> +0+801e <F1\+0xf> addb \*0x0+37 <_table\+0x5> +0+8020 <F1\+0x11> addd \*0x0+38 <_table\+0x6> +0+8022 <F1\+0x13> anda \*0x0+39 <_table\+0x7> +0+8024 <F1\+0x15> andb \*0x0+3a <_table\+0x8> +0+8026 <F1\+0x17> cmpa \*0x0+3b <_table\+0x9> +0+8028 <F1\+0x19> cmpb \*0x0+3c <_table\+0xa> +0+802a <F1\+0x1b> cpd \*0x0+3d <_table\+0xb> +0+802d <F1\+0x1e> cpx \*0x0+3e <_table\+0xc> +0+802f <F1\+0x20> cpy \*0x0+3f <_table\+0xd> +0+8032 <F1\+0x23> eora \*0x0+40 <_table\+0xe> +0+8034 <F1\+0x25> eorb \*0x0+41 <_table\+0xf> +0+8036 <F1\+0x27> jsr \*0x0+42 <_table\+0x10> +0+8038 <F1\+0x29> ldaa \*0x0+43 <_table\+0x11> +0+803a <F1\+0x2b> ldab \*0x0+44 <_table\+0x12> +0+803c <F1\+0x2d> ldd \*0x0+45 <_table\+0x13> +0+803e <F1\+0x2f> lds \*0x0+46 <_table\+0x14> +0+8040 <F1\+0x31> ldx \*0x0+47 <_table\+0x15> +0+8042 <F1\+0x33> ldy \*0x0+48 <_table\+0x16> +0+8045 <F1\+0x36> oraa \*0x0+49 <_table\+0x17> +0+8047 <F1\+0x38> orab \*0x0+4a <_table\+0x18> +0+8049 <F1\+0x3a> sbcb \*0x0+4b <_table\+0x19> +0+804b <F1\+0x3c> sbca \*0x0+4c <_table\+0x1a> +0+804d <F1\+0x3e> staa \*0x0+4d <_table\+0x1b> +0+804f <F1\+0x40> stab \*0x0+4e <_table\+0x1c> +0+8051 <F1\+0x42> std \*0x0+4f <_table\+0x1d> +0+8053 <F1\+0x44> sts \*0x0+50 <_table\+0x1e> +0+8055 <F1\+0x46> stx \*0x0+51 <_table\+0x1f> +0+8057 <F1\+0x48> sty \*0x0+52 <_table\+0x20> +0+805a <F1\+0x4b> suba \*0x0+53 <_table\+0x21> +0+805c <F1\+0x4d> subb \*0x0+54 <_table\+0x22> +0+805e <F1\+0x4f> subd \*0x0+55 <_table\+0x23> +0+8060 <F1\+0x51> bne 0x0+8000 <_start> +0+8062 <F1\+0x53> bra 0x0+800f <F1> 0+8064 <F1\+0x55> rts -0+8065 <no_relax> addd 0+136 <_stack_top\+0x3c> -0+8068 <no_relax\+0x3> std 0+122 <_stack_top\+0x28> -0+806b <no_relax\+0x6> tst 0+5 <_toto\+0x1> -0+806e <no_relax\+0x9> bne 0+8065 <no_relax> +0+8065 <no_relax> addd 0x0+136 <_stack_top\+0x3c> +0+8068 <no_relax\+0x3> std 0x0+122 <_stack_top\+0x28> +0+806b <no_relax\+0x6> tst 0x0+5 <_toto\+0x1> +0+806e <no_relax\+0x9> bne 0x0+8065 <no_relax> ... -0+8138 <F2> jmp 0+8000 <_start> +0+8138 <F2> jmp 0x0+8000 <_start> diff --git a/ld/testsuite/ld-m68hc11/relax-group.d b/ld/testsuite/ld-m68hc11/relax-group.d index 25ac588..8c4fb24 100644 --- a/ld/testsuite/ld-m68hc11/relax-group.d +++ b/ld/testsuite/ld-m68hc11/relax-group.d @@ -6,57 +6,57 @@ .*: +file format elf32-m68hc11 Disassembly of section .text: -0+8000 <_start> bset \*0+ <__bss_size> #\$04 -0+8003 <L1x> bset \*0+ <__bss_size> #\$04 -0+8006 <L1y> bset \*0+3 <__bss_size\+0x3> #\$04 -0+8009 <L1y\+0x3> bset \*0+4 <table4> #\$08 -0+800c <L2x> bset \*0+3 <__bss_size\+0x3> #\$04 -0+800f <L2x\+0x3> bset \*0+4 <table4> #\$08 -0+8012 <L2y> bset \*0+6 <table4\+0x2> #\$04 -0+8015 <L2y\+0x3> bset \*0+7 <table4\+0x3> #\$08 -0+8018 <L2y\+0x6> bset \*0+8 <table8> #\$0c -0+801b <L2y\+0x9> bset \*0+9 <table8\+0x1> #\$0c -0+801e <L2y\+0xc> bset \*0+a <table8\+0x2> #\$0c -0+8021 <L2y\+0xf> bset \*0+b <table8\+0x3> #\$0c -0+8024 <L3x> bset \*0+6 <table4\+0x2> #\$04 -0+8027 <L3x\+0x3> bset \*0+7 <table4\+0x3> #\$08 -0+802a <L3x\+0x6> bset \*0+8 <table8> #\$0c -0+802d <L3x\+0x9> bset \*0+9 <table8\+0x1> #\$0c -0+8030 <L3x\+0xc> bset \*0+a <table8\+0x2> #\$0c -0+8033 <L3x\+0xf> bset \*0+b <table8\+0x3> #\$0c -0+8036 <L3y> bra 0+8000 <_start> -0+8038 <L3y\+0x2> ldx #0+fe <end_table\+0xe8> -0+803b <L3y\+0x5> bset \*0+fe <end_table\+0xe8> #\$04 -0+803e <L3y\+0x8> bset \*0+ff <end_table\+0xe9> #\$08 -0+8041 <L3y\+0xb> bset 2,x #\$0c -0+8044 <L3y\+0xe> bset 3,x #\$0c -0+8047 <L3y\+0x11> bset 4,x #\$0c -0+804a <L3y\+0x14> bset 5,x #\$0c -0+804d <L4x> ldy #0+fe <end_table\+0xe8> -0+8051 <L4x\+0x4> bset \*0+fe <end_table\+0xe8> #\$04 -0+8054 <L4x\+0x7> bset \*0+ff <end_table\+0xe9> #\$08 -0+8057 <L4x\+0xa> bset 2,y #\$0c -0+805b <L4x\+0xe> bset 3,y #\$0c -0+805f <L4x\+0x12> bset 4,y #\$0c -0+8063 <L4x\+0x16> bset 5,y #\$0c -0+8067 <L4y> bclr \*0+a <table8\+0x2> #\$04 -0+806a <L4y\+0x3> bclr \*0+b <table8\+0x3> #\$08 -0+806d <L5x> bclr \*0+1a <end_table\+0x4> #\$04 -0+8070 <L5x\+0x3> bclr \*0+1b <end_table\+0x5> #\$08 -0+8073 <L5y> brset \*0+8 <table8> #\$04 0+8073 <L5y> -0+8077 <L6x> brset \*0+8 <table8> #\$04 0+8077 <L6x> -0+807b <L7x> brset \*0+8 <table8> #\$04 0+8094 <brend> -0+807f <L8x> brset \*0+8 <table8> #\$04 0+8094 <brend> -0+8083 <L8y> brclr \*0+8 <table8> #\$04 0+8083 <L8y> -0+8087 <L9x> brclr \*0+8 <table8> #\$04 0+8087 <L9x> -0+808b <L9y> brclr \*0+8 <table8> #\$04 0+8094 <brend> -0+808f <L10x> brclr \*0+8 <table8> #\$04 0+8094 <brend> +0+8000 <_start> bset \*0x0+ <__bss_size>, #0x04 +0+8003 <L1x> bset \*0x0+ <__bss_size>, #0x04 +0+8006 <L1y> bset \*0x0+3 <__bss_size\+0x3>, #0x04 +0+8009 <L1y\+0x3> bset \*0x0+4 <table4>, #0x08 +0+800c <L2x> bset \*0x0+3 <__bss_size\+0x3>, #0x04 +0+800f <L2x\+0x3> bset \*0x0+4 <table4>, #0x08 +0+8012 <L2y> bset \*0x0+6 <table4\+0x2>, #0x04 +0+8015 <L2y\+0x3> bset \*0x0+7 <table4\+0x3>, #0x08 +0+8018 <L2y\+0x6> bset \*0x0+8 <table8>, #0x0c +0+801b <L2y\+0x9> bset \*0x0+9 <table8\+0x1>, #0x0c +0+801e <L2y\+0xc> bset \*0x0+a <table8\+0x2>, #0x0c +0+8021 <L2y\+0xf> bset \*0x0+b <table8\+0x3>, #0x0c +0+8024 <L3x> bset \*0x0+6 <table4\+0x2>, #0x04 +0+8027 <L3x\+0x3> bset \*0x0+7 <table4\+0x3>, #0x08 +0+802a <L3x\+0x6> bset \*0x0+8 <table8>, #0x0c +0+802d <L3x\+0x9> bset \*0x0+9 <table8\+0x1>, #0x0c +0+8030 <L3x\+0xc> bset \*0x0+a <table8\+0x2>, #0x0c +0+8033 <L3x\+0xf> bset \*0x0+b <table8\+0x3>, #0x0c +0+8036 <L3y> bra 0x0+8000 <_start> +0+8038 <L3y\+0x2> ldx #0x0+fe <end_table\+0xe8> +0+803b <L3y\+0x5> bset \*0x0+fe <end_table\+0xe8>, #0x04 +0+803e <L3y\+0x8> bset \*0x0+ff <end_table\+0xe9>, #0x08 +0+8041 <L3y\+0xb> bset 0x2,x, #0x0c +0+8044 <L3y\+0xe> bset 0x3,x, #0x0c +0+8047 <L3y\+0x11> bset 0x4,x, #0x0c +0+804a <L3y\+0x14> bset 0x5,x, #0x0c +0+804d <L4x> ldy #0x0+fe <end_table\+0xe8> +0+8051 <L4x\+0x4> bset \*0x0+fe <end_table\+0xe8>, #0x04 +0+8054 <L4x\+0x7> bset \*0x0+ff <end_table\+0xe9>, #0x08 +0+8057 <L4x\+0xa> bset 0x2,y, #0x0c +0+805b <L4x\+0xe> bset 0x3,y, #0x0c +0+805f <L4x\+0x12> bset 0x4,y, #0x0c +0+8063 <L4x\+0x16> bset 0x5,y, #0x0c +0+8067 <L4y> bclr \*0x0+a <table8\+0x2>, #0x04 +0+806a <L4y\+0x3> bclr \*0x0+b <table8\+0x3>, #0x08 +0+806d <L5x> bclr \*0x0+1a <end_table\+0x4>, #0x04 +0+8070 <L5x\+0x3> bclr \*0x0+1b <end_table\+0x5>, #0x08 +0+8073 <L5y> brset \*0x0+8 <table8>, #0x04, 0x0+8073 <L5y> +0+8077 <L6x> brset \*0x0+8 <table8>, #0x04, 0x0+8077 <L6x> +0+807b <L7x> brset \*0x0+8 <table8>, #0x04, 0x0+8094 <brend> +0+807f <L8x> brset \*0x0+8 <table8>, #0x04, 0x0+8094 <brend> +0+8083 <L8y> brclr \*0x0+8 <table8>, #0x04, 0x0+8083 <L8y> +0+8087 <L9x> brclr \*0x0+8 <table8>, #0x04, 0x0+8087 <L9x> +0+808b <L9y> brclr \*0x0+8 <table8>, #0x04, 0x0+8094 <brend> +0+808f <L10x> brclr \*0x0+8 <table8>, #0x04, 0x0+8094 <brend> 0+8093 <L10y> nop -0+8094 <brend> bset 0,x #\$04 -0+8097 <w2> ldx #0+ <__bss_size> -0+809a <w3> ldy #0+8 <table8> +0+8094 <brend> bset 0x0,x, #0x04 +0+8097 <w2> ldx #0x0+ <__bss_size> +0+809a <w3> ldy #0x0+8 <table8> 0+809e <w4> rts -0+809f <w5> ldx #0+ <__bss_size> -0+80a2 <w5\+0x3> bset 0,x #\$05 -0+80a5 <w5\+0x6> jmp 0+8000 <_start> +0+809f <w5> ldx #0x0+ <__bss_size> +0+80a2 <w5\+0x3> bset 0x0,x, #0x05 +0+80a5 <w5\+0x6> jmp 0x0+8000 <_start> 0+80a8 <w5\+0x9> rts diff --git a/ld/testsuite/ld-m68hc11/xgate-link.d b/ld/testsuite/ld-m68hc11/xgate-link.d new file mode 100644 index 0000000..cdf80ab --- /dev/null +++ b/ld/testsuite/ld-m68hc11/xgate-link.d @@ -0,0 +1,25 @@ +#as: -mm9s12xg +#source: xgate-link.s +#ld: --relax -mm68hc12elf -defsym var1=0xfeed -defsym var2=0xdeaf -defsym var3=0xa1b2 -defsym var4=0x3456 -defsym var5=0xfa -defsym var6=0x20fe +#objdump: -d --prefix-addresses -r -mm9s12xg + +tmpdir/dump: file format elf32-m68hc12 + + +Disassembly of section .text: +00008000 <_start> ldl R1, #0xed +00008002 <_start\+0x2> ldh R1, #0xfe +00008004 <_start\+0x4> addl R5, #0xaf +00008006 <_start\+0x6> addh R5, #0xde +00008008 <_start\+0x8> ldl R2, #0x56 +0000800a <_start\+0xa> ldh R2, #0x34 +0000800c <_start\+0xc> ldl R3, #0x21 +0000800e <_start\+0xe> ldh R6, #0xfa +00008010 <_start\+0x10> cmpl R1, #0xcd +00008012 <_start\+0x12> cpch R1, #0xab +00008014 <_start\+0x14> cmpl R2, #0xb2 +00008016 <_start\+0x16> cpch R2, #0xa1 +00008018 <_start\+0x18> ldl R1, #0xfe +0000801a <_start\+0x1a> ldh R1, #0x20 +0000801c <_start\+0x1c> ldl R2, #0x02 +0000801e <_start\+0x1e> ldh R2, #0x22 diff --git a/ld/testsuite/ld-m68hc11/xgate-link.s b/ld/testsuite/ld-m68hc11/xgate-link.s new file mode 100644 index 0000000..8413bd9 --- /dev/null +++ b/ld/testsuite/ld-m68hc11/xgate-link.s @@ -0,0 +1,16 @@ +;;; Test 16bit relocate with XGATE +;;; + .sect .text + .globl _start +_start: + + ldw r1,#var1 ; expands to two IMM8 %hi,%lo relocate + add r5,#var2 ; expands to two IMM8 %hi,%lo relocate + ldl r2,#%lovar4 ; test explicit %lo + ldh r2,#%hivar4 ; test explicit %hi + ldl r3,#0x21 ; regular IMM8 + ldh r6,#var5 ; IMM8 with relocate + cmp r1,#0xabcd ; expands to two IMM8 with constant + cmp r2,#var3 ; expands to two IMM8 %hi,%lo relocate + ldw r1,#var6 + ldw r2,#var6+0x104 ; check for correct carry diff --git a/ld/testsuite/ld-m68hc11/xgate-offset.d b/ld/testsuite/ld-m68hc11/xgate-offset.d new file mode 100644 index 0000000..ee8d492 --- /dev/null +++ b/ld/testsuite/ld-m68hc11/xgate-offset.d @@ -0,0 +1,13 @@ +#as: -mm9s12xg --xgate-ramoffset +#source: xgate-offset.s +#ld: --relax -mm68hc12elf -defsym var=0x20fe +#objdump: -d --prefix-addresses -r -mm9s12xg + +tmpdir/dump: file format elf32-m68hc12 + + +Disassembly of section .text: +00008000 <_start> ldl R1, #0xfe +00008002 <_start\+0x2> ldh R1, #0xe0 +00008004 <_start\+0x4> ldl R2, #0x04 +00008006 <_start\+0x6> ldh R2, #0xe2 diff --git a/ld/testsuite/ld-m68hc11/xgate-offset.s b/ld/testsuite/ld-m68hc11/xgate-offset.s new file mode 100644 index 0000000..f81bc89 --- /dev/null +++ b/ld/testsuite/ld-m68hc11/xgate-offset.s @@ -0,0 +1,8 @@ +;;; Test 16bit relocate with --xgate-ramoffset +;;; + .sect .text + .globl _start +_start: + + ldw r1,#var + ldw r2,#var+0x106 ; check for correct carry too diff --git a/ld/testsuite/ld-m68hc11/xgate1.d b/ld/testsuite/ld-m68hc11/xgate1.d new file mode 100644 index 0000000..abe6bbc --- /dev/null +++ b/ld/testsuite/ld-m68hc11/xgate1.d @@ -0,0 +1,24 @@ +#as: -mm9s12xg +#source: xgate1.s +#source: xgate2.s +#ld: --relax -mm68hc12elf +#objdump: -d --prefix-addresses -r -mm9s12xg + +tmpdir/dump: file format elf32-m68hc12 + + +Disassembly of section .text: +00008000 <_start> ldl R1, \#0x00 +00008002 <_start\+0x2> ldh R1, \#0x11 +00008004 <_start\+0x4> sub R0, R1, R0 +00008006 <_start\+0x6> beq 0x0+8010 <linked_ad1> +00008008 <_start\+0x8> sub R0, R2, R0 +0000800a <_start\+0xa> beq 0x0+800e <the_end> +0000800c <_start\+0xc> bra 0x0+8018 <linked_ad2> +0000800e <the_end> rts +00008010 <linked_ad1> cmpl R4, \#0x01 +00008012 <linked_ad1\+0x2> bne 0x0+8018 <linked_ad2> +00008014 <label1> nop +00008016 <label1\+0x2> par R5 +00008018 <linked_ad2> csem \#0x2 +0000801a <linked_ad2\+0x2> rts diff --git a/ld/testsuite/ld-m68hc11/xgate1.s b/ld/testsuite/ld-m68hc11/xgate1.s new file mode 100644 index 0000000..26baf67 --- /dev/null +++ b/ld/testsuite/ld-m68hc11/xgate1.s @@ -0,0 +1,18 @@ +;;; Test branches and branch relocate with XGATE +;;; + .sect .text + .globl _start +_start: + + ldw r1,#var1 ; expands to two IMM8 %hi,%lo relocate + tst r1 + beq linked_ad1 + tst r2 + beq the_end + bra linked_ad2 + +the_end: + rts + + .sect .data +var1: fdb 0x1234 diff --git a/ld/testsuite/ld-m68hc11/xgate2.s b/ld/testsuite/ld-m68hc11/xgate2.s new file mode 100644 index 0000000..54b1ed9 --- /dev/null +++ b/ld/testsuite/ld-m68hc11/xgate2.s @@ -0,0 +1,16 @@ +;;; Part2 of branch test +;;; +.globl linked_ad1, linked_ad2 + .sect .text + +linked_ad1: + cmpl r4,#1 + bne linked_ad2 + +label1: + nop + par r5 + +linked_ad2: + csem #2 + rts diff --git a/ld/testsuite/ld-plugin/plugin.exp b/ld/testsuite/ld-plugin/plugin.exp index 02319bf..d28505d 100644 --- a/ld/testsuite/ld-plugin/plugin.exp +++ b/ld/testsuite/ld-plugin/plugin.exp @@ -57,6 +57,10 @@ set regclm "-plugin-opt registerclaimfile" set regas "-plugin-opt registerallsymbolsread" set regcln "-plugin-opt registercleanup" +if { [istarget m681*-*-*] || [istarget m68hc1*-*-*] || [istarget m9s12x*-*-*] } { + # otherwise get FAILS due to _.frame + set CFLAGS "$CFLAGS -fomit-frame-pointer" +} # In order to define symbols in plugin options in the list of tests below, # we need to know if the platform prepends an underscore to C symbols, # which we find out by compiling the test objects now. If there is any diff --git a/ld/testsuite/ld-srec/srec.exp b/ld/testsuite/ld-srec/srec.exp index 5e741e0..4c21320 100644 --- a/ld/testsuite/ld-srec/srec.exp +++ b/ld/testsuite/ld-srec/srec.exp @@ -276,6 +276,21 @@ proc run_srec_test { test objs } { setup_xfail "epiphany*-*-*" } + if [istarget m681*-*-*] { + set flags "$flags --defsym _start=0xc000" + setup_xfail "m681*-*-*" + } + + if [istarget m68hc1*-*-*] { + set flags "$flags --defsym _start=0xc000" + setup_xfail "m68hc1*-*-*" + } + + if [istarget m9s12x*-*-*] { + set flags "$flags --defsym _start=0xc000" + setup_xfail "m9s12x*-*-*" + } + if { ![ld_simple_link $ld tmpdir/sr1 "$flags $objs"] \ || ![ld_simple_link $ld tmpdir/sr2.sr "$flags --oformat srec $objs"] } { fail $test diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e8a816d..abfec32 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> + Stephane Carrez <stcarrez@nerim.fr> + + * configure.in: Add S12X and XGATE co-processor support to m68hc11 + target. + * disassemble.c: Likewise. + * configure: Regenerate. + * m68hc11-dis.c: Make objdump output more consistent, use hex + instead of decimal and use 0x prefix for hex. + * m68hc11-opc.c: Add S12X and XGATE opcodes. + 2012-05-14 James Lemke <jwlemke@codesourcery.com> * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle. diff --git a/opcodes/configure b/opcodes/configure index 1613ae0..9426e7e 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12468,6 +12468,8 @@ if test x${all_targets} = xfalse ; then bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m9s12xg_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index 1d3f2d9..9c84816 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -251,6 +251,8 @@ if test x${all_targets} = xfalse ; then bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m9s12xg_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 7ff5f22..3dad64b 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -248,13 +248,20 @@ disassembler (abfd) disassemble = print_insn_m32r; break; #endif -#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) +#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \ + || defined(ARCH_9s12x) || defined(ARCH_m9s12xg) case bfd_arch_m68hc11: disassemble = print_insn_m68hc11; break; case bfd_arch_m68hc12: disassemble = print_insn_m68hc12; break; + case bfd_arch_m9s12x: + disassemble = print_insn_m9s12x; + break; + case bfd_arch_m9s12xg: + disassemble = print_insn_m9s12xg; + break; #endif #ifdef ARCH_m68k case bfd_arch_m68k: diff --git a/opcodes/m68hc11-dis.c b/opcodes/m68hc11-dis.c index f6d6184..98ef4d9 100644 --- a/opcodes/m68hc11-dis.c +++ b/opcodes/m68hc11-dis.c @@ -1,7 +1,8 @@ /* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly - Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007 + Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2012 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) + XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk) This file is part of the GNU opcodes library. @@ -28,15 +29,18 @@ #define PC_REGNUM 3 -static const char *const reg_name[] = { +static const char *const reg_name[] = +{ "X", "Y", "SP", "PC" }; -static const char *const reg_src_table[] = { +static const char *const reg_src_table[] = +{ "A", "B", "CCR", "TMP3", "D", "X", "Y", "SP" }; -static const char *const reg_dst_table[] = { +static const char *const reg_dst_table[] = +{ "A", "B", "CCR", "TMP2", "D", "X", "Y", "SP" }; @@ -45,7 +49,7 @@ static const char *const reg_dst_table[] = { /* Prototypes for local functions. */ static int read_memory (bfd_vma, bfd_byte *, int, struct disassemble_info *); static int print_indexed_operand (bfd_vma, struct disassemble_info *, - int*, int, int, bfd_vma); + int*, int, int, bfd_vma, int); static int print_insn (bfd_vma, struct disassemble_info *, int); static int @@ -71,7 +75,7 @@ read_memory (bfd_vma memaddr, bfd_byte* buffer, int size, static int print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info, int* indirect, int mov_insn, int pc_offset, - bfd_vma endaddr) + bfd_vma endaddr, int arch) { bfd_byte buffer[4]; int reg; @@ -98,12 +102,14 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info, /* 68HC12 requires an adjustment for movb/movw pc relative modes. */ if (reg == PC_REGNUM && info->mach == bfd_mach_m6812 && mov_insn) sval += pc_offset; - (*info->fprintf_func) (info->stream, "%d,%s", - (int) sval, reg_name[reg]); + (*info->fprintf_func) (info->stream, "0x%x,%s", + (unsigned short) sval, reg_name[reg]); if (reg == PC_REGNUM) { (* info->fprintf_func) (info->stream, " {"); + if (info->symtab_size > 0) /* Avoid duplicate 0x from core binutils. */ + (*info->fprintf_func) (info->stream, "0x"); (* info->print_address_func) (endaddr + sval, info); (* info->fprintf_func) (info->stream, "}"); } @@ -128,7 +134,7 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info, mode = "+"; } (*info->fprintf_func) (info->stream, "%d,%s%s%s", - (int) sval, + (unsigned short) sval, (buffer[0] & 0x10 ? "" : mode), reg_name[reg], (buffer[0] & 0x10 ? mode : "")); } @@ -136,12 +142,12 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info, /* [n,r] 16-bits offset indexed indirect. */ else if ((buffer[0] & 0x07) == 3) { - if (mov_insn) - { - (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>", - buffer[0] & 0x0ff); - return 0; - } + if ((mov_insn) && (!(arch & cpu9s12x))) + { + (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>", + buffer[0] & 0x0ff); + return 0; + } reg = (buffer[0] >> 3) & 0x03; status = read_memory (memaddr + pos, &buffer[0], 2, info); if (status != 0) @@ -151,7 +157,7 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info, pos += 2; sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); - (*info->fprintf_func) (info->stream, "[%u,%s]", + (*info->fprintf_func) (info->stream, "[0x%x,%s]", sval & 0x0ffff, reg_name[reg]); if (indirect) *indirect = 1; @@ -160,12 +166,13 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info, /* n,r with 9 and 16 bit signed constant. */ else if ((buffer[0] & 0x4) == 0) { - if (mov_insn) - { - (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>", - buffer[0] & 0x0ff); - return 0; - } + if ((mov_insn) && (!(arch & cpu9s12x))) + { + (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; status = read_memory (memaddr + pos, &buffer[1], (buffer[0] & 0x2 ? 2 : 1), info); @@ -188,11 +195,11 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info, pos++; endaddr++; } - (*info->fprintf_func) (info->stream, "%d,%s", - (int) sval, reg_name[reg]); + (*info->fprintf_func) (info->stream, "0x%x,%s", + (unsigned short) sval, reg_name[reg]); if (reg == PC_REGNUM) { - (* info->fprintf_func) (info->stream, " {"); + (* info->fprintf_func) (info->stream, " {0x"); (* info->print_address_func) (endaddr + sval, info); (* info->fprintf_func) (info->stream, "}"); } @@ -230,18 +237,114 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) { int status; bfd_byte buffer[4]; - unsigned char code; + unsigned int code; long format, pos, i; short sval; const struct m68hc11_opcode *opcode; + if (arch & cpuxgate) + { + int val; + /* Get two bytes as all XGATE instructions are 16bit. */ + status = read_memory (memaddr, buffer, 2, info); + if (status != 0) + return status; + + format = 0; + code = (buffer[0] << 8) + buffer[1]; + + /* Scan the opcode table until we find the opcode + with the corresponding page. */ + opcode = m68hc11_opcodes; + for (i = 0; i < m68hc11_num_opcodes; i++, opcode++) + { + if ((opcode->opcode != (code & opcode->xg_mask)) || (opcode->arch != cpuxgate)) + continue; + /* We have found the opcode. Extract the operand and print it. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + format = opcode->format; + if (format & (M68XG_OP_NONE)) + { + /* Nothing to print. */ + } + else if (format & M68XG_OP_IMM3) + (*info->fprintf_func) (info->stream, " #0x%x", (code >> 8) & 0x7); + else if (format & M68XG_OP_R_R) + (*info->fprintf_func) (info->stream, " R%x, R%x", + (code >> 8) & 0x7, (code >> 5) & 0x7); + else if (format & M68XG_OP_R_R_R) + (*info->fprintf_func) (info->stream, " R%x, R%x, R%x", + (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7); + else if (format & M68XG_OP_RD_RB_RI) + (*info->fprintf_func) (info->stream, " R%x, (R%x, R%x)", + (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7); + else if (format & M68XG_OP_RD_RB_RIp) + (*info->fprintf_func) (info->stream, " R%x, (R%x, R%x+)", + (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7); + else if (format & M68XG_OP_RD_RB_mRI) + (*info->fprintf_func) (info->stream, " R%x, (R%x, -R%x)", + (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7); + else if (format & M68XG_OP_R_R_OFFS5) + (*info->fprintf_func) (info->stream, " R%x, (R%x, #0x%x)", + (code >> 8) & 0x7, (code >> 5) & 0x7, code & 0x1f); + else if (format & M68XG_OP_R_IMM8) + (*info->fprintf_func) (info->stream, " R%x, #0x%02x", + (code >> 8) & 0x7, code & 0xff); + else if (format & M68XG_OP_R_IMM4) + (*info->fprintf_func) (info->stream, " R%x, #0x%x", + (code >> 8) & 0x7, (code & 0xf0) >> 4); + else if (format & M68XG_OP_REL9) + { + (*info->fprintf_func) (info->stream, " 0x"); + val = (buffer[0] & 0x1) ? buffer[1] | 0xFFFFFF00 : buffer[1]; + (*info->print_address_func) (memaddr + (val << 1) + 2, info); + } + else if (format & M68XG_OP_REL10) + { + (*info->fprintf_func) (info->stream, " 0x"); + val = (buffer[0] << 8) | (unsigned int) buffer[1]; + if (val & 0x200) + val |= 0xfffffc00; + else + val &= 0x000001ff; + (*info->print_address_func) (memaddr + (val << 1) + 2, info); + } + else if ((code & 0x00ff) == 0x00f8) + (*info->fprintf_func) (info->stream, " R%x, CCR", (code >> 8) & 0x7); + else if ((code & 0x00ff) == 0x00f9) + (*info->fprintf_func) (info->stream, " CCR, R%x", (code >> 8) & 0x7); + else if ((code & 0x00ff) == 0x0) + (*info->fprintf_func) (info->stream, " R%x, PC", (code >> 8) & 0x7); + else if (format & M68XG_OP_R) + { + /* Special cases for TFR. */ + if ((code & 0xf8ff) == 0x00f8) + (*info->fprintf_func) (info->stream, " R%x, CCR", (code >> 8) & 0x7); + else if ((code & 0xf8ff) == 0x00f9) + (*info->fprintf_func) (info->stream, " CCR, R%x", (code >> 8) & 0x7); + else if ((code & 0xf8ff) == 0x00fa) + (*info->fprintf_func) (info->stream, " R%x, PC", (code >> 8) & 0x7); + else + (*info->fprintf_func) (info->stream, " R%x", (code >> 8) & 0x7); + } + else + /* Opcode not recognized. */ + (*info->fprintf_func) (info->stream, "Not yet handled TEST .byte\t0x%04x", code); + return 2; + } + + /* Opcode not recognized. */ + (*info->fprintf_func) (info->stream, ".byte\t0x%04x", code); + return 2; /* Everything is two bytes. */ + } + + /* HC11 and HC12. */ + /* Get first byte. Only one at a time because we don't know the size of the insn. */ status = read_memory (memaddr, buffer, 1, info); if (status != 0) - { - return status; - } + return status; format = 0; code = buffer[0]; @@ -269,13 +372,11 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) { status = read_memory (memaddr + pos, &buffer[1], 1, info); if (status != 0) - { - return status; - } + return status; + code = buffer[1]; } - /* Look first for a 68HC12 alias. All of them are 2-bytes long and in page 1. There is no operand to print. We read the second byte only when we have a possible match. */ @@ -374,6 +475,10 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) && (((buffer[0] & 0x07) >= 3 && (buffer[0] & 7) <= 7)) && ((buffer[0] & 0x0f0) <= 0x20)) break; + if ((opcode[j].format & M6812_OP_SEX_MARKER) + && (arch & cpu9s12x) + && ((buffer[0] == 0x4d) || (buffer[0] == 0x4e))) + break; if (opcode[j].format & M6812_OP_TFR_MARKER && !(buffer[0] & 0x80)) break; @@ -393,73 +498,107 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) } /* The movb and movw must be handled in a special way... - The source constant 'ii' is not always at the same place. - This is the same for the destination for the post-indexed byte. - The 'offset' is used to do the appropriate correction. - - offset offset - for constant for destination - movb 18 OB ii hh ll 0 0 - 18 08 xb ii 1 -1 - 18 0C hh ll hh ll 0 0 - 18 09 xb hh ll 1 -1 - 18 0D xb hh ll 0 0 - 18 0A xb xb 0 0 - - movw 18 03 jj kk hh ll 0 0 - 18 00 xb jj kk 1 -1 - 18 04 hh ll hh ll 0 0 - 18 01 xb hh ll 1 -1 - 18 05 xb hh ll 0 0 - 18 02 xb xb 0 0 - - After the source operand is read, the position 'pos' is incremented - this explains the negative offset for destination. - - movb/movw above are the only instructions with this matching - format. */ + The source constant 'ii' is not always at the same place. + This is the same for the destination for the post-indexed byte. + The 'offset' is used to do the appropriate correction. + + offset offset + for constant for destination + movb 18 OB ii hh ll 0 0 + 18 08 xb ii 1 -1 + 18 08 xb ff ii 2 1 9 bit + 18 08 xb ee ff ii 3 1 16 bit + 18 0C hh ll hh ll 0 0 + 18 09 xb hh ll 1 -1 + 18 0D xb hh ll 0 0 + 18 0A xb xb 0 0 + + movw 18 03 jj kk hh ll 0 0 + 18 00 xb jj kk 1 -1 + 18 04 hh ll hh ll 0 0 + 18 01 xb hh ll 1 -1 + 18 05 xb hh ll 0 0 + 18 02 xb xb 0 0 + + After the source operand is read, the position 'pos' is incremented + this explains the negative offset for destination. + + movb/movw above are the only instructions with this matching + format. */ offset = ((format & M6812_OP_IDX_P2) - && (format & (M6811_OP_IMM8 | M6811_OP_IMM16 | - M6811_OP_IND16))); + && (format & (M6811_OP_IMM8 | M6811_OP_IMM16 | + M6811_OP_IND16))); + + if (offset) + { + /* Check xb to see position of data. */ + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + if (((buffer[0] & 0xe0) == 0xe0) && ((buffer[0] & 0x04) == 0)) + { + /* 9 or 16 bit. */ + if ((buffer[0] & 0x02) == 0) + { + /* 9 bit. */ + offset = 2; + } + else + { + /* 16 bit. */ + offset = 3; + } + } + } /* Operand with one more byte: - immediate, offset, - direct-low address. */ + direct-low address. */ if (format & (M6811_OP_IMM8 | M6811_OP_IX | M6811_OP_IY | M6811_OP_DIRECT)) { status = read_memory (memaddr + pos + offset, &buffer[0], 1, info); if (status != 0) + return status; + + /* This movb/movw is special (see above). */ + if (offset < 2) { - return status; + offset = -offset; + pc_dst_offset = 2; + } + else + { + offset = -1; + pc_dst_offset = 5; } - pos++; - /* This movb/movw is special (see above). */ - offset = -offset; - - pc_dst_offset = 2; if (format & M6811_OP_IMM8) { - (*info->fprintf_func) (info->stream, "#%d", (int) buffer[0]); + (*info->fprintf_func) (info->stream, "#0x%x", (int) buffer[0]); format &= ~M6811_OP_IMM8; - /* Set PC destination offset. */ - pc_dst_offset = 1; + /* Set PC destination offset. */ + pc_dst_offset = 1; } else if (format & M6811_OP_IX) { /* Offsets are in range 0..255, print them unsigned. */ - (*info->fprintf_func) (info->stream, "%u,x", buffer[0] & 0x0FF); + (*info->fprintf_func) (info->stream, "0x%x,x", buffer[0] & 0x0FF); format &= ~M6811_OP_IX; } else if (format & M6811_OP_IY) { - (*info->fprintf_func) (info->stream, "%u,y", buffer[0] & 0x0FF); + (*info->fprintf_func) (info->stream, "0x%x,y", buffer[0] & 0x0FF); format &= ~M6811_OP_IY; } else if (format & M6811_OP_DIRECT) { (*info->fprintf_func) (info->stream, "*"); + if (info->symtab_size > 0) /* Avoid duplicate 0x. */ + (*info->fprintf_func) (info->stream, "0x"); (*info->print_address_func) (buffer[0] & 0x0FF, info); format &= ~M6811_OP_DIRECT; } @@ -470,27 +609,26 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) /* Analyze the 68HC12 indexed byte. */ if (format & M6812_INDEXED_FLAGS) { - int indirect; - bfd_vma endaddr; - - endaddr = memaddr + pos + 1; - if (format & M6811_OP_IND16) - endaddr += 2; - pc_src_offset = -1; - pc_dst_offset = 1; + int indirect; + bfd_vma endaddr; + + endaddr = memaddr + pos + 1; + if (format & M6811_OP_IND16) + endaddr += 2; + pc_src_offset = -1; + pc_dst_offset = 1; status = print_indexed_operand (memaddr + pos, info, &indirect, - (format & M6812_DST_MOVE), - pc_src_offset, endaddr); + (format & M6812_DST_MOVE), + pc_src_offset, endaddr, arch); if (status < 0) - { - return status; - } + return status; + pos += status; - /* The indirect addressing mode of the call instruction does - not need the page code. */ - if ((format & M6812_OP_PAGE) && indirect) - format &= ~M6812_OP_PAGE; + /* The indirect addressing mode of the call instruction does + not need the page code. */ + if ((format & M6812_OP_PAGE) && indirect) + format &= ~M6812_OP_PAGE; } /* 68HC12 dbcc/ibcc/tbcc operands. */ @@ -498,9 +636,8 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) { status = read_memory (memaddr + pos, &buffer[0], 2, info); if (status != 0) - { - return status; - } + return status; + (*info->fprintf_func) (info->stream, "%s,", reg_src_table[buffer[0] & 0x07]); sval = buffer[1] & 0x0ff; @@ -508,6 +645,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) sval |= 0xff00; pos += 2; + (*info->fprintf_func) (info->stream, "0x"); (*info->print_address_func) (memaddr + pos + sval, info); format &= ~(M6812_OP_REG | M6811_OP_JUMP_REL); } @@ -515,9 +653,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) { status = read_memory (memaddr + pos, &buffer[0], 1, info); if (status != 0) - { - return status; - } + return status; pos++; (*info->fprintf_func) (info->stream, "%s,%s", @@ -528,14 +664,13 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) { int val; - bfd_vma addr; - unsigned page = 0; + bfd_vma addr; + unsigned page = 0; status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); if (status != 0) - { - return status; - } + return status; + if (format & M6812_OP_IDX_P2) offset = -2; else @@ -544,64 +679,71 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); val &= 0x0FFFF; - addr = val; - pc_dst_offset = 2; - if (format & M6812_OP_PAGE) - { - status = read_memory (memaddr + pos + offset, buffer, 1, info); - if (status != 0) - return status; - - page = (unsigned) buffer[0]; - if (addr >= M68HC12_BANK_BASE && addr < 0x0c000) - addr = ((val - M68HC12_BANK_BASE) - | (page << M68HC12_BANK_SHIFT)) - + M68HC12_BANK_VIRT; - } - else if ((arch & cpu6812) - && addr >= M68HC12_BANK_BASE && addr < 0x0c000) - { - int cur_page; - bfd_vma vaddr; + addr = val; + pc_dst_offset = 2; + if (format & M6812_OP_PAGE) + { + status = read_memory (memaddr + pos + offset, buffer, 1, info); + if (status != 0) + return status; + + page = (unsigned) buffer[0]; + if (addr >= M68HC12_BANK_BASE && addr < 0x0c000) + addr = ((val - M68HC12_BANK_BASE) + | (page << M68HC12_BANK_SHIFT)) + + M68HC12_BANK_VIRT; + } + else if ((arch & cpu6812) + && addr >= M68HC12_BANK_BASE && addr < 0x0c000) + { + int cur_page; + bfd_vma vaddr; - if (memaddr >= M68HC12_BANK_VIRT) - cur_page = ((memaddr - M68HC12_BANK_VIRT) - >> M68HC12_BANK_SHIFT); - else - cur_page = 0; - - vaddr = ((addr - M68HC12_BANK_BASE) - + (cur_page << M68HC12_BANK_SHIFT)) - + M68HC12_BANK_VIRT; - if (!info->symbol_at_address_func (addr, info) - && info->symbol_at_address_func (vaddr, info)) - addr = vaddr; - } + if (memaddr >= M68HC12_BANK_VIRT) + cur_page = ((memaddr - M68HC12_BANK_VIRT) + >> M68HC12_BANK_SHIFT); + else + cur_page = 0; + + vaddr = ((addr - M68HC12_BANK_BASE) + + (cur_page << M68HC12_BANK_SHIFT)) + + M68HC12_BANK_VIRT; + if (!info->symbol_at_address_func (addr, info) + && info->symbol_at_address_func (vaddr, info)) + addr = vaddr; + } if (format & M6811_OP_IMM16) { format &= ~M6811_OP_IMM16; (*info->fprintf_func) (info->stream, "#"); } else - format &= ~M6811_OP_IND16; + { + format &= ~M6811_OP_IND16; + } + + if (info->symtab_size > 0) /* Avoid duplicate 0x from core binutils. */ + (*info->fprintf_func) (info->stream, "0x"); (*info->print_address_func) (addr, info); - if (format & M6812_OP_PAGE) - { - (* info->fprintf_func) (info->stream, " {"); - (* info->print_address_func) (val, info); - (* info->fprintf_func) (info->stream, ", %d}", page); - format &= ~M6812_OP_PAGE; - pos += 1; - } + if (format & M6812_OP_PAGE) + { + (* info->fprintf_func) (info->stream, " {"); + if (info->symtab_size > 0) /* Avoid duplicate 0x from core binutils. */ + (*info->fprintf_func) (info->stream, "0x"); + (* info->print_address_func) (val, info); + (* info->fprintf_func) (info->stream, ", 0x%x}", page); + format &= ~M6812_OP_PAGE; + pos += 1; + } } if (format & M6812_OP_IDX_P2) { (*info->fprintf_func) (info->stream, ", "); status = print_indexed_operand (memaddr + pos + offset, info, - 0, 1, pc_dst_offset, - memaddr + pos + offset + 1); + 0, 1, pc_dst_offset, + memaddr + pos + offset + 1, arch); if (status < 0) return status; pos += status; @@ -615,30 +757,30 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); if (status != 0) - { - return status; - } + return status; + pos += 2; val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); val &= 0x0FFFF; + if (info->symtab_size > 0) /* Avoid duplicate 0x from core binutils. */ + (*info->fprintf_func) (info->stream, "0x"); (*info->print_address_func) (val, info); } /* M6811_OP_BITMASK and M6811_OP_JUMP_REL must be treated separately - and in that order. The brset/brclr insn have a bitmask and then - a relative branch offset. */ + and in that order. The brset/brclr insn have a bitmask and then + a relative branch offset. */ if (format & M6811_OP_BITMASK) { status = read_memory (memaddr + pos, &buffer[0], 1, info); if (status != 0) - { - return status; - } + return status; + pos++; - (*info->fprintf_func) (info->stream, " #$%02x%s", + (*info->fprintf_func) (info->stream, ", #0x%02x%s", buffer[0] & 0x0FF, - (format & M6811_OP_JUMP_REL ? " " : "")); + (format & M6811_OP_JUMP_REL ? ", " : "")); format &= ~M6811_OP_BITMASK; } if (format & M6811_OP_JUMP_REL) @@ -647,10 +789,9 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) status = read_memory (memaddr + pos, &buffer[0], 1, info); if (status != 0) - { - return status; - } + return status; + (*info->fprintf_func) (info->stream, "0x"); pos++; val = (buffer[0] & 0x80) ? buffer[0] | 0xFFFFFF00 : buffer[0]; (*info->print_address_func) (memaddr + pos + val, info); @@ -662,15 +803,14 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) status = read_memory (memaddr + pos, &buffer[0], 2, info); if (status != 0) - { - return status; - } + return status; pos += 2; val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); if (val & 0x8000) val |= 0xffff0000; + (*info->fprintf_func) (info->stream, "0x"); (*info->print_address_func) (memaddr + pos + val, info); format &= ~M6812_OP_JUMP_REL16; } @@ -681,28 +821,24 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) status = read_memory (memaddr + pos + offset, &buffer[0], 1, info); if (status != 0) - { - return status; - } + return status; + pos += 1; val = buffer[0] & 0x0ff; - (*info->fprintf_func) (info->stream, ", %d", val); + (*info->fprintf_func) (info->stream, ", 0x%x", val); } #ifdef DEBUG /* Consistency check. 'format' must be 0, so that we have handled - all formats; and the computed size of the insn must match the - opcode table content. */ + all formats; and the computed size of the insn must match the + opcode table content. */ if (format & ~(M6811_OP_PAGE4 | M6811_OP_PAGE3 | M6811_OP_PAGE2)) - { - (*info->fprintf_func) (info->stream, "; Error, format: %lx", format); - } + (*info->fprintf_func) (info->stream, "; Error, format: %lx", format); + if (pos != opcode->size) - { - (*info->fprintf_func) (info->stream, "; Error, size: %ld expect %d", - pos, opcode->size); - } + (*info->fprintf_func) (info->stream, "; Error, size: %ld expect %d", + pos, opcode->size); #endif return pos; } @@ -710,7 +846,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) /* Opcode not recognized. */ if (format == M6811_OP_PAGE2 && arch & cpu6812 && ((code >= 0x30 && code <= 0x39) || (code >= 0x40))) - (*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff); + (*info->fprintf_func) (info->stream, "trap\t#0x%02x", code & 0x0ff); else if (format == M6811_OP_PAGE2) (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", @@ -740,3 +876,15 @@ print_insn_m68hc12 (bfd_vma memaddr, struct disassemble_info* info) { return print_insn (memaddr, info, cpu6812); } + +int +print_insn_m9s12x (bfd_vma memaddr, struct disassemble_info* info) +{ + return print_insn (memaddr, info, cpu6812|cpu9s12x); +} + +int +print_insn_m9s12xg (bfd_vma memaddr, struct disassemble_info* info) +{ + return print_insn (memaddr, info, cpuxgate); +} diff --git a/opcodes/m68hc11-opc.c b/opcodes/m68hc11-opc.c index ac6259d..79c1d27 100644 --- a/opcodes/m68hc11-opc.c +++ b/opcodes/m68hc11-opc.c @@ -1,6 +1,9 @@ -/* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list - Copyright 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc. +/* m68hc11-opc.c -- Motorola 68HC11, 68HC12, 9S12X and XGATE opcode list + Copyright 1999, 2000, 2002, 2005, 2007, 2012 + Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) + XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk) + Note: min/max cycles not updated for S12X opcodes. This file is part of the GNU opcodes library. @@ -103,956 +106,1611 @@ #define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER) /* - { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, - +-- cpu + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811, 0 }, + +-- cpu +-- XGATE opcode mask Name -+ +------- Insn CCR changes Format ------+ +----------- Max # cycles Size --------------------+ +--------------- Min # cycles +--------------------- Opcode */ const struct m68hc11_opcode m68hc11_opcodes[] = { - { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 }, - { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 }, - { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 }, - { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 }, - - { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, - { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, - { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, - { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 }, - { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 }, - { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, - { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, - { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 }, - { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, - { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, - - { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, - { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, - { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, - { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 }, - { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 }, - { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, - { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, - { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 }, - { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, - { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, - - { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, - { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, - { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, - { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 }, - { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 }, - { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, - { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, - { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 }, - { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, - { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, - - { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, - { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, - { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, - { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 }, - { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 }, - { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, - { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, - { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 }, - { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, - { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, - - { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, - { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 }, - { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 }, - { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, - { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, - { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 }, - { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, - { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, - - { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 }, - - { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, - { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, - { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, - { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, - { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, - { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, - { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, - { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, - - { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, - { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, - - { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, - { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 }, - { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 }, - { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 }, - { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 }, - { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 }, - { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 }, - { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 }, - - { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - - { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812 }, - - { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 }, - { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811}, - { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - - { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812 }, - - { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811, 0 }, + { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811, 0 }, + { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811, 0 }, + + { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811, 0 }, + { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811, 0 }, + { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + + { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811, 0 }, + { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811, 0 }, + { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + + { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811, 0 }, + { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811, 0 }, + { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + + { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811, 0 }, + { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811, 0 }, + { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + + { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "addx", OP_IMM16 | OP_PAGE2, 3, 0x8b, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "addx", OP_DIRECT | OP_PAGE2, 2, 0x9b, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "addx", OP_IND16 | OP_PAGE2, 3, 0xbb, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "addx", OP_IDX | OP_PAGE2, 2, 0xab, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "addx", OP_IDX_1 | OP_PAGE2, 3, 0xab, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "addx", OP_IDX_2 | OP_PAGE2, 4, 0xab, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "addx", OP_D_IDX | OP_PAGE2, 2, 0xab, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "addx", OP_D_IDX_2 | OP_PAGE2, 4, 0xab, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "addy", OP_IMM16 | OP_PAGE2, 3, 0xcb, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "addy", OP_DIRECT | OP_PAGE2, 2, 0xdb, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "addy", OP_IND16 | OP_PAGE2, 3, 0xfb, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "addy", OP_IDX | OP_PAGE2, 2, 0xeb, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "addy", OP_IDX_1 | OP_PAGE2, 3, 0xeb, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "addy", OP_IDX_2 | OP_PAGE2, 4, 0xeb, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "addy", OP_D_IDX | OP_PAGE2, 2, 0xeb, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "addy", OP_D_IDX_2 | OP_PAGE2, 4, 0xeb, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "aded", OP_IMM16 | OP_PAGE2, 3, 0xc3, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "aded", OP_DIRECT | OP_PAGE2, 2, 0xd3, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "aded", OP_IND16 | OP_PAGE2, 3, 0xf3, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "aded", OP_IDX | OP_PAGE2, 2, 0xe3, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "aded", OP_IDX_1 | OP_PAGE2, 3, 0xe3, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "aded", OP_IDX_2 | OP_PAGE2, 4, 0xe3, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "aded", OP_D_IDX | OP_PAGE2, 2, 0xe3, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "aded", OP_D_IDX_2 | OP_PAGE2, 4, 0xe3, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "adex", OP_IMM16 | OP_PAGE2, 3, 0x89, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "adex", OP_DIRECT | OP_PAGE2, 2, 0x99, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "adex", OP_IND16 | OP_PAGE2, 3, 0xb9, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "adex", OP_IDX | OP_PAGE2, 2, 0xa9, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "adex", OP_IDX_1 | OP_PAGE2, 3, 0xa9, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "adex", OP_IDX_2 | OP_PAGE2, 4, 0xa9, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "adex", OP_D_IDX | OP_PAGE2, 2, 0xa9, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "adex", OP_D_IDX_2 | OP_PAGE2, 4, 0xa9, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "adey", OP_IMM16 | OP_PAGE2, 3, 0xc9, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "adey", OP_DIRECT | OP_PAGE2, 2, 0xd9, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "adey", OP_IND16 | OP_PAGE2, 3, 0xf9, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "adey", OP_IDX | OP_PAGE2, 2, 0xe9, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "adey", OP_IDX_1 | OP_PAGE2, 3, 0xe9, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "adey", OP_IDX_2 | OP_PAGE2, 4, 0xe9, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "adey", OP_D_IDX | OP_PAGE2, 2, 0xe9, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "adey", OP_D_IDX_2 | OP_PAGE2, 4, 0xe9, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812|cpu9s12x, 0 }, + + { "andx", OP_IMM16 | OP_PAGE2, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andx", OP_DIRECT | OP_PAGE2, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andx", OP_IND16 | OP_PAGE2, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andx", OP_IDX | OP_PAGE2, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andx", OP_IDX_1 | OP_PAGE2, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andx", OP_IDX_2 | OP_PAGE2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andx", OP_D_IDX | OP_PAGE2, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andx", OP_D_IDX_2 | OP_PAGE2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "andy", OP_IMM16 | OP_PAGE2, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andy", OP_DIRECT | OP_PAGE2, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andy", OP_IND16 | OP_PAGE2, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andy", OP_IDX | OP_PAGE2, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andy", OP_IDX_1 | OP_PAGE2, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andy", OP_IDX_2 | OP_PAGE2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andy", OP_D_IDX | OP_PAGE2, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "andy", OP_D_IDX_2 | OP_PAGE2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811, 0 }, + { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "aslw", OP_IND16 | OP_PAGE2, 3, 0x78, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "aslw", OP_IDX | OP_PAGE2, 2, 0x68, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "aslw", OP_IDX_1 | OP_PAGE2, 3, 0x68, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "aslw", OP_IDX_2 | OP_PAGE2, 4, 0x68, 5, 5, CHG_NZVC, cpu9s12x, 0 }, + { "aslw", OP_D_IDX | OP_PAGE2, 2, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "aslw", OP_D_IDX_2 | OP_PAGE2, 4, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "aslx", OP_NONE | OP_PAGE2, 1, 0x48, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "asly", OP_NONE | OP_PAGE2, 1, 0x58, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + + { "asrw", OP_IND16 | OP_PAGE2, 3, 0x77, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "asrw", OP_IDX | OP_PAGE2, 2, 0x67, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "asrw", OP_IDX_1 | OP_PAGE2, 3, 0x67, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "asrw", OP_IDX_2 | OP_PAGE2, 4, 0x67, 5, 5, CHG_NZVC, cpu9s12x, 0 }, + { "asrw", OP_D_IDX | OP_PAGE2, 2, 0x67, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "asrw", OP_D_IDX_2 | OP_PAGE2, 4, 0x67, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "asrx", OP_NONE | OP_PAGE2, 1, 0x47, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "asry", OP_NONE | OP_PAGE2, 1, 0x57, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 }, + + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + + { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + + { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, - { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "bitx", OP_IMM16 | OP_PAGE2, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bitx", OP_DIRECT | OP_PAGE2, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bitx", OP_IND16 | OP_PAGE2, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bitx", OP_IDX | OP_PAGE2, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bitx", OP_IDX_1 | OP_PAGE2, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bitx", OP_IDX_2 | OP_PAGE2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bitx", OP_D_IDX | OP_PAGE2, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bitx", OP_D_IDX_2 | OP_PAGE2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "bity", OP_IMM16 | OP_PAGE2, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bity", OP_DIRECT | OP_PAGE2, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bity", OP_IND16 | OP_PAGE2, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bity", OP_IDX | OP_PAGE2, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bity", OP_IDX_1 | OP_PAGE2, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bity", OP_IDX_2 | OP_PAGE2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bity", OP_D_IDX | OP_PAGE2, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "bity", OP_D_IDX_2 | OP_PAGE2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, { "brclr", OP_BITMASK | OP_JUMP_REL - | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 }, + | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811, 0 }, { "brclr", OP_BITMASK | OP_JUMP_REL - | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 }, + | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811, 0 }, { "brclr", OP_BITMASK | OP_JUMP_REL - | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 }, + | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811, 0 }, { "brclr", OP_BITMASK | OP_JUMP_REL - | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 }, + | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "brclr", OP_BITMASK | OP_JUMP_REL - | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 }, + | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "brclr", OP_BITMASK | OP_JUMP_REL - | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 }, + | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "brclr", OP_BITMASK | OP_JUMP_REL - | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 }, + | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "brclr", OP_BITMASK | OP_JUMP_REL - | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 }, + | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 }, - { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 }, { "brset", OP_BITMASK | OP_JUMP_REL - | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 }, + | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811, 0 }, { "brset", OP_BITMASK | OP_JUMP_REL - | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 }, + | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811, 0 }, { "brset", OP_BITMASK | OP_JUMP_REL - | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 }, + | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811, 0 }, { "brset", OP_BITMASK | OP_JUMP_REL - | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 }, + | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "brset", OP_BITMASK | OP_JUMP_REL - | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 }, + | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "brset", OP_BITMASK | OP_JUMP_REL - | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 }, + | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "brset", OP_BITMASK | OP_JUMP_REL - | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 }, + | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "brset", OP_BITMASK | OP_JUMP_REL - | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 }, + | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 }, - { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 }, - { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 }, - { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811, 0 }, + { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, - { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 }, - { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 }, + { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811, 0 }, + { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, - { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "btas", OP_BITMASK|OP_DIRECT | OP_PAGE2, 3, 0x35, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "btas", OP_BITMASK|OP_IND16 | OP_PAGE2, 4, 0x36, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "btas", OP_BITMASK|OP_IDX | OP_PAGE2, 3, 0x37, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "btas", OP_BITMASK|OP_IDX_1 | OP_PAGE2, 4, 0x37, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "btas", OP_BITMASK|OP_IDX_2 | OP_PAGE2, 5, 0x37, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, + { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 }, { "call", OP_IND16 | OP_PAGE - | OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 }, + | OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "call", OP_IDX | OP_PAGE - | OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + | OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "call", OP_IDX_1 | OP_PAGE - | OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + | OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "call", OP_IDX_2 | OP_PAGE - | OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 }, + | OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "call", OP_D_IDX - | OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + | OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "call", OP_D_IDX_2 - | OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 }, - - { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 }, - { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 }, - - { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 }, - { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 }, - - { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, - { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, - { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 }, - { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 }, - { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 }, - { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 }, - { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 }, - { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, - { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, - - { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, - { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, - { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 }, - { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 }, - - { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 }, - - { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 }, - { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 }, - { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, - { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, - { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 }, - { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, - { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, - - { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 }, - { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 }, - { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, - { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, - { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 }, - { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, - { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, - - { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, - { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, - { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 }, - { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, - { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 }, - { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, - { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 }, - { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, - { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, - - { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, - { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, - { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, - { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, - - { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 }, - { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 }, - { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 }, - { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, - { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, - { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 }, - { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 }, - { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 }, - { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 }, - { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 }, - { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 }, - { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 }, - { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 }, - - { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 }, - { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 }, - { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 }, - { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, - { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, - { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 }, - { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, - { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, - - { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 }, - { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 }, - { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 }, - { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 }, - { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, - { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 }, - { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 }, - { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 }, - { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 }, - { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 }, - { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 }, - { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 }, - { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 }, - - { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 }, - { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 }, - { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, - { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 }, - { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, - { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 }, - { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 }, - { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 }, - { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 }, - { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 }, - { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 }, - { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 }, - { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + | OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811, 0 }, + { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811, 0 }, + { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811, 0 }, + + { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811, 0 }, + { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811, 0 }, + { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811, 0 }, + { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 }, + { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 }, + { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 }, + { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 }, + { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 }, + { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 }, + + { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811, 0 }, + { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811, 0 }, + { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 }, + { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 }, + + { "clrw", OP_IND16 | OP_PAGE2, 3, 0x79, 4, 4, SET_Z_CLR_NVC, cpu9s12x, 0 }, + { "clrw", OP_IDX | OP_PAGE2, 2, 0x69, 3, 3, SET_Z_CLR_NVC, cpu9s12x, 0 }, + { "clrw", OP_IDX_1 | OP_PAGE2, 3, 0x69, 4, 4, SET_Z_CLR_NVC, cpu9s12x, 0 }, + { "clrw", OP_IDX_2 | OP_PAGE2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu9s12x, 0 }, + { "clrw", OP_D_IDX | OP_PAGE2, 2, 0x69, 6, 6, SET_Z_CLR_NVC, cpu9s12x, 0 }, + { "clrw", OP_D_IDX_2 | OP_PAGE2, 4, 0x69, 6, 6, SET_Z_CLR_NVC, cpu9s12x, 0 }, + + { "clrx", OP_NONE | OP_PAGE2, 3, 0x87, 4, 4, SET_Z_CLR_NVC, cpu9s12x, 0 }, + + { "clry", OP_NONE | OP_PAGE2, 3, 0xc7, 4, 4, SET_Z_CLR_NVC, cpu9s12x, 0 }, + + { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811, 0 }, + + { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811, 0 }, + { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811, 0 }, + { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811, 0 }, + { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811, 0 }, + { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811, 0 }, + { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811, 0 }, + { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811, 0 }, + { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "comw", OP_IND16 | OP_PAGE2, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "comw", OP_IDX | OP_PAGE2, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "comw", OP_IDX_1 | OP_PAGE2, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "comw", OP_IDX_2 | OP_PAGE2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "comw", OP_D_IDX | OP_PAGE2, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "comw", OP_D_IDX_2 | OP_PAGE2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "comx", OP_NONE | OP_PAGE2, 1, 0x41, 2, 2, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "comy", OP_NONE | OP_PAGE2, 1, 0x51, 2, 2, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "cped", OP_IMM16 | OP_PAGE2, 3, 0x8c, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "cped", OP_DIRECT | OP_PAGE2, 2, 0x9c, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cped", OP_IND16 | OP_PAGE2, 3, 0xbc, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cped", OP_IDX | OP_PAGE2, 2, 0xac, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cped", OP_IDX_1 | OP_PAGE2, 3, 0xac, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cped", OP_IDX_2 | OP_PAGE2, 4, 0xac, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "cped", OP_D_IDX | OP_PAGE2, 2, 0xac, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "cped", OP_D_IDX_2 | OP_PAGE2, 4, 0xac, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "cpes", OP_IMM16 | OP_PAGE2, 3, 0x8f, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "cpes", OP_DIRECT | OP_PAGE2, 2, 0x9f, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpes", OP_IND16 | OP_PAGE2, 3, 0xbf, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpes", OP_IDX | OP_PAGE2, 2, 0xaf, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpes", OP_IDX_1 | OP_PAGE2, 3, 0xaf, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpes", OP_IDX_2 | OP_PAGE2, 4, 0xaf, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "cpes", OP_D_IDX | OP_PAGE2, 2, 0xaf, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "cpes", OP_D_IDX_2 | OP_PAGE2, 4, 0xaf, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "cpex", OP_IMM16 | OP_PAGE2, 3, 0x8e, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "cpex", OP_DIRECT | OP_PAGE2, 2, 0x9e, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpex", OP_IND16 | OP_PAGE2, 3, 0xbe, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpex", OP_IDX | OP_PAGE2, 2, 0xae, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpex", OP_IDX_1 | OP_PAGE2, 3, 0xae, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpex", OP_IDX_2 | OP_PAGE2, 4, 0xae, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "cpex", OP_D_IDX | OP_PAGE2, 2, 0xae, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "cpex", OP_D_IDX_2 | OP_PAGE2, 4, 0xae, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "cpey", OP_IMM16 | OP_PAGE2, 3, 0x8d, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "cpey", OP_DIRECT | OP_PAGE2, 2, 0x9d, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpey", OP_IND16 | OP_PAGE2, 3, 0xbd, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpey", OP_IDX | OP_PAGE2, 2, 0xad, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpey", OP_IDX_1 | OP_PAGE2, 3, 0xad, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "cpey", OP_IDX_2 | OP_PAGE2, 4, 0xad, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "cpey", OP_D_IDX | OP_PAGE2, 2, 0xad, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "cpey", OP_D_IDX_2 | OP_PAGE2, 4, 0xad, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811, 0 }, + { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, /* After 'daa', the Z flag is undefined. Mark it as changed. */ - { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 }, - { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 }, + { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811, 0 }, + { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, { "dbeq", OP_DBEQ_MARKER - | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "dbne", OP_DBNE_MARKER - | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, - - { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 }, - { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 }, - { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 }, - { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 }, - { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 }, - { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 }, - { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 }, - { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 }, - { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 }, - - { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 }, - - { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 }, - { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 }, - { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 }, - { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 }, - - { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu6811 }, - { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 }, - { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 }, - - { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 }, - { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 }, - { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 }, - - { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, - { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, - { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 }, - { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, - { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, - - { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 }, - { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 }, - { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 }, - { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, - { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, - - { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, - { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, - { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 }, - { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, - { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, - - { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 }, - { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 }, - { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 }, - { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, - { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, - - { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 }, - { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 }, - - { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 }, - + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811, 0 }, + { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811, 0 }, + { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811, 0 }, + { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812|cpu9s12x, 0 }, + + { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811, 0 }, + + { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811, 0 }, + { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811, 0 }, + { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812|cpu9s12x, 0 }, + + { "decw", OP_IND16 | OP_PAGE2, 3, 0x73, 4, 4, CHG_NZV, cpu9s12x, 0 }, + { "decw", OP_IDX | OP_PAGE2, 2, 0x63, 3, 3, CHG_NZV, cpu9s12x, 0 }, + { "decw", OP_IDX_1 | OP_PAGE2, 3, 0x63, 4, 4, CHG_NZV, cpu9s12x, 0 }, + { "decw", OP_IDX_2 | OP_PAGE2, 4, 0x63, 5, 5, CHG_NZV, cpu9s12x, 0 }, + { "decw", OP_D_IDX | OP_PAGE2, 2, 0x63, 6, 6, CHG_NZV, cpu9s12x, 0 }, + { "decw", OP_D_IDX_2 | OP_PAGE2, 4, 0x63, 6, 6, CHG_NZV, cpu9s12x, 0 }, + + { "decx", OP_NONE | OP_PAGE2, 3, 0x43, 4, 4, CHG_NZV, cpu9s12x, 0 }, + + { "decy", OP_NONE | OP_PAGE2, 3, 0x53, 4, 4, CHG_NZV, cpu9s12x, 0 }, + + { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu9s12x|cpu6811, 0 }, + { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811, 0 }, + { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812|cpu9s12x, 0 }, + + { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812|cpu9s12x, 0 }, + { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812|cpu9s12x, 0 }, + + { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "eorx", OP_IMM16 | OP_PAGE2, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eorx", OP_DIRECT | OP_PAGE2, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eorx", OP_IND16 | OP_PAGE2, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eorx", OP_IDX | OP_PAGE2, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eorx", OP_IDX_1 | OP_PAGE2, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eorx", OP_IDX_2 | OP_PAGE2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eorx", OP_D_IDX | OP_PAGE2, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eorx", OP_D_IDX_2 | OP_PAGE2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "eory", OP_IMM16 | OP_PAGE2, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eory", OP_DIRECT | OP_PAGE2, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eory", OP_IND16 | OP_PAGE2, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eory", OP_IDX | OP_PAGE2, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eory", OP_IDX_1 | OP_PAGE2, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eory", OP_IDX_2 | OP_PAGE2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eory", OP_D_IDX | OP_PAGE2, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "eory", OP_D_IDX_2 | OP_PAGE2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812|cpu9s12x, 0 }, + +/* S12X has more exg variants, most are pointless so not supported */ { "exg", OP_EXG_MARKER - | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, - - { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811}, - { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 }, + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811, 0 }, + { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812|cpu9s12x, 0 }, + + { "gldaa", OP_DIRECT | OP_PAGE2, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldaa", OP_IND16 | OP_PAGE2, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldaa", OP_IDX | OP_PAGE2, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldaa", OP_IDX_1 | OP_PAGE2, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldaa", OP_IDX_2 | OP_PAGE2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldaa", OP_D_IDX | OP_PAGE2, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldaa", OP_D_IDX_2 | OP_PAGE2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gldab", OP_DIRECT | OP_PAGE2, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldab", OP_IND16 | OP_PAGE2, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldab", OP_IDX | OP_PAGE2, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldab", OP_IDX_1 | OP_PAGE2, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldab", OP_IDX_2 | OP_PAGE2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldab", OP_D_IDX | OP_PAGE2, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldab", OP_D_IDX_2 | OP_PAGE2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gldd", OP_DIRECT | OP_PAGE2, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldd", OP_IND16 | OP_PAGE2, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldd", OP_IDX | OP_PAGE2, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldd", OP_IDX_1 | OP_PAGE2, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldd", OP_IDX_2 | OP_PAGE2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldd", OP_D_IDX | OP_PAGE2, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldd", OP_D_IDX_2 | OP_PAGE2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "glds", OP_DIRECT | OP_PAGE2, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "glds", OP_IND16 | OP_PAGE2, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "glds", OP_IDX | OP_PAGE2, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "glds", OP_IDX_1 | OP_PAGE2, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "glds", OP_IDX_2 | OP_PAGE2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "glds", OP_D_IDX | OP_PAGE2, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "glds", OP_D_IDX_2 | OP_PAGE2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gldx", OP_DIRECT | OP_PAGE2, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldx", OP_IND16 | OP_PAGE2, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldx", OP_IDX | OP_PAGE2, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldx", OP_IDX_1 | OP_PAGE2, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldx", OP_IDX_2 | OP_PAGE2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldx", OP_D_IDX | OP_PAGE2, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldx", OP_D_IDX_2 | OP_PAGE2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gldy", OP_DIRECT | OP_PAGE2, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldy", OP_IND16 | OP_PAGE2, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldy", OP_IDX | OP_PAGE2, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldy", OP_IDX_1 | OP_PAGE2, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldy", OP_IDX_2 | OP_PAGE2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldy", OP_D_IDX | OP_PAGE2, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gldy", OP_D_IDX_2 | OP_PAGE2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gstaa", OP_DIRECT | OP_PAGE2, 2, 0x5a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstaa", OP_IND16 | OP_PAGE2, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstaa", OP_IDX | OP_PAGE2, 2, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstaa", OP_IDX_1 | OP_PAGE2, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstaa", OP_IDX_2 | OP_PAGE2, 4, 0x6a, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstaa", OP_D_IDX | OP_PAGE2, 2, 0x6a, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstaa", OP_D_IDX_2 | OP_PAGE2, 4, 0x6a, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gstab", OP_DIRECT | OP_PAGE2, 2, 0x5b, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstab", OP_IND16 | OP_PAGE2, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstab", OP_IDX | OP_PAGE2, 2, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstab", OP_IDX_1 | OP_PAGE2, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstab", OP_IDX_2 | OP_PAGE2, 4, 0x6b, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstab", OP_D_IDX | OP_PAGE2, 2, 0x6b, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstab", OP_D_IDX_2 | OP_PAGE2, 4, 0x6b, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gstd", OP_DIRECT | OP_PAGE2, 2, 0x5c, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstd", OP_IND16 | OP_PAGE2, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstd", OP_IDX | OP_PAGE2, 2, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstd", OP_IDX_1 | OP_PAGE2, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstd", OP_IDX_2 | OP_PAGE2, 4, 0x6c, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstd", OP_D_IDX | OP_PAGE2, 2, 0x6c, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstd", OP_D_IDX_2 | OP_PAGE2, 4, 0x6c, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gsts", OP_DIRECT | OP_PAGE2, 2, 0x5f, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsts", OP_IND16 | OP_PAGE2, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsts", OP_IDX | OP_PAGE2, 2, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsts", OP_IDX_1 | OP_PAGE2, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsts", OP_IDX_2 | OP_PAGE2, 4, 0x6f, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsts", OP_D_IDX | OP_PAGE2, 2, 0x6f, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsts", OP_D_IDX_2 | OP_PAGE2, 4, 0x6f, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gstx", OP_DIRECT | OP_PAGE2, 2, 0x5e, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstx", OP_IND16 | OP_PAGE2, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstx", OP_IDX | OP_PAGE2, 2, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstx", OP_IDX_1 | OP_PAGE2, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstx", OP_IDX_2 | OP_PAGE2, 4, 0x6e, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstx", OP_D_IDX | OP_PAGE2, 2, 0x6e, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gstx", OP_D_IDX_2 | OP_PAGE2, 4, 0x6e, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "gsty", OP_DIRECT | OP_PAGE2, 2, 0x5d, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsty", OP_IND16 | OP_PAGE2, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsty", OP_IDX | OP_PAGE2, 2, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsty", OP_IDX_1 | OP_PAGE2, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsty", OP_IDX_2 | OP_PAGE2, 4, 0x6d, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsty", OP_D_IDX | OP_PAGE2, 2, 0x6d, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "gsty", OP_D_IDX_2 | OP_PAGE2, 4, 0x6d, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, { "ibeq", OP_IBEQ_MARKER - | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, { "ibne", OP_IBNE_MARKER - | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, - - { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811}, - { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 }, - { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 }, - - { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 }, - { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 }, - { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 }, - { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 }, - { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 }, - { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 }, - { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 }, - { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 }, - { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 }, - - { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 }, - { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 }, - { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 }, - { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 }, - - { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 }, - - { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812 }, - { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 }, - { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 }, - - { "jmp", OP_IND16 | OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 }, - { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 }, - { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 }, - { "jmp", OP_IND16 | OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812 }, - { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 }, - { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 }, - { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 }, - { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 }, - { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 }, - - { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 }, - { "jsr", OP_IND16 | OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 }, - { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 }, - { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 }, - { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812 }, - { "jsr", OP_IND16 | OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812 }, - { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 }, - { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 }, - { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 }, - { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 }, - { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 }, - - { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, - { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, - { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 }, - { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 }, - { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 }, - { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 }, - { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, - { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 }, - { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, - { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 }, - { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 }, - { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 }, - { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 }, - { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 }, - { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 }, - { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 }, - { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 }, - { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 }, - - { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 }, - { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 }, - { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 }, - { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 }, - - { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 }, - { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 }, - { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 }, - - { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 }, - { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 }, - { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 }, - - { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, - { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, - { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, - { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, - { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, - { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, - { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, - { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, - - { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, - { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, - - { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812}, - { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 }, - { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 }, - { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 }, - { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 }, - { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 }, - { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, - { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, - - { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, - { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, - { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 }, - { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 }, - - { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 }, - { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 }, - { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 }, - { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 }, - { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 }, - - { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 }, - { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 }, - { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 }, - { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, - { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, - - { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 }, - - { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 }, - { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 }, - { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 }, - { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 }, - { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 }, - - { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 }, - { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 }, - { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 }, - { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, - { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, - - { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 }, - { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 }, - { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 }, - { "movb", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812 }, - { "movb", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812 }, - { "movb", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812 }, - - { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812 }, - { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812 }, - { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812 }, - { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812 }, - { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812 }, - { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812 }, - - { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 }, - { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 }, - - { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, - { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 }, - { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 }, - { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 }, - { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 }, - { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 }, - { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 }, - { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 }, - - { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 }, - { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 }, - - { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, - { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 }, - { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, - - { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 }, - - { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812 }, - { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812 }, - { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 }, - { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 }, - { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 }, - { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 }, - { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 }, - { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 }, - - { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812 }, - { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812 }, - { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 }, - { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 }, - { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 }, - { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 }, - { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 }, - { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 }, - - { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 }, - { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 }, - - { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 }, - { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 }, - { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 }, - { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 }, - { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 }, - { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 }, - { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 }, - { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 }, - { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 }, - - { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 }, - { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 }, - { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 }, - { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 }, - - { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, - { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 }, - { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 }, - { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 }, - { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 }, - { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 }, - { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 }, - { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 }, - - { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - - { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 }, - { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811}, - { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812}, - { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 }, - { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 }, - - { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 }, - { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 }, - - { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 }, - { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 }, - { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, - { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, - { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 }, - { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, - { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, - - { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 }, - { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 }, - { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, - { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, - { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 }, - { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, - { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, - - { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 }, - { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 }, - { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 }, - + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811, 0 }, + { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812|cpu9s12x, 0 }, + { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811, 0 }, + { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811, 0 }, + { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811, 0 }, + { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812|cpu9s12x, 0 }, + + { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811, 0 }, + { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812|cpu9s12x, 0 }, + { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811, 0 }, + { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812|cpu9s12x, 0 }, + + { "incw", OP_IND16 | OP_PAGE2, 3, 0x72, 4, 4, CHG_NZV, cpu9s12x, 0 }, + { "incw", OP_IDX | OP_PAGE2, 2, 0x62, 3, 3, CHG_NZV, cpu9s12x, 0 }, + { "incw", OP_IDX_1 | OP_PAGE2, 3, 0x62, 4, 4, CHG_NZV, cpu9s12x, 0 }, + { "incw", OP_IDX_2 | OP_PAGE2, 4, 0x62, 5, 5, CHG_NZV, cpu9s12x, 0 }, + { "incw", OP_D_IDX | OP_PAGE2, 2, 0x62, 6, 6, CHG_NZV, cpu9s12x, 0 }, + { "incw", OP_D_IDX_2 | OP_PAGE2, 4, 0x62, 6, 6, CHG_NZV, cpu9s12x, 0 }, + + { "incx", OP_NONE | OP_PAGE2, 3, 0x42, 4, 4, CHG_NZV, cpu9s12x, 0 }, + + { "incy", OP_NONE | OP_PAGE2, 3, 0x52, 4, 4, CHG_NZV, cpu9s12x, 0 }, + + { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811, 0 }, + + { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812|cpu9s12x, 0 }, + { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811, 0 }, + { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812|cpu9s12x, 0 }, + + { "jmp", OP_IND16 | OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811, 0 }, + { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811, 0 }, + { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811, 0 }, + { "jmp", OP_IND16 | OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811, 0 }, + { "jsr", OP_IND16 | OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811, 0 }, + { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811, 0 }, + { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811, 0 }, + { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jsr", OP_IND16 | OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 }, + { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811, 0 }, + { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812|cpu9s12x, 0 }, +/* lslw is the same as aslw. */ + { "lslw", OP_IND16 | OP_PAGE2, 3, 0x78, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "lslw", OP_IDX | OP_PAGE2, 2, 0x68, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "lslw", OP_IDX_1 | OP_PAGE2, 3, 0x68, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "lslw", OP_IDX_2 | OP_PAGE2, 4, 0x68, 5, 5, CHG_NZVC, cpu9s12x, 0 }, + { "lslw", OP_D_IDX | OP_PAGE2, 2, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "lslw", OP_D_IDX_2 | OP_PAGE2, 4, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 }, +/* lslx is same as aslx. */ + { "lslx", OP_NONE | OP_PAGE2, 1, 0x48, 1, 1, CHG_NZVC, cpu9s12x, 0 }, +/* lsly is the same as asly. */ + { "lsly", OP_NONE | OP_PAGE2, 1, 0x58, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811, 0 }, + { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811, 0 }, + { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 }, + { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 }, + { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 }, + { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 }, + { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 }, + + { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811, 0 }, + { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 }, + + { "lsrw", OP_IND16 | OP_PAGE2, 3, 0x74, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "lsrw", OP_IDX | OP_PAGE2, 2, 0x64, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "lsrw", OP_IDX_1 | OP_PAGE2, 3, 0x64, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "lsrw", OP_IDX_2 | OP_PAGE2, 4, 0x64, 5, 5, CHG_NZVC, cpu9s12x, 0 }, + { "lsrw", OP_D_IDX | OP_PAGE2, 2, 0x64, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "lsrw", OP_D_IDX_2 | OP_PAGE2, 4, 0x64, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "lsrx", OP_NONE | OP_PAGE2, 1, 0x44, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "lsry", OP_NONE | OP_PAGE2, 1, 0x54, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + + { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + +/* The S12X additional modes are implemented, but uncommenting here causes a problem */ + { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, +/* { "movb", OP_IMM8|OP_IDX1_p2|OP_PAGE2, 5, 0x08, 4, 4, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IMM8|OP_IDX2_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IMM8|OP_D_IDX|OP_PAGE2, 5, 0x08, 4, 4, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IMM8|OP_D_IDX2_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu9s12x, 0 },*/ + + { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "movb", OP_IND16|OP_IDX_p2|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, +/* { "movb", OP_IND16|OP_IDX1_p2|OP_PAGE2, 6, 0x09, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IND16|OP_IDX2_p2|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IND16|OP_D_IDX_p2|OP_PAGE2, 6, 0x09, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IND16|OP_D_IDX2_p2|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu9s12x, 0 }, */ + + { "movb", OP_IDX|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "movb", OP_IDX|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, +/* { "movb", OP_IDX|OP_IDX1_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX|OP_IDX2_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX|OP_D_IDX_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX|OP_D_IDX2_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + + { "movb", OP_IDX_1|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_1|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_1|OP_IDX1_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_1|OP_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_1|OP_D_IDX_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_1|OP_D_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + + { "movb", OP_IDX_2|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_2|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_2|OP_IDX1_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_2|OP_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_2|OP_D_IDX_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_IDX_2|OP_D_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + + { "movb", OP_D_IDX|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX|OP_IDX1_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX|OP_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX|OP_D_IDX_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX|OP_D_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + + { "movb", OP_D_IDX_2|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX_2|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX_2|OP_IDX1_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX_2|OP_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX_2|OP_D_IDX_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movb", OP_D_IDX_2|OP_D_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },*/ + + { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 }, +/* { "movw", OP_IMM16|OP_IDX1_p2|OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IMM16|OP_IDX2_p2|OP_PAGE2, 4, 0x00, 4, 4, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IMM16|OP_D_IDX_p2|OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IMM16|OP_D_IDX2_p2|OP_PAGE2, 4, 0x00, 4, 4, CHG_NONE, cpu9s12x, 0 },*/ + + { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, +/* { "movw", OP_IND16|OP_IDX1_p2|OP_PAGE2, 6, 0x01, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IND16|OP_IDX2_p2|OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IND16|OP_D_IDX_p2|OP_PAGE2, 6, 0x01, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IND16|OP_D_IDX2_p2|OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu9s12x, 0 },*/ + + { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, +/* { "movw", OP_IDX|OP_IDX1_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX|OP_IDX2_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX|OP_D_IDX_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX|OP_D_IDX2_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + + { "movw", OP_IDX_1|OP_IND16_p2|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_1|OP_IDX_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_1|OP_IDX1_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_1|OP_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_1|OP_D_IDX_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_1|OP_D_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + + { "movw", OP_IDX_2|OP_IND16_p2|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_2|OP_IDX_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_2|OP_IDX1_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_2|OP_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_2|OP_D_IDX_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_IDX_2|OP_D_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + + { "movw", OP_D_IDX|OP_IND16_p2|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX|OP_IDX_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX|OP_IDX1_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX|OP_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX|OP_D_IDX_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX|OP_D_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + + { "movw", OP_D_IDX_2|OP_IND16_p2|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX_2|OP_IDX_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX_2|OP_IDX1_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX_2|OP_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX_2|OP_D_IDX_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 }, + { "movw", OP_D_IDX_2|OP_D_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },*/ + + { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811, 0 }, + { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812|cpu9s12x, 0 }, + + { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + + { "negw", OP_IND16| OP_PAGE2, 3, 0x70, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "negw", OP_IDX| OP_PAGE2, 2, 0x60, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "negw", OP_IDX_1| OP_PAGE2, 3, 0x60, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "negw", OP_IDX_2| OP_PAGE2, 4, 0x60, 5, 5, CHG_NZVC, cpu9s12x, 0 }, + { "negw", OP_D_IDX| OP_PAGE2, 2, 0x60, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "negw", OP_D_IDX_2| OP_PAGE2, 4, 0x60, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "negx", OP_NONE| OP_PAGE2, 1, 0x40, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "negy", OP_NONE| OP_PAGE2, 1, 0x50, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811, 0 }, + { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 }, + { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812|cpu9s12x, 0 }, + + { "orx", OP_IMM16| OP_PAGE2, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "orx", OP_DIRECT| OP_PAGE2, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "orx", OP_IND16| OP_PAGE2, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "orx", OP_IDX| OP_PAGE2, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "orx", OP_IDX_1| OP_PAGE2, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "orx", OP_IDX_2| OP_PAGE2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "orx", OP_D_IDX| OP_PAGE2, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "orx", OP_D_IDX_2| OP_PAGE2,4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "ory", OP_IMM16| OP_PAGE2, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "ory", OP_DIRECT| OP_PAGE2, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "ory", OP_IND16| OP_PAGE2, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "ory", OP_IDX| OP_PAGE2, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "ory", OP_IDX_1| OP_PAGE2, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "ory", OP_IDX_2| OP_PAGE2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "ory", OP_D_IDX| OP_PAGE2, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + { "ory", OP_D_IDX_2| OP_PAGE2,4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 }, + + { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 }, + { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 }, + { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "pshcw", OP_NONE| OP_PAGE2,1, 0x39, 2, 2, CHG_NONE, cpu9s12x, 0 }, + { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811, 0 }, + { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811, 0 }, + { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 }, + { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 }, + { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "pulcw", OP_NONE| OP_PAGE2,1, 0x38, 2, 2, CHG_NONE, cpu9s12x, 0 }, + { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811, 0 }, + { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811, 0 }, + { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812|cpu9s12x, 0 }, + + { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811, 0 }, + { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811, 0 }, + { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "rolw", OP_IND16 | OP_PAGE2, 3, 0x75, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "rolw", OP_IDX | OP_PAGE2, 2, 0x65, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "rolw", OP_IDX_1 | OP_PAGE2, 3, 0x65, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "rolw", OP_IDX_2 | OP_PAGE2, 4, 0x65, 5, 5, CHG_NZVC, cpu9s12x, 0 }, + { "rolw", OP_D_IDX | OP_PAGE2, 2, 0x65, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "rolw", OP_D_IDX_2 | OP_PAGE2, 4, 0x65, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "rolx", OP_NONE | OP_PAGE2, 1, 0x45, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + { "roly", OP_NONE | OP_PAGE2, 1, 0x55, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + + { "rorw", OP_IND16 | OP_PAGE2, 3, 0x76, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "rorw", OP_IDX | OP_PAGE2, 2, 0x66, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "rorw", OP_IDX_1 | OP_PAGE2, 3, 0x66, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "rorw", OP_IDX_2 | OP_PAGE2, 4, 0x66, 5, 5, CHG_NZVC, cpu9s12x, 0 }, + { "rorw", OP_D_IDX | OP_PAGE2, 2, 0x66, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "rorw", OP_D_IDX_2 | OP_PAGE2, 4, 0x66, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "rorx", OP_NONE | OP_PAGE2, 1, 0x46, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + { "rory", OP_NONE | OP_PAGE2, 1, 0x56, 1, 1, CHG_NZVC, cpu9s12x, 0 }, + + { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 }, + { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811, 0 }, + { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812|cpu9s12x, 0 }, + { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811, 0 }, + { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811, 0 }, + { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811, 0 }, + { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811, 0 }, + { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "sbed", OP_IMM16 | OP_PAGE2, 3, 0x83, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "sbed", OP_DIRECT | OP_PAGE2, 2, 0x93, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbed", OP_IND16 | OP_PAGE2, 3, 0xb3, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbed", OP_IDX | OP_PAGE2, 2, 0xa3, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbed", OP_IDX_1 | OP_PAGE2, 3, 0xa3, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbed", OP_IDX_2 | OP_PAGE2, 4, 0xa3, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "sbed", OP_D_IDX | OP_PAGE2, 2, 0xa3, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "sbed", OP_D_IDX_2 | OP_PAGE2, 4, 0xa3, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "sbex", OP_IMM16 | OP_PAGE2, 3, 0x82, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "sbex", OP_DIRECT | OP_PAGE2, 2, 0x92, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbex", OP_IND16 | OP_PAGE2, 3, 0xb2, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbex", OP_IDX | OP_PAGE2, 2, 0xa2, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbex", OP_IDX_1 | OP_PAGE2, 3, 0xa2, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbex", OP_IDX_2 | OP_PAGE2, 4, 0xa2, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "sbex", OP_D_IDX | OP_PAGE2, 2, 0xa2, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "sbex", OP_D_IDX_2 | OP_PAGE2, 4, 0xa2, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "sbey", OP_IMM16 | OP_PAGE2, 3, 0xc2, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "sbey", OP_DIRECT | OP_PAGE2, 2, 0xd2, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbey", OP_IND16 | OP_PAGE2, 3, 0xf2, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbey", OP_IDX | OP_PAGE2, 2, 0xe2, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbey", OP_IDX_1 | OP_PAGE2, 3, 0xe2, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "sbey", OP_IDX_2 | OP_PAGE2, 4, 0xe2, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "sbey", OP_D_IDX | OP_PAGE2, 2, 0xe2, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "sbey", OP_D_IDX_2 | OP_PAGE2, 4, 0xe2, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811, 0 }, + { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811, 0 }, + { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811, 0 }, + +/* Some sex opcodes are synonyms for tfr. */ { "sex", M6812_OP_SEX_MARKER - | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, - - { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 }, - { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - - { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 }, - { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - - { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - - { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 }, - { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 }, - - { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - - { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 }, - { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - - { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, - { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, - { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, - { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, - - { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 }, - { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 }, - { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, - { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, - { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 }, - { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, - { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, - - { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, - { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 }, - { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 }, - { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, - { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, - { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 }, - { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, - { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, - - { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, - { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, - { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 }, - { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, - { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, - { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, - { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 }, - { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, - { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, - - { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812 }, - - { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 }, - { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - - { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 }, - - { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 }, - { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, - - { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, - - { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 }, + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 }, + { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 }, + { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811, 0 }, + { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 }, + { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 }, + { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 }, + { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811, 0 }, + { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811, 0 }, + { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811, 0 }, + { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 }, + { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811, 0 }, + { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 }, + { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 }, + + { "subx", OP_IMM16 | OP_PAGE2, 3, 0x80, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "subx", OP_DIRECT | OP_PAGE2, 2, 0x90, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "subx", OP_IND16 | OP_PAGE2, 3, 0xb0, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "subx", OP_IDX | OP_PAGE2, 2, 0xa0, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "subx", OP_IDX_1 | OP_PAGE2, 3, 0xa0, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "subx", OP_IDX_2 | OP_PAGE2, 4, 0xa0, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "subx", OP_D_IDX | OP_PAGE2, 2, 0xa0, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "subx", OP_D_IDX_2 | OP_PAGE2, 4, 0xa0, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "suby", OP_IMM16 | OP_PAGE2, 3, 0xc0, 2, 2, CHG_NZVC, cpu9s12x, 0 }, + { "suby", OP_DIRECT | OP_PAGE2, 2, 0xd0, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "suby", OP_IND16 | OP_PAGE2, 3, 0xf0, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "suby", OP_IDX | OP_PAGE2, 2, 0xe0, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "suby", OP_IDX_1 | OP_PAGE2, 3, 0xe0, 3, 3, CHG_NZVC, cpu9s12x, 0 }, + { "suby", OP_IDX_2 | OP_PAGE2, 4, 0xe0, 4, 4, CHG_NZVC, cpu9s12x, 0 }, + { "suby", OP_D_IDX | OP_PAGE2, 2, 0xe0, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + { "suby", OP_D_IDX_2 | OP_PAGE2, 4, 0xe0, 6, 6, CHG_NZVC, cpu9s12x, 0 }, + + { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 }, + { "sys", OP_NONE | OP_PAGE2,2, 0xa7, 9, 9, SET_I, cpu9s12x, 0 }, + + { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811, 0 }, + { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811, 0 }, + + { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811, 0 }, + { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811, 0 }, + + { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811, 0 }, { "tbeq", OP_TBEQ_MARKER - | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, - { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 }, + { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812|cpu9s12x, 0 }, { "tbne", OP_TBNE_MARKER - | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 }, +/* The S12X has more tfr variants, but most are pointless so not supported. */ { "tfr", OP_TFR_MARKER - | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, - - { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 }, - - { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, - { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, - { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 }, - { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, - { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, - { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, - { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 }, - { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, - { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, - - { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, - { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, - { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, - { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, - - { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 }, - { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 }, - { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 }, - { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 }, - - { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812 }, - - { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 }, - - { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 }, - { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 } + | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812|cpu9s12x, 0 }, + + { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812|cpu9s12x, 0 }, + + { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811, 0 }, + { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811, 0 }, + { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811, 0 }, + { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811, 0 }, + { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 }, + { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811, 0 }, + { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 }, + + { "tstw", OP_IND16| OP_PAGE2, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu9s12x, 0 }, + { "tstw", OP_IDX| OP_PAGE2, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu9s12x, 0 }, + { "tstw", OP_IDX_1| OP_PAGE2, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu9s12x, 0 }, + { "tstw", OP_IDX_2| OP_PAGE2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu9s12x, 0 }, + { "tstw", OP_D_IDX| OP_PAGE2, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu9s12x, 0 }, + { "tstw", OP_D_IDX_2| OP_PAGE2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu9s12x, 0 }, + + { "tstx", OP_NONE| OP_PAGE2, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu9s12x, 0 }, + { "tsty", OP_NONE| OP_PAGE2, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu9s12x, 0 }, + + { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811, 0 }, + { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811, 0 }, + { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811, 0 }, + { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811, 0 }, + + { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 }, + + { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812|cpu9s12x, 0 }, + + { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811, 0 }, + { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811, 0 }, + +/* XGATE opcodes */ +/* Return to Scheduler and Others*/ + { "brk", M68XG_OP_NONE, 2, 0x0000, 0, 0, 0, 0, 0, cpuxgate, 0xffff }, + { "nop", M68XG_OP_NONE, 2, 0x0100, 0, 0, 0, 0, 0, cpuxgate, 0xffff }, + { "rts", M68XG_OP_NONE, 2, 0x0200, 0, 0, 0, 0, 0, cpuxgate, 0xffff }, + { "sif", M68XG_OP_NONE, 2, 0x0300, 0, 0, 0, 0, 0, cpuxgate, 0xffff }, +/* Semaphore Instructions */ + { "csem", M68XG_OP_IMM3, 2, 0x00f0, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, + { "csem", M68XG_OP_R, 2, 0x00f1, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, + { "ssem", M68XG_OP_IMM3, 2, 0x00f2, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, + { "ssem", M68XG_OP_R, 2, 0x00f3, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, +/* Single Register Instructions */ + { "sex", M68XG_OP_R, 2, 0x00f4, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, + { "par", M68XG_OP_R, 2, 0x00f5, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, + { "jal", M68XG_OP_R, 2, 0x00f6, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, + { "sif", M68XG_OP_R, 2, 0x00f7, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, +/* Special Move instructions */ + { "tfr", M68XG_OP_R, 2, 0x00f8, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* RD,CCR */ + { "tfr", M68XG_OP_R, 2, 0x00f9, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* CCR,RS */ + { "tfr", M68XG_OP_R, 2, 0x00fa, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* RD,PC */ +/* Shift instructions Dyadic */ + { "bffo", M68XG_OP_R_R, 2, 0x0810, 0, 0, 0, 0, 0, cpuxgate, 0xf81f }, + { "asr", M68XG_OP_R_R, 2, 0x0811, 0, 0, 0, 0, 0, cpuxgate, 0xf81f }, + { "csl", M68XG_OP_R_R, 2, 0x0812, 0, 0, 0, 0, 0, cpuxgate, 0xf81f }, + { "csr", M68XG_OP_R_R, 2, 0x0813, 0, 0, 0, 0, 0, cpuxgate, 0xf81f }, + { "lsl", M68XG_OP_R_R, 2, 0x0814, 0, 0, 0, 0, 0, cpuxgate, 0xf81f }, + { "lsr", M68XG_OP_R_R, 2, 0x0815, 0, 0, 0, 0, 0, cpuxgate, 0xf81f }, + { "rol", M68XG_OP_R_R, 2, 0x0816, 0, 0, 0, 0, 0, cpuxgate, 0xf81f }, + { "ror", M68XG_OP_R_R, 2, 0x0817, 0, 0, 0, 0, 0, cpuxgate, 0xf81f }, +/* Dyadic aliases */ + { "cmp", M68XG_OP_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "com", M68XG_OP_R_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "cpc", M68XG_OP_R_R, 2, 0x1801, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "mov", M68XG_OP_R_R, 2, 0x1002, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "neg", M68XG_OP_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, +/* Monadic aliases */ + { "com", M68XG_OP_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "neg", M68XG_OP_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "tst", M68XG_OP_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, +/* Shift instructions immediate */ + { "asr", M68XG_OP_R_IMM4, 2, 0x0809, 0, 0, 0, 0, 0, cpuxgate, 0xf80f }, + { "csl", M68XG_OP_R_IMM4, 2, 0x080a, 0, 0, 0, 0, 0, cpuxgate, 0xf80f }, + { "csr", M68XG_OP_R_IMM4, 2, 0x080b, 0, 0, 0, 0, 0, cpuxgate, 0xf80f }, + { "lsl", M68XG_OP_R_IMM4, 2, 0x080c, 0, 0, 0, 0, 0, cpuxgate, 0xf80f }, + { "lsr", M68XG_OP_R_IMM4, 2, 0x080d, 0, 0, 0, 0, 0, cpuxgate, 0xf80f }, + { "rol", M68XG_OP_R_IMM4, 2, 0x080e, 0, 0, 0, 0, 0, cpuxgate, 0xf80f }, + { "ror", M68XG_OP_R_IMM4, 2, 0x080f, 0, 0, 0, 0, 0, cpuxgate, 0xf80f }, +/* Logical Triadic */ + { "and", M68XG_OP_R_R_R, 2, 0x1000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "or", M68XG_OP_R_R_R, 2, 0x1002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "xnor", M68XG_OP_R_R_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, +/* Arithmetic Triadic */ + { "sub", M68XG_OP_R_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "sbc", M68XG_OP_R_R_R, 2, 0x1801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "add", M68XG_OP_R_R_R, 2, 0x1802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "adc", M68XG_OP_R_R_R, 2, 0x1803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, +/* Branches */ + { "bcc", M68XG_OP_REL9, 2, 0x2000, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bhs", M68XG_OP_REL9, 2, 0x2000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, /* Synonym. */ + { "bcs", M68XG_OP_REL9, 2, 0x2200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "blo", M68XG_OP_REL9, 2, 0x2200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, /* Synonym. */ + { "bne", M68XG_OP_REL9, 2, 0x2400, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "beq", M68XG_OP_REL9, 2, 0x2600, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bpl", M68XG_OP_REL9, 2, 0x2800, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bmi", M68XG_OP_REL9, 2, 0x2a00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bvc", M68XG_OP_REL9, 2, 0x2c00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bvs", M68XG_OP_REL9, 2, 0x2e00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bhi", M68XG_OP_REL9, 2, 0x3000, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bls", M68XG_OP_REL9, 2, 0x3200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bge", M68XG_OP_REL9, 2, 0x3400, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "blt", M68XG_OP_REL9, 2, 0x3600, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bgt", M68XG_OP_REL9, 2, 0x3800, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "ble", M68XG_OP_REL9, 2, 0x3a00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, + { "bra", M68XG_OP_REL10, 2, 0x3c00, 0, 0, 0, 0, 0, cpuxgate, 0xfc00 }, +/* Load and Store Instructions */ + { "ldb", M68XG_OP_R_R_OFFS5, 2, 0x4000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "ldw", M68XG_OP_R_R_OFFS5, 2, 0x4800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "stb", M68XG_OP_R_R_OFFS5, 2, 0x5000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "stw", M68XG_OP_R_R_OFFS5, 2, 0x5800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + + { "ldb", M68XG_OP_RD_RB_RI, 2, 0x6000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "ldw", M68XG_OP_RD_RB_RI, 2, 0x6800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "stb", M68XG_OP_RD_RB_RI, 2, 0x7000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "stw", M68XG_OP_RD_RB_RI, 2, 0x7800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + + { "ldb", M68XG_OP_RD_RB_RIp, 2, 0x6001, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "ldw", M68XG_OP_RD_RB_RIp, 2, 0x6801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "stb", M68XG_OP_RD_RB_RIp, 2, 0x7001, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "stw", M68XG_OP_RD_RB_RIp, 2, 0x7801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + + { "ldb", M68XG_OP_RD_RB_mRI, 2, 0x6002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "ldw", M68XG_OP_RD_RB_mRI, 2, 0x6802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "stb", M68XG_OP_RD_RB_mRI, 2, 0x7002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "stw", M68XG_OP_RD_RB_mRI, 2, 0x7802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, +/* Bit Field Instructions */ + { "bfext", M68XG_OP_R_R_R, 2, 0x6003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "bfins", M68XG_OP_R_R_R, 2, 0x6803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "bfinsi",M68XG_OP_R_R_R, 2, 0x7003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, + { "bfinsx",M68XG_OP_R_R_R, 2, 0x7803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 }, +/* Logic Immediate Instructions */ + { "andl", M68XG_OP_R_IMM8, 2, 0x8000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "andh", M68XG_OP_R_IMM8, 2, 0x8800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "bitl", M68XG_OP_R_IMM8, 2, 0x9000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "bith", M68XG_OP_R_IMM8, 2, 0x9800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "orl", M68XG_OP_R_IMM8, 2, 0xa000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "orh", M68XG_OP_R_IMM8, 2, 0xa800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "xnorl", M68XG_OP_R_IMM8, 2, 0xb000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "xnorh", M68XG_OP_R_IMM8, 2, 0xb800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, +/* Arithmetic Immediate Instructions */ + { "subl", M68XG_OP_R_IMM8, 2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "subh", M68XG_OP_R_IMM8, 2, 0xc800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "cmpl", M68XG_OP_R_IMM8, 2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "cpch", M68XG_OP_R_IMM8, 2, 0xd800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "addl", M68XG_OP_R_IMM8, 2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "addh", M68XG_OP_R_IMM8, 2, 0xe800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "ldl", M68XG_OP_R_IMM8, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, + { "ldh", M68XG_OP_R_IMM8, 2, 0xf800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 }, +/* 16 bit versions. + * These are pseudo opcodes to allow 16 bit addresses to be passed. + * The mask ensures that we will never disassemble to these instructions. + */ +/* Logic Immediate Instructions */ + { "and", M68XG_OP_R_IMM16, 2, 0x8000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "bit", M68XG_OP_R_IMM16, 2, 0x9000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "or", M68XG_OP_R_IMM16, 2, 0xa000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "xnor", M68XG_OP_R_IMM16, 2, 0xb000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, +/* Arithmetic Immediate Instructions */ + { "sub", M68XG_OP_R_IMM16, 2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "cmp", M68XG_OP_R_IMM16, 2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "add", M68XG_OP_R_IMM16, 2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + /* ld is for backwards compatability only, the correct opcode is ldw */ + { "ld", M68XG_OP_R_IMM16, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, + { "ldw", M68XG_OP_R_IMM16, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 } }; const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes); |