Merge from branch into devo. CGEN generic files moved to common

	directory.  K&R C support is no longer provided.

9 files changed, 8326 insertions, 0 deletions

diff --git a/sim/m32r/.Sanitize b/sim/m32r/.Sanitize
index fb4f084..7ea15d9 100644
--- a/sim/m32r/.Sanitize
+++ b/sim/m32r/.Sanitize
@@ -24,7 +24,28 @@ Do-first:
 
 Things-to-keep:
 
+ChangeLog
+Makefile.in
 README
+TODO
+arch-defs.h
+config.in
+configure
+configure.in
+decode.c
+decode.h
+extract.c
+m32r-sim.h
+m32r.c
+mainloop.in
+mem-ops.h
+model.c
+sem-ops.h
+sem-switch.c
+semantics.c
+sim-if.c
+sim-main.h
+tconfig.in
 
 Things-to-lose:
 
diff --git a/sim/m32r/arch-defs.h b/sim/m32r/arch-defs.h
new file mode 100644
index 0000000..7dee7ca
--- /dev/null
+++ b/sim/m32r/arch-defs.h
@@ -0,0 +1,241 @@
+/* Simulator header for m32r.
+
+This file is machine generated.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef M32R_ARCH_DEFS_H
+#define M32R_ARCH_DEFS_H
+
+#define MAX_INSNS 128
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Word and address accesses.  */
+/* FIXME: Later need to allow runtime selection.  */
+
+#define GETTWI(addr) GETTSI (addr)
+#define GETTUWI(addr) GETTUSI (addr)
+#define GETTAI(addr) GETTSI (addr)
+
+#define SETTWI(addr, val) SETTSI ((addr), (val))
+#define SETTUWI(addr, val) SETTUSI ((addr), (val))
+#define SETTAI(addr, val) SETTSI ((addr), (val))
+
+#define GETMEMWI(cpu, addr) GETMEMSI ((cpu), (addr))
+#define GETMEMUWI(cpu, addr) GETMEMUSI ((cpu), (addr))
+#define GETMEMAI(cpu, addr) GETMEMSI ((cpu), (addr))
+
+#define SETMEMWI(cpu, addr, val) SETMEMSI ((cpu), (addr), (val))
+#define SETMEMUWI(cpu, addr, val) SETMEMUSI ((cpu), (addr), (val))
+#define SETMEMAI(cpu, addr, val) SETMEMSI ((cpu), (addr), (val))
+
+/* FIXME: Used? */
+#define SETMEM(addr, val, len) (*STATE_MEM_WRITE (current_state)) (current_state, (addr), (val), (len))
+
+/* FIXME */
+typedef SI WI;
+typedef USI UWI;
+
+/* CPU state information.  */
+typedef struct {
+  /* program counter */
+  SI pc;
+  /* general registers */
+  SI h_gr[16];
+  /* control registers */
+  SI h_cr[7];
+  /* accumulator */
+  DI h_accum;
+  /* condition bit */
+  UBI h_cond;
+  /* sm */
+  UBI h_sm;
+  /* bsm */
+  UBI h_bsm;
+  /* ie */
+  UBI h_ie;
+  /* bie */
+  UBI h_bie;
+  /* bcond */
+  UBI h_bcond;
+  /* bpc */
+  SI h_bpc;
+} CPU_DATA;
+
+#ifdef USING_SIM_BASE_H /* FIXME:quick hack */
+#define CPU(x) (STATE_CPU_CPU (current_state, 0)->x)
+#else
+#define CPU(x) (STATE_CPU (current_state).x)
+#endif
+
+/* CPU profiling state information.  */
+typedef struct {
+  /* general registers */
+  unsigned long h_gr;
+} CPU_PROFILE;
+
+/* Enum declaration for mode types.  */
+typedef enum mode_type {
+  MODE_VM, MODE_BI, MODE_QI, MODE_HI,
+  MODE_SI, MODE_DI, MODE_UBI, MODE_UQI,
+  MODE_UHI, MODE_USI, MODE_UDI, MODE_SF,
+  MODE_DF, MODE_XF, MODE_TF, MODE_MAX
+} MODE_TYPE;
+
+#define MAX_MODES ((int) MODE_MAX)
+
+/* Return name of instruction numbered INSN.  */
+#define INSN_NAME(insn) (m32r_cgen_insn_table_entries[insn].syntax.name)
+
+/* Enum declaration for model types.  */
+typedef enum model_type {
+  MODEL_M32R_D, MODEL_TEST, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types.  */
+typedef enum unit_type {
+  UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_EXEC,
+  UNIT_TEST_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (1)
+
+typedef struct argbuf {
+  union {
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+  } fmt_0;
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+    HI f_simm16;
+  } fmt_1;
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+    USI f_uimm16;
+  } fmt_2;
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+    UHI f_uimm16;
+  } fmt_3;
+  struct {
+    SI * f_r1;
+    SI f_simm8;
+  } fmt_4;
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+    SI f_simm16;
+  } fmt_5;
+  struct {
+    IADDR f_disp8;
+  } fmt_6;
+  struct {
+    IADDR f_disp24;
+  } fmt_7;
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+    IADDR f_disp16;
+  } fmt_8;
+  struct {
+    SI * f_r2;
+    IADDR f_disp16;
+  } fmt_9;
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+  } fmt_10;
+  struct {
+    SI * f_r2;
+    SI f_simm16;
+  } fmt_11;
+  struct {
+    SI * f_r2;
+    USI f_uimm16;
+  } fmt_12;
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+  } fmt_13;
+  struct {
+    SI * f_r2;
+  } fmt_14;
+  struct {
+    SI * f_r1;
+    ADDR f_uimm24;
+  } fmt_15;
+  struct {
+    SI * f_r1;
+    HI f_simm16;
+  } fmt_16;
+  struct {
+    SI * f_r1;
+  } fmt_17;
+  struct {
+    SI * f_r1;
+    UINT f_r2;
+  } fmt_18;
+  struct {
+    SI * f_r1;
+  } fmt_19;
+  struct {
+    UINT f_r1;
+    SI * f_r2;
+  } fmt_20;
+  struct {
+    int empty;
+  } fmt_21;
+  struct {
+    SI * f_r1;
+    UHI f_hi16;
+  } fmt_22;
+  struct {
+    SI * f_r1;
+    USI f_uimm5;
+  } fmt_23;
+  struct {
+    SI * f_r1;
+    SI * f_r2;
+    HI f_simm16;
+  } fmt_24;
+  struct {
+    USI f_uimm4;
+  } fmt_25;
+  } fields;
+  unsigned int length;
+  PCADDR addr;
+#if 1 || defined (MODULE_trace) || defined (MODULE_profile) /*FIXME:wip*/
+  const struct cgen_insn *opcode;
+#endif
+#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
+  unsigned long h_gr_get;
+  unsigned long h_gr_set;
+#endif
+} ARGBUF;
+
+#endif /* M32R_ARCH_DEFS_H */
diff --git a/sim/m32r/configure.in b/sim/m32r/configure.in
new file mode 100644
index 0000000..9618408
--- /dev/null
+++ b/sim/m32r/configure.in
@@ -0,0 +1,16 @@
+dnl Process this file with autoconf to produce a configure script.
+sinclude(../common/aclocal.m4)
+AC_PREREQ(2.5)dnl
+AC_INIT(Makefile.in)
+
+SIM_AC_COMMON
+
+sim_link_files="${sim_link_files} m32r-sim.h ../../opcodes/m32r-opc.h"
+sim_link_links="${sim_link_links} cpu-sim.h cpu-opc.h"
+
+SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(1024)
+SIM_AC_OPTION_DEFAULT_MODEL(m32r/d)
+
+SIM_AC_OUTPUT
diff --git a/sim/m32r/extract.c b/sim/m32r/extract.c
new file mode 100644
index 0000000..479d6aa
--- /dev/null
+++ b/sim/m32r/extract.c
@@ -0,0 +1,3685 @@
+/* Simulator instruction extractor for m32r.
+
+This file is machine generated.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "decode.h"
+#include "cpu-sim.h"
+
+void
+EX_FN_NAME (add) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (add3) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "add3", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (and) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "and", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (and3) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_2.f
+  /* Instruction fields.  */
+  int f_uimm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_uimm16) = f_uimm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "and3", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (or) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "or", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (or3) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_3.f
+  /* Instruction fields.  */
+  int f_uimm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_uimm16) = f_uimm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "or3", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "ulo16 0x%x", 'x', f_uimm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (xor) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "xor", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (xor3) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_2.f
+  /* Instruction fields.  */
+  int f_uimm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_uimm16) = f_uimm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "xor3", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (addi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_4.f
+  /* Instruction fields.  */
+  int f_simm8;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_simm8) = f_simm8;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "addi", "dr 0x%x", 'x', f_r1, "simm8 0x%x", 'x', f_simm8, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (addv) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (addv3) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_5.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "addv3", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (addx) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bc8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_6.f
+  /* Instruction fields.  */
+  int f_disp8;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  RECORD_IADDR (FLD (f_disp8), (pc & -4L) + f_disp8);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (bc24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_7.f
+  /* Instruction fields.  */
+  int f_disp24;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  RECORD_IADDR (FLD (f_disp24), pc + f_disp24);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (beq) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_8.f
+  /* Instruction fields.  */
+  int f_disp16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  RECORD_IADDR (FLD (f_disp16), pc + f_disp16);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (beqz) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  /* Instruction fields.  */
+  int f_disp16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  RECORD_IADDR (FLD (f_disp16), pc + f_disp16);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bgez) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  /* Instruction fields.  */
+  int f_disp16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  RECORD_IADDR (FLD (f_disp16), pc + f_disp16);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bgez", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bgtz) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  /* Instruction fields.  */
+  int f_disp16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  RECORD_IADDR (FLD (f_disp16), pc + f_disp16);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bgtz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (blez) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  /* Instruction fields.  */
+  int f_disp16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  RECORD_IADDR (FLD (f_disp16), pc + f_disp16);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "blez", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bltz) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  /* Instruction fields.  */
+  int f_disp16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  RECORD_IADDR (FLD (f_disp16), pc + f_disp16);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bltz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bnez) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  /* Instruction fields.  */
+  int f_disp16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  RECORD_IADDR (FLD (f_disp16), pc + f_disp16);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bnez", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bl8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_6.f
+  /* Instruction fields.  */
+  int f_disp8;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  RECORD_IADDR (FLD (f_disp8), (pc & -4L) + f_disp8);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << 14);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bl24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_7.f
+  /* Instruction fields.  */
+  int f_disp24;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  RECORD_IADDR (FLD (f_disp24), pc + f_disp24);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << 14);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bnc8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_6.f
+  /* Instruction fields.  */
+  int f_disp8;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  RECORD_IADDR (FLD (f_disp8), (pc & -4L) + f_disp8);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bnc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (bnc24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_7.f
+  /* Instruction fields.  */
+  int f_disp24;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  RECORD_IADDR (FLD (f_disp24), pc + f_disp24);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bnc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (bne) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_8.f
+  /* Instruction fields.  */
+  int f_disp16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  RECORD_IADDR (FLD (f_disp16), pc + f_disp16);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bne", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (bra8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_6.f
+  /* Instruction fields.  */
+  int f_disp8;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  RECORD_IADDR (FLD (f_disp8), (pc & -4L) + f_disp8);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (bra24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_7.f
+  /* Instruction fields.  */
+  int f_disp24;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  RECORD_IADDR (FLD (f_disp24), pc + f_disp24);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (cmp) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (cmpi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_11.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_op2;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "cmpi", "src2 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (cmpu) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "cmpu", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (cmpui) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_12.f
+  /* Instruction fields.  */
+  int f_uimm16;
+  int f_r2;
+  int f_op2;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_uimm16) = f_uimm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "cmpui", "src2 0x%x", 'x', f_r2, "uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (div) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_13.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (divu) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_13.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "divu", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (rem) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_13.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "rem", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (remu) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_13.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "remu", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (jl) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_14.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_op2;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "jl", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << 14);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (jmp) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_14.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_op2;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ld) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ld", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ld_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ld_d", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ldb) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ldb", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ldb_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ldb_d", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ldh) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ldh", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ldh_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ldh_d", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ldub) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ldub", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ldub_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ldub_d", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (lduh) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "lduh", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (lduh_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "lduh_d", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ld_plus) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_op2;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ld_plus", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ld24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_15.f
+  /* Instruction fields.  */
+  int f_uimm24;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_uimm24) = f_uimm24;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ld24", "dr 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ldi8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_4.f
+  /* Instruction fields.  */
+  int f_simm8;
+  int f_r1;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_simm8) = f_simm8;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ldi8", "dr 0x%x", 'x', f_r1, "simm8 0x%x", 'x', f_simm8, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (ldi16) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_16.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r1;
+  int f_r2;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "ldi16", "dr 0x%x", 'x', f_r1, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (lock) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "lock", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (machi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (maclo) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "maclo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (macwhi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "macwhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (macwlo) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "macwlo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mul) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mul", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mulhi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mullo) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mullo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mulwhi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mulwhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mulwlo) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mulwlo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mv) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mvfachi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_17.f
+  /* Instruction fields.  */
+  int f_r1;
+  int f_r2;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mvfaclo) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_17.f
+  /* Instruction fields.  */
+  int f_r1;
+  int f_r2;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mvfaclo", "dr 0x%x", 'x', f_r1, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mvfacmi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_17.f
+  /* Instruction fields.  */
+  int f_r1;
+  int f_r2;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mvfacmi", "dr 0x%x", 'x', f_r1, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mvfc) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_18.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = f_r2;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mvfc", "dr 0x%x", 'x', f_r1, "scr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mvtachi) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_19.f
+  /* Instruction fields.  */
+  int f_r1;
+  int f_r2;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mvtaclo) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_19.f
+  /* Instruction fields.  */
+  int f_r1;
+  int f_r2;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mvtaclo", "src1 0x%x", 'x', f_r1, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (mvtc) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_20.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "mvtc", "dcr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (neg) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "neg", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (nop) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_21.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "nop", (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (not) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "not", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (rac) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_21.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "rac", (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (rach) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_21.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "rach", (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (rte) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_21.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "rte", (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (seth) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_22.f
+  /* Instruction fields.  */
+  int f_hi16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_hi16) = f_hi16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "seth", "dr 0x%x", 'x', f_r1, "hi16 0x%x", 'x', f_hi16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (sll) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "sll", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (sll3) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_5.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "sll3", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (slli) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_23.f
+  /* Instruction fields.  */
+  int f_uimm5;
+  int f_r1;
+  int f_shift_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_uimm5) = f_uimm5;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (sra) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "sra", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (sra3) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_5.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "sra3", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (srai) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_23.f
+  /* Instruction fields.  */
+  int f_uimm5;
+  int f_r1;
+  int f_shift_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_uimm5) = f_uimm5;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "srai", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (srl) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "srl", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (srl3) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_5.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "srl3", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (srli) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_23.f
+  /* Instruction fields.  */
+  int f_uimm5;
+  int f_r1;
+  int f_shift_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_uimm5) = f_uimm5;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "srli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (st) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (st_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_24.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "st_d", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (stb) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (stb_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_24.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "stb_d", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (sth) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (sth_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_24.f
+  /* Instruction fields.  */
+  int f_simm16;
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 4;
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16);
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "sth_d", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (st_plus) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (st_minus) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "st_minus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (sub) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "sub", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (subv) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "subv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (subx) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "subx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << f_r1);
+    }
+#endif
+#undef FLD
+}
+
+void
+EX_FN_NAME (trap) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_25.f
+  /* Instruction fields.  */
+  int f_uimm4;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_uimm4) = f_uimm4;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (unlock) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  /* Instruction fields.  */
+  int f_r2;
+  int f_r1;
+  int f_op2;
+  int f_op1;
+  /* The length of the insn may be fixed or variable.  */
+  int length;
+
+  /* Extract the fields of the insn, computing the length as we go.  */
+  length = 2;
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4);
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4);
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4);
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = & CPU (h_gr[f_r1]);
+  FLD (f_r2) = & CPU (h_gr[f_r2]);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2);
+    }
+#endif
+#undef FLD
+}
+
diff --git a/sim/m32r/mainloop.in b/sim/m32r/mainloop.in
new file mode 100644
index 0000000..a7cd751
--- /dev/null
+++ b/sim/m32r/mainloop.in
@@ -0,0 +1,321 @@
+# This shell script emits C code. -*- C -*-
+# Main loop and support routines for the M32R.
+# Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+# Contributed by Cygnus Support.
+#
+# This file is part of GDB, the GNU debugger.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in {init|normal|fast|support}
+
+# ??? There's lots of conditional compilation here.
+# After a few more ports are done, revisit.
+
+case "x$1" in
+
+xinit)
+
+cat <<EOF
+#if defined (WITH_SCACHE) && defined (USE_SEM_SWITCH) && defined (__GNUC__)
+{
+  static decode_init_p = 0;
+  if (! decode_init_p)
+    {
+/* ??? Later maybe paste sem-switch.c in when building mainloop.c.  */
+#define DEFINE_LABELS
+#include "sem-switch.c"
+      decode_init_p = 1;
+    }
+}
+#endif
+EOF
+
+;;
+
+xnormal | xfast)
+
+cat <<EOF
+
+#if WITH_SCACHE
+
+{
+  int hash;
+  SCACHE *sc;
+
+  /* First step: look up current insn in hash table.  */
+  hash = SCACHE_HASH_PC (sd, PC);
+  sc = CPU_SCACHE_CACHE (current_cpu) + hash;
+
+  /* If the entry isn't the one we want (cache miss),
+     fetch and decode the instruction.  */
+  if (sc->argbuf.addr != PC)
+    {
+      PCADDR pc = PC;
+      insn_t insn;
+
+#if ! FAST
+      PROFILE_COUNT_SCACHE_MISS (current_cpu);
+#endif
+
+      /* This only occurs when single stepping.
+	 The test is unnecessary otherwise, but the cost is teensy,
+	 compared with decoding/extraction.  */
+      if (pc & 3)
+	{
+	  insn = GETMEMUHI (current_cpu, pc);
+	  do_extract_insn16 (current_cpu, pc, insn & 0x7fff, sc, FAST);
+	}
+      else
+	{
+	  insn = GETMEMUSI (current_cpu, pc);
+
+	  if (insn & 0x80000000)
+	    {
+	      do_extract_insn32 (current_cpu, pc, insn, sc, FAST);
+	    }
+	  else
+	    {
+	      /* 2 16 bit insns.  Ignore parallel case for now
+		 (2nd always nop).  Decode both as we know there's room.
+		 ??? Could do a test for an unconditional branch in the
+		 left slot if one wanted to.  */
+	      do_extract_insn16 (current_cpu, pc, insn >> 16, sc, FAST);
+	      do_extract_insn16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, FAST);
+	    }
+	}
+    }
+#if ! FAST
+  else
+    {
+      PROFILE_COUNT_SCACHE_HIT (current_cpu);
+    }
+#endif
+
+#if 0 /*FIXME:wip*/
+
+  /* Run until we get a cache miss.  */
+  do
+    {
+#if ! FAST
+      TRACE_INSN_INIT (current_cpu);
+      TRACE_INSN (current_cpu, sc->argbuf.opcode, &sc->argbuf, sc->argbuf.addr);
+#endif
+
+      sc = (*sc->semantic.sem_fn) (current_cpu, sc);
+
+#if ! FAST
+      TRACE_INSN_FINI (current_cpu);
+#endif
+    }
+  while (sc->argbuf.addr == PC);
+
+#if ! FAST
+  PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (sc->argbuf.opcode));
+#endif
+
+#else /* !wip */
+
+#if ! FAST
+  TRACE_INSN_INIT (current_cpu);
+  TRACE_INSN (current_cpu, sc->argbuf.opcode, &sc->argbuf, sc->argbuf.addr);
+#endif
+
+#if FAST && defined (USE_SEM_SWITCH)
+#define DEFINE_SWITCH
+#include "sem-switch.c"
+#else
+  PC = (*sc->semantic.sem_fn) (current_cpu, sc);
+#endif
+
+#if ! FAST
+  TRACE_INSN_FINI (current_cpu);
+
+  PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (sc->argbuf.opcode));
+#endif
+
+#endif /* !wip */
+}
+
+#else /* ! WITH_SCACHE */
+
+{
+  insn_t insn;
+
+  if (PC & 3)
+    {
+      insn = GETMEMUHI (current_cpu, PC);
+      PC = do_insn16 (current_cpu, PC, insn & 0x7fff);
+    }
+  else
+    {
+      insn = GETMEMUSI (current_cpu, PC);
+
+      if (insn & 0x80000000)
+	{
+	  /* 32 bit insn */
+	  PC = do_insn32 (current_cpu, PC, insn);
+	}
+      else
+	{
+	  /* 2 16 bit insns.  Ignore parallel case for now
+	     (2nd always nop).  */
+
+	  PCADDR oldpc = PC;
+	  PC = do_insn16 (current_cpu, PC, insn >> 16);
+	  if (PC == oldpc + 2)
+	    {
+	      PC = do_insn16 (current_cpu, PC, insn & 0x7fff);
+	    }
+	}
+    }
+}
+
+#endif /* ! WITH_SCACHE */
+
+EOF
+
+;;
+
+xsupport)
+
+cat <<EOF
+
+#if WITH_SCACHE
+
+#ifdef __GNUC__
+#define DO_INLINE inline
+#else
+#define DO_INLINE
+#endif
+
+/* FAST is optimized out by GCC.  */
+
+static DO_INLINE void
+do_extract_insn16 (SIM_CPU *cpu, PCADDR pc, insn_t insn,
+		   SCACHE *sc, int fast)
+{
+  DECODE *d = decode (insn);
+  (*d->extract) (cpu, pc, insn, &sc->argbuf);
+  if (fast)
+    {
+#ifdef USE_SEM_SWITCH
+#ifdef __GNUC__
+      sc->semantic.sem_case = d->semantic_lab;
+#else
+      sc->semantic.sem_case = d->insn_type;
+#endif
+#else
+      sc->semantic.sem_fn = d->semantic_fast;
+#endif
+    }
+  else
+    {
+      sc->semantic.sem_fn = d->semantic_fast;
+      sc->argbuf.opcode = d->opcode;
+    }
+  sc->next = pc + 2;
+}
+
+static DO_INLINE void
+do_extract_insn32 (SIM_CPU *cpu, PCADDR pc, insn_t insn,
+		   SCACHE *sc, int fast)
+{
+  /* 32 bit insn */
+  DECODE *d = decode (insn >> 16);
+  (*d->extract) (cpu, pc, insn, &sc->argbuf);
+  if (fast)
+    {
+#ifdef USE_SEM_SWITCH
+#ifdef __GNUC__
+      sc->semantic.sem_case = d->semantic_lab;
+#else
+      sc->semantic.sem_case = d->insn_type;
+#endif
+#else
+      sc->semantic.sem_fn = d->semantic_fast;
+#endif
+    }
+  else
+    {
+      sc->semantic.sem_fn = d->semantic_fast;
+      sc->argbuf.opcode = d->opcode;
+    }
+  sc->next = pc + 4;
+}
+
+#endif /* WITH_SCACHE */
+
+static PCADDR
+do_insn16 (cpu, pc, insn)
+     SIM_CPU *cpu;
+     PCADDR pc;
+     insn_t insn;
+{
+  DECODE *d;
+  ARGBUF argbuf;
+
+  d = decode (insn);
+  (*d->extract) (cpu, pc, insn, &argbuf);
+  argbuf.opcode = d->opcode;
+
+  TRACE_INSN_INIT (cpu);
+  TRACE_INSN (cpu, d->opcode, &argbuf, pc);
+
+  pc = (*d->semantic) (cpu, &argbuf);
+
+  TRACE_INSN_FINI (cpu);
+
+  PROFILE_COUNT_INSN (cpu, pc, d->insn_type);
+
+  return pc;
+}
+
+static PCADDR
+do_insn32 (cpu, pc, insn)
+     SIM_CPU *cpu;
+     PCADDR pc;
+     insn_t insn;
+{
+  DECODE *d;
+  ARGBUF argbuf;
+
+  d = decode (insn >> 16);
+  (*d->extract) (cpu, pc, insn, &argbuf);
+  argbuf.opcode = d->opcode;
+
+  TRACE_INSN_INIT (cpu);
+  TRACE_INSN (cpu, d->opcode, &argbuf, pc);
+
+  pc = (*d->semantic) (cpu, &argbuf);
+
+  TRACE_INSN_FINI (cpu);
+
+  PROFILE_COUNT_INSN (cpu, pc, d->insn_type);
+
+  return pc;
+}
+
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac
diff --git a/sim/m32r/mem-ops.h b/sim/m32r/mem-ops.h
new file mode 100644
index 0000000..cd8cc4b
--- /dev/null
+++ b/sim/m32r/mem-ops.h
@@ -0,0 +1,503 @@
+/* Memory ops header for CGEN-based simlators.
+
+This file is machine generated.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CGEN_MEM_OPS_H
+#define CGEN_MEM_OPS_H
+
+#ifdef MEMOPS_DEFINE_INLINE
+#define MEMOPS_INLINE
+#else
+#define MEMOPS_INLINE extern inline
+#endif
+
+/* Only used in this file.  */
+typedef unsigned char *ptr;
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE QI
+GETTQI (ptr p)
+{
+  if (TARGET_BIG_ENDIAN)
+    return p[0];
+  else
+    return p[0];
+}
+#else
+extern QI GETTQI (ptr);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE HI
+GETTHI (ptr p)
+{
+  if (TARGET_BIG_ENDIAN)
+    return ((p[0] << 8) | p[1]);
+  else
+    return ((p[1] << 8) | p[0]);
+}
+#else
+extern HI GETTHI (ptr);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE SI
+GETTSI (ptr p)
+{
+  if (TARGET_BIG_ENDIAN)
+    return ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]);
+  else
+    return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
+}
+#else
+extern SI GETTSI (ptr);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE DI
+GETTDI (ptr p)
+{
+  if (TARGET_BIG_ENDIAN)
+    return MAKEDI ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3], (p[4] << 24) | (p[5] << 16) | (p[6] << 8) | p[7]);
+  else
+    return MAKEDI ((p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4], (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
+}
+#else
+extern DI GETTDI (ptr);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE UQI
+GETTUQI (ptr p)
+{
+  if (TARGET_BIG_ENDIAN)
+    return p[0];
+  else
+    return p[0];
+}
+#else
+extern UQI GETTUQI (ptr);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE UHI
+GETTUHI (ptr p)
+{
+  if (TARGET_BIG_ENDIAN)
+    return ((p[0] << 8) | p[1]);
+  else
+    return ((p[1] << 8) | p[0]);
+}
+#else
+extern UHI GETTUHI (ptr);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE USI
+GETTUSI (ptr p)
+{
+  if (TARGET_BIG_ENDIAN)
+    return ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]);
+  else
+    return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
+}
+#else
+extern USI GETTUSI (ptr);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE UDI
+GETTUDI (ptr p)
+{
+  if (TARGET_BIG_ENDIAN)
+    return MAKEDI ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3], (p[4] << 24) | (p[5] << 16) | (p[6] << 8) | p[7]);
+  else
+    return MAKEDI ((p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4], (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
+}
+#else
+extern UDI GETTUDI (ptr);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETTQI (ptr p, QI val)
+{
+  if (TARGET_BIG_ENDIAN)
+    do { p[0] = val; } while (0);
+else
+    do { p[0] = val; } while (0);
+}
+#else
+extern void SETTQI (ptr, QI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETTHI (ptr p, HI val)
+{
+  if (TARGET_BIG_ENDIAN)
+    do { p[0] = val >> 8; p[1] = val; } while (0);
+else
+    do { p[1] = val >> 8; p[0] = val; } while (0);
+}
+#else
+extern void SETTHI (ptr, HI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETTSI (ptr p, SI val)
+{
+  if (TARGET_BIG_ENDIAN)
+    do { p[0] = val >> 24; p[1] = val >> 16; p[2] = val >> 8; p[3] = val; } while (0);
+else
+    do { p[3] = val >> 24; p[2] = val >> 16; p[1] = val >> 8; p[0] = val; } while (0);
+}
+#else
+extern void SETTSI (ptr, SI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETTDI (ptr p, DI val)
+{
+  if (TARGET_BIG_ENDIAN)
+    do { SI t = GETHIDI (val); p[0] = t >> 24; p[1] = t >> 16; p[2] = t >> 8; p[3] = t; t = GETLODI (val); p[4] = t >> 24; p[5] = t >> 16; p[6] = t >> 8; p[7] = t; } while (0);
+else
+    do { SI t = GETHIDI (val); p[7] = t >> 24; p[6] = t >> 16; p[5] = t >> 8; p[4] = t; t = GETLODI (val); p[3] = t >> 24; p[2] = t >> 16; p[1] = t >> 8; p[0] = t; } while (0);
+}
+#else
+extern void SETTDI (ptr, DI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETTUQI (ptr p, UQI val)
+{
+  if (TARGET_BIG_ENDIAN)
+    do { p[0] = val; } while (0);
+else
+    do { p[0] = val; } while (0);
+}
+#else
+extern void SETTUQI (ptr, UQI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETTUHI (ptr p, UHI val)
+{
+  if (TARGET_BIG_ENDIAN)
+    do { p[0] = val >> 8; p[1] = val; } while (0);
+else
+    do { p[1] = val >> 8; p[0] = val; } while (0);
+}
+#else
+extern void SETTUHI (ptr, UHI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETTUSI (ptr p, USI val)
+{
+  if (TARGET_BIG_ENDIAN)
+    do { p[0] = val >> 24; p[1] = val >> 16; p[2] = val >> 8; p[3] = val; } while (0);
+else
+    do { p[3] = val >> 24; p[2] = val >> 16; p[1] = val >> 8; p[0] = val; } while (0);
+}
+#else
+extern void SETTUSI (ptr, USI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETTUDI (ptr p, UDI val)
+{
+  if (TARGET_BIG_ENDIAN)
+    do { SI t = GETHIDI (val); p[0] = t >> 24; p[1] = t >> 16; p[2] = t >> 8; p[3] = t; t = GETLODI (val); p[4] = t >> 24; p[5] = t >> 16; p[6] = t >> 8; p[7] = t; } while (0);
+else
+    do { SI t = GETHIDI (val); p[7] = t >> 24; p[6] = t >> 16; p[5] = t >> 8; p[4] = t; t = GETLODI (val); p[3] = t >> 24; p[2] = t >> 16; p[1] = t >> 8; p[0] = t; } while (0);
+}
+#else
+extern void SETTUDI (ptr, UDI);
+#endif
+
+
+/* FIXME: Need to merge with sim-core.  */
+/* FIXME: Don't perform >= 4, text section checks if OEA.  */
+#ifndef MEM_CHECK_READ
+#define MEM_CHECK_READ(addr, type) \
+     ((addr) >= 4 /*&& (addr) < STATE_MEM_SIZE (current_state)*/)
+#endif
+#ifndef MEM_CHECK_WRITE
+#define MEM_CHECK_WRITE(addr, type) \
+     ((addr) >= 4 /*&& (addr) < STATE_MEM_SIZE (current_state)*/ \
+      && ((addr) >= STATE_TEXT_END (current_state) \
+	  || (addr) < STATE_TEXT_START (current_state)))
+#endif
+#ifndef MEM_CHECK_ALIGNMENT
+#define MEM_CHECK_ALIGNMENT(addr, type) \
+     (((addr) & (sizeof (type) - 1)) == 0)
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE QI
+GETMEMQI (SIM_CPU *cpu, ADDR a)
+{
+  if (! MEM_CHECK_READ (a, QI))
+    { engine_signal (cpu, SIM_SIGACCESS); }
+  if (! MEM_CHECK_ALIGNMENT (a, QI))
+    { engine_signal (cpu, SIM_SIGALIGN); }
+  PROFILE_COUNT_READ (cpu, a, MODE_QI);
+  return sim_core_read_1 (CPU_STATE (cpu), sim_core_read_map, a);
+}
+#else
+extern QI GETMEMQI (SIM_CPU *, ADDR);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE HI
+GETMEMHI (SIM_CPU *cpu, ADDR a)
+{
+  if (! MEM_CHECK_READ (a, HI))
+    { engine_signal (cpu, SIM_SIGACCESS); }
+  if (! MEM_CHECK_ALIGNMENT (a, HI))
+    { engine_signal (cpu, SIM_SIGALIGN); }
+  PROFILE_COUNT_READ (cpu, a, MODE_HI);
+  return sim_core_read_2 (CPU_STATE (cpu), sim_core_read_map, a);
+}
+#else
+extern HI GETMEMHI (SIM_CPU *, ADDR);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE SI
+GETMEMSI (SIM_CPU *cpu, ADDR a)
+{
+  if (! MEM_CHECK_READ (a, SI))
+    { engine_signal (cpu, SIM_SIGACCESS); }
+  if (! MEM_CHECK_ALIGNMENT (a, SI))
+    { engine_signal (cpu, SIM_SIGALIGN); }
+  PROFILE_COUNT_READ (cpu, a, MODE_SI);
+  return sim_core_read_4 (CPU_STATE (cpu), sim_core_read_map, a);
+}
+#else
+extern SI GETMEMSI (SIM_CPU *, ADDR);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE DI
+GETMEMDI (SIM_CPU *cpu, ADDR a)
+{
+  if (! MEM_CHECK_READ (a, DI))
+    { engine_signal (cpu, SIM_SIGACCESS); }
+  if (! MEM_CHECK_ALIGNMENT (a, DI))
+    { engine_signal (cpu, SIM_SIGALIGN); }
+  PROFILE_COUNT_READ (cpu, a, MODE_DI);
+  return sim_core_read_8 (CPU_STATE (cpu), sim_core_read_map, a);
+}
+#else
+extern DI GETMEMDI (SIM_CPU *, ADDR);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE UQI
+GETMEMUQI (SIM_CPU *cpu, ADDR a)
+{
+  if (! MEM_CHECK_READ (a, UQI))
+    { engine_signal (cpu, SIM_SIGACCESS); }
+  if (! MEM_CHECK_ALIGNMENT (a, UQI))
+    { engine_signal (cpu, SIM_SIGALIGN); }
+  PROFILE_COUNT_READ (cpu, a, MODE_UQI);
+  return sim_core_read_1 (CPU_STATE (cpu), sim_core_read_map, a);
+}
+#else
+extern UQI GETMEMUQI (SIM_CPU *, ADDR);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE UHI
+GETMEMUHI (SIM_CPU *cpu, ADDR a)
+{
+  if (! MEM_CHECK_READ (a, UHI))
+    { engine_signal (cpu, SIM_SIGACCESS); }
+  if (! MEM_CHECK_ALIGNMENT (a, UHI))
+    { engine_signal (cpu, SIM_SIGALIGN); }
+  PROFILE_COUNT_READ (cpu, a, MODE_UHI);
+  return sim_core_read_2 (CPU_STATE (cpu), sim_core_read_map, a);
+}
+#else
+extern UHI GETMEMUHI (SIM_CPU *, ADDR);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE USI
+GETMEMUSI (SIM_CPU *cpu, ADDR a)
+{
+  if (! MEM_CHECK_READ (a, USI))
+    { engine_signal (cpu, SIM_SIGACCESS); }
+  if (! MEM_CHECK_ALIGNMENT (a, USI))
+    { engine_signal (cpu, SIM_SIGALIGN); }
+  PROFILE_COUNT_READ (cpu, a, MODE_USI);
+  return sim_core_read_4 (CPU_STATE (cpu), sim_core_read_map, a);
+}
+#else
+extern USI GETMEMUSI (SIM_CPU *, ADDR);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE UDI
+GETMEMUDI (SIM_CPU *cpu, ADDR a)
+{
+  if (! MEM_CHECK_READ (a, UDI))
+    { engine_signal (cpu, SIM_SIGACCESS); }
+  if (! MEM_CHECK_ALIGNMENT (a, UDI))
+    { engine_signal (cpu, SIM_SIGALIGN); }
+  PROFILE_COUNT_READ (cpu, a, MODE_UDI);
+  return sim_core_read_8 (CPU_STATE (cpu), sim_core_read_map, a);
+}
+#else
+extern UDI GETMEMUDI (SIM_CPU *, ADDR);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETMEMQI (SIM_CPU *cpu, ADDR a, QI val)
+{
+  if (! MEM_CHECK_WRITE (a, QI))
+    { engine_signal (cpu, SIM_SIGACCESS); return; }
+  if (! MEM_CHECK_ALIGNMENT (a, QI))
+    { engine_signal (cpu, SIM_SIGALIGN); return; }
+  PROFILE_COUNT_WRITE (cpu, a, MODE_QI);
+  sim_core_write_1 (CPU_STATE (cpu), sim_core_read_map, a, val);
+}
+#else
+extern void SETMEMQI (SIM_CPU *, ADDR, QI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETMEMHI (SIM_CPU *cpu, ADDR a, HI val)
+{
+  if (! MEM_CHECK_WRITE (a, HI))
+    { engine_signal (cpu, SIM_SIGACCESS); return; }
+  if (! MEM_CHECK_ALIGNMENT (a, HI))
+    { engine_signal (cpu, SIM_SIGALIGN); return; }
+  PROFILE_COUNT_WRITE (cpu, a, MODE_HI);
+  sim_core_write_2 (CPU_STATE (cpu), sim_core_read_map, a, val);
+}
+#else
+extern void SETMEMHI (SIM_CPU *, ADDR, HI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETMEMSI (SIM_CPU *cpu, ADDR a, SI val)
+{
+  if (! MEM_CHECK_WRITE (a, SI))
+    { engine_signal (cpu, SIM_SIGACCESS); return; }
+  if (! MEM_CHECK_ALIGNMENT (a, SI))
+    { engine_signal (cpu, SIM_SIGALIGN); return; }
+  PROFILE_COUNT_WRITE (cpu, a, MODE_SI);
+  sim_core_write_4 (CPU_STATE (cpu), sim_core_read_map, a, val);
+}
+#else
+extern void SETMEMSI (SIM_CPU *, ADDR, SI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETMEMDI (SIM_CPU *cpu, ADDR a, DI val)
+{
+  if (! MEM_CHECK_WRITE (a, DI))
+    { engine_signal (cpu, SIM_SIGACCESS); return; }
+  if (! MEM_CHECK_ALIGNMENT (a, DI))
+    { engine_signal (cpu, SIM_SIGALIGN); return; }
+  PROFILE_COUNT_WRITE (cpu, a, MODE_DI);
+  sim_core_write_8 (CPU_STATE (cpu), sim_core_read_map, a, val);
+}
+#else
+extern void SETMEMDI (SIM_CPU *, ADDR, DI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETMEMUQI (SIM_CPU *cpu, ADDR a, UQI val)
+{
+  if (! MEM_CHECK_WRITE (a, UQI))
+    { engine_signal (cpu, SIM_SIGACCESS); return; }
+  if (! MEM_CHECK_ALIGNMENT (a, UQI))
+    { engine_signal (cpu, SIM_SIGALIGN); return; }
+  PROFILE_COUNT_WRITE (cpu, a, MODE_UQI);
+  sim_core_write_1 (CPU_STATE (cpu), sim_core_read_map, a, val);
+}
+#else
+extern void SETMEMUQI (SIM_CPU *, ADDR, UQI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETMEMUHI (SIM_CPU *cpu, ADDR a, UHI val)
+{
+  if (! MEM_CHECK_WRITE (a, UHI))
+    { engine_signal (cpu, SIM_SIGACCESS); return; }
+  if (! MEM_CHECK_ALIGNMENT (a, UHI))
+    { engine_signal (cpu, SIM_SIGALIGN); return; }
+  PROFILE_COUNT_WRITE (cpu, a, MODE_UHI);
+  sim_core_write_2 (CPU_STATE (cpu), sim_core_read_map, a, val);
+}
+#else
+extern void SETMEMUHI (SIM_CPU *, ADDR, UHI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETMEMUSI (SIM_CPU *cpu, ADDR a, USI val)
+{
+  if (! MEM_CHECK_WRITE (a, USI))
+    { engine_signal (cpu, SIM_SIGACCESS); return; }
+  if (! MEM_CHECK_ALIGNMENT (a, USI))
+    { engine_signal (cpu, SIM_SIGALIGN); return; }
+  PROFILE_COUNT_WRITE (cpu, a, MODE_USI);
+  sim_core_write_4 (CPU_STATE (cpu), sim_core_read_map, a, val);
+}
+#else
+extern void SETMEMUSI (SIM_CPU *, ADDR, USI);
+#endif
+
+#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
+MEMOPS_INLINE void
+SETMEMUDI (SIM_CPU *cpu, ADDR a, UDI val)
+{
+  if (! MEM_CHECK_WRITE (a, UDI))
+    { engine_signal (cpu, SIM_SIGACCESS); return; }
+  if (! MEM_CHECK_ALIGNMENT (a, UDI))
+    { engine_signal (cpu, SIM_SIGALIGN); return; }
+  PROFILE_COUNT_WRITE (cpu, a, MODE_UDI);
+  sim_core_write_8 (CPU_STATE (cpu), sim_core_read_map, a, val);
+}
+#else
+extern void SETMEMUDI (SIM_CPU *, ADDR, UDI);
+#endif
+
+#endif /* MEM_OPS_H */
diff --git a/sim/m32r/sem-ops.h b/sim/m32r/sem-ops.h
new file mode 100644
index 0000000..6ae08a5
--- /dev/null
+++ b/sim/m32r/sem-ops.h
@@ -0,0 +1,978 @@
+/* Semantics ops support for CGEN-based simulators.
+
+This file is machine generated.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CGEN_SEM_OPS_H
+#define CGEN_SEM_OPS_H
+
+/* Semantic operations.  */
+
+#define ADDBI(x, y) ((x) + (y))
+#define SUBBI(x, y) ((x) - (y))
+#define MULBI(x, y) ((x) * (y))
+#define DIVBI(x, y) ((BI) (x) / (BI) (y))
+#define UDIVBI(x, y) ((BI) (x) / (BI) (y))
+#define MODBI(x, y) ((BI) (x) % (BI) (y))
+#define UMODBI(x, y) ((BI) (x) % (BI) (y))
+#define SRABI(x, y) ((BI) (x) >> (y))
+#define SRLBI(x, y) ((UBI) (x) >> (y))
+#define SHLBI(x, y) ((UBI) (x) << (y))
+extern BI RORBI PARAMS ((BI, int));
+extern BI ROLBI PARAMS ((BI, int));
+#define ANDBI(x, y) ((x) & (y))
+#define ORBI(x, y) ((x) | (y))
+#define XORBI(x, y) ((x) ^ (y))
+#define ANDIFBI(x, y) ((BI) (x) && (BI) (y))
+#define ORIFBI(x, y) ((BI) (x) || (BI) (y))
+#define NEGBI(x) (- (x))
+#define NOTBI(x) (! (BI) (x))
+#define INVBI(x) (~ (x))
+#define EQBI(x, y) ((BI) (x) == (BI) (y))
+#define NEBI(x, y) ((BI) (x) != (BI) (y))
+#define LTBI(x, y) ((BI) (x) < (BI) (y))
+#define LEBI(x, y) ((BI) (x) <= (BI) (y))
+#define GTBI(x, y) ((BI) (x) > (BI) (y))
+#define GEBI(x, y) ((BI) (x) >= (BI) (y))
+#define LTUBI(x, y) ((UBI) (x) < (UBI) (y))
+#define LEUBI(x, y) ((UBI) (x) <= (UBI) (y))
+#define GTUBI(x, y) ((UBI) (x) > (UBI) (y))
+#define GEUBI(x, y) ((UBI) (x) >= (UBI) (y))
+
+#define ADDQI(x, y) ((x) + (y))
+#define SUBQI(x, y) ((x) - (y))
+#define MULQI(x, y) ((x) * (y))
+#define DIVQI(x, y) ((QI) (x) / (QI) (y))
+#define UDIVQI(x, y) ((QI) (x) / (QI) (y))
+#define MODQI(x, y) ((QI) (x) % (QI) (y))
+#define UMODQI(x, y) ((QI) (x) % (QI) (y))
+#define SRAQI(x, y) ((QI) (x) >> (y))
+#define SRLQI(x, y) ((UQI) (x) >> (y))
+#define SHLQI(x, y) ((UQI) (x) << (y))
+extern QI RORQI PARAMS ((QI, int));
+extern QI ROLQI PARAMS ((QI, int));
+#define ANDQI(x, y) ((x) & (y))
+#define ORQI(x, y) ((x) | (y))
+#define XORQI(x, y) ((x) ^ (y))
+#define ANDIFQI(x, y) ((QI) (x) && (QI) (y))
+#define ORIFQI(x, y) ((QI) (x) || (QI) (y))
+#define NEGQI(x) (- (x))
+#define NOTQI(x) (! (QI) (x))
+#define INVQI(x) (~ (x))
+#define EQQI(x, y) ((QI) (x) == (QI) (y))
+#define NEQI(x, y) ((QI) (x) != (QI) (y))
+#define LTQI(x, y) ((QI) (x) < (QI) (y))
+#define LEQI(x, y) ((QI) (x) <= (QI) (y))
+#define GTQI(x, y) ((QI) (x) > (QI) (y))
+#define GEQI(x, y) ((QI) (x) >= (QI) (y))
+#define LTUQI(x, y) ((UQI) (x) < (UQI) (y))
+#define LEUQI(x, y) ((UQI) (x) <= (UQI) (y))
+#define GTUQI(x, y) ((UQI) (x) > (UQI) (y))
+#define GEUQI(x, y) ((UQI) (x) >= (UQI) (y))
+
+#define ADDHI(x, y) ((x) + (y))
+#define SUBHI(x, y) ((x) - (y))
+#define MULHI(x, y) ((x) * (y))
+#define DIVHI(x, y) ((HI) (x) / (HI) (y))
+#define UDIVHI(x, y) ((HI) (x) / (HI) (y))
+#define MODHI(x, y) ((HI) (x) % (HI) (y))
+#define UMODHI(x, y) ((HI) (x) % (HI) (y))
+#define SRAHI(x, y) ((HI) (x) >> (y))
+#define SRLHI(x, y) ((UHI) (x) >> (y))
+#define SHLHI(x, y) ((UHI) (x) << (y))
+extern HI RORHI PARAMS ((HI, int));
+extern HI ROLHI PARAMS ((HI, int));
+#define ANDHI(x, y) ((x) & (y))
+#define ORHI(x, y) ((x) | (y))
+#define XORHI(x, y) ((x) ^ (y))
+#define ANDIFHI(x, y) ((HI) (x) && (HI) (y))
+#define ORIFHI(x, y) ((HI) (x) || (HI) (y))
+#define NEGHI(x) (- (x))
+#define NOTHI(x) (! (HI) (x))
+#define INVHI(x) (~ (x))
+#define EQHI(x, y) ((HI) (x) == (HI) (y))
+#define NEHI(x, y) ((HI) (x) != (HI) (y))
+#define LTHI(x, y) ((HI) (x) < (HI) (y))
+#define LEHI(x, y) ((HI) (x) <= (HI) (y))
+#define GTHI(x, y) ((HI) (x) > (HI) (y))
+#define GEHI(x, y) ((HI) (x) >= (HI) (y))
+#define LTUHI(x, y) ((UHI) (x) < (UHI) (y))
+#define LEUHI(x, y) ((UHI) (x) <= (UHI) (y))
+#define GTUHI(x, y) ((UHI) (x) > (UHI) (y))
+#define GEUHI(x, y) ((UHI) (x) >= (UHI) (y))
+
+#define ADDSI(x, y) ((x) + (y))
+#define SUBSI(x, y) ((x) - (y))
+#define MULSI(x, y) ((x) * (y))
+#define DIVSI(x, y) ((SI) (x) / (SI) (y))
+#define UDIVSI(x, y) ((SI) (x) / (SI) (y))
+#define MODSI(x, y) ((SI) (x) % (SI) (y))
+#define UMODSI(x, y) ((SI) (x) % (SI) (y))
+#define SRASI(x, y) ((SI) (x) >> (y))
+#define SRLSI(x, y) ((USI) (x) >> (y))
+#define SHLSI(x, y) ((USI) (x) << (y))
+extern SI RORSI PARAMS ((SI, int));
+extern SI ROLSI PARAMS ((SI, int));
+#define ANDSI(x, y) ((x) & (y))
+#define ORSI(x, y) ((x) | (y))
+#define XORSI(x, y) ((x) ^ (y))
+#define ANDIFSI(x, y) ((SI) (x) && (SI) (y))
+#define ORIFSI(x, y) ((SI) (x) || (SI) (y))
+#define NEGSI(x) (- (x))
+#define NOTSI(x) (! (SI) (x))
+#define INVSI(x) (~ (x))
+#define EQSI(x, y) ((SI) (x) == (SI) (y))
+#define NESI(x, y) ((SI) (x) != (SI) (y))
+#define LTSI(x, y) ((SI) (x) < (SI) (y))
+#define LESI(x, y) ((SI) (x) <= (SI) (y))
+#define GTSI(x, y) ((SI) (x) > (SI) (y))
+#define GESI(x, y) ((SI) (x) >= (SI) (y))
+#define LTUSI(x, y) ((USI) (x) < (USI) (y))
+#define LEUSI(x, y) ((USI) (x) <= (USI) (y))
+#define GTUSI(x, y) ((USI) (x) > (USI) (y))
+#define GEUSI(x, y) ((USI) (x) >= (USI) (y))
+
+#ifdef DI_FN_SUPPORT
+extern DI ADDDI PARAMS ((DI, DI));
+extern DI SUBDI PARAMS ((DI, DI));
+extern DI MULDI PARAMS ((DI, DI));
+extern DI DIVDI PARAMS ((DI, DI));
+extern DI UDIVDI PARAMS ((DI, DI));
+extern DI MODDI PARAMS ((DI, DI));
+extern DI UMODDI PARAMS ((DI, DI));
+extern DI SRADI PARAMS ((DI, int));
+extern UDI SRLDI PARAMS ((UDI, int));
+extern UDI SHLDI PARAMS ((UDI, int));
+extern DI RORDI PARAMS ((DI, int));
+extern DI ROLDI PARAMS ((DI, int));
+extern DI ANDDI PARAMS ((DI, DI));
+extern DI ORDI PARAMS ((DI, DI));
+extern DI XORDI PARAMS ((DI, DI));
+extern int ANDIFDI PARAMS ((DI, DI));
+extern int ORIFDI PARAMS ((DI, DI));
+extern DI NEGDI PARAMS ((DI));
+extern int NOTDI PARAMS ((DI));
+extern DI INVDI PARAMS ((DI));
+extern int EQDI PARAMS ((DI, DI));
+extern int NEDI PARAMS ((DI, DI));
+extern int LTDI PARAMS ((DI, DI));
+extern int LEDI PARAMS ((DI, DI));
+extern int GTDI PARAMS ((DI, DI));
+extern int GEDI PARAMS ((DI, DI));
+extern int LTUDI PARAMS ((UDI, UDI));
+extern int LEUDI PARAMS ((UDI, UDI));
+extern int GTUDI PARAMS ((UDI, UDI));
+extern int GEUDI PARAMS ((UDI, UDI));
+#else /* ! DI_FN_SUPPORT */
+#define ADDDI(x, y) ((x) + (y))
+#define SUBDI(x, y) ((x) - (y))
+#define MULDI(x, y) ((x) * (y))
+#define DIVDI(x, y) ((DI) (x) / (DI) (y))
+#define UDIVDI(x, y) ((DI) (x) / (DI) (y))
+#define MODDI(x, y) ((DI) (x) % (DI) (y))
+#define UMODDI(x, y) ((DI) (x) % (DI) (y))
+#define SRADI(x, y) ((DI) (x) >> (y))
+#define SRLDI(x, y) ((UDI) (x) >> (y))
+#define SHLDI(x, y) ((UDI) (x) << (y))
+extern DI RORDI PARAMS ((DI, int));
+extern DI ROLDI PARAMS ((DI, int));
+#define ANDDI(x, y) ((x) & (y))
+#define ORDI(x, y) ((x) | (y))
+#define XORDI(x, y) ((x) ^ (y))
+#define ANDIFDI(x, y) ((DI) (x) && (DI) (y))
+#define ORIFDI(x, y) ((DI) (x) || (DI) (y))
+#define NEGDI(x) (- (x))
+#define NOTDI(x) (! (DI) (x))
+#define INVDI(x) (~ (x))
+#define EQDI(x, y) ((DI) (x) == (DI) (y))
+#define NEDI(x, y) ((DI) (x) != (DI) (y))
+#define LTDI(x, y) ((DI) (x) < (DI) (y))
+#define LEDI(x, y) ((DI) (x) <= (DI) (y))
+#define GTDI(x, y) ((DI) (x) > (DI) (y))
+#define GEDI(x, y) ((DI) (x) >= (DI) (y))
+#define LTUDI(x, y) ((UDI) (x) < (UDI) (y))
+#define LEUDI(x, y) ((UDI) (x) <= (UDI) (y))
+#define GTUDI(x, y) ((UDI) (x) > (UDI) (y))
+#define GEUDI(x, y) ((UDI) (x) >= (UDI) (y))
+#endif /* DI_FN_SUPPORT */
+
+#ifdef SF_FN_SUPPORT
+extern SF ADDSF PARAMS ((SF, SF));
+extern SF SUBSF PARAMS ((SF, SF));
+extern SF NEGSF PARAMS ((SF));
+extern SF MULSF PARAMS ((SF, SF));
+extern SF DIVSF PARAMS ((SF, SF));
+extern int EQSF PARAMS ((SF, SF));
+extern int NESF PARAMS ((SF, SF));
+extern int LTSF PARAMS ((SF, SF));
+extern int LESF PARAMS ((SF, SF));
+extern int GTSF PARAMS ((SF, SF));
+extern int GESF PARAMS ((SF, SF));
+extern SF ABSSF PARAMS ((SF));
+extern SF SQRTSF PARAMS ((SF));
+extern SF COSSF PARAMS ((SF));
+extern SF SINSF PARAMS ((SF));
+#else /* ! SF_FN_SUPPORT */
+#define ADDSF(x, y) ((x) + (y))
+#define SUBSF(x, y) ((x) - (y))
+#define NEGSF(x) (- (x))
+#define MULSF(x, y) ((x) * (y))
+#define DIVSF(x, y) ((x) / (y))
+#define EQSF(x, y) ((SF) (x) == (SF) (y))
+#define NESF(x, y) ((SF) (x) != (SF) (y))
+#define LTSF(x, y) ((SF) (x) < (SF) (y))
+#define LESF(x, y) ((SF) (x) <= (SF) (y))
+#define GTSF(x, y) ((SF) (x) > (SF) (y))
+#define GESF(x, y) ((SF) (x) >= (SF) (y))
+extern SF ABSSF PARAMS ((SF));
+extern SF SQRTSF PARAMS ((SF));
+extern SF COSSF PARAMS ((SF));
+extern SF SINSF PARAMS ((SF));
+#endif /* SF_FN_SUPPORT */
+
+#ifdef DF_FN_SUPPORT
+extern DF ADDDF PARAMS ((DF, DF));
+extern DF SUBDF PARAMS ((DF, DF));
+extern DF NEGDF PARAMS ((DF));
+extern DF MULDF PARAMS ((DF, DF));
+extern DF DIVDF PARAMS ((DF, DF));
+extern int EQDF PARAMS ((DF, DF));
+extern int NEDF PARAMS ((DF, DF));
+extern int LTDF PARAMS ((DF, DF));
+extern int LEDF PARAMS ((DF, DF));
+extern int GTDF PARAMS ((DF, DF));
+extern int GEDF PARAMS ((DF, DF));
+extern DF ABSDF PARAMS ((DF));
+extern DF SQRTDF PARAMS ((DF));
+extern DF COSDF PARAMS ((DF));
+extern DF SINDF PARAMS ((DF));
+#else /* ! DF_FN_SUPPORT */
+#define ADDDF(x, y) ((x) + (y))
+#define SUBDF(x, y) ((x) - (y))
+#define NEGDF(x) (- (x))
+#define MULDF(x, y) ((x) * (y))
+#define DIVDF(x, y) ((x) / (y))
+#define EQDF(x, y) ((DF) (x) == (DF) (y))
+#define NEDF(x, y) ((DF) (x) != (DF) (y))
+#define LTDF(x, y) ((DF) (x) < (DF) (y))
+#define LEDF(x, y) ((DF) (x) <= (DF) (y))
+#define GTDF(x, y) ((DF) (x) > (DF) (y))
+#define GEDF(x, y) ((DF) (x) >= (DF) (y))
+extern DF ABSDF PARAMS ((DF));
+extern DF SQRTDF PARAMS ((DF));
+extern DF COSDF PARAMS ((DF));
+extern DF SINDF PARAMS ((DF));
+#endif /* DF_FN_SUPPORT */
+
+#ifdef XF_FN_SUPPORT
+extern XF ADDXF PARAMS ((XF, XF));
+extern XF SUBXF PARAMS ((XF, XF));
+extern XF NEGXF PARAMS ((XF));
+extern XF MULXF PARAMS ((XF, XF));
+extern XF DIVXF PARAMS ((XF, XF));
+extern int EQXF PARAMS ((XF, XF));
+extern int NEXF PARAMS ((XF, XF));
+extern int LTXF PARAMS ((XF, XF));
+extern int LEXF PARAMS ((XF, XF));
+extern int GTXF PARAMS ((XF, XF));
+extern int GEXF PARAMS ((XF, XF));
+extern XF ABSXF PARAMS ((XF));
+extern XF SQRTXF PARAMS ((XF));
+extern XF COSXF PARAMS ((XF));
+extern XF SINXF PARAMS ((XF));
+#else /* ! XF_FN_SUPPORT */
+#define ADDXF(x, y) ((x) + (y))
+#define SUBXF(x, y) ((x) - (y))
+#define NEGXF(x) (- (x))
+#define MULXF(x, y) ((x) * (y))
+#define DIVXF(x, y) ((x) / (y))
+#define EQXF(x, y) ((XF) (x) == (XF) (y))
+#define NEXF(x, y) ((XF) (x) != (XF) (y))
+#define LTXF(x, y) ((XF) (x) < (XF) (y))
+#define LEXF(x, y) ((XF) (x) <= (XF) (y))
+#define GTXF(x, y) ((XF) (x) > (XF) (y))
+#define GEXF(x, y) ((XF) (x) >= (XF) (y))
+extern XF ABSXF PARAMS ((XF));
+extern XF SQRTXF PARAMS ((XF));
+extern XF COSXF PARAMS ((XF));
+extern XF SINXF PARAMS ((XF));
+#endif /* XF_FN_SUPPORT */
+
+#ifdef TF_FN_SUPPORT
+extern TF ADDTF PARAMS ((TF, TF));
+extern TF SUBTF PARAMS ((TF, TF));
+extern TF NEGTF PARAMS ((TF));
+extern TF MULTF PARAMS ((TF, TF));
+extern TF DIVTF PARAMS ((TF, TF));
+extern int EQTF PARAMS ((TF, TF));
+extern int NETF PARAMS ((TF, TF));
+extern int LTTF PARAMS ((TF, TF));
+extern int LETF PARAMS ((TF, TF));
+extern int GTTF PARAMS ((TF, TF));
+extern int GETF PARAMS ((TF, TF));
+extern TF ABSTF PARAMS ((TF));
+extern TF SQRTTF PARAMS ((TF));
+extern TF COSTF PARAMS ((TF));
+extern TF SINTF PARAMS ((TF));
+#else /* ! TF_FN_SUPPORT */
+#define ADDTF(x, y) ((x) + (y))
+#define SUBTF(x, y) ((x) - (y))
+#define NEGTF(x) (- (x))
+#define MULTF(x, y) ((x) * (y))
+#define DIVTF(x, y) ((x) / (y))
+#define EQTF(x, y) ((TF) (x) == (TF) (y))
+#define NETF(x, y) ((TF) (x) != (TF) (y))
+#define LTTF(x, y) ((TF) (x) < (TF) (y))
+#define LETF(x, y) ((TF) (x) <= (TF) (y))
+#define GTTF(x, y) ((TF) (x) > (TF) (y))
+#define GETF(x, y) ((TF) (x) >= (TF) (y))
+extern TF ABSTF PARAMS ((TF));
+extern TF SQRTTF PARAMS ((TF));
+extern TF COSTF PARAMS ((TF));
+extern TF SINTF PARAMS ((TF));
+#endif /* TF_FN_SUPPORT */
+
+
+#define EXTBIQI(x) ((QI) (BI) (x))
+#define EXTBIHI(x) ((HI) (BI) (x))
+#define EXTBISI(x) ((SI) (BI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI EXTBIDI PARAMS ((BI));
+#else
+#define EXTBIDI(x) ((DI) (BI) (x))
+#endif
+#define EXTQIHI(x) ((HI) (QI) (x))
+#define EXTQISI(x) ((SI) (QI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI EXTQIDI PARAMS ((QI));
+#else
+#define EXTQIDI(x) ((DI) (QI) (x))
+#endif
+#define EXTHISI(x) ((SI) (HI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI EXTHIDI PARAMS ((HI));
+#else
+#define EXTHIDI(x) ((DI) (HI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern DI EXTSIDI PARAMS ((SI));
+#else
+#define EXTSIDI(x) ((DI) (SI) (x))
+#endif
+#if defined (SF_FN_SUPPORT) || defined (DF_FN_SUPPORT)
+extern DF EXTSFDF PARAMS ((SF));
+#else
+#define EXTSFDF(x) ((DF) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT) || defined (XF_FN_SUPPORT)
+extern XF EXTSFXF PARAMS ((SF));
+#else
+#define EXTSFXF(x) ((XF) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT) || defined (TF_FN_SUPPORT)
+extern TF EXTSFTF PARAMS ((SF));
+#else
+#define EXTSFTF(x) ((TF) (SF) (x))
+#endif
+#if defined (DF_FN_SUPPORT) || defined (XF_FN_SUPPORT)
+extern XF EXTDFXF PARAMS ((DF));
+#else
+#define EXTDFXF(x) ((XF) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT) || defined (TF_FN_SUPPORT)
+extern TF EXTDFTF PARAMS ((DF));
+#else
+#define EXTDFTF(x) ((TF) (DF) (x))
+#endif
+#if defined (XF_FN_SUPPORT) || defined (TF_FN_SUPPORT)
+extern TF EXTXFTF PARAMS ((XF));
+#else
+#define EXTXFTF(x) ((TF) (XF) (x))
+#endif
+#define ZEXTBIQI(x) ((QI) (UBI) (x))
+#define ZEXTBIHI(x) ((HI) (UBI) (x))
+#define ZEXTBISI(x) ((SI) (UBI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI ZEXTBIDI PARAMS ((BI));
+#else
+#define ZEXTBIDI(x) ((DI) (UBI) (x))
+#endif
+#define ZEXTQIHI(x) ((HI) (UQI) (x))
+#define ZEXTQISI(x) ((SI) (UQI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI ZEXTQIDI PARAMS ((QI));
+#else
+#define ZEXTQIDI(x) ((DI) (UQI) (x))
+#endif
+#define ZEXTHISI(x) ((SI) (UHI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI ZEXTHIDI PARAMS ((HI));
+#else
+#define ZEXTHIDI(x) ((DI) (UHI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern DI ZEXTSIDI PARAMS ((SI));
+#else
+#define ZEXTSIDI(x) ((DI) (USI) (x))
+#endif
+#define TRUNCQIBI(x) ((BI) (QI) (x))
+#define TRUNCHIBI(x) ((BI) (HI) (x))
+#define TRUNCHIQI(x) ((QI) (HI) (x))
+#define TRUNCSIBI(x) ((BI) (SI) (x))
+#define TRUNCSIQI(x) ((QI) (SI) (x))
+#define TRUNCSIHI(x) ((HI) (SI) (x))
+#if defined (DI_FN_SUPPORT)
+extern BI TRUNCDIBI PARAMS ((DI));
+#else
+#define TRUNCDIBI(x) ((BI) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern QI TRUNCDIQI PARAMS ((DI));
+#else
+#define TRUNCDIQI(x) ((QI) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern HI TRUNCDIHI PARAMS ((DI));
+#else
+#define TRUNCDIHI(x) ((HI) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern SI TRUNCDISI PARAMS ((DI));
+#else
+#define TRUNCDISI(x) ((SI) (DI) (x))
+#endif
+#if defined (DF_FN_SUPPORT) || defined (SF_FN_SUPPORT)
+extern SF TRUNCDFSF PARAMS ((DF));
+#else
+#define TRUNCDFSF(x) ((SF) (DF) (x))
+#endif
+#if defined (XF_FN_SUPPORT) || defined (SF_FN_SUPPORT)
+extern SF TRUNCXFSF PARAMS ((XF));
+#else
+#define TRUNCXFSF(x) ((SF) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT) || defined (DF_FN_SUPPORT)
+extern DF TRUNCXFDF PARAMS ((XF));
+#else
+#define TRUNCXFDF(x) ((DF) (XF) (x))
+#endif
+#if defined (TF_FN_SUPPORT) || defined (SF_FN_SUPPORT)
+extern SF TRUNCTFSF PARAMS ((TF));
+#else
+#define TRUNCTFSF(x) ((SF) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT) || defined (DF_FN_SUPPORT)
+extern DF TRUNCTFDF PARAMS ((TF));
+#else
+#define TRUNCTFDF(x) ((DF) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT) || defined (XF_FN_SUPPORT)
+extern XF TRUNCTFXF PARAMS ((TF));
+#else
+#define TRUNCTFXF(x) ((XF) (TF) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SF FLOATBISF PARAMS ((BI));
+#else
+#define FLOATBISF(x) ((SF) (BI) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern DF FLOATBIDF PARAMS ((BI));
+#else
+#define FLOATBIDF(x) ((DF) (BI) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern XF FLOATBIXF PARAMS ((BI));
+#else
+#define FLOATBIXF(x) ((XF) (BI) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern TF FLOATBITF PARAMS ((BI));
+#else
+#define FLOATBITF(x) ((TF) (BI) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SF FLOATQISF PARAMS ((QI));
+#else
+#define FLOATQISF(x) ((SF) (QI) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern DF FLOATQIDF PARAMS ((QI));
+#else
+#define FLOATQIDF(x) ((DF) (QI) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern XF FLOATQIXF PARAMS ((QI));
+#else
+#define FLOATQIXF(x) ((XF) (QI) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern TF FLOATQITF PARAMS ((QI));
+#else
+#define FLOATQITF(x) ((TF) (QI) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SF FLOATHISF PARAMS ((HI));
+#else
+#define FLOATHISF(x) ((SF) (HI) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern DF FLOATHIDF PARAMS ((HI));
+#else
+#define FLOATHIDF(x) ((DF) (HI) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern XF FLOATHIXF PARAMS ((HI));
+#else
+#define FLOATHIXF(x) ((XF) (HI) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern TF FLOATHITF PARAMS ((HI));
+#else
+#define FLOATHITF(x) ((TF) (HI) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SF FLOATSISF PARAMS ((SI));
+#else
+#define FLOATSISF(x) ((SF) (SI) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern DF FLOATSIDF PARAMS ((SI));
+#else
+#define FLOATSIDF(x) ((DF) (SI) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern XF FLOATSIXF PARAMS ((SI));
+#else
+#define FLOATSIXF(x) ((XF) (SI) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern TF FLOATSITF PARAMS ((SI));
+#else
+#define FLOATSITF(x) ((TF) (SI) (x))
+#endif
+#if defined (DI_FN_SUPPORT) || defined (SF_FN_SUPPORT)
+extern SF FLOATDISF PARAMS ((DI));
+#else
+#define FLOATDISF(x) ((SF) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT) || defined (DF_FN_SUPPORT)
+extern DF FLOATDIDF PARAMS ((DI));
+#else
+#define FLOATDIDF(x) ((DF) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT) || defined (XF_FN_SUPPORT)
+extern XF FLOATDIXF PARAMS ((DI));
+#else
+#define FLOATDIXF(x) ((XF) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT) || defined (TF_FN_SUPPORT)
+extern TF FLOATDITF PARAMS ((DI));
+#else
+#define FLOATDITF(x) ((TF) (DI) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SF UFLOATBISF PARAMS ((BI));
+#else
+#define UFLOATBISF(x) ((SF) (UBI) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern DF UFLOATBIDF PARAMS ((BI));
+#else
+#define UFLOATBIDF(x) ((DF) (UBI) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern XF UFLOATBIXF PARAMS ((BI));
+#else
+#define UFLOATBIXF(x) ((XF) (UBI) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern TF UFLOATBITF PARAMS ((BI));
+#else
+#define UFLOATBITF(x) ((TF) (UBI) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SF UFLOATQISF PARAMS ((QI));
+#else
+#define UFLOATQISF(x) ((SF) (UQI) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern DF UFLOATQIDF PARAMS ((QI));
+#else
+#define UFLOATQIDF(x) ((DF) (UQI) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern XF UFLOATQIXF PARAMS ((QI));
+#else
+#define UFLOATQIXF(x) ((XF) (UQI) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern TF UFLOATQITF PARAMS ((QI));
+#else
+#define UFLOATQITF(x) ((TF) (UQI) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SF UFLOATHISF PARAMS ((HI));
+#else
+#define UFLOATHISF(x) ((SF) (UHI) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern DF UFLOATHIDF PARAMS ((HI));
+#else
+#define UFLOATHIDF(x) ((DF) (UHI) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern XF UFLOATHIXF PARAMS ((HI));
+#else
+#define UFLOATHIXF(x) ((XF) (UHI) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern TF UFLOATHITF PARAMS ((HI));
+#else
+#define UFLOATHITF(x) ((TF) (UHI) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SF UFLOATSISF PARAMS ((SI));
+#else
+#define UFLOATSISF(x) ((SF) (USI) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern DF UFLOATSIDF PARAMS ((SI));
+#else
+#define UFLOATSIDF(x) ((DF) (USI) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern XF UFLOATSIXF PARAMS ((SI));
+#else
+#define UFLOATSIXF(x) ((XF) (USI) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern TF UFLOATSITF PARAMS ((SI));
+#else
+#define UFLOATSITF(x) ((TF) (USI) (x))
+#endif
+#if defined (DI_FN_SUPPORT) || defined (SF_FN_SUPPORT)
+extern SF UFLOATDISF PARAMS ((DI));
+#else
+#define UFLOATDISF(x) ((SF) (UDI) (x))
+#endif
+#if defined (DI_FN_SUPPORT) || defined (DF_FN_SUPPORT)
+extern DF UFLOATDIDF PARAMS ((DI));
+#else
+#define UFLOATDIDF(x) ((DF) (UDI) (x))
+#endif
+#if defined (DI_FN_SUPPORT) || defined (XF_FN_SUPPORT)
+extern XF UFLOATDIXF PARAMS ((DI));
+#else
+#define UFLOATDIXF(x) ((XF) (UDI) (x))
+#endif
+#if defined (DI_FN_SUPPORT) || defined (TF_FN_SUPPORT)
+extern TF UFLOATDITF PARAMS ((DI));
+#else
+#define UFLOATDITF(x) ((TF) (UDI) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern BI FIXSFBI PARAMS ((SF));
+#else
+#define FIXSFBI(x) ((BI) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern QI FIXSFQI PARAMS ((SF));
+#else
+#define FIXSFQI(x) ((QI) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern HI FIXSFHI PARAMS ((SF));
+#else
+#define FIXSFHI(x) ((HI) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SI FIXSFSI PARAMS ((SF));
+#else
+#define FIXSFSI(x) ((SI) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT) || defined (DI_FN_SUPPORT)
+extern DI FIXSFDI PARAMS ((SF));
+#else
+#define FIXSFDI(x) ((DI) (SF) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern BI FIXDFBI PARAMS ((DF));
+#else
+#define FIXDFBI(x) ((BI) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern QI FIXDFQI PARAMS ((DF));
+#else
+#define FIXDFQI(x) ((QI) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern HI FIXDFHI PARAMS ((DF));
+#else
+#define FIXDFHI(x) ((HI) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern SI FIXDFSI PARAMS ((DF));
+#else
+#define FIXDFSI(x) ((SI) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT) || defined (DI_FN_SUPPORT)
+extern DI FIXDFDI PARAMS ((DF));
+#else
+#define FIXDFDI(x) ((DI) (DF) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern BI FIXXFBI PARAMS ((XF));
+#else
+#define FIXXFBI(x) ((BI) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern QI FIXXFQI PARAMS ((XF));
+#else
+#define FIXXFQI(x) ((QI) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern HI FIXXFHI PARAMS ((XF));
+#else
+#define FIXXFHI(x) ((HI) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern SI FIXXFSI PARAMS ((XF));
+#else
+#define FIXXFSI(x) ((SI) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT) || defined (DI_FN_SUPPORT)
+extern DI FIXXFDI PARAMS ((XF));
+#else
+#define FIXXFDI(x) ((DI) (XF) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern BI FIXTFBI PARAMS ((TF));
+#else
+#define FIXTFBI(x) ((BI) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern QI FIXTFQI PARAMS ((TF));
+#else
+#define FIXTFQI(x) ((QI) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern HI FIXTFHI PARAMS ((TF));
+#else
+#define FIXTFHI(x) ((HI) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern SI FIXTFSI PARAMS ((TF));
+#else
+#define FIXTFSI(x) ((SI) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT) || defined (DI_FN_SUPPORT)
+extern DI FIXTFDI PARAMS ((TF));
+#else
+#define FIXTFDI(x) ((DI) (TF) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern BI UFIXSFBI PARAMS ((SF));
+#else
+#define UFIXSFBI(x) ((UBI) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern QI UFIXSFQI PARAMS ((SF));
+#else
+#define UFIXSFQI(x) ((UQI) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern HI UFIXSFHI PARAMS ((SF));
+#else
+#define UFIXSFHI(x) ((UHI) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT)
+extern SI UFIXSFSI PARAMS ((SF));
+#else
+#define UFIXSFSI(x) ((USI) (SF) (x))
+#endif
+#if defined (SF_FN_SUPPORT) || defined (DI_FN_SUPPORT)
+extern DI UFIXSFDI PARAMS ((SF));
+#else
+#define UFIXSFDI(x) ((UDI) (SF) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern BI UFIXDFBI PARAMS ((DF));
+#else
+#define UFIXDFBI(x) ((UBI) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern QI UFIXDFQI PARAMS ((DF));
+#else
+#define UFIXDFQI(x) ((UQI) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern HI UFIXDFHI PARAMS ((DF));
+#else
+#define UFIXDFHI(x) ((UHI) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT)
+extern SI UFIXDFSI PARAMS ((DF));
+#else
+#define UFIXDFSI(x) ((USI) (DF) (x))
+#endif
+#if defined (DF_FN_SUPPORT) || defined (DI_FN_SUPPORT)
+extern DI UFIXDFDI PARAMS ((DF));
+#else
+#define UFIXDFDI(x) ((UDI) (DF) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern BI UFIXXFBI PARAMS ((XF));
+#else
+#define UFIXXFBI(x) ((UBI) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern QI UFIXXFQI PARAMS ((XF));
+#else
+#define UFIXXFQI(x) ((UQI) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern HI UFIXXFHI PARAMS ((XF));
+#else
+#define UFIXXFHI(x) ((UHI) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT)
+extern SI UFIXXFSI PARAMS ((XF));
+#else
+#define UFIXXFSI(x) ((USI) (XF) (x))
+#endif
+#if defined (XF_FN_SUPPORT) || defined (DI_FN_SUPPORT)
+extern DI UFIXXFDI PARAMS ((XF));
+#else
+#define UFIXXFDI(x) ((UDI) (XF) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern BI UFIXTFBI PARAMS ((TF));
+#else
+#define UFIXTFBI(x) ((UBI) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern QI UFIXTFQI PARAMS ((TF));
+#else
+#define UFIXTFQI(x) ((UQI) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern HI UFIXTFHI PARAMS ((TF));
+#else
+#define UFIXTFHI(x) ((UHI) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT)
+extern SI UFIXTFSI PARAMS ((TF));
+#else
+#define UFIXTFSI(x) ((USI) (TF) (x))
+#endif
+#if defined (TF_FN_SUPPORT) || defined (DI_FN_SUPPORT)
+extern DI UFIXTFDI PARAMS ((TF));
+#else
+#define UFIXTFDI(x) ((UDI) (TF) (x))
+#endif
+
+/* Semantic support utilities.  */
+
+#ifdef __GNUC__
+
+#ifdef SEMOPS_DEFINE_INLINE
+#define SEMOPS_INLINE
+#else
+#define SEMOPS_INLINE extern inline
+#endif
+
+SEMOPS_INLINE SI
+ADDCSI (SI a, SI b, UBI c)
+{
+  SI res = ADDSI (a, ADDSI (b, c));
+  return res;
+}
+
+SEMOPS_INLINE UBI
+ADDCFSI (SI a, SI b, UBI c)
+{
+  SI tmp = ADDSI (a, ADDSI (b, c));
+  BI res = (USI) tmp < (USI) a || (USI) tmp < (USI) b;
+  return res;
+}
+
+SEMOPS_INLINE UBI
+ADDOFSI (SI a, SI b, UBI c)
+{
+  SI tmp = ADDSI (a, ADDSI (b, c));
+  BI res = (((a < 0) == (b < 0))
+	    && ((a < 0) != (tmp < 0)));
+  return res;
+}
+
+SEMOPS_INLINE SI
+SUBCSI (SI a, SI b, UBI c)
+{
+  SI res = SUBSI (a, ADDSI (b, c));
+  return res;
+}
+
+SEMOPS_INLINE UBI
+SUBCFSI (SI a, SI b, UBI c)
+{
+  BI res = ((USI) a < (USI) b) || ((a == b) && c);
+  return res;
+}
+
+SEMOPS_INLINE UBI
+SUBOFSI (SI a, SI b, UBI c)
+{
+  SI tmp = SUBSI (a, ADDSI (b, c));
+  BI res = (((a < 0) != (b < 0))
+	    && ((a < 0) != (tmp < 0)));
+  return res;
+}
+
+#else
+
+SI ADDCSI (SI, SI, UBI);
+UBI ADDCFSI (SI, SI, UBI);
+UBI ADDOFSI (SI, SI, UBI);
+SI SUBCSI (SI, SI, UBI);
+UBI SUBCFSI (SI, SI, UBI);
+UBI SUBOFSI (SI, SI, UBI);
+
+#endif
+
+/* DI mode support if "long long" doesn't exist.
+   At one point CGEN supported K&R C compilers, and ANSI C compilers without
+   "long long".  One can argue the various merits of keeping this in or
+   throwing it out.  I went to the trouble of adding it so for the time being
+   I'm leaving it in.  */
+
+#ifdef DI_FN_SUPPORT
+
+DI make_struct_di (SI, SI);
+/* FIXME: needed? */
+DI CONVHIDI (HI);
+DI CONVSIDI (SI);
+SI CONVDISI (DI);
+
+#endif /* DI_FN_SUPPORT */
+
+#endif /* CGEN_SEM_OPS_H */
diff --git a/sim/m32r/semantics.c b/sim/m32r/semantics.c
new file mode 100644
index 0000000..453c392
--- /dev/null
+++ b/sim/m32r/semantics.c
@@ -0,0 +1,2233 @@
+/* Simulator instruction semantics for m32r.
+
+This file is machine generated.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "mem-ops.h"
+#include "sem-ops.h"
+#include "decode.h"
+#include "cpu-sim.h"
+
+/* Perform add: add $dr,$sr.  */
+CIA
+SEM_FN_NAME (add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ADDSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform add3: add3 $dr,$sr,$slo16.  */
+CIA
+SEM_FN_NAME (add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ADDSI (* FLD (f_r2), FLD (f_simm16));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform and: and $dr,$sr.  */
+CIA
+SEM_FN_NAME (and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ANDSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform and3: and3 $dr,$sr,$uimm16.  */
+CIA
+SEM_FN_NAME (and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ANDSI (* FLD (f_r2), FLD (f_uimm16));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform or: or $dr,$sr.  */
+CIA
+SEM_FN_NAME (or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ORSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform or3: or3 $dr,$sr,$ulo16.  */
+CIA
+SEM_FN_NAME (or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ORSI (* FLD (f_r2), FLD (f_uimm16));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform xor: xor $dr,$sr.  */
+CIA
+SEM_FN_NAME (xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = XORSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform xor3: xor3 $dr,$sr,$uimm16.  */
+CIA
+SEM_FN_NAME (xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = XORSI (* FLD (f_r2), FLD (f_uimm16));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform addi: addi $dr,$simm8.  */
+CIA
+SEM_FN_NAME (addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_4.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ADDSI (* FLD (f_r1), FLD (f_simm8));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform addv: addv $dr,$sr.  */
+CIA
+SEM_FN_NAME (addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2));
+temp1 = ADDOFSI (* FLD (f_r1), * FLD (f_r2), 0);
+* FLD (f_r1) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "h_cond", 'x', temp1);
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform addv3: addv3 $dr,$sr,$simm16.  */
+CIA
+SEM_FN_NAME (addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_5.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16));
+temp1 = ADDOFSI (* FLD (f_r2), FLD (f_simm16), 0);
+* FLD (f_r1) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "h_cond", 'x', temp1);
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform addx: addx $dr,$sr.  */
+CIA
+SEM_FN_NAME (addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
+temp1 = ADDCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
+* FLD (f_r1) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "h_cond", 'x', temp1);
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bc8: bc $disp8.  */
+CIA
+SEM_FN_NAME (bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_6.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (CPU (h_cond))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bc24: bc $disp24.  */
+CIA
+SEM_FN_NAME (bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_7.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (CPU (h_cond))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform beq: beq $src1,$src2,$disp16.  */
+CIA
+SEM_FN_NAME (beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (EQSI (* FLD (f_r1), * FLD (f_r2)))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform beqz: beqz $src2,$disp16.  */
+CIA
+SEM_FN_NAME (beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (EQSI (* FLD (f_r2), 0))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bgez: bgez $src2,$disp16.  */
+CIA
+SEM_FN_NAME (bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (GESI (* FLD (f_r2), 0))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bgtz: bgtz $src2,$disp16.  */
+CIA
+SEM_FN_NAME (bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (GTSI (* FLD (f_r2), 0))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform blez: blez $src2,$disp16.  */
+CIA
+SEM_FN_NAME (blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (LESI (* FLD (f_r2), 0))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bltz: bltz $src2,$disp16.  */
+CIA
+SEM_FN_NAME (bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (LTSI (* FLD (f_r2), 0))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bnez: bnez $src2,$disp16.  */
+CIA
+SEM_FN_NAME (bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_9.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NESI (* FLD (f_r2), 0))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bl8: bl $disp8.  */
+CIA
+SEM_FN_NAME (bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_6.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+{
+CPU (h_gr[14]) = ADDSI (ANDSI (CPU (pc), -4), 4);
+  TRACE_RESULT (current_cpu, "h_gr[14]", 'x', ADDSI (ANDSI (CPU (pc), -4), 4));
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bl24: bl $disp24.  */
+CIA
+SEM_FN_NAME (bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_7.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+{
+CPU (h_gr[14]) = ADDSI (CPU (pc), 4);
+  TRACE_RESULT (current_cpu, "h_gr[14]", 'x', ADDSI (CPU (pc), 4));
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bnc8: bnc $disp8.  */
+CIA
+SEM_FN_NAME (bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_6.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NOTBI (CPU (h_cond)))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bnc24: bnc $disp24.  */
+CIA
+SEM_FN_NAME (bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_7.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NOTBI (CPU (h_cond)))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bne: bne $src1,$src2,$disp16.  */
+CIA
+SEM_FN_NAME (bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NESI (* FLD (f_r1), * FLD (f_r2)))
+{
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bra8: bra $disp8.  */
+CIA
+SEM_FN_NAME (bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_6.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform bra24: bra $disp24.  */
+CIA
+SEM_FN_NAME (bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_7.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+  new_pc = SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform cmp: cmp $src1,$src2.  */
+CIA
+SEM_FN_NAME (cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_cond) = LTSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "h_cond", 'x', LTSI (* FLD (f_r1), * FLD (f_r2)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform cmpi: cmpi $src2,$simm16.  */
+CIA
+SEM_FN_NAME (cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_11.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_cond) = LTSI (* FLD (f_r2), FLD (f_simm16));
+  TRACE_RESULT (current_cpu, "h_cond", 'x', LTSI (* FLD (f_r2), FLD (f_simm16)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform cmpu: cmpu $src1,$src2.  */
+CIA
+SEM_FN_NAME (cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_cond) = LTUSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "h_cond", 'x', LTUSI (* FLD (f_r1), * FLD (f_r2)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform cmpui: cmpui $src2,$uimm16.  */
+CIA
+SEM_FN_NAME (cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_12.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_cond) = LTUSI (* FLD (f_r2), FLD (f_uimm16));
+  TRACE_RESULT (current_cpu, "h_cond", 'x', LTUSI (* FLD (f_r2), FLD (f_uimm16)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform div: div $dr,$sr.  */
+CIA
+SEM_FN_NAME (div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_13.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NESI (* FLD (f_r2), 0))
+{
+* FLD (f_r1) = DIVSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform divu: divu $dr,$sr.  */
+CIA
+SEM_FN_NAME (divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_13.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NESI (* FLD (f_r2), 0))
+{
+* FLD (f_r1) = UDIVSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform rem: rem $dr,$sr.  */
+CIA
+SEM_FN_NAME (rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_13.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NESI (* FLD (f_r2), 0))
+{
+* FLD (f_r1) = MODSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform remu: remu $dr,$sr.  */
+CIA
+SEM_FN_NAME (remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_13.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NESI (* FLD (f_r2), 0))
+{
+* FLD (f_r1) = UMODSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform jl: jl $sr.  */
+CIA
+SEM_FN_NAME (jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_14.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+do {
+  SI temp1;SI temp0;
+temp0 = ADDSI (ANDSI (CPU (pc), -4), 4);
+temp1 = * FLD (f_r2);
+CPU (h_gr[14]) = temp0;
+  TRACE_RESULT (current_cpu, "h_gr[14]", 'x', temp0);
+  new_pc = SEM_BRANCH_VIA_ADDR (sem_arg, temp1);
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform jmp: jmp $sr.  */
+CIA
+SEM_FN_NAME (jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_14.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+  new_pc = SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ld: ld $dr,@$sr.  */
+CIA
+SEM_FN_NAME (ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ld-d: ld $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ldb: ldb $dr,@$sr.  */
+CIA
+SEM_FN_NAME (ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ldb-d: ldb $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ldh: ldh $dr,@$sr.  */
+CIA
+SEM_FN_NAME (ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ldh-d: ldh $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ldub: ldub $dr,@$sr.  */
+CIA
+SEM_FN_NAME (ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ldub-d: ldub $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform lduh: lduh $dr,@$sr.  */
+CIA
+SEM_FN_NAME (lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform lduh-d: lduh $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ld-plus: ld $dr,@$sr+.  */
+CIA
+SEM_FN_NAME (ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  SI temp1;SI temp0;
+temp0 = GETMEMSI (current_cpu, * FLD (f_r2));
+temp1 = ADDSI (* FLD (f_r2), 4);
+* FLD (f_r1) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+* FLD (f_r2) = temp1;
+  TRACE_RESULT (current_cpu, "sr", 'x', * FLD (f_r2));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ld24: ld24 $dr,$uimm24.  */
+CIA
+SEM_FN_NAME (ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_15.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = FLD (f_uimm24);
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ldi8: ldi $dr,$simm8.  */
+CIA
+SEM_FN_NAME (ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_4.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = FLD (f_simm8);
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform ldi16: ldi $dr,$slo16.  */
+CIA
+SEM_FN_NAME (ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_16.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = FLD (f_simm16);
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform lock: lock $dr,@$sr.  */
+CIA
+SEM_FN_NAME (lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform machi: machi $src1,$src2.  */
+CIA
+SEM_FN_NAME (machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = SRADI (SHLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform maclo: maclo $src1,$src2.  */
+CIA
+SEM_FN_NAME (maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = SRADI (SHLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (SHLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (SHLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform macwhi: macwhi $src1,$src2.  */
+CIA
+SEM_FN_NAME (macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = SRADI (SHLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform macwlo: macwlo $src1,$src2.  */
+CIA
+SEM_FN_NAME (macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = SRADI (SHLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mul: mul $dr,$sr.  */
+CIA
+SEM_FN_NAME (mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = MULSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mulhi: mulhi $src1,$src2.  */
+CIA
+SEM_FN_NAME (mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = SRADI (SHLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mullo: mullo $src1,$src2.  */
+CIA
+SEM_FN_NAME (mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = SRADI (SHLDI (MULDI (EXTSIDI (SHLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (MULDI (EXTSIDI (SHLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mulwhi: mulwhi $src1,$src2.  */
+CIA
+SEM_FN_NAME (mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = SRADI (SHLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mulwlo: mulwlo $src1,$src2.  */
+CIA
+SEM_FN_NAME (mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = SRADI (SHLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mv: mv $dr,$sr.  */
+CIA
+SEM_FN_NAME (mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = * FLD (f_r2);
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mvfachi: mvfachi $dr.  */
+CIA
+SEM_FN_NAME (mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 32));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mvfaclo: mvfaclo $dr.  */
+CIA
+SEM_FN_NAME (mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = TRUNCDISI (CPU (h_accum));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mvfacmi: mvfacmi $dr.  */
+CIA
+SEM_FN_NAME (mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 16));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mvfc: mvfc $dr,$scr.  */
+CIA
+SEM_FN_NAME (mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_18.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = h_cr_get (FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mvtachi: mvtachi $src1.  */
+CIA
+SEM_FN_NAME (mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_19.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0, 0xffffffff)), SHLDI (EXTSIDI (* FLD (f_r1)), 32));
+  TRACE_RESULT (current_cpu, "h_accum", 'D', ORDI (ANDDI (CPU (h_accum), MAKEDI (0, 0xffffffff)), SHLDI (EXTSIDI (* FLD (f_r1)), 32)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mvtaclo: mvtaclo $src1.  */
+CIA
+SEM_FN_NAME (mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_19.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1)));
+  TRACE_RESULT (current_cpu, "h_accum", 'D', ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1))));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform mvtc: mvtc $sr,$dcr.  */
+CIA
+SEM_FN_NAME (mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_20.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+h_cr_set (FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dcr", 'x', h_cr_get (FLD (f_r1)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform neg: neg $dr,$sr.  */
+CIA
+SEM_FN_NAME (neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = NEGSI (* FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform nop: nop.  */
+CIA
+SEM_FN_NAME (nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_21.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform not: not $dr,$sr.  */
+CIA
+SEM_FN_NAME (not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = INVSI (* FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform rac: rac.  */
+CIA
+SEM_FN_NAME (rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_21.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+{
+  DI tmp_tmp1;
+tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff))))
+{
+  tmp_tmp1 = MAKEDI (16383, 0xffff8000);
+} else {
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0))))
+{
+  tmp_tmp1 = MAKEDI (16760832, 0);
+} else {
+  tmp_tmp1 = ANDDI (ADDDI (CPU (h_accum), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000));
+}
+}
+  tmp_tmp1 = SHLDI (tmp_tmp1, 1);
+CPU (h_accum) = SRADI (SHLDI (tmp_tmp1, 7), 7);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (tmp_tmp1, 7), 7));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform rach: rach.  */
+CIA
+SEM_FN_NAME (rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_21.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+{
+  DI tmp_tmp1;
+tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff))))
+{
+  tmp_tmp1 = MAKEDI (16383, 0x80000000);
+} else {
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0))))
+{
+  tmp_tmp1 = MAKEDI (16760832, 0);
+} else {
+  tmp_tmp1 = ANDDI (ADDDI (CPU (h_accum), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
+}
+}
+  tmp_tmp1 = SHLDI (tmp_tmp1, 1);
+CPU (h_accum) = SRADI (SHLDI (tmp_tmp1, 7), 7);
+  TRACE_RESULT (current_cpu, "h_accum", 'D', SRADI (SHLDI (tmp_tmp1, 7), 7));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform rte: rte.  */
+CIA
+SEM_FN_NAME (rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_21.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+{
+CPU (h_sm) = CPU (h_bsm);
+  TRACE_RESULT (current_cpu, "h_sm", 'x', CPU (h_bsm));
+CPU (h_ie) = CPU (h_bie);
+  TRACE_RESULT (current_cpu, "h_ie", 'x', CPU (h_bie));
+CPU (h_cond) = CPU (h_bcond);
+  TRACE_RESULT (current_cpu, "h_cond", 'x', CPU (h_bcond));
+  new_pc = SEM_BRANCH_VIA_ADDR (sem_arg, CPU (h_bpc));
+  TRACE_RESULT (current_cpu, "new_pc", 'x', SEM_NEW_PC_ADDR (new_pc));
+  taken_p = 1;
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform seth: seth $dr,$hi16.  */
+CIA
+SEM_FN_NAME (seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_22.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SHLSI (FLD (f_hi16), 16);
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform sll: sll $dr,$sr.  */
+CIA
+SEM_FN_NAME (sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SHLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform sll3: sll3 $dr,$sr,$simm16.  */
+CIA
+SEM_FN_NAME (sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_5.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SHLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform slli: slli $dr,$uimm5.  */
+CIA
+SEM_FN_NAME (slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_23.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SHLSI (* FLD (f_r1), FLD (f_uimm5));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform sra: sra $dr,$sr.  */
+CIA
+SEM_FN_NAME (sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform sra3: sra3 $dr,$sr,$simm16.  */
+CIA
+SEM_FN_NAME (sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_5.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform srai: srai $dr,$uimm5.  */
+CIA
+SEM_FN_NAME (srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_23.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SRASI (* FLD (f_r1), FLD (f_uimm5));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform srl: srl $dr,$sr.  */
+CIA
+SEM_FN_NAME (srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform srl3: srl3 $dr,$sr,$simm16.  */
+CIA
+SEM_FN_NAME (srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_5.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform srli: srli $dr,$uimm5.  */
+CIA
+SEM_FN_NAME (srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_23.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SRLSI (* FLD (f_r1), FLD (f_uimm5));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform st: st $src1,@$src2.  */
+CIA
+SEM_FN_NAME (st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
+  TRACE_RESULT (current_cpu, "memory", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform st-d: st $src1,@($slo16,$src2).  */
+CIA
+SEM_FN_NAME (st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
+  TRACE_RESULT (current_cpu, "memory", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform stb: stb $src1,@$src2.  */
+CIA
+SEM_FN_NAME (stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));
+  TRACE_RESULT (current_cpu, "memory", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform stb-d: stb $src1,@($slo16,$src2).  */
+CIA
+SEM_FN_NAME (stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
+  TRACE_RESULT (current_cpu, "memory", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform sth: sth $src1,@$src2.  */
+CIA
+SEM_FN_NAME (sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));
+  TRACE_RESULT (current_cpu, "memory", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform sth-d: sth $src1,@($slo16,$src2).  */
+CIA
+SEM_FN_NAME (sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
+  TRACE_RESULT (current_cpu, "memory", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform st-plus: st $src1,@+$src2.  */
+CIA
+SEM_FN_NAME (st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+{
+* FLD (f_r2) = ADDSI (* FLD (f_r2), 4);
+  TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
+SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
+  TRACE_RESULT (current_cpu, "memory", 'x', * FLD (f_r1));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform st-minus: st $src1,@-$src2.  */
+CIA
+SEM_FN_NAME (st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+{
+* FLD (f_r2) = SUBSI (* FLD (f_r2), 4);
+  TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
+SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
+  TRACE_RESULT (current_cpu, "memory", 'x', * FLD (f_r1));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform sub: sub $dr,$sr.  */
+CIA
+SEM_FN_NAME (sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+* FLD (f_r1) = SUBSI (* FLD (f_r1), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform subv: subv $dr,$sr.  */
+CIA
+SEM_FN_NAME (subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2));
+temp1 = SUBOFSI (* FLD (f_r1), * FLD (f_r2), 0);
+* FLD (f_r1) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "h_cond", 'x', temp1);
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform subx: subx $dr,$sr.  */
+CIA
+SEM_FN_NAME (subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
+temp1 = SUBCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
+* FLD (f_r1) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "h_cond", 'x', temp1);
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_mark_set_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform trap: trap $uimm4.  */
+CIA
+SEM_FN_NAME (trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_25.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+do_trap (current_cpu, FLD (f_uimm4));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
+/* Perform unlock: unlock $src1,@$src2.  */
+CIA
+SEM_FN_NAME (unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      model_mark_get_h_gr (current_cpu, abuf);
+      model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef FLD
+}
+
diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
new file mode 100644
index 0000000..620a44a
--- /dev/null
+++ b/sim/m32r/sim-if.c
@@ -0,0 +1,328 @@
+/* Main simulator entry points for the M32R.
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+   Contributed by Cygnus Support.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+#include <signal.h>
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#include "libiberty.h"
+#include "bfd.h"
+#include "sim-core.h"
+#include "cpu-sim.h"
+
+struct host_callback_struct *sim_callback;
+
+/* Global state until sim_open starts creating and returning it
+   [and the other simulator i/f fns take it as an argument].  */
+struct sim_state sim_global_state;
+
+/* FIXME: Do we *need* to pass state to the semantic routines?  */
+STATE current_state;
+
+/* Create an instance of the simulator.  */
+
+SIM_DESC
+sim_open (kind, argv)
+     SIM_OPEN_KIND kind;
+     char **argv;
+{
+  int i;
+  SIM_DESC sd = &sim_global_state;
+
+  /* FIXME: until we alloc one, use the global.  */
+  memset (sd, 0, sizeof (sim_global_state));
+  STATE_OPEN_KIND (sd) = kind;
+  STATE_CALLBACK (sd) = sim_callback;
+
+  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+    return 0;
+
+#if 0 /* FIXME: 'twould be nice if we could do this */
+  /* These options override any module options.
+     Obviously ambiguity should be avoided, however the caller may wish to
+     augment the meaning of an option.  */
+  if (extra_options != NULL)
+    sim_add_option_table (sd, extra_options);
+#endif
+
+  /* getopt will print the error message so we just have to exit if this fails.
+     FIXME: Hmmm...  in the case of gdb we need getopt to call
+     print_filtered.  */
+  if (sim_parse_args (sd, argv) != SIM_RC_OK)
+    {
+      sim_module_uninstall (sd);
+      return 0;
+    }
+
+  if (sim_post_argv_init (sd) != SIM_RC_OK)
+    {
+      sim_module_uninstall (sd);
+      return 0;
+    }
+
+  /* Initialize various cgen things not done by common framework.  */
+  cgen_init (sd);
+
+  /* FIXME:wip */
+  sim_core_attach (sd,
+		   attach_raw_memory,
+		   access_read_write_exec,
+		   0, 0, 0x100000, NULL, NULL);
+
+  /* We could only do this if profiling has been enabled, but the
+     structure member is small so we don't bother.  */
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+    memset (& CPU_M32R_PROFILE (STATE_CPU (sd, i)), 0,
+	    sizeof (CPU_M32R_PROFILE (STATE_CPU (sd, i))));
+
+  return &sim_global_state;
+}
+
+void
+sim_close (sd, quitting)
+     SIM_DESC sd;
+     int quitting;
+{
+  sim_module_uninstall (sd);
+}
+
+SIM_RC
+sim_load (sd, prog, abfd, from_tty)
+     SIM_DESC sd;
+     char *prog;
+     bfd *abfd;
+     int from_tty;
+{
+  extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
+  bfd *prog_bfd;
+
+  prog_bfd = sim_load_file (sd, STATE_MY_NAME (sd),
+			    STATE_CALLBACK (sd),
+			    prog,
+			    /* pass NULL for abfd, we always open our own */
+			    NULL,
+			    STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG);
+  if (prog_bfd == NULL)
+    return SIM_RC_FAIL;
+  sim_analyze_program (sd, prog_bfd);
+  STATE_CPU_CPU (sd, 0)->pc = STATE_START_ADDR (sd);
+  return SIM_RC_OK;
+} 
+
+SIM_RC
+sim_create_inferior (sd, argv, envp)
+     SIM_DESC sd;
+     char **argv;
+     char **envp;
+{
+#if 0
+  STATE_ARGV (sd) = sim_copy_argv (argv);
+  STATE_ENVP (sd) = sim_copy_argv (envp);
+#endif
+  return SIM_RC_OK;
+}
+
+void
+sim_kill (sd)
+     SIM_DESC sd;
+{
+  /* nothing to do */
+}
+
+int
+sim_stop (SIM_DESC sd)
+{
+  return engine_stop (sd);
+}
+
+void
+sim_resume (sd, step, siggnal)
+     SIM_DESC sd;
+     int step, siggnal;
+{
+  engine_run (sd, step, siggnal);
+}
+
+void
+sim_stop_reason (sd, reason, sigrc)
+     SIM_DESC sd;
+     enum sim_stop *reason;
+     int *sigrc;
+{
+  sim_cpu *cpu = STATE_CPU (sd, 0);
+
+  /* Map sim_state to sim_stop.  */
+  switch (CPU_EXEC_STATE (cpu))
+    {
+    case EXEC_STATE_EXITED :
+      *reason = sim_exited;
+      *sigrc = CPU_HALT_SIGRC (cpu);
+      break;
+    case EXEC_STATE_STOPPED :
+      *reason = sim_stopped;
+      *sigrc = sim_signal_to_host (CPU_HALT_SIGRC (cpu));
+      break;
+    case EXEC_STATE_SIGNALLED :
+      *reason = sim_signalled;
+      *sigrc = sim_signal_to_host (CPU_HALT_SIGRC (cpu));
+      break;
+    }
+}
+
+/* PROFILE_CPU_CALLBACK */
+
+static void
+print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
+    {
+      sim_io_printf (sd, "Miscellaneous Statistics\n\n");
+      sim_io_printf (sd, "  %-*s %ld\n\n",
+		     PROFILE_LABEL_WIDTH, "Fill nops:",
+		     CPU_M32R_PROFILE (cpu).fillnop_count);
+    }
+}
+
+void
+sim_info (sd, verbose)
+     SIM_DESC sd;
+     int verbose;
+{
+  profile_print (sd, STATE_VERBOSE_P (sd), NULL, print_m32r_misc_cpu);
+}
+
+void
+sim_set_callbacks (sd, p)
+     SIM_DESC sd;
+     host_callback *p;
+{
+  if (sd == NULL)
+    sim_callback = p;
+  else
+    STATE_CALLBACK (sd) = p;
+}
+
+/* The contents of BUF are in target byte order.  */
+
+void
+sim_fetch_register (sd, rn, buf)
+     SIM_DESC sd;
+     int rn;
+     unsigned char *buf;
+{
+  if (rn < 16)
+    SETTWI (buf, STATE_CPU_CPU (sd, 0)->h_gr[rn]);
+  else if (rn < 21)
+    SETTWI (buf, STATE_CPU_CPU (sd, 0)->h_cr[rn - 16]);
+  else switch (rn) {
+    case PC_REGNUM:
+      SETTWI (buf, STATE_CPU_CPU (sd, 0)->pc);
+      break;
+    case ACCL_REGNUM:
+      SETTWI (buf, GETLODI (STATE_CPU_CPU (sd, 0)->h_accum));
+      break;
+    case ACCH_REGNUM:
+      SETTWI (buf, GETHIDI (STATE_CPU_CPU (sd, 0)->h_accum));
+      break;
+#if 0
+    case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond;		break;
+    case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm;		break;
+    case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm;		break;
+    case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie;		break;
+    case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie;		break;
+    case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry;		break; /* rename: bc */
+    case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI));	break; /* duplicate */
+#endif
+    default: abort ();
+  }
+}
+ 
+/* The contents of BUF are in target byte order.  */
+
+void
+sim_store_register (sd, rn, buf)
+     SIM_DESC sd;
+     int rn;
+     unsigned char *buf;
+{
+  if (rn < 16)
+    STATE_CPU_CPU (sd, 0)->h_gr[rn] = GETTWI (buf);
+  else if (rn < 21)
+    STATE_CPU_CPU (sd, 0)->h_cr[rn - 16] = GETTWI (buf);
+  else switch (rn) {
+    case PC_REGNUM:
+      STATE_CPU_CPU (sd, 0)->pc = GETTWI (buf);
+      break;
+    case ACCL_REGNUM:
+      SETLODI (STATE_CPU_CPU (sd, 0)->h_accum, GETTWI (buf));
+      break;
+    case ACCH_REGNUM:
+      SETHIDI (STATE_CPU_CPU (sd, 0)->h_accum, GETTWI (buf));
+      break;
+#if 0
+    case 23: STATE_CPU_CPU (sd, 0)->h_cond   = *reg;			break;
+    case 24: STATE_CPU_CPU (sd, 0)->h_sm     = *reg;			break;
+    case 25: STATE_CPU_CPU (sd, 0)->h_bsm    = *reg;			break;
+    case 26: STATE_CPU_CPU (sd, 0)->h_ie     = *reg;			break;
+    case 27: STATE_CPU_CPU (sd, 0)->h_bie    = *reg;			break;
+    case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg;			break; /* rename: bc */
+    case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI));	break; /* duplicate */
+#endif
+  }
+}
+
+int
+sim_read (sd, addr, buf, len)
+     SIM_DESC sd;
+     SIM_ADDR addr;
+     unsigned char *buf;
+     int len;
+{
+#if 1
+  return sim_core_read_buffer (sd, sim_core_read_map,
+				buf, addr, len);
+#else
+  return (*STATE_MEM_READ (sd)) (sd, addr, buf, len);
+#endif
+} 
+
+int
+sim_write (sd, addr, buf, len)
+     SIM_DESC sd;
+     SIM_ADDR addr;
+     unsigned char *buf;
+     int len;
+{
+#if 1
+  return sim_core_write_buffer (sd, sim_core_write_map,
+				buf, addr, len);
+#else
+  return (*STATE_MEM_WRITE (sd)) (sd, addr, buf, len);
+#endif
+}
+
+void
+sim_do_command (sd, cmd)
+     SIM_DESC sd;
+     char *cmd;
+{ 
+  sim_io_error (sd, "sim_do_command - unimplemented");
+}