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| author | Gavin Romig-Koch <gavin@redhat.com> | 1997-11-04 05:50:22 +0000 |
|---|---|---|
| committer | Gavin Romig-Koch <gavin@redhat.com> | 1997-11-04 05:50:22 +0000 |
| commit | 0425cfb3af921f909554c5bd0c6feebd471fd50b (patch) | |
| tree | f37b666b32599e1fa3f4830f9bf1f44e26da0746 | |
| parent | d66e8c4bef506d6fed78d267916dd69b968e4f8b (diff) | |
| download | gdb-0425cfb3af921f909554c5bd0c6feebd471fd50b.zip gdb-0425cfb3af921f909554c5bd0c6feebd471fd50b.tar.gz gdb-0425cfb3af921f909554c5bd0c6feebd471fd50b.tar.bz2 | |
Correct r5900 sanitization.
| -rw-r--r-- | sim/mips/interp.c | 2 | ||||
| -rw-r--r-- | sim/mips/sim-main.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c index b605dbc..835dbdb 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -3735,10 +3735,12 @@ sim_engine_run (sd, next_cpu_nr, siggnal) HIACCESS--; if (LOACCESS > 0) LOACCESS--; + /* start-sanitize-r5900 */ if (HI1ACCESS > 0) HI1ACCESS--; if (LO1ACCESS > 0) LO1ACCESS--; + /* end-sanitize-r5900 */ #endif /* WARN_LOHI */ /* For certain MIPS architectures, GPR[0] is hardwired to zero. We diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index b096069..7809714 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -471,7 +471,7 @@ struct _sim_cpu { if ((HIACCESS != 0) || (LOACCESS != 0)) \ sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\ } - /* end-sanitize-r5900 */ + /* start-sanitize-r5900 */ #undef CHECKHILO #define CHECKHILO(s) {\ if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\ |