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authorRichard Sandiford <rdsandiford@googlemail.com>2010-02-10 19:59:07 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2010-02-10 19:59:07 +0000
commitcdc51b0748c418670cd15476234146993d202449 (patch)
tree6a4b9a767be7d50c4371c4108763a62ca3905e61
parent45e481d13b770b743fb0be9d9f5fe8c0e03c2a12 (diff)
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gas/
* config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x, -mpwr6 and -mpwr7. opcodes/ * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6" and "pwr7". Move "a2" into alphabetical order.
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-ppc.c9
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/ppc-dis.c26
4 files changed, 37 insertions, 8 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6e30f26..9d78944 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
+
+ * config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x,
+ -mpwr6 and -mpwr7.
+
2010-02-09 Sterling Augustine <sterling@tensilica.com>
* config/tc-xtensa.c (RELAXED_LOOP_INSN_BYTES): New.
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 3f366fe..5a26d36 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1199,10 +1199,11 @@ PowerPC options:\n\
-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
-mbooke generate code for 32-bit PowerPC BookE\n\
-ma2 generate code for A2 architecture\n\
--mpower4 generate code for Power4 architecture\n\
--mpower5 generate code for Power5 architecture\n\
--mpower6 generate code for Power6 architecture\n\
--mpower7 generate code for Power7 architecture\n\
+-mpower4, -mpwr4 generate code for Power4 architecture\n\
+-mpower5, -mpwr5, -mpwr5x\n\
+ generate code for Power5 architecture\n\
+-mpower6, -mpwr6 generate code for Power6 architecture\n\
+-mpower7, -mpwr7 generate code for Power7 architecture\n\
-mcell generate code for Cell Broadband Engine architecture\n\
-mcom generate code Power/PowerPC common instructions\n\
-many generate code for any architecture (PWR/PWRX/PPC)\n"));
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c03049d..aec487e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
+
+ * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
+ and "pwr7". Move "a2" into alphabetical order.
+
2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* ppc-dis.c (ppc_opts): Add titan entry.
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 12833a8..2504d42 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -89,6 +89,10 @@ struct ppc_mopt ppc_opts[] = {
0 },
{ "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
, 0 },
+ { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK
+ | PPC_OPCODE_64 | PPC_OPCODE_A2),
+ 0 },
{ "altivec", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
PPC_OPCODE_ALTIVEC },
{ "any", 0,
@@ -150,16 +154,30 @@ struct ppc_mopt ppc_opts[] = {
{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64_BRIDGE
| PPC_OPCODE_64),
0 },
- { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
- | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK
- | PPC_OPCODE_64 | PPC_OPCODE_A2),
- 0 },
{ "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
0 },
{ "pwr", (PPC_OPCODE_POWER | PPC_OPCODE_32),
0 },
{ "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
0 },
+ { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4),
+ 0 },
+ { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
+ 0 },
+ { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
+ 0 },
+ { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_ALTIVEC),
+ 0 },
+ { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
+ | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
+ | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC
+ | PPC_OPCODE_VSX),
+ 0 },
{ "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
0 },
{ "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),