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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-06-23 20:12:53 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-06-23 20:12:53 +0000 |
| commit | c3678916c694b6af469a882ae1df0dc15b89f44a (patch) | |
| tree | 961262a8c453d7901b4cf62dfeee6c45a276872c | |
| parent | 42429eacb42f0cc6dfe7fbd6d74a59e652945794 (diff) | |
| download | gdb-c3678916c694b6af469a882ae1df0dc15b89f44a.zip gdb-c3678916c694b6af469a882ae1df0dc15b89f44a.tar.gz gdb-c3678916c694b6af469a882ae1df0dc15b89f44a.tar.bz2 | |
include/opcode/
* mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
gas/
* config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
| -rw-r--r-- | gas/ChangeLog | 4 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 24 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 2 |
4 files changed, 22 insertions, 12 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 26b13ed..d6d9f5e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,9 @@ 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com> + * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments. + +2013-06-23 Richard Sandiford <rdsandiford@googlemail.com> + * config/tc-mips.c: Assert that offsetT and valueT are at least 8 bytes in size. (GPR_SMIN, GPR_SMAX): New macros. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index e259071..dba8b21 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -11386,8 +11386,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '3': - /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS - code) or 21 (for microMIPS code). */ + /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS + code) or 13 (for microMIPS code). */ { unsigned long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); @@ -11405,8 +11405,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '4': - /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS - code) or 21 (for microMIPS code). */ + /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS + code) or 12 (for microMIPS code). */ { unsigned long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); @@ -11424,8 +11424,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '5': - /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS - code) or 16 (for microMIPS code). */ + /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS + code) or 13 (for microMIPS code). */ { unsigned long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); @@ -11443,8 +11443,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '6': - /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS - code) or 21 (for microMIPS code). */ + /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS + code) or 16 (for microMIPS code). */ { unsigned long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_RS : OP_MASK_RS); @@ -11461,7 +11461,9 @@ mips_ip (char *str, struct mips_cl_insn *ip) } continue; - case '7': /* Four DSP accumulators in bits 11,12. */ + case '7': + /* Four DSP accumulators in bit 11 (for standard MIPS code) + or 14 (for microMIPS code). */ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && s[3] >= '0' && s[3] <= '3') { @@ -11509,8 +11511,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) break; case '0': - /* DSP 6-bit signed immediate in bit 16 (for standard MIPS - code) or 20 (for microMIPS code). */ + /* DSP 6-bit signed immediate in bit 20 (for standard MIPS + code) or 16 (for microMIPS code). */ { long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 4daf47b..189a1d4 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-06-23 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. + 2013-06-17 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Chao-Ying Fu <fu@mips.com> diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 9d241e8..e62ecd6 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1811,7 +1811,7 @@ extern const int bfd_mips16_num_opcodes; Coprocessor instructions: "E" 5-bit target register (MICROMIPSOP_*_RT) - "G" 5-bit destination register (MICROMIPSOP_*_RD) + "G" 5-bit destination register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) "+D" combined destination register ("G") and sel ("H") for CP0 ops, for pretty-printing in disassembly only |