Peter Targett's backwards compatibility and other arc fixes.

12 files changed, 253 insertions, 193 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index c97b46a..66d8fb7 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,13 @@
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* cpu-arc.c (arch_info_struct): Add entry 'base' representing old
+	name for 'arc5' core versions.
+	(bfd_arc_arch): Make bfd_mach_arc_6 default.
+
+	* elf32-arc.c (arc_elf_object_p): Make E_ARC_MACH_ARC6 default
+	architecture.
+	(arc_elf_final_write_processing): Make bfd_mach_arc_6 default.
+
 2001-05-11  Jakub Jelinek  <jakub@redhat.com>
 
 	* elfxx-ia64.c (is_unwind_section_name): Consider linkonce unwind
diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
index 8e8e09a..2904ae3 100644
--- a/bfd/cpu-arc.c
+++ b/bfd/cpu-arc.c
@@ -33,7 +33,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
     print_name,				\
     4, /* section alignment power  */	\
     default_p,				\
-    bfd_default_compatible, 		\
+    bfd_default_compatible,		\
     bfd_default_scan,			\
     next,				\
   }
@@ -41,13 +41,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 static const bfd_arch_info_type arch_info_struct[] =
 {
   ARC ( bfd_mach_arc_5, "arc5", false, &arch_info_struct[1] ),
-  ARC ( bfd_mach_arc_6, "arc6", false, &arch_info_struct[2] ),
-  ARC ( bfd_mach_arc_7, "arc7", false, &arch_info_struct[3] ),
+  ARC ( bfd_mach_arc_5, "base", false, &arch_info_struct[2] ),
+  ARC ( bfd_mach_arc_6, "arc6", false, &arch_info_struct[3] ),
+  ARC ( bfd_mach_arc_7, "arc7", false, &arch_info_struct[4] ),
   ARC ( bfd_mach_arc_8, "arc8", false, NULL ),
 };
 
 const bfd_arch_info_type bfd_arc_arch =
-  ARC ( bfd_mach_arc_5, "arc", true, &arch_info_struct[0] );
+  ARC ( bfd_mach_arc_6, "arc", true, &arch_info_struct[0] );
 
 /* Utility routines.  */
 
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index 1cc8bba..82b6104 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -57,18 +57,18 @@ static reloc_howto_type elf_arc_howto_table[] =
 
   /* A standard 32 bit relocation.  */
   HOWTO (R_ARC_32,		/* type  */
-	 0,	                /* rightshift  */
-	 2,	                /* size (0 = byte, 1 = short, 2 = long)  */
-	 32,	                /* bitsize  */
-	 false,	                /* pc_relative  */
-	 0,	                /* bitpos  */
+	 0,			/* rightshift  */
+	 2,			/* size (0 = byte, 1 = short, 2 = long)  */
+	 32,			/* bitsize  */
+	 false,			/* pc_relative  */
+	 0,			/* bitpos  */
 	 complain_overflow_bitfield, /* complain_on_overflow  */
-	 bfd_elf_generic_reloc, /* special_function  */
+	 bfd_elf_generic_reloc,	/* special_function  */
 	 "R_ARC_32",		/* name  */
-	 false,	                /* partial_inplace  */
-	 0xffffffff,	        /* src_mask  */
-	 0xffffffff,   		/* dst_mask  */
-	 false),                /* pcrel_offset  */
+	 false,			/* partial_inplace  */
+	 0xffffffff,		/* src_mask  */
+	 0xffffffff,		/* dst_mask  */
+	 false),		/* pcrel_offset  */
 
   /* A 26 bit absolute branch, right shifted by 2.  */
   HOWTO (R_ARC_B26,		/* type  */
@@ -155,7 +155,7 @@ static boolean
 arc_elf_object_p (abfd)
      bfd *abfd;
 {
-  int mach = bfd_mach_arc_5;
+  int mach = bfd_mach_arc_6;
 
   if (elf_elfheader(abfd)->e_machine == EM_ARC)
     {
@@ -163,10 +163,10 @@ arc_elf_object_p (abfd)
 
       switch (arch)
 	{
-	default:
 	case E_ARC_MACH_ARC5:
 	  mach = bfd_mach_arc_5;
 	  break;
+	default:
 	case E_ARC_MACH_ARC6:
 	  mach = bfd_mach_arc_6;
 	  break;
@@ -193,10 +193,10 @@ arc_elf_final_write_processing (abfd, linker)
 
   switch (bfd_get_mach (abfd))
     {
-    default:
     case bfd_mach_arc_5:
       val = E_ARC_MACH_ARC5;
       break;
+    default:
     case bfd_mach_arc_6:
       val = E_ARC_MACH_ARC6;
       break;
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 21e5209..f0de913 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,21 @@
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* config/tc-arc.c: Update copyright and tidy source comments.
+	(md_pseudo_table): Add directive .cpu back as an alias for
+	.option.  Add .file and .line for dwarf2 support.
+	(arc_mach_type): Make bfd_mach_arc_6 default.
+	(md_longopts): Add entry 'pre-v6' representing old command line
+	option when assembling for 'arc5' core versions.
+	(md_parse_option): Make OPTION_ARC same as OPTION_ARC6, for new
+	default behaviour.
+	(arc_code_symbol): Make symbol value for @h30 fixup expression
+	equal to O_constant.
+	(md_assemble): Call dwarf2_emit_insn.
+	Include "dwarf2dbg2.h".  Formatting fixes throughout file.
+	* config/tc-arc.h (DWARF2_LINE_MIN_INSN_LENGTH): Define.
+
+	* doc/c-arc.texi (ARC_CORE_DEFAULT): Update to new default.
+
 2001-05-11  Jakub Jelinek  <jakub@redhat.com>
 
 	* config/tc-ia64.c (special_linkonce_name): New.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 778b24c..3cbd3c0 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -28,6 +28,7 @@
 #include "opcode/arc.h"
 #include "../opcodes/arc-ext.h"
 #include "elf/arc.h"
+#include "dwarf2dbg.h"
 
 extern int arc_get_mach PARAMS ((char *));
 extern int arc_operand_type PARAMS ((int));
@@ -76,7 +77,7 @@ const struct syntax_classes {
 #define MAXSYNTAXCLASS (sizeof (syntaxclass) / sizeof (struct syntax_classes))
 
 const pseudo_typeS md_pseudo_table[] = {
-  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0) */
+  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
   { "comm", arc_common, 0 },
   { "common", arc_common, 0 },
   { "lcomm", arc_common, 1 },
@@ -88,7 +89,10 @@ const pseudo_typeS md_pseudo_table[] = {
   { "4byte", cons, 4 },
   { "word", cons, 4 },
   { "option", arc_option, 0 },
+  { "cpu", arc_option, 0 },
   { "block", s_space, 0 },
+  { "file", dwarf2_directive_file, 0 },
+  { "loc", dwarf2_directive_loc, 0 },
   { "extcondcode", arc_extoper, 0 },
   { "extcoreregister", arc_extoper, 1 },
   { "extauxregister", arc_extoper, 2 },
@@ -97,7 +101,7 @@ const pseudo_typeS md_pseudo_table[] = {
 };
 
 /* This array holds the chars that always start a comment.  If the
-   pre-processor is disabled, these aren't very useful */
+   pre-processor is disabled, these aren't very useful.  */
 const char comment_chars[] = "#;";
 
 /* This array holds the chars that only start a comment at the beginning of
@@ -112,12 +116,11 @@ const char line_comment_chars[] = "#";
 
 const char line_separator_chars[] = "";
 
-/* Chars that can be used to separate mant from exp in floating point nums */
+/* Chars that can be used to separate mant from exp in floating point nums.  */
 const char EXP_CHARS[] = "eE";
 
-/* Chars that mean this number is a floating point constant */
-/* As in 0f12.456 */
-/* or    0d1.2345e12 */
+/* Chars that mean this number is a floating point constant
+   As in 0f12.456 or 0d1.2345e12.  */
 const char FLT_CHARS[] = "rRsSfFdD";
 
 /* Byte order.  */
@@ -128,13 +131,13 @@ static int byte_order = DEFAULT_BYTE_ORDER;
 static segT arcext_section;
 
 /* One of bfd_mach_arc_n.  */
-static int arc_mach_type = bfd_mach_arc_5;
+static int arc_mach_type = bfd_mach_arc_6;
 
 /* Non-zero if the cpu type has been explicitly specified.  */
 static int mach_type_specified_p = 0;
 
 /* Non-zero if opcode tables have been initialized.
-   A .cpu command must appear before any instructions.  */
+   A .option command must appear before any instructions.  */
 static int cpu_tables_init_p = 0;
 
 static struct hash_control *arc_suffix_hash = NULL;
@@ -142,19 +145,20 @@ static struct hash_control *arc_suffix_hash = NULL;
 const char *md_shortopts = "";
 struct option md_longopts[] = {
 #define OPTION_EB (OPTION_MD_BASE + 0)
-  {"EB", no_argument, NULL, OPTION_EB},
+  { "EB", no_argument, NULL, OPTION_EB },
 #define OPTION_EL (OPTION_MD_BASE + 1)
-  {"EL", no_argument, NULL, OPTION_EL},
+  { "EL", no_argument, NULL, OPTION_EL },
 #define OPTION_ARC5 (OPTION_MD_BASE + 2)
-  {"marc5", no_argument, NULL, OPTION_ARC5},
+  { "marc5", no_argument, NULL, OPTION_ARC5 },
+  { "pre-v6", no_argument, NULL, OPTION_ARC5 },
 #define OPTION_ARC6 (OPTION_MD_BASE + 3)
-  {"marc6", no_argument, NULL, OPTION_ARC6},
+  { "marc6", no_argument, NULL, OPTION_ARC6 },
 #define OPTION_ARC7 (OPTION_MD_BASE + 4)
-  {"marc7", no_argument, NULL, OPTION_ARC7},
+  { "marc7", no_argument, NULL, OPTION_ARC7 },
 #define OPTION_ARC8 (OPTION_MD_BASE + 5)
-  {"marc8", no_argument, NULL, OPTION_ARC8},
+  { "marc8", no_argument, NULL, OPTION_ARC8 },
 #define OPTION_ARC (OPTION_MD_BASE + 6)
-  {"marc", no_argument, NULL, OPTION_ARC},
+  { "marc", no_argument, NULL, OPTION_ARC },
   { NULL, no_argument, NULL, 0 }
 };
 size_t md_longopts_size = sizeof (md_longopts);
@@ -174,10 +178,10 @@ md_parse_option (c, arg)
 {
   switch (c)
     {
-    case OPTION_ARC:
     case OPTION_ARC5:
       arc_mach_type = bfd_mach_arc_5;
       break;
+    case OPTION_ARC:
     case OPTION_ARC6:
       arc_mach_type = bfd_mach_arc_6;
       break;
@@ -214,7 +218,7 @@ ARC Options:\n\
 
 /* This function is called once, at assembler startup time.  It should
    set up all the tables, etc. that the MD part of the assembler will need.
-   Opcode selection is defered until later because we might see a .cpu
+   Opcode selection is deferred until later because we might see a .option
    command.  */
 
 void
@@ -226,16 +230,14 @@ md_begin ()
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
     as_warn ("could not set architecture and machine");
 
-  /* This call is necessary because we need to
-     initialize `arc_operand_map' which may be needed before we see the
-     first insn.  */
+  /* This call is necessary because we need to initialize `arc_operand_map'
+     which may be needed before we see the first insn.  */
   arc_opcode_init_tables (arc_get_opcode_mach (arc_mach_type,
 					       target_big_endian));
 }
 
 /* Initialize the various opcode and operand tables.
    MACH is one of bfd_mach_arc_xxx.  */
-
 static void
 init_opcode_tables (mach)
      int mach;
@@ -277,8 +279,10 @@ init_opcode_tables (mach)
 	continue;
       /* Use symbol_create here instead of symbol_new so we don't try to
 	 output registers into the object file's symbol table.  */
-      symbol_table_insert (symbol_create (arc_reg_names[i].name, reg_section,
-                           (int) &arc_reg_names[i], &zero_address_frag));
+      symbol_table_insert (symbol_create (arc_reg_names[i].name,
+					  reg_section,
+					  (int) &arc_reg_names[i],
+					  &zero_address_frag));
     }
 
   /* Tell `.option' it's too late.  */
@@ -357,7 +361,7 @@ arc_insert_operand (insn, operand, mods, reg, val, file, line)
    that would screw up references to ``.''.  */
 
 struct arc_fixup {
-  /* index into `arc_operands' */
+  /* index into `arc_operands'  */
   int opindex;
   expressionS exp;
 };
@@ -381,7 +385,7 @@ md_assemble (str)
   static int init_tables_p = 0;
 
   /* Opcode table initialization is deferred until here because we have to
-     wait for a possible .cpu command.  */
+     wait for a possible .option command.  */
   if (!init_tables_p)
     {
       init_opcode_tables (arc_mach_type);
@@ -866,6 +870,8 @@ md_assemble (str)
 			   (bfd_reloc_code_real_type) reloc_type);
 	    }
 
+	  dwarf2_emit_insn (4);
+
 	  /* All done.  */
 	  return;
 	}
@@ -912,7 +918,7 @@ arc_extoper (opertype)
       p++;
     }
 
-  /* just after name is now '\0' */
+  /* just after name is now '\0'  */
   p = input_line_pointer;
   *p = c;
   SKIP_WHITESPACE ();
@@ -925,7 +931,7 @@ arc_extoper (opertype)
       return;
     }
 
-  input_line_pointer++;		/* skip ',' */
+  input_line_pointer++;		/* skip ','  */
   number = get_absolute_expression ();
 
   if (number < 0)
@@ -948,7 +954,7 @@ arc_extoper (opertype)
 	  return;
 	}
 
-      input_line_pointer++;		/* skip ',' */
+      input_line_pointer++;		/* skip ','  */
       mode = input_line_pointer;
 
       if (!strncmp (mode, "r|w", 3))
@@ -990,7 +996,7 @@ arc_extoper (opertype)
 	      return;
 	    }
 
-	  input_line_pointer++;             /* skip ',' */
+	  input_line_pointer++;		/* skip ','  */
 
 	  if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
 	    {
@@ -1155,7 +1161,7 @@ arc_extinst (ignore)
   strcpy (syntax, name);
   name_len = strlen (name);
 
-  /* just after name is now '\0' */
+  /* just after name is now '\0'  */
   p = input_line_pointer;
   *p = c;
 
@@ -1168,7 +1174,7 @@ arc_extinst (ignore)
       return;
     }
 
-  input_line_pointer++;		/* skip ',' */
+  input_line_pointer++;		/* skip ','  */
   opcode = get_absolute_expression ();
 
   SKIP_WHITESPACE ();
@@ -1180,7 +1186,7 @@ arc_extinst (ignore)
       return;
     }
 
-  input_line_pointer++;		/* skip ',' */
+  input_line_pointer++;		/* skip ','  */
   subopcode = get_absolute_expression ();
 
   if (subopcode < 0)
@@ -1218,7 +1224,7 @@ arc_extinst (ignore)
       return;
     }
 
-  input_line_pointer++;         /* skip ',' */
+  input_line_pointer++;		/* skip ','  */
 
   for (i = 0; i < (int) MAXSUFFIXCLASS; i++)
     {
@@ -1246,7 +1252,7 @@ arc_extinst (ignore)
       return;
     }
 
-  input_line_pointer++;         /* skip ',' */
+  input_line_pointer++;		/* skip ','  */
 
   for (i = 0; i < (int) MAXSYNTAXCLASS; i++)
     {
@@ -1373,7 +1379,7 @@ arc_common (localScope)
 
   name = input_line_pointer;
   c = get_symbol_end ();
-  /* just after name is now '\0' */
+  /* just after name is now '\0'  */
   p = input_line_pointer;
   *p = c;
   SKIP_WHITESPACE ();
@@ -1385,7 +1391,7 @@ arc_common (localScope)
       return;
     }
 
-  input_line_pointer++;		/* skip ',' */
+  input_line_pointer++;		/* skip ','  */
   size = get_absolute_expression ();
 
   if (size < 0)
@@ -1437,7 +1443,7 @@ arc_common (localScope)
       old_sec    = now_seg;
       old_subsec = now_subseg;
       record_alignment (bss_section, align);
-      subseg_set (bss_section, 0);  /* ??? subseg_set (bss_section, 1); ??? */
+      subseg_set (bss_section, 0);  /* ??? subseg_set (bss_section, 1); ???  */
 
       if (align)
 	/* Do alignment.  */
@@ -1631,12 +1637,13 @@ arc_code_symbol (expressionP)
     {
       expressionS two;
       expressionP->X_op = O_right_shift;
+      expressionP->X_add_symbol->sy_value.X_op = O_constant;
       two.X_op = O_constant;
       two.X_add_symbol = two.X_op_symbol = NULL;
       two.X_add_number = 2;
       expressionP->X_op_symbol = make_expr_symbol (&two);
     }
-  /* Allow %st(sym1-sym2) */
+  /* Allow %st(sym1-sym2)  */
   else if (expressionP->X_op == O_subtract
 	   && expressionP->X_add_symbol != NULL
 	   && expressionP->X_op_symbol != NULL
@@ -1687,7 +1694,8 @@ md_operand (expressionP)
 	arc_code_symbol (expressionP);
       }
     else
-      {       /* It could be a register.  */
+      {
+	/* It could be a register.  */
 	int i, l;
 	struct arc_ext_operand_value *ext_oper = arc_ext_operands;
 	p++;
diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h
index 2aa790b..463400c 100644
--- a/gas/config/tc-arc.h
+++ b/gas/config/tc-arc.h
@@ -66,3 +66,5 @@ arc_parse_cons_expression (EXP, NBYTES)
 extern void arc_cons_fix_new ();
 #define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \
 arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP)
+
+#define DWARF2_LINE_MIN_INSN_LENGTH 4
diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index 56822de..700a01d 100644
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -13,7 +13,7 @@
 @chapter ARC Dependent Features
 @end ifclear
 
-@set ARC_CORE_DEFAULT 5
+@set ARC_CORE_DEFAULT 6
 
 @cindex ARC support
 @menu
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5178586..0d688e9 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* gas/arc/st.s: Add test case @h30 fixup.
+	* gas/arc/st.d: Update to suit.
+
 2001-05-12  Alan Modra  <amodra@one.net.au>
 
 	* gas/i386/sse2.s: Correct cvtps2dq, movdq2q, and movq2dq
diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d
index 0ed6b80..65ee840 100644
--- a/gas/testsuite/gas/arc/st.d
+++ b/gas/testsuite/gas/arc/st.d
@@ -23,5 +23,11 @@ Disassembly of section .text:
   34:	02 02 01 14 	14010202     st.di      r1,\[r2,2\]
   38:	03 02 01 15 	15010203     st.a.di    r1,\[r2,3\]
   3c:	04 02 81 15 	15810204     stw.a.di   r1,\[r2,4\]
-  40:	00 02 01 12 	12010200     sr         r1,\[r2\]
-  44:	0e 82 1f 12 	121f820e     sr         r1,\[0xe\]
+  40:	04 7c 06 10 	10067c04     st         80,\[r12,4\]
+  44:	50 00 00 00 
+			44: R_ARC_32	.text
+  48:	04 7c 06 10 	10067c04     st         20,\[r12,4\]
+  4c:	14 00 00 00 
+			4c: R_ARC_B26	.text
+  50:	00 02 01 12 	12010200     sr         r1,\[r2\]
+  54:	0e 82 1f 12 	121f820e     sr         r1,\[0xe\]
diff --git a/gas/testsuite/gas/arc/st.s b/gas/testsuite/gas/arc/st.s
index 2754d27..38ba009 100644
--- a/gas/testsuite/gas/arc/st.s
+++ b/gas/testsuite/gas/arc/st.s
@@ -13,6 +13,10 @@
 	st.di	r1,[r2,2]
 	st.a.di	r1,[r2,3]
 	stw.a.di r1,[r2,4]
-	
+
+	st .L1,[r12,4]
+	st .L1@h30,[r12,4]
+.L1:
+
 	sr	r1,[r2]
 	sr	r1,[14]
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ed1b0a8..6736d2b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* arc-opc.c (arc_reg_names): Correct attribute for lp_count
+	register to r/w.  Formatting fixes throughout file.
+
 2001-05-12  Alan Modra  <amodra@one.net.au>
 
 	* i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 8151904..1e5ac1a 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -2,7 +2,7 @@
    Copyright 1994, 1995, 1997, 1998, 2000, 2001
    Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
-   
+
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2, or (at your option)
@@ -382,7 +382,7 @@ const struct arc_operand_value arc_reg_names[] =
   { "r59", 59, REG, 0 },
 
   /* Loop count register (24 bits).  */
-  { "lp_count", 60, REG, ARC_REGISTER_READONLY },
+  { "lp_count", 60, REG, 0 },
   /* Short immediate data indicator setting flags.  */
   { "r61", 61, REG, ARC_REGISTER_READONLY },
   /* Long immediate data indicator setting flags.  */
@@ -694,21 +694,21 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	{
 	  int marker;
 
-          op_type = OP_SHIMM;
-	 /* forget about shimm as dest mlm.  */
+	  op_type = OP_SHIMM;
+	  /* forget about shimm as dest mlm.  */
 
-	  if('a' != operand->fmt)
+	  if ('a' != operand->fmt)
 	    {
 	      shimm_p = 1;
 	      shimm = value;
 	      flagshimm_handled_p = 1;
 	      marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
 	    }
-          else
-            {
+	  else
+	    {
 	      /* don't request flag setting on shimm as dest.  */
 	      marker = ARC_REG_SHIMM;
-            }
+	    }
 	  insn |= marker << operand->shift;
 	  /* insn |= value & 511; - done later.  */
 	}
@@ -736,33 +736,33 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	    *errmsg = "auxiliary register not allowed here";
 	  else
 	    {
-              if((insn & I(-1)) == I(2)) /* check for use validity.  */
-                 {
-		   if(reg->flags & ARC_REGISTER_READONLY)
-		     *errmsg = "attempt to set readonly register";
-                 }
-               else
-                 {
-		   if(reg->flags & ARC_REGISTER_WRITEONLY)
-		     *errmsg = "attempt to read writeonly register";
-                 }
+	      if ((insn & I(-1)) == I(2)) /* check for use validity.  */
+		{
+		  if (reg->flags & ARC_REGISTER_READONLY)
+		    *errmsg = "attempt to set readonly register";
+		}
+	      else
+		{
+		  if (reg->flags & ARC_REGISTER_WRITEONLY)
+		    *errmsg = "attempt to read writeonly register";
+		}
 	      insn |= ARC_REG_SHIMM << operand->shift;
 	      insn |= reg->value << arc_operands[reg->type].shift;
 	    }
 	}
       else
 	{
-      /* check for use validity.  */
-          if('a' == operand->fmt || ((insn & I(-1)) < I(2)))
-            {
-	      if(reg->flags & ARC_REGISTER_READONLY)
+	  /* check for use validity.  */
+	  if ('a' == operand->fmt || ((insn & I(-1)) < I(2)))
+	    {
+	      if (reg->flags & ARC_REGISTER_READONLY)
 		*errmsg = "attempt to set readonly register";
-            }
-          if('a' != operand->fmt)
-            {
-	      if(reg->flags & ARC_REGISTER_WRITEONLY)
+	    }
+	  if ('a' != operand->fmt)
+	    {
+	      if (reg->flags & ARC_REGISTER_WRITEONLY)
 		*errmsg = "attempt to read writeonly register";
-            }
+	    }
 	  /* We should never get an invalid register number here.  */
 	  if ((unsigned int) reg->value > 60)
 	    {
@@ -770,23 +770,23 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	      *errmsg = buf;
 	    }
 	  insn |= reg->value << operand->shift;
-          op_type = OP_REG;
+	  op_type = OP_REG;
 	}
     }
 
   switch (operand->fmt)
     {
     case 'a':
-      ls_operand[LS_DEST] = op_type; 
+      ls_operand[LS_DEST] = op_type;
       break;
     case 's':
-      ls_operand[LS_BASE] = op_type; 
+      ls_operand[LS_BASE] = op_type;
       break;
     case 'c':
       if ((insn & I(-1)) == I(2))
-          ls_operand[LS_VALUE] = op_type; 
+	ls_operand[LS_VALUE] = op_type;
       else
-          ls_operand[LS_OFFSET] = op_type;
+	ls_operand[LS_OFFSET] = op_type;
       break;
     case 'o': case 'O':
       ls_operand[LS_OFFSET] = op_type;
@@ -916,19 +916,19 @@ insert_base (insn, operand, mods, reg, value, errmsg)
       arc_insn myinsn;
       myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift;
       insn |= B(myinsn);
-      ls_operand[LS_BASE] = OP_REG; 
+      ls_operand[LS_BASE] = OP_REG;
     }
   else if (ARC_SHIMM_CONST_P (value) && !cond_p)
     {
       if (shimm_p && value != shimm)
-        {
-          /* convert the previous shimm operand to a limm.  */
-          limm_p = 1;
-          limm = shimm;
-          insn &= ~C(-1); /* we know where the value is in insn.  */
-          insn |= C(ARC_REG_LIMM);
-          ls_operand[LS_VALUE] = OP_LIMM;
-        }
+	{
+	  /* convert the previous shimm operand to a limm.  */
+	  limm_p = 1;
+	  limm = shimm;
+	  insn &= ~C(-1); /* we know where the value is in insn.  */
+	  insn |= C(ARC_REG_LIMM);
+	  ls_operand[LS_VALUE] = OP_LIMM;
+	}
       insn |= ARC_REG_SHIMM << operand->shift;
       shimm_p = 1;
       shimm = value;
@@ -937,10 +937,10 @@ insert_base (insn, operand, mods, reg, value, errmsg)
   else
     {
       if (limm_p && value != limm)
-        {
-          *errmsg = "too many long constants";
-          return insn;
-        }
+	{
+	  *errmsg = "too many long constants";
+	  return insn;
+	}
       limm_p = 1;
       limm = value;
       insn |= B(ARC_REG_LIMM);
@@ -970,8 +970,8 @@ insert_offset (insn, operand, mods, reg, value, errmsg)
       myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
       ls_operand[LS_OFFSET] = OP_REG;
       if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later.  */
-          if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later.  */
-              insn |= C(myinsn);
+	if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later.  */
+	  insn |= C(myinsn);
     }
   else
     {
@@ -989,26 +989,26 @@ insert_offset (insn, operand, mods, reg, value, errmsg)
 	}
       if ((cond_p && !limm_p) || (value < minval || value > maxval))
 	{
-        if (limm_p && value != limm)
-          {
-	    *errmsg = "too many long constants";
-          }
-        else
-          {
-	    limm_p = 1;
-	    limm = value;
-	    if (operand->flags & ARC_OPERAND_STORE)
-	      insn |= B(ARC_REG_LIMM);
-	    if (operand->flags & ARC_OPERAND_LOAD)
-	      insn |= C(ARC_REG_LIMM);
-	    ls_operand[LS_OFFSET] = OP_LIMM;
-          }
+	  if (limm_p && value != limm)
+	    {
+	      *errmsg = "too many long constants";
+	    }
+	  else
+	    {
+	      limm_p = 1;
+	      limm = value;
+	      if (operand->flags & ARC_OPERAND_STORE)
+		insn |= B(ARC_REG_LIMM);
+	      if (operand->flags & ARC_OPERAND_LOAD)
+		insn |= C(ARC_REG_LIMM);
+	      ls_operand[LS_OFFSET] = OP_LIMM;
+	    }
 	}
       else
-        {
+	{
 	  if ((value < minval || value > maxval))
 	    *errmsg = "need too many limms";
-	  else if (shimm_p && value != shimm) 
+	  else if (shimm_p && value != shimm)
 	    {
 	      /* check for bad operand combinations before we lose info about them.  */
 	      if ((insn & I(-1)) == I(1))
@@ -1040,7 +1040,7 @@ insert_offset (insn, operand, mods, reg, value, errmsg)
 	  shimm = value;
 	  shimm_p = 1;
 	  ls_operand[LS_OFFSET] = OP_SHIMM;
-        }
+	}
     }
  out:
   return insn;
@@ -1060,14 +1060,15 @@ extract_st_syntax (insn, operand, mods, opval, invalid)
 ((ls_operand[LS_VALUE]  == (V) && \
   ls_operand[LS_BASE]   == (B) && \
   ls_operand[LS_OFFSET] == (O)))
-  if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE)   && (insn[0] & 511) == 0)
+
+  if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
 	|| ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
 	|| (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
 	|| (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0)
 	|| ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
 	|| ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM)
 	|| ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
-	|| (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE)  && (insn[0] & 511) == 0)
+	|| (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
 	|| ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
 	|| ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
 	|| ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
@@ -1086,13 +1087,13 @@ arc_limm_fixup_adjust(insn)
 
   /* check for st shimm,[limm].  */
   if ((insn & (I(-1) | C(-1) | B(-1))) ==
-     (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
+      (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
     {
       retval = insn & 0x1ff;
       if (retval & 0x100) /* sign extend 9 bit offset.  */
 	retval |= ~0x1ff;
     }
-  return(-retval); /* negate offset for return.  */
+  return -retval; /* negate offset for return.  */
 }
 
 /* Used in st insns to do final syntax check.  */
@@ -1122,27 +1123,27 @@ insert_st_syntax (insn, operand, mods, reg, value, errmsg)
   if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE))
     {
       /* try to salvage this syntax.  */
-    if (shimm & 0x1) /* odd shimms won't work.  */
-      {
-	if (limm_p) /* do we have a limm already?  */
-	  {
-	    *errmsg = "impossible store";
-	  }
-	limm_p = 1;
-	limm = shimm;
-	shimm = 0;
-	shimm_p = 0;
-	insn = insn & ~(B(-1) | 511);
-	insn |= B(ARC_REG_LIMM);
-	ls_operand[LS_BASE] = OP_LIMM;
-      }
-    else
-      {
-	shimm >>= 1;
-	insn = insn & ~511;
-	insn |= shimm;
-	ls_operand[LS_OFFSET] = OP_SHIMM;
-      }
+      if (shimm & 0x1) /* odd shimms won't work.  */
+	{
+	  if (limm_p) /* do we have a limm already?  */
+	    {
+	      *errmsg = "impossible store";
+	    }
+	  limm_p = 1;
+	  limm = shimm;
+	  shimm = 0;
+	  shimm_p = 0;
+	  insn = insn & ~(B(-1) | 511);
+	  insn |= B(ARC_REG_LIMM);
+	  ls_operand[LS_BASE] = OP_LIMM;
+	}
+      else
+	{
+	  shimm >>= 1;
+	  insn = insn & ~511;
+	  insn |= shimm;
+	  ls_operand[LS_OFFSET] = OP_SHIMM;
+	}
     }
   if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
     {
@@ -1166,7 +1167,7 @@ insert_st_syntax (insn, operand, mods, reg, value, errmsg)
 	|| ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
 	|| ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
 	|| ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
-	|| ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) 
+	|| ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE)
 	|| ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
     *errmsg = "st operand error";
   if (addrwb_p)
@@ -1199,19 +1200,19 @@ insert_ld_syntax (insn, operand, mods, reg, value, errmsg)
   int test = insn & I(-1);
 
   if (!(test == I(1)))
-   {
-     if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
-	  || ls_operand[LS_OFFSET] == OP_SHIMM))
-       *errmsg = "invalid load/shimm insn";
-   }
+    {
+      if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
+	   || ls_operand[LS_OFFSET] == OP_SHIMM))
+	*errmsg = "invalid load/shimm insn";
+    }
   if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
 	|| LD_SYNTAX(OP_REG,OP_REG,OP_REG)
 	|| LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
 	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
 	|| (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
-	|| LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) 
+	|| LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
 	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
-      *errmsg = "ld operand error";
+    *errmsg = "ld operand error";
   if (addrwb_p)
     {
       if (ls_operand[LS_BASE] != OP_REG)
@@ -1235,8 +1236,8 @@ extract_ld_syntax (insn, operand, mods, opval, invalid)
 
   if (!(test == I(1)))
     {
-      if((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
-	  || ls_operand[LS_OFFSET] == OP_SHIMM))
+      if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
+	   || ls_operand[LS_OFFSET] == OP_SHIMM))
 	*invalid = 1;
     }
   if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1)))
@@ -1326,8 +1327,8 @@ insert_jumpflags (insn, operand, mods, reg, value, errmsg)
       *errmsg = "bad jump flags value";
     }
   jumpflags_p = 1;
-  limm = (limm & ((1 << operand->shift) - 1))
-    | ((value & ((1 << operand->bits) - 1)) << operand->shift); 
+  limm = ((limm & ((1 << operand->shift) - 1))
+	  | ((value & ((1 << operand->bits) - 1)) << operand->shift));
   return insn;
 }
 
@@ -1397,7 +1398,7 @@ insert_absaddr (insn, operand, mods, reg, value, errmsg)
 	    }
 	  else
 	    {
-	      if(nullify != 0x02)
+	      if (nullify != 0x02)
 		{
 		  *errmsg = "must specify .jd or no nullify suffix";
 		}
@@ -1450,7 +1451,7 @@ extract_reg (insn, operand, mods, opval, invalid)
   if (regno == ARC_REG_SHIMM)
     {
       op_type = OP_SHIMM;
-    /* always return zero if dest is a shimm  mlm.  */
+      /* always return zero if dest is a shimm  mlm.  */
 
       if ('a' != operand->fmt)
 	{
@@ -1492,10 +1493,10 @@ extract_reg (insn, operand, mods, opval, invalid)
       value = insn[1];
       limm_p = 1;
       /* if this is a jump instruction (j,jl), show new pc correctly.  */
-      if(0x07 == ((*insn & I(-1)) >> 27))
-        {
+      if (0x07 == ((*insn & I(-1)) >> 27))
+	{
 	  value = (value & 0xffffff);
-        }
+	}
     }
   /* It's a register, set OPVAL (that's the only way we distinguish registers
      from constants here).  */
@@ -1523,23 +1524,23 @@ extract_reg (insn, operand, mods, opval, invalid)
 	*opval = reg;
     }
   switch(operand->fmt)
-   {
-   case 'a':
-     ls_operand[LS_DEST] = op_type; 
-     break;
-   case 's':
-     ls_operand[LS_BASE] = op_type; 
-     break;
-   case 'c':
-     if((insn[0]& I(-1)) == I(2))
-       ls_operand[LS_VALUE] = op_type; 
-     else
-       ls_operand[LS_OFFSET] = op_type;
-     break;
-   case 'o': case 'O':
-     ls_operand[LS_OFFSET] = op_type;
-     break;
-   }
+    {
+    case 'a':
+      ls_operand[LS_DEST] = op_type;
+      break;
+    case 's':
+      ls_operand[LS_BASE] = op_type;
+      break;
+    case 'c':
+      if ((insn[0]& I(-1)) == I(2))
+	ls_operand[LS_VALUE] = op_type;
+      else
+	ls_operand[LS_OFFSET] = op_type;
+      break;
+    case 'o': case 'O':
+      ls_operand[LS_OFFSET] = op_type;
+      break;
+    }
 
   return value;
 }
@@ -1633,8 +1634,8 @@ extract_jumpflags(insn, operand, mods, opval, invalid)
 {
   if (!flag_p || !limm_p)
     *invalid = 1;
-  return((flag_p && limm_p)
-         ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
+  return ((flag_p && limm_p)
+	  ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
 }
 
 /* extract st insn's offset.  */
@@ -1654,7 +1655,7 @@ extract_st_offset (insn, operand, mods, opval, invalid)
       value = insn[0] & 511;
       if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
 	value -= 512;
-      if(value)
+      if (value)
 	ls_operand[LS_OFFSET] = OP_SHIMM;
     }
   else
@@ -1686,9 +1687,9 @@ extract_ld_offset (insn, operand, mods, opval, invalid)
 	ls_operand[LS_OFFSET] = OP_SHIMM;
       return(value);
     }
-/* if it isn't in the insn, it's concealed behind reg 'c'.  */
-  return extract_reg(insn,
-                     &arc_operands[arc_operand_map['c']], mods, opval, invalid);
+  /* if it isn't in the insn, it's concealed behind reg 'c'.  */
+  return extract_reg (insn, &arc_operands[arc_operand_map['c']],
+		      mods, opval, invalid);
 }
 
 /* The only thing this does is set the `invalid' flag if B != C.
@@ -1779,8 +1780,8 @@ int
 arc_insn_not_jl(insn)
   arc_insn insn;
 {
-  return (insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) !=
-    (I(0x7) | R(-1,9,1));
+  return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
+	  != (I(0x7) | R(-1,9,1)));
 }
 
 int
@@ -1814,11 +1815,11 @@ get_ext_suffix(s)
 	return(&suffix->operand);
       suffix = suffix->next;
     }
-  return(NULL);
+  return NULL;
 }
 
 int
 arc_get_noshortcut_flag()
 {
-  return(ARC_REGISTER_NOSHORT_CUT);
+  return ARC_REGISTER_NOSHORT_CUT;
 }