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| author | Ramana Radhakrishnan <ramana.r@gmail.com> | 2013-10-15 13:30:40 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana.r@gmail.com> | 2013-10-15 13:30:40 +0000 |
| commit | 85181173183083283b896dc5adbfa318506d9fe4 (patch) | |
| tree | afc37ae7b349cdd2717f02282e2e304bb06862c9 | |
| parent | 02fb2970366197c8726943b89f164fc604284d66 (diff) | |
| download | gdb-85181173183083283b896dc5adbfa318506d9fe4.zip gdb-85181173183083283b896dc5adbfa318506d9fe4.tar.gz gdb-85181173183083283b896dc5adbfa318506d9fe4.tar.bz2 | |
Fix neon vshll disassembly.
opcodes/
2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* arm-dis.c (neon_opcodes): Adjust print string for vshll.
gas/testsuite/
2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/arm/neon-cov.d: Adjust output.
| -rw-r--r-- | gas/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/neon-cov.d | 12 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 6 |
4 files changed, 17 insertions, 9 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 782d30d..7116862 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * gas/arm/neon-cov.d: Adjust output. + 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> * gas/mips/micromips@msa-relax.d, gas/mips/micromips@msa.d, diff --git a/gas/testsuite/gas/arm/neon-cov.d b/gas/testsuite/gas/arm/neon-cov.d index e3f02f8..3d7a488 100644 --- a/gas/testsuite/gas/arm/neon-cov.d +++ b/gas/testsuite/gas/arm/neon-cov.d @@ -1106,12 +1106,12 @@ Disassembly of section \.text: 0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 0[0-9a-f]+ <[^>]+> f2a10850 vrshrn\.i64 d0, q0, #31 -0[0-9a-f]+ <[^>]+> f2890a10 vshll\.s8 d0, q0, #1 -0[0-9a-f]+ <[^>]+> f2910a10 vshll\.s16 d0, q0, #1 -0[0-9a-f]+ <[^>]+> f2a10a10 vshll\.s32 d0, q0, #1 -0[0-9a-f]+ <[^>]+> f3890a10 vshll\.u8 d0, q0, #1 -0[0-9a-f]+ <[^>]+> f3910a10 vshll\.u16 d0, q0, #1 -0[0-9a-f]+ <[^>]+> f3a10a10 vshll\.u32 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f2890a10 vshll\.s8 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f2910a10 vshll\.s16 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f2a10a10 vshll\.s32 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f3890a10 vshll\.u8 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f3910a10 vshll\.u16 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f3a10a10 vshll\.u32 q0, d0, #1 0[0-9a-f]+ <[^>]+> f3b20300 vshll\.i8 q0, d0, #8 0[0-9a-f]+ <[^>]+> f3b60300 vshll\.i16 q0, d0, #16 0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 97a9d0d..bc42de4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * arm-dis.c (neon_opcodes): Adjust print string for vshll. + 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W, diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 18a553b..fd11d11 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -711,7 +711,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, @@ -722,7 +722,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, @@ -734,7 +734,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, |