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| author | Yao Qi <yao.qi@linaro.org> | 2016-04-22 15:53:05 +0100 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2016-04-22 15:54:43 +0100 |
| commit | 3539aa13fbcadd930b0b6d8a97f9f125f02a73dc (patch) | |
| tree | 6518aa835631d8c4a65391b9f2d1f3ff2290f125 | |
| parent | 495346f6f07ea711662106f0e6f8d684fe489cd8 (diff) | |
| download | gdb-3539aa13fbcadd930b0b6d8a97f9f125f02a73dc.zip gdb-3539aa13fbcadd930b0b6d8a97f9f125f02a73dc.tar.gz gdb-3539aa13fbcadd930b0b6d8a97f9f125f02a73dc.tar.bz2 | |
[ARM] Clear reserved bits in CPSR
Bits 20 ~ 23 of CPSR are reserved (RAZ, read as zero), but they are not
zero if the arm program runs on aarch64-linux. AArch64 tracer gets PSTATE
from arm 32-bit tracee as CPSR, but bits 20 ~ 23 are used in PSTATE. I
think kernel should clear these bits when it is read through ptrace, but
the fix in user space is still needed.
This patch fixes these two fails,
-FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr d7, [r11, #-12]
-FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr d7, [r7]
gdb:
2016-04-22 Yao Qi <yao.qi@linaro.org>
* aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR
bits 20 to 23.
gdb/gdbserver:
2016-04-22 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20
to 23.
| -rw-r--r-- | gdb/ChangeLog | 5 | ||||
| -rw-r--r-- | gdb/aarch32-linux-nat.c | 6 | ||||
| -rw-r--r-- | gdb/gdbserver/ChangeLog | 5 | ||||
| -rw-r--r-- | gdb/gdbserver/linux-aarch32-low.c | 5 |
4 files changed, 19 insertions, 2 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 8b6a7da..e9321db 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2016-04-22 Yao Qi <yao.qi@linaro.org> + + * aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR + bits 20 to 23. + 2016-04-22 Joel Brobecker <brobecker@adacore.com> * MAINTAINER: Remove myself as AIX Maintainer. diff --git a/gdb/aarch32-linux-nat.c b/gdb/aarch32-linux-nat.c index 568dfa6..72bf644 100644 --- a/gdb/aarch32-linux-nat.c +++ b/gdb/aarch32-linux-nat.c @@ -37,7 +37,11 @@ aarch32_gp_regcache_supply (struct regcache *regcache, uint32_t *regs, regcache_raw_supply (regcache, regno, ®s[regno]); if (arm_apcs_32) - regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + { + /* Clear reserved bits bit 20 to bit 23. */ + regs[ARM_CPSR_GREGNUM] &= 0xff0fffff; + regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + } else regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_PC_REGNUM]); diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog index e0ed616..a7ffbf8 100644 --- a/gdb/gdbserver/ChangeLog +++ b/gdb/gdbserver/ChangeLog @@ -1,5 +1,10 @@ 2016-04-22 Yao Qi <yao.qi@linaro.org> + * linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20 + to 23. + +2016-04-22 Yao Qi <yao.qi@linaro.org> + * linux-low.c (lwp_signal_can_be_delivered): Don't deliver signal when stepping over breakpoint with software single step. diff --git a/gdb/gdbserver/linux-aarch32-low.c b/gdb/gdbserver/linux-aarch32-low.c index 0c4b140..e6971d5 100644 --- a/gdb/gdbserver/linux-aarch32-low.c +++ b/gdb/gdbserver/linux-aarch32-low.c @@ -77,6 +77,7 @@ arm_store_gregset (struct regcache *regcache, const void *buf) int i; char zerobuf[8]; const uint32_t *regs = (const uint32_t *) buf; + uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; memset (zerobuf, 0, 8); for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++) @@ -85,7 +86,9 @@ arm_store_gregset (struct regcache *regcache, const void *buf) for (; i < ARM_PS_REGNUM; i++) supply_register (regcache, i, zerobuf); - supply_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + /* Clear reserved bits bit 20 to bit 23. */ + cpsr &= 0xff0fffff; + supply_register (regcache, ARM_PS_REGNUM, &cpsr); } /* Collect NUM number of VFP registers from REGCACHE to buffer BUF. */ |