gas/

	* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
	instructions to loose any special insn->architecture mask.

	* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
	(sparc_md_end, sparc_arch_types, sparc_arch,
	sparc_elf_final_processing): Handle v8plusb and v9b architectures.
	(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
	request v9b architecture if they are used).

bfd/
	* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
	elf32_sparc_object_p, elf32_sparc_final_write_processing):
	Support v8plusb.
	* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
	sparc64_elf_object_p): Support v9b.
	* archures.c: Declare v8plusb and v9b machines.
	* bfd-in2.h: Ditto.
	* cpu-sparc.c: Ditto.

include/opcode/
	* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
	Note that '3' is used for siam operand.

opcodes/
	* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
	(compute_arch_mask): Add v8plusb and v9b machines.
	(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
	* opcodes/sparc-opc.c: Support for Cheetah instruction set.
	(prefetch_table): Add #invalidate.

13 files changed, 215 insertions, 95 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index c11b809..51a601f 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,14 @@
+2000-10-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
+	elf32_sparc_object_p, elf32_sparc_final_write_processing):
+	Support v8plusb.
+	* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
+	sparc64_elf_object_p): Support v9b.
+	* archures.c: Declare v8plusb and v9b machines.
+	* bfd-in2.h: Ditto.
+	* cpu-sparc.c: Ditto.
+
 2000-10-16  Geoffrey Keating  <geoffk@shoggoth.cygnus.com>
 
 	* elf64-sparc.c (sparc64_elf_relocate_section): Clear the location
diff --git a/bfd/archures.c b/bfd/archures.c
index 70fa086..5729217 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -109,9 +109,12 @@ DESCRIPTION
 .#define bfd_mach_sparc_sparclite_le	6
 .#define bfd_mach_sparc_v9		7
 .#define bfd_mach_sparc_v9a		8 {* with ultrasparc add'ns *}
+.#define bfd_mach_sparc_v8plusb		9 {* with cheetah add'ns *}
+.#define bfd_mach_sparc_v9b		10 {* with cheetah add'ns *}
 .{* Nonzero if MACH has the v9 instruction set.  *}
 .#define bfd_mach_sparc_v9_p(mach) \
-.  ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a)
+.  ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
+.   && (mach) != bfd_mach_sparc_sparclite_le)
 .  bfd_arch_mips,      {* MIPS Rxxxx *}
 .#define bfd_mach_mips3000		3000
 .#define bfd_mach_mips3900		3900
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 64238ac..55c2dba 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1379,9 +1379,12 @@ enum bfd_architecture
 #define bfd_mach_sparc_sparclite_le    6
 #define bfd_mach_sparc_v9              7
 #define bfd_mach_sparc_v9a             8 /* with ultrasparc add'ns */
+#define bfd_mach_sparc_v8plusb         9 /* with cheetah add'ns */
+#define bfd_mach_sparc_v9b             10 /* with cheetah add'ns */
 /* Nonzero if MACH has the v9 instruction set.  */
 #define bfd_mach_sparc_v9_p(mach) \
-  ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a)
+  ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a \
+   && (mach) != bfd_mach_sparc_sparclite_le)
   bfd_arch_mips,      /* MIPS Rxxxx */
 #define bfd_mach_mips3000              3000
 #define bfd_mach_mips3900              3900
diff --git a/bfd/cpu-sparc.c b/bfd/cpu-sparc.c
index 234bd92..57ccc2e 100644
--- a/bfd/cpu-sparc.c
+++ b/bfd/cpu-sparc.c
@@ -1,5 +1,5 @@
 /* BFD support for the SPARC architecture.
-   Copyright (C) 1992, 94, 95, 96, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1992, 94, 95, 96, 97, 2000 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
@@ -135,6 +135,34 @@ static const bfd_arch_info_type arch_info_struct[] =
     false,
     sparc_compatible, 
     bfd_default_scan,
+    &arch_info_struct[7],
+  },
+  {
+    32,	/* bits in a word */
+    32,	/* bits in an address */
+    8,	/* bits in a byte */
+    bfd_arch_sparc,
+    bfd_mach_sparc_v8plusb,
+    "sparc",
+    "sparc:v8plusb",
+    3,
+    false,
+    sparc_compatible, 
+    bfd_default_scan,
+    &arch_info_struct[8],
+  },
+  {
+    64,	/* bits in a word */
+    64,	/* bits in an address */
+    8,	/* bits in a byte */
+    bfd_arch_sparc,
+    bfd_mach_sparc_v9b,
+    "sparc",
+    "sparc:v9b",
+    3,
+    false,
+    sparc_compatible, 
+    bfd_default_scan,
     0,
   }
 };
diff --git a/bfd/elf32-sparc.c b/bfd/elf32-sparc.c
index 1dd0351..11ac539 100644
--- a/bfd/elf32-sparc.c
+++ b/bfd/elf32-sparc.c
@@ -1959,33 +1959,6 @@ elf32_sparc_merge_private_bfd_data (ibfd, obfd)
 
   error = false;
 
-#if 0
-  /* ??? The native linker doesn't do this so we can't (otherwise gcc would
-     have to know which linker is being used).  Instead, the native linker
-     bumps up the architecture level when it has to.  However, I still think
-     warnings like these are good, so it would be nice to have them turned on
-     by some option.  */
-
-  /* If the output machine is normal sparc, we can't allow v9 input files.  */
-  if (bfd_get_mach (obfd) == bfd_mach_sparc
-      && (bfd_get_mach (ibfd) == bfd_mach_sparc_v8plus
-	  || bfd_get_mach (ibfd) == bfd_mach_sparc_v8plusa))
-    {
-      error = true;
-      (*_bfd_error_handler)
-	(_("%s: compiled for a v8plus system and target is v8"),
-	 bfd_get_filename (ibfd));
-    }
-  /* If the output machine is v9, we can't allow v9+vis input files.  */
-  if (bfd_get_mach (obfd) == bfd_mach_sparc_v8plus
-      && bfd_get_mach (ibfd) == bfd_mach_sparc_v8plusa)
-    {
-      error = true;
-      (*_bfd_error_handler)
-	(_("%s: compiled for a v8plusa system and target is v8plus"),
-	 bfd_get_filename (ibfd));
-    }
-#else
   if (bfd_get_mach (ibfd) >= bfd_mach_sparc_v9)
     {
       error = true;
@@ -1998,7 +1971,6 @@ elf32_sparc_merge_private_bfd_data (ibfd, obfd)
       if (bfd_get_mach (obfd) < bfd_get_mach (ibfd))
 	bfd_set_arch_mach (obfd, bfd_arch_sparc, bfd_get_mach (ibfd));
     }
-#endif
 
   if (((elf_elfheader (ibfd)->e_flags & EF_SPARC_LEDATA)
        != previous_ibfd_e_flags)
@@ -2028,7 +2000,10 @@ elf32_sparc_object_p (abfd)
 {
   if (elf_elfheader (abfd)->e_machine == EM_SPARC32PLUS)
     {
-      if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US1)
+      if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
+	return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
+					  bfd_mach_sparc_v8plusb);
+      else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US1)
 	return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
 					  bfd_mach_sparc_v8plusa);
       else if (elf_elfheader (abfd)->e_flags & EF_SPARC_32PLUS)
@@ -2066,6 +2041,12 @@ elf32_sparc_final_write_processing (abfd, linker)
       elf_elfheader (abfd)->e_flags &=~ EF_SPARC_32PLUS_MASK;
       elf_elfheader (abfd)->e_flags |= EF_SPARC_32PLUS | EF_SPARC_SUN_US1;
       break;
+    case bfd_mach_sparc_v8plusb :
+      elf_elfheader (abfd)->e_machine = EM_SPARC32PLUS;
+      elf_elfheader (abfd)->e_flags &=~ EF_SPARC_32PLUS_MASK;
+      elf_elfheader (abfd)->e_flags |= EF_SPARC_32PLUS | EF_SPARC_SUN_US1
+				       | EF_SPARC_SUN_US3;
+      break;
     case bfd_mach_sparc_sparclite_le :
       elf_elfheader (abfd)->e_machine = EM_SPARC;
       elf_elfheader (abfd)->e_flags |= EF_SPARC_LEDATA;
diff --git a/bfd/elf64-sparc.c b/bfd/elf64-sparc.c
index 2efe034..e63bc3b 100644
--- a/bfd/elf64-sparc.c
+++ b/bfd/elf64-sparc.c
@@ -2929,25 +2929,26 @@ sparc64_elf_merge_private_bfd_data (ibfd, obfd)
   else                                  /* Incompatible flags */
     {
       error = false;
-  
+
+#define EF_SPARC_ISA_EXTENSIONS \
+  (EF_SPARC_SUN_US1 | EF_SPARC_SUN_US3 | EF_SPARC_HAL_R1)
+
       if ((ibfd->flags & DYNAMIC) != 0)
 	{
 	  /* We don't want dynamic objects memory ordering and
 	     architecture to have any role. That's what dynamic linker
 	     should do.  */
-	  new_flags &= ~(EF_SPARCV9_MM | EF_SPARC_SUN_US1 | EF_SPARC_HAL_R1);
+	  new_flags &= ~(EF_SPARCV9_MM | EF_SPARC_ISA_EXTENSIONS);
 	  new_flags |= (old_flags
-			& (EF_SPARCV9_MM
-			   | EF_SPARC_SUN_US1
-			   | EF_SPARC_HAL_R1));
+			& (EF_SPARCV9_MM | EF_SPARC_ISA_EXTENSIONS));
 	}
       else
 	{
 	  /* Choose the highest architecture requirements.  */
-	  old_flags |= (new_flags & (EF_SPARC_SUN_US1 | EF_SPARC_HAL_R1));
-	  new_flags |= (old_flags & (EF_SPARC_SUN_US1 | EF_SPARC_HAL_R1));
-	  if ((old_flags & (EF_SPARC_SUN_US1 | EF_SPARC_HAL_R1))
-	      == (EF_SPARC_SUN_US1 | EF_SPARC_HAL_R1))
+	  old_flags |= (new_flags & EF_SPARC_ISA_EXTENSIONS);
+	  new_flags |= (old_flags & EF_SPARC_ISA_EXTENSIONS);
+	  if ((old_flags & (EF_SPARC_SUN_US1 | EF_SPARC_SUN_US3))
+	      && (old_flags & EF_SPARC_HAL_R1))
 	    {
 	      error = true;
 	      (*_bfd_error_handler)
@@ -3020,8 +3021,10 @@ sparc64_elf_object_p (abfd)
      bfd *abfd;
 {
   unsigned long mach = bfd_mach_sparc_v9;
-  
-  if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US1)
+
+  if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
+    mach = bfd_mach_sparc_v9b;
+  else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US1)
     mach = bfd_mach_sparc_v9a;
   return bfd_default_set_arch_mach (abfd, bfd_arch_sparc, mach);
 }
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d4a67d4..1187bb2 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,14 @@
+2000-10-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
+	instructions to loose any special insn->architecture mask.
+
+	* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
+	(sparc_md_end, sparc_arch_types, sparc_arch,
+	sparc_elf_final_processing): Handle v8plusb and v9b architectures.
+	(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
+	request v9b architecture if they are used).
+
 2000-10-18  Michael Sokolov  <msokolov@ivan.Harhan.ORG>
 
 	* config/tc-m68k.c: Fix the previous misapplied patch.
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 64d74ef..7b577b1 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -217,7 +217,7 @@ static void output_insn
    and file formats.  */
 
 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
-		       v8plusa, v9, v9a, v9_64};
+		       v8plusa, v9, v9a, v9b, v9_64};
 
 static struct sparc_arch {
   char *name;
@@ -237,8 +237,10 @@ static struct sparc_arch {
   { "sparc86x", "sparclite", sparc86x, 32, 1 },
   { "v8plus", "v9", v9, 0, 1 },
   { "v8plusa", "v9a", v9, 0, 1 },
+  { "v8plusb", "v9b", v9, 0, 1 },
   { "v9", "v9", v9, 0, 1 },
   { "v9a", "v9a", v9, 0, 1 },
+  { "v9b", "v9b", v9, 0, 1 },
   /* This exists to allow configure.in/Makefile.in to pass one
      value to specify both the default machine and default word size.  */
   { "v9-64", "v9", v9, 64, 0 },
@@ -337,19 +339,20 @@ sparc_target_format ()
  *
  *	-Av6, -Av7, -Av8, -Asparclite, -Asparclet
  *		Standard 32 bit architectures.
- *	-Av9, -Av9a
+ *	-Av9, -Av9a, -Av9b
  *		Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
  *		This used to only mean 64 bits, but properly specifying it
  *		complicated gcc's ASM_SPECs, so now opcode selection is
  *		specified orthogonally to word size (except when specifying
  *		the default, but that is an internal implementation detail).
- *	-Av8plus, -Av8plusa
- *		Same as -Av9{,a}.
- *	-xarch=v8plus, -xarch=v8plusa
- *		Same as -Av8plus{,a} -32, for compatibility with Sun's
+ *	-Av8plus, -Av8plusa, -Av8plusb
+ *		Same as -Av9{,a,b}.
+ *	-xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
+ *		Same as -Av8plus{,a,b} -32, for compatibility with Sun's
+ *		assembler.
+ *	-xarch=v9, -xarch=v9a, -xarch=v9b
+ *		Same as -Av9{,a,b} -64, for compatibility with Sun's
  *		assembler.
- *	-xarch=v9, -xarch=v9a
- *		Same as -Av9{,a} -64, for compatibility with Sun's assembler.
  *
  *		Select the architecture and possibly the file format.
  *		Instructions or features not supported by the selected
@@ -358,7 +361,7 @@ sparc_target_format ()
  *		The default is to start at v6, and bump the architecture up
  *		whenever an instruction is seen at a higher level.  In 32 bit
  *		environments, v9 is not bumped up to, the user must pass
- * 		-Av8plus{,a}.
+ * 		-Av8plus{,a,b}.
  *
  *		If -bump is specified, a warning is printing when bumping to
  *		higher levels.
@@ -745,6 +748,8 @@ struct priv_reg_entry priv_reg_table[] =
 struct priv_reg_entry v9a_asr_table[] =
 {
   {"tick_cmpr", 23},
+  {"sys_tick_cmpr", 25},
+  {"sys_tick", 24},
   {"softint", 22},
   {"set_softint", 20},
   {"pic", 17},
@@ -870,31 +875,28 @@ md_begin ()
 void
 sparc_md_end ()
 {
+  unsigned long mach = bfd_mach_sparc;
+
   if (sparc_arch_size == 64)
-    {
-      if (current_architecture == SPARC_OPCODE_ARCH_V9A)
-	bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
-      else
-	bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
-    }
+    switch (current_architecture)
+      {
+      case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
+      case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
+      default: mach = bfd_mach_sparc_v9; break;
+      }
   else
-    {
-      if (current_architecture == SPARC_OPCODE_ARCH_V9)
-	bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
-      else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
-	bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
-      else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
-	bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
-      else if (default_arch_type == sparc86x && target_little_endian_data)
-	bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
-      else
-	{
-	  /* The sparclite is treated like a normal sparc.  Perhaps it
-	     shouldn't be but for now it is (since that's the way it's
-	     always been treated).  */
-	  bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
-	}
-    }
+    switch (current_architecture)
+      {
+      case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
+      case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
+      case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
+      case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
+      /* The sparclite is treated like a normal sparc.  Perhaps it shouldn't
+	 be but for now it is (since that's the way it's always been
+	 treated).  */
+      default: break;
+      }
+  bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
 }
 
 /* Return non-zero if VAL is in the range -(MAX+1) to MAX.  */
@@ -1472,6 +1474,24 @@ sparc_ip (str, pinsn)
 		continue;
 	      }
 
+	    case '3':
+	      {
+		int smask = 0;
+
+		if (! parse_const_expr_arg (&s, &smask))
+		  {
+		    error_message = _(": invalid siam mode expression");
+		    goto error;
+		  }
+		if (smask < 0 || smask > 7)
+		  {
+		    error_message = _(": invalid siam mode number");
+		    goto error;
+		  }
+		opcode |= smask;
+		continue;
+	      }
+
 	    case '*':
 	      {
 		int fcn = 0;
@@ -1540,7 +1560,7 @@ sparc_ip (str, pinsn)
 
 	    case '_':
 	    case '/':
-	      /* Parse a v9a ancillary state register.  */
+	      /* Parse a v9a/v9b ancillary state register.  */
 	      if (*s == '%')
 		{
 		  struct priv_reg_entry *p = v9a_asr_table;
@@ -1558,7 +1578,7 @@ sparc_ip (str, pinsn)
 		    }
 		  if (p->name[0] != s[0])
 		    {
-		      error_message = _(": unrecognizable v9a ancillary state register");
+		      error_message = _(": unrecognizable v9a or v9b ancillary state register");
 		      goto error;
 		    }
 		  if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
@@ -1566,6 +1586,14 @@ sparc_ip (str, pinsn)
 		      error_message = _(": rd on write only ancillary state register");
 		      goto error;
 		    }
+		  if (p->regnum >= 24
+		      && (insn->architecture
+			  & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
+		    {
+		      /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
+		      error_message = _(": unrecognizable v9a ancillary state register");
+		      goto error;
+		    }
 		  if (*args == '/')
 		    opcode |= (p->regnum << 14);
 		  else
@@ -1575,7 +1603,7 @@ sparc_ip (str, pinsn)
 		}
 	      else
 		{
-		  error_message = _(": unrecognizable v9a ancillary state register");
+		  error_message = _(": unrecognizable v9a or v9b ancillary state register");
 		  goto error;
 		}
 
@@ -2541,9 +2569,11 @@ sparc_ip (str, pinsn)
 
 	  if (v9_arg_p)
 	    {
-	      needed_arch_mask &= ~((1 << SPARC_OPCODE_ARCH_V9)
-				    | (1 << SPARC_OPCODE_ARCH_V9A));
-	      needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
+	      needed_arch_mask &=
+		~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
+	      if (! needed_arch_mask)
+		needed_arch_mask =
+		  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
 	    }
 
 	  if (needed_arch_mask
@@ -4124,6 +4154,8 @@ sparc_elf_final_processing ()
     elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
   if (current_architecture == SPARC_OPCODE_ARCH_V9A)
     elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
+  else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
+    elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
 }
 #endif
 
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 60b910d..32e2baf 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2000-10-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
+	Note that '3' is used for siam operand.
+
 2000-09-22  Jim Wilson  <wilson@cygnus.com>
 
 	* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 4f159bd..423cea7 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -1,5 +1,5 @@
 /* Definitions for opcode table for the sparc.
-   Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997
+   Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 2000
    Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
@@ -46,6 +46,7 @@ enum sparc_opcode_arch_val {
   /* v9 variants must appear last */
   SPARC_OPCODE_ARCH_V9,
   SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
+  SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
   SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
 };
 
@@ -141,6 +142,7 @@ Kinds of operands:
 	h	22 high bits.
 	X	5 bit unsigned immediate
 	Y	6 bit unsigned immediate
+	3	SIAM mode (3 bits). (v9b)
 	K	MEMBAR mask (7 bits). (v9)
 	j	10 bit Immediate. (v9)
 	I	11 bit Immediate. (v9)
@@ -187,7 +189,7 @@ Kinds of operands:
 	/	Ancillary state register in rs1 (v9a)
 
 The following chars are unused: (note: ,[] are used as punctuation)
-[345]
+[45]
 
 */
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5480774..fbf3062 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2000-10-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
+	(compute_arch_mask): Add v8plusb and v9b machines.
+	(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
+	* opcodes/sparc-opc.c: Support for Cheetah instruction set.
+	(prefetch_table): Add #invalidate.
+
 2000-10-16  Nick Clifton  <nickc@redhat.com>
 
 	* mcore-dis.c (imsk): Change mask for OC to 0xFE00.
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index a595d0f..cebff52 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -1,5 +1,5 @@
 /* Print SPARC instructions.
-   Copyright (C) 1989, 91-97, 1998 Free Software Foundation, Inc.
+   Copyright (C) 1989, 91-97, 1998, 2000 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -25,7 +25,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 /* Bitmask of v9 architectures.  */
 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
-		 | (1 << SPARC_OPCODE_ARCH_V9A))
+		 | (1 << SPARC_OPCODE_ARCH_V9A) \
+		 | (1 << SPARC_OPCODE_ARCH_V9B))
 /* 1 if INSN is for v9 only.  */
 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
 /* 1 if INSN is for v9.  */
@@ -95,7 +96,7 @@ static char *v9_priv_reg_names[] =
 static char *v9a_asr_reg_names[] =
 {
   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
-  "softint", "tick_cmpr"
+  "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
 };
 
 /* Macros used to extract instruction fields.  Not all fields have
@@ -463,6 +464,10 @@ print_insn_sparc (memaddr, info)
 		    }
 		    break;
 
+		  case '3':
+		    (info->fprintf_func) (stream, "%d", X_IMM (insn, 3));
+		    break;
+
 		  case 'K':
 		    {
 		      int mask = X_MEMBAR (insn);
@@ -551,7 +556,7 @@ print_insn_sparc (memaddr, info)
 		    break;
 
 		  case '/':
-		    if (X_RS1 (insn) < 16 || X_RS1 (insn) > 23)
+		    if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
 		      (*info->fprintf_func) (stream, "%%reserved");
 		    else
 		      (*info->fprintf_func) (stream, "%%%s",
@@ -559,7 +564,7 @@ print_insn_sparc (memaddr, info)
 		    break;
 
 		  case '_':
-		    if (X_RD (insn) < 16 || X_RD (insn) > 23)
+		    if (X_RD (insn) < 16 || X_RD (insn) > 25)
 		      (*info->fprintf_func) (stream, "%%reserved");
 		    else
 		      (*info->fprintf_func) (stream, "%%%s",
@@ -770,6 +775,9 @@ compute_arch_mask (mach)
     case bfd_mach_sparc_v8plusa :
     case bfd_mach_sparc_v9a :
       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
+    case bfd_mach_sparc_v8plusb :
+    case bfd_mach_sparc_v9b :
+      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
     }
   abort ();
 }
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 0d044e0..2e20d2e 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1,5 +1,5 @@
 /* Table of opcodes for the sparc.
-   Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999
+   Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
    Free Software Foundation, Inc.
 
 This file is part of the BFD library.
@@ -35,27 +35,30 @@ Boston, MA 02111-1307, USA.	*/
 #define MASK_SPARCLITE	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
 #define MASK_V9		SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
 #define MASK_V9A	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
+#define MASK_V9B	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
 
 /* Bit masks of architectures supporting the insn.  */
 
 #define v6		(MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
-			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
+			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
 /* v6 insns not supported on the sparclet */
 #define v6notlet	(MASK_V6 | MASK_V7 | MASK_V8 \
-			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
+			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
 #define v7		(MASK_V7 | MASK_V8 | MASK_SPARCLET \
-			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
+			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
 /* Although not all insns are implemented in hardware, sparclite is defined
    to be a superset of v8.  Unimplemented insns trap and are then theoretically
    implemented in software.
    It's not clear that the same is true for sparclet, although the docs
    suggest it is.  Rather than complicating things, the sparclet assembler
    recognizes all v8 insns.  */
-#define v8		(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
+#define v8		(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
+			 | MASK_V9 | MASK_V9A | MASK_V9B)
 #define sparclet	(MASK_SPARCLET)
 #define sparclite	(MASK_SPARCLITE)
-#define v9		(MASK_V9 | MASK_V9A)
-#define v9a		(MASK_V9A)
+#define v9		(MASK_V9 | MASK_V9A | MASK_V9B)
+#define v9a		(MASK_V9A | MASK_V9B)
+#define v9b		(MASK_V9B)
 /* v6 insns not supported by v9 */
 #define v6notv9		(MASK_V6 | MASK_V7 | MASK_V8 \
 			 | MASK_SPARCLET | MASK_SPARCLITE)
@@ -76,6 +79,8 @@ const struct sparc_opcode_arch sparc_opcode_archs[] = {
   { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
   /* v9 with ultrasparc additions */
   { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
+  /* v9 with cheetah additions */
+  { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
   { NULL, 0 }
 };
 
@@ -843,6 +848,10 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "wr", F3(2, 0x30, 1)|RD(22),	F3(~2, ~0x30, ~1)|RD(~22),		"1,i,_", 0, v9a }, /* wr r,i,%softint */
 { "wr", F3(2, 0x30, 0)|RD(23),	F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0),	"1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
 { "wr", F3(2, 0x30, 1)|RD(23),	F3(~2, ~0x30, ~1)|RD(~23),		"1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
+{ "wr", F3(2, 0x30, 0)|RD(24),	F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0),	"1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
+{ "wr", F3(2, 0x30, 1)|RD(24),	F3(~2, ~0x30, ~1)|RD(~24),		"1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
+{ "wr", F3(2, 0x30, 0)|RD(25),	F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0),	"1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
+{ "wr", F3(2, 0x30, 1)|RD(25),	F3(~2, ~0x30, ~1)|RD(~25),		"1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
 
 { "rd",	F3(2, 0x28, 0),			F3(~2, ~0x28, ~0)|SIMM13(~0),		"M,d", 0, v8 }, /* rd %asrX,r */
 { "rd",	F3(2, 0x28, 0),			F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),	"y,d", 0, v6 }, /* rd %y,r */
@@ -862,6 +871,8 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "rd",	F3(2, 0x28, 0)|RS1(19),		F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),	"/,d", 0, v9a }, /* rd %gsr,r */
 { "rd",	F3(2, 0x28, 0)|RS1(22),		F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),	"/,d", 0, v9a }, /* rd %softint,r */
 { "rd",	F3(2, 0x28, 0)|RS1(23),		F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),	"/,d", 0, v9a }, /* rd %tick_cmpr,r */
+{ "rd",	F3(2, 0x28, 0)|RS1(24),		F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),	"/,d", 0, v9b }, /* rd %sys_tick,r */
+{ "rd",	F3(2, 0x28, 0)|RS1(25),		F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),	"/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
 
 { "rdpr",	F3(2, 0x2a, 0),		F3(~2, ~0x2a, ~0)|SIMM13(~0),	"?,d", 0, v9 },   /* rdpr %priv,r */
 { "wrpr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0),		"1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
@@ -1814,6 +1825,19 @@ SLCBCC("cbnefr", 15),
 { "array16",	F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
 { "array32",	F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
 
+/* Cheetah instructions */
+{ "edge8n",    F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
+{ "edge8ln",   F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
+{ "edge16n",   F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
+{ "edge16ln",  F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
+{ "edge32n",   F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
+{ "edge32ln",  F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
+
+{ "bmask",     F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
+{ "bshuffle",  F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
+
+{ "siam",      F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
+
 /* More v9 specific insns, these need to come last so they do not clash
    with v9a instructions such as "edge8" which looks like impdep1. */
 
@@ -1976,6 +2000,7 @@ static arg prefetch_table[] =
   { 2, "#n_writes" },
   { 3, "#one_write" },
   { 4, "#page" },
+  { 16, "#invalidate" },
   { 0, 0 }
 };