Range of element index is too large on MIPS MSA element selection instructions.

The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large.  This patch fixes this issue.

ChangeLog:

	gas/testsuite/gas/mips/
	* msa.s: Reduced maximum element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.
	* msa64.s: Likewise.
	* micromips@msa.d: Likewise.
	* micromips@msa64.d: Likewise.
	* msa.d: Likewise.
	* msa64.d: Likewise.

	include/opcode/
	* mips.h: Updated description of +o, +u, +v and +w for MIPS and
	microMIPS.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
	+v and +w.
	(micromips_opcodes): Reduced element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.
	* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
	+v and +w.
	(mips_builtin_opcodes): Reduced element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.

12 files changed, 162 insertions, 136 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d9ae4c0..2c51853 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* gas/mips/msa.s: Reduced maximum element index range
+	for sldi, splati, copy_s, copy_u, insert and insve instructions.
+	* gas/mips/msa64.s: Likewise.
+	* gas/mips/micromips@msa.d: Likewise.
+	* gas/mips/micromips@msa64.d: Likewise.
+	* gas/mips/msa.d: Likewise.
+	* gas/mips/msa64.d: Likewise.
+
 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 
 	* gas/all/gas.exp: Add expected failures for NDS32.
diff --git a/gas/testsuite/gas/mips/micromips@msa.d b/gas/testsuite/gas/mips/micromips@msa.d
index c30bf4d..0ea25af 100644
--- a/gas/testsuite/gas/mips/micromips@msa.d
+++ b/gas/testsuite/gas/mips/micromips@msa.d
@@ -381,25 +381,25 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 5846 290b 	sld\.w	\$w4,\$w5\[a2\]
 [0-9a-f]+ <[^>]*> 5869 41cb 	sld\.d	\$w7,\$w8\[t1\]
 [0-9a-f]+ <[^>]*> 5800 5a96 	sldi\.b	\$w10,\$w11\[0\]
-[0-9a-f]+ <[^>]*> 581f 6b16 	sldi\.b	\$w12,\$w13\[31\]
+[0-9a-f]+ <[^>]*> 580f 6b16 	sldi\.b	\$w12,\$w13\[15\]
 [0-9a-f]+ <[^>]*> 5820 7b96 	sldi\.h	\$w14,\$w15\[0\]
-[0-9a-f]+ <[^>]*> 582f 8c16 	sldi\.h	\$w16,\$w17\[15\]
+[0-9a-f]+ <[^>]*> 5827 8c16 	sldi\.h	\$w16,\$w17\[7\]
 [0-9a-f]+ <[^>]*> 5830 9c96 	sldi\.w	\$w18,\$w19\[0\]
-[0-9a-f]+ <[^>]*> 5837 ad16 	sldi\.w	\$w20,\$w21\[7\]
+[0-9a-f]+ <[^>]*> 5833 ad16 	sldi\.w	\$w20,\$w21\[3\]
 [0-9a-f]+ <[^>]*> 5838 bd96 	sldi\.d	\$w22,\$w23\[0\]
-[0-9a-f]+ <[^>]*> 583b ce16 	sldi\.d	\$w24,\$w25\[3\]
+[0-9a-f]+ <[^>]*> 5839 ce16 	sldi\.d	\$w24,\$w25\[1\]
 [0-9a-f]+ <[^>]*> 589c de8b 	splat\.b	\$w26,\$w27\[gp\]
 [0-9a-f]+ <[^>]*> 58bf f74b 	splat\.h	\$w29,\$w30\[ra\]
 [0-9a-f]+ <[^>]*> 58c2 080b 	splat\.w	\$w0,\$w1\[v0\]
 [0-9a-f]+ <[^>]*> 58e5 20cb 	splat\.d	\$w3,\$w4\[a1\]
 [0-9a-f]+ <[^>]*> 5840 3996 	splati\.b	\$w6,\$w7\[0\]
-[0-9a-f]+ <[^>]*> 585f 4a16 	splati\.b	\$w8,\$w9\[31\]
+[0-9a-f]+ <[^>]*> 584f 4a16 	splati\.b	\$w8,\$w9\[15\]
 [0-9a-f]+ <[^>]*> 5860 5a96 	splati\.h	\$w10,\$w11\[0\]
-[0-9a-f]+ <[^>]*> 586f 6b16 	splati\.h	\$w12,\$w13\[15\]
+[0-9a-f]+ <[^>]*> 5867 6b16 	splati\.h	\$w12,\$w13\[7\]
 [0-9a-f]+ <[^>]*> 5870 7b96 	splati\.w	\$w14,\$w15\[0\]
-[0-9a-f]+ <[^>]*> 5877 8c16 	splati\.w	\$w16,\$w17\[7\]
+[0-9a-f]+ <[^>]*> 5873 8c16 	splati\.w	\$w16,\$w17\[3\]
 [0-9a-f]+ <[^>]*> 5878 9c96 	splati\.d	\$w18,\$w19\[0\]
-[0-9a-f]+ <[^>]*> 587b ad16 	splati\.d	\$w20,\$w21\[3\]
+[0-9a-f]+ <[^>]*> 5879 ad16 	splati\.d	\$w20,\$w21\[1\]
 [0-9a-f]+ <[^>]*> 5918 bd8b 	pckev\.b	\$w22,\$w23,\$w24
 [0-9a-f]+ <[^>]*> 593b d64b 	pckev\.h	\$w25,\$w26,\$w27
 [0-9a-f]+ <[^>]*> 595e ef0b 	pckev\.w	\$w28,\$w29,\$w30
@@ -531,31 +531,31 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 5b0e 41ee 	nlzc\.w	\$w7,\$w8
 [0-9a-f]+ <[^>]*> 5b0f 526e 	nlzc\.d	\$w9,\$w10
 [0-9a-f]+ <[^>]*> 5880 62d6 	copy_s\.b	t3,\$w12\[0\]
-[0-9a-f]+ <[^>]*> 589f 7356 	copy_s\.b	t5,\$w14\[31\]
+[0-9a-f]+ <[^>]*> 588f 7356 	copy_s\.b	t5,\$w14\[15\]
 [0-9a-f]+ <[^>]*> 58a0 83d6 	copy_s\.h	t7,\$w16\[0\]
-[0-9a-f]+ <[^>]*> 58af 9456 	copy_s\.h	s1,\$w18\[15\]
+[0-9a-f]+ <[^>]*> 58a7 9456 	copy_s\.h	s1,\$w18\[7\]
 [0-9a-f]+ <[^>]*> 58b0 a4d6 	copy_s\.w	s3,\$w20\[0\]
-[0-9a-f]+ <[^>]*> 58b7 b556 	copy_s\.w	s5,\$w22\[7\]
+[0-9a-f]+ <[^>]*> 58b3 b556 	copy_s\.w	s5,\$w22\[3\]
 [0-9a-f]+ <[^>]*> 58c0 e6d6 	copy_u\.b	k1,\$w28\[0\]
-[0-9a-f]+ <[^>]*> 58df f756 	copy_u\.b	sp,\$w30\[31\]
+[0-9a-f]+ <[^>]*> 58cf f756 	copy_u\.b	sp,\$w30\[15\]
 [0-9a-f]+ <[^>]*> 58e0 07d6 	copy_u\.h	ra,\$w0\[0\]
-[0-9a-f]+ <[^>]*> 58ef 1056 	copy_u\.h	at,\$w2\[15\]
+[0-9a-f]+ <[^>]*> 58e7 1056 	copy_u\.h	at,\$w2\[7\]
 [0-9a-f]+ <[^>]*> 58f0 20d6 	copy_u\.w	v1,\$w4\[0\]
-[0-9a-f]+ <[^>]*> 58f7 3156 	copy_u\.w	a1,\$w6\[7\]
+[0-9a-f]+ <[^>]*> 58f3 3156 	copy_u\.w	a1,\$w6\[3\]
 [0-9a-f]+ <[^>]*> 5900 62d6 	insert\.b	\$w11\[0\],t4
-[0-9a-f]+ <[^>]*> 591f 7356 	insert\.b	\$w13\[31\],t6
+[0-9a-f]+ <[^>]*> 590f 7356 	insert\.b	\$w13\[15\],t6
 [0-9a-f]+ <[^>]*> 5920 83d6 	insert\.h	\$w15\[0\],s0
-[0-9a-f]+ <[^>]*> 592f 9456 	insert\.h	\$w17\[15\],s2
+[0-9a-f]+ <[^>]*> 5927 9456 	insert\.h	\$w17\[7\],s2
 [0-9a-f]+ <[^>]*> 5930 a4d6 	insert\.w	\$w19\[0\],s4
-[0-9a-f]+ <[^>]*> 5937 b556 	insert\.w	\$w21\[7\],s6
+[0-9a-f]+ <[^>]*> 5933 b556 	insert\.w	\$w21\[3\],s6
 [0-9a-f]+ <[^>]*> 5940 e6d6 	insve\.b	\$w27\[0\],\$w28\[0\]
-[0-9a-f]+ <[^>]*> 595f f756 	insve\.b	\$w29\[31\],\$w30\[0\]
+[0-9a-f]+ <[^>]*> 594f f756 	insve\.b	\$w29\[15\],\$w30\[0\]
 [0-9a-f]+ <[^>]*> 5960 07d6 	insve\.h	\$w31\[0\],\$w0\[0\]
-[0-9a-f]+ <[^>]*> 596f 1056 	insve\.h	\$w1\[15\],\$w2\[0\]
+[0-9a-f]+ <[^>]*> 5967 1056 	insve\.h	\$w1\[7\],\$w2\[0\]
 [0-9a-f]+ <[^>]*> 5970 20d6 	insve\.w	\$w3\[0\],\$w4\[0\]
-[0-9a-f]+ <[^>]*> 5977 3156 	insve\.w	\$w5\[7\],\$w6\[0\]
+[0-9a-f]+ <[^>]*> 5973 3156 	insve\.w	\$w5\[3\],\$w6\[0\]
 [0-9a-f]+ <[^>]*> 5978 41d6 	insve\.d	\$w7\[0\],\$w8\[0\]
-[0-9a-f]+ <[^>]*> 597b 5256 	insve\.d	\$w9\[3\],\$w10\[0\]
+[0-9a-f]+ <[^>]*> 5979 5256 	insve\.d	\$w9\[1\],\$w10\[0\]
 [0-9a-f]+ <[^>]*> 838b 8000 	bnz\.b	\$w11,[0-9a-f]+ <[^>]*>
 [	]*[0-9a-f]+: R_MICROMIPS_PC16_S1	.*
 [0-9a-f]+ <[^>]*> 0c00      	nop
diff --git a/gas/testsuite/gas/mips/micromips@msa64.d b/gas/testsuite/gas/mips/micromips@msa64.d
index f6fefaa..d8369a8 100644
--- a/gas/testsuite/gas/mips/micromips@msa64.d
+++ b/gas/testsuite/gas/mips/micromips@msa64.d
@@ -8,11 +8,11 @@
 Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 5b03 946e 	fill\.d	\$w17,s2
 [0-9a-f]+ <[^>]*> 58b8 c5d6 	copy_s\.d	s7,\$w24\[0\]
-[0-9a-f]+ <[^>]*> 58bb d656 	copy_s\.d	t9,\$w26\[3\]
+[0-9a-f]+ <[^>]*> 58b9 d656 	copy_s\.d	t9,\$w26\[1\]
 [0-9a-f]+ <[^>]*> 58f8 41d6 	copy_u\.d	a3,\$w8\[0\]
-[0-9a-f]+ <[^>]*> 58fb 5256 	copy_u\.d	a5,\$w10\[3\]
+[0-9a-f]+ <[^>]*> 58f9 5256 	copy_u\.d	a5,\$w10\[1\]
 [0-9a-f]+ <[^>]*> 5938 c5d6 	insert\.d	\$w23\[0\],t8
-[0-9a-f]+ <[^>]*> 593b d656 	insert\.d	\$w25\[3\],k0
+[0-9a-f]+ <[^>]*> 5939 d656 	insert\.d	\$w25\[1\],k0
 [0-9a-f]+ <[^>]*> 5b7a c820 	dlsa	t9,k0,k1,0x1
 [0-9a-f]+ <[^>]*> 5bdd e0e0 	dlsa	gp,sp,s8,0x4
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/msa.d b/gas/testsuite/gas/mips/msa.d
index 73f8baa..488fb5d 100644
--- a/gas/testsuite/gas/mips/msa.d
+++ b/gas/testsuite/gas/mips/msa.d
@@ -380,25 +380,25 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 78462914 	sld\.w	\$w4,\$w5\[a2\]
 [0-9a-f]+ <[^>]*> 786941d4 	sld\.d	\$w7,\$w8\[t1\]
 [0-9a-f]+ <[^>]*> 78005a99 	sldi\.b	\$w10,\$w11\[0\]
-[0-9a-f]+ <[^>]*> 781f6b19 	sldi\.b	\$w12,\$w13\[31\]
+[0-9a-f]+ <[^>]*> 780f6b19 	sldi\.b	\$w12,\$w13\[15\]
 [0-9a-f]+ <[^>]*> 78207b99 	sldi\.h	\$w14,\$w15\[0\]
-[0-9a-f]+ <[^>]*> 782f8c19 	sldi\.h	\$w16,\$w17\[15\]
+[0-9a-f]+ <[^>]*> 78278c19 	sldi\.h	\$w16,\$w17\[7\]
 [0-9a-f]+ <[^>]*> 78309c99 	sldi\.w	\$w18,\$w19\[0\]
-[0-9a-f]+ <[^>]*> 7837ad19 	sldi\.w	\$w20,\$w21\[7\]
+[0-9a-f]+ <[^>]*> 7833ad19 	sldi\.w	\$w20,\$w21\[3\]
 [0-9a-f]+ <[^>]*> 7838bd99 	sldi\.d	\$w22,\$w23\[0\]
-[0-9a-f]+ <[^>]*> 783bce19 	sldi\.d	\$w24,\$w25\[3\]
+[0-9a-f]+ <[^>]*> 7839ce19 	sldi\.d	\$w24,\$w25\[1\]
 [0-9a-f]+ <[^>]*> 789cde94 	splat\.b	\$w26,\$w27\[gp\]
 [0-9a-f]+ <[^>]*> 78bff754 	splat\.h	\$w29,\$w30\[ra\]
 [0-9a-f]+ <[^>]*> 78c20814 	splat\.w	\$w0,\$w1\[v0\]
 [0-9a-f]+ <[^>]*> 78e520d4 	splat\.d	\$w3,\$w4\[a1\]
 [0-9a-f]+ <[^>]*> 78403999 	splati\.b	\$w6,\$w7\[0\]
-[0-9a-f]+ <[^>]*> 785f4a19 	splati\.b	\$w8,\$w9\[31\]
+[0-9a-f]+ <[^>]*> 784f4a19 	splati\.b	\$w8,\$w9\[15\]
 [0-9a-f]+ <[^>]*> 78605a99 	splati\.h	\$w10,\$w11\[0\]
-[0-9a-f]+ <[^>]*> 786f6b19 	splati\.h	\$w12,\$w13\[15\]
+[0-9a-f]+ <[^>]*> 78676b19 	splati\.h	\$w12,\$w13\[7\]
 [0-9a-f]+ <[^>]*> 78707b99 	splati\.w	\$w14,\$w15\[0\]
-[0-9a-f]+ <[^>]*> 78778c19 	splati\.w	\$w16,\$w17\[7\]
+[0-9a-f]+ <[^>]*> 78738c19 	splati\.w	\$w16,\$w17\[3\]
 [0-9a-f]+ <[^>]*> 78789c99 	splati\.d	\$w18,\$w19\[0\]
-[0-9a-f]+ <[^>]*> 787bad19 	splati\.d	\$w20,\$w21\[3\]
+[0-9a-f]+ <[^>]*> 7879ad19 	splati\.d	\$w20,\$w21\[1\]
 [0-9a-f]+ <[^>]*> 7918bd94 	pckev\.b	\$w22,\$w23,\$w24
 [0-9a-f]+ <[^>]*> 793bd654 	pckev\.h	\$w25,\$w26,\$w27
 [0-9a-f]+ <[^>]*> 795eef14 	pckev\.w	\$w28,\$w29,\$w30
@@ -524,31 +524,31 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7b0e41de 	nlzc\.w	\$w7,\$w8
 [0-9a-f]+ <[^>]*> 7b0f525e 	nlzc\.d	\$w9,\$w10
 [0-9a-f]+ <[^>]*> 788062d9 	copy_s\.b	t3,\$w12\[0\]
-[0-9a-f]+ <[^>]*> 789f7359 	copy_s\.b	t5,\$w14\[31\]
+[0-9a-f]+ <[^>]*> 788f7359 	copy_s\.b	t5,\$w14\[15\]
 [0-9a-f]+ <[^>]*> 78a083d9 	copy_s\.h	t7,\$w16\[0\]
-[0-9a-f]+ <[^>]*> 78af9459 	copy_s\.h	s1,\$w18\[15\]
+[0-9a-f]+ <[^>]*> 78a79459 	copy_s\.h	s1,\$w18\[7\]
 [0-9a-f]+ <[^>]*> 78b0a4d9 	copy_s\.w	s3,\$w20\[0\]
-[0-9a-f]+ <[^>]*> 78b7b559 	copy_s\.w	s5,\$w22\[7\]
+[0-9a-f]+ <[^>]*> 78b3b559 	copy_s\.w	s5,\$w22\[3\]
 [0-9a-f]+ <[^>]*> 78c0e6d9 	copy_u\.b	k1,\$w28\[0\]
-[0-9a-f]+ <[^>]*> 78dff759 	copy_u\.b	sp,\$w30\[31\]
+[0-9a-f]+ <[^>]*> 78cff759 	copy_u\.b	sp,\$w30\[15\]
 [0-9a-f]+ <[^>]*> 78e007d9 	copy_u\.h	ra,\$w0\[0\]
-[0-9a-f]+ <[^>]*> 78ef1059 	copy_u\.h	at,\$w2\[15\]
+[0-9a-f]+ <[^>]*> 78e71059 	copy_u\.h	at,\$w2\[7\]
 [0-9a-f]+ <[^>]*> 78f020d9 	copy_u\.w	v1,\$w4\[0\]
-[0-9a-f]+ <[^>]*> 78f73159 	copy_u\.w	a1,\$w6\[7\]
+[0-9a-f]+ <[^>]*> 78f33159 	copy_u\.w	a1,\$w6\[3\]
 [0-9a-f]+ <[^>]*> 790062d9 	insert\.b	\$w11\[0\],t4
-[0-9a-f]+ <[^>]*> 791f7359 	insert\.b	\$w13\[31\],t6
+[0-9a-f]+ <[^>]*> 790f7359 	insert\.b	\$w13\[15\],t6
 [0-9a-f]+ <[^>]*> 792083d9 	insert\.h	\$w15\[0\],s0
-[0-9a-f]+ <[^>]*> 792f9459 	insert\.h	\$w17\[15\],s2
+[0-9a-f]+ <[^>]*> 79279459 	insert\.h	\$w17\[7\],s2
 [0-9a-f]+ <[^>]*> 7930a4d9 	insert\.w	\$w19\[0\],s4
-[0-9a-f]+ <[^>]*> 7937b559 	insert\.w	\$w21\[7\],s6
+[0-9a-f]+ <[^>]*> 7933b559 	insert\.w	\$w21\[3\],s6
 [0-9a-f]+ <[^>]*> 7940e6d9 	insve\.b	\$w27\[0\],\$w28\[0\]
-[0-9a-f]+ <[^>]*> 795ff759 	insve\.b	\$w29\[31\],\$w30\[0\]
+[0-9a-f]+ <[^>]*> 794ff759 	insve\.b	\$w29\[15\],\$w30\[0\]
 [0-9a-f]+ <[^>]*> 796007d9 	insve\.h	\$w31\[0\],\$w0\[0\]
-[0-9a-f]+ <[^>]*> 796f1059 	insve\.h	\$w1\[15\],\$w2\[0\]
+[0-9a-f]+ <[^>]*> 79671059 	insve\.h	\$w1\[7\],\$w2\[0\]
 [0-9a-f]+ <[^>]*> 797020d9 	insve\.w	\$w3\[0\],\$w4\[0\]
-[0-9a-f]+ <[^>]*> 79773159 	insve\.w	\$w5\[7\],\$w6\[0\]
+[0-9a-f]+ <[^>]*> 79733159 	insve\.w	\$w5\[3\],\$w6\[0\]
 [0-9a-f]+ <[^>]*> 797841d9 	insve\.d	\$w7\[0\],\$w8\[0\]
-[0-9a-f]+ <[^>]*> 797b5259 	insve\.d	\$w9\[3\],\$w10\[0\]
+[0-9a-f]+ <[^>]*> 79795259 	insve\.d	\$w9\[1\],\$w10\[0\]
 [0-9a-f]+ <[^>]*> 478b8000 	bnz\.b	\$w11,[0-9a-f]+ <[^>]*>
 [0-9a-f]+ <[^>]*> 00000000 	nop
 [0-9a-f]+ <[^>]*> 478c7fff 	bnz\.b	\$w12,[0-9a-f]+ <[^>]*>
diff --git a/gas/testsuite/gas/mips/msa.s b/gas/testsuite/gas/mips/msa.s
index b30197b..e16b6af 100644
--- a/gas/testsuite/gas/mips/msa.s
+++ b/gas/testsuite/gas/mips/msa.s
@@ -378,25 +378,25 @@ test_msa:
 	sld.w	$w4,$w5[$6]
 	sld.d	$w7,$w8[$9]
 	sldi.b	$w10,$w11[0]
-	sldi.b	$w12,$w13[31]
+	sldi.b	$w12,$w13[15]
 	sldi.h	$w14,$w15[0]
-	sldi.h	$w16,$w17[15]
+	sldi.h	$w16,$w17[7]
 	sldi.w	$w18,$w19[0]
-	sldi.w	$w20,$w21[7]
+	sldi.w	$w20,$w21[3]
 	sldi.d	$w22,$w23[0]
-	sldi.d	$w24,$w25[3]
+	sldi.d	$w24,$w25[1]
 	splat.b	$w26,$w27[$28]
 	splat.h	$w29,$w30[$31]
 	splat.w	$w0,$w1[$2]
 	splat.d	$w3,$w4[$5]
 	splati.b	$w6,$w7[0]
-	splati.b	$w8,$w9[31]
+	splati.b	$w8,$w9[15]
 	splati.h	$w10,$w11[0]
-	splati.h	$w12,$w13[15]
+	splati.h	$w12,$w13[7]
 	splati.w	$w14,$w15[0]
-	splati.w	$w16,$w17[7]
+	splati.w	$w16,$w17[3]
 	splati.d	$w18,$w19[0]
-	splati.d	$w20,$w21[3]
+	splati.d	$w20,$w21[1]
 	pckev.b	$w22,$w23,$w24
 	pckev.h	$w25,$w26,$w27
 	pckev.w	$w28,$w29,$w30
@@ -522,31 +522,31 @@ test_msa:
 	nlzc.w	$w7,$w8
 	nlzc.d	$w9,$w10
 	copy_s.b	$11,$w12[0]
-	copy_s.b	$13,$w14[31]
+	copy_s.b	$13,$w14[15]
 	copy_s.h	$15,$w16[0]
-	copy_s.h	$17,$w18[15]
+	copy_s.h	$17,$w18[7]
 	copy_s.w	$19,$w20[0]
-	copy_s.w	$21,$w22[7]
+	copy_s.w	$21,$w22[3]
 	copy_u.b	$27,$w28[0]
-	copy_u.b	$29,$w30[31]
+	copy_u.b	$29,$w30[15]
 	copy_u.h	$31,$w0[0]
-	copy_u.h	$1,$w2[15]
+	copy_u.h	$1,$w2[7]
 	copy_u.w	$3,$w4[0]
-	copy_u.w	$5,$w6[7]
+	copy_u.w	$5,$w6[3]
 	insert.b	$w11[0],$12
-	insert.b	$w13[31],$14
+	insert.b	$w13[15],$14
 	insert.h	$w15[0],$16
-	insert.h	$w17[15],$18
+	insert.h	$w17[7],$18
 	insert.w	$w19[0],$20
-	insert.w	$w21[7],$22
+	insert.w	$w21[3],$22
 	insve.b	$w27[0],$w28[0]
-	insve.b	$w29[31],$w30[0]
+	insve.b	$w29[15],$w30[0]
 	insve.h	$w31[0],$w0[0]
-	insve.h	$w1[15],$w2[0]
+	insve.h	$w1[7],$w2[0]
 	insve.w	$w3[0],$w4[0]
-	insve.w	$w5[7],$w6[0]
+	insve.w	$w5[3],$w6[0]
 	insve.d	$w7[0],$w8[0]
-	insve.d	$w9[3],$w10[0]
+	insve.d	$w9[1],$w10[0]
 1:
 	bnz.b	$w11,. + 4 + (-32768 << insn_log2)
 	nop
diff --git a/gas/testsuite/gas/mips/msa64.d b/gas/testsuite/gas/mips/msa64.d
index 5c1e082..2ade93f 100644
--- a/gas/testsuite/gas/mips/msa64.d
+++ b/gas/testsuite/gas/mips/msa64.d
@@ -7,11 +7,11 @@
 Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7b03945e 	fill\.d	\$w17,s2
 [0-9a-f]+ <[^>]*> 78b8c5d9 	copy_s\.d	s7,\$w24\[0\]
-[0-9a-f]+ <[^>]*> 78bbd659 	copy_s\.d	t9,\$w26\[3\]
+[0-9a-f]+ <[^>]*> 78b9d659 	copy_s\.d	t9,\$w26\[1\]
 [0-9a-f]+ <[^>]*> 78f841d9 	copy_u\.d	a3,\$w8\[0\]
-[0-9a-f]+ <[^>]*> 78fb5259 	copy_u\.d	a5,\$w10\[3\]
+[0-9a-f]+ <[^>]*> 78f95259 	copy_u\.d	a5,\$w10\[1\]
 [0-9a-f]+ <[^>]*> 7938c5d9 	insert\.d	\$w23\[0\],t8
-[0-9a-f]+ <[^>]*> 793bd659 	insert\.d	\$w25\[3\],k0
+[0-9a-f]+ <[^>]*> 7939d659 	insert\.d	\$w25\[1\],k0
 [0-9a-f]+ <[^>]*> 035bc815 	dlsa	t9,k0,k1,0x1
 [0-9a-f]+ <[^>]*> 03bee0d5 	dlsa	gp,sp,s8,0x4
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/msa64.s b/gas/testsuite/gas/mips/msa64.s
index ce994b1..665220b 100644
--- a/gas/testsuite/gas/mips/msa64.s
+++ b/gas/testsuite/gas/mips/msa64.s
@@ -2,11 +2,11 @@
 test_msa64:
 	fill.d	$w17,$18
 	copy_s.d	$23,$w24[0]
-	copy_s.d	$25,$w26[3]
+	copy_s.d	$25,$w26[1]
 	copy_u.d	$7,$w8[0]
-	copy_u.d	$9,$w10[3]
+	copy_u.d	$9,$w10[1]
 	insert.d	$w23[0],$24
-	insert.d	$w25[3],$26
+	insert.d	$w25[1],$26
 	dlsa	$25,$26,$27,1
 	dlsa	$28,$29,$30,4
 
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 26621b5..1635684 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* mips.h: Updated description of +o, +u, +v and +w for MIPS and
+	microMIPS.
+
 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 	    Wei-Cheng Wang  <cole945@gmail.com>
 
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index c9dc52b..7ea0900 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -910,10 +910,10 @@ struct mips_opcode
    "+k" 5-bit GPR at bit 6
    "+l" 5-bit MSA control register at bit 6
    "+n" 5-bit MSA control register at bit 11
-   "+o" 5-bit vector element index at bit 16
-   "+u" 4-bit vector element index at bit 16
-   "+v" 3-bit vector element index at bit 16
-   "+w" 2-bit vector element index at bit 16
+   "+o" 4-bit vector element index at bit 16
+   "+u" 3-bit vector element index at bit 16
+   "+v" 2-bit vector element index at bit 16
+   "+w" 1-bit vector element index at bit 16
    "+T" (-512 .. 511) << 0 at bit 16
    "+U" (-512 .. 511) << 1 at bit 16
    "+V" (-512 .. 511) << 2 at bit 16
@@ -2093,10 +2093,10 @@ extern const int bfd_mips16_num_opcodes;
    "+k" 5-bit GPR at bit 6
    "+l" 5-bit MSA control register at bit 6
    "+n" 5-bit MSA control register at bit 11
-   "+o" 5-bit vector element index at bit 16
-   "+u" 4-bit vector element index at bit 16
-   "+v" 3-bit vector element index at bit 16
-   "+w" 2-bit vector element index at bit 16
+   "+o" 4-bit vector element index at bit 16
+   "+u" 3-bit vector element index at bit 16
+   "+v" 2-bit vector element index at bit 16
+   "+w" 1-bit vector element index at bit 16
    "+x" 5-bit shift amount at bit 16
    "+T" (-512 .. 511) << 0 at bit 16
    "+U" (-512 .. 511) << 1 at bit 16
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 955ace37..9c88d3f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
+	+v and +w.
+	(micromips_opcodes): Reduced element index range for sldi, splati,
+	copy_s, copy_u, insert and insve instructions.
+	* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
+	+v and +w.
+	(mips_builtin_opcodes): Reduced element index range for sldi, splati,
+	copy_s, copy_u, insert and insve instructions.
+
 2013-12-13  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
 
 	* nds32-dis.c (mnemonic_96): Fix typo.
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index a68916a..f03aa0a 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -120,10 +120,10 @@ decode_micromips_operand (const char *p)
 	case 'k': REG (5, 6, GP);
 	case 'l': REG (5, 6, MSA_CTRL);
 	case 'n': REG (5, 11, MSA_CTRL);
-	case 'o': SPECIAL (5, 16, IMM_INDEX);
-	case 'u': SPECIAL (4, 16, IMM_INDEX);
-	case 'v': SPECIAL (3, 16, IMM_INDEX);
-	case 'w': SPECIAL (2, 16, IMM_INDEX);
+	case 'o': SPECIAL (4, 16, IMM_INDEX);
+	case 'u': SPECIAL (3, 16, IMM_INDEX);
+	case 'v': SPECIAL (2, 16, IMM_INDEX);
+	case 'w': SPECIAL (1, 16, IMM_INDEX);
 	case 'x': BIT (5, 16, 0);		/* (0 .. 31) */
 
 	case '~': BIT (2, 6, 1);		/* (1 .. 4) */
@@ -1601,18 +1601,18 @@ const struct mips_opcode micromips_opcodes[] =
 {"sld.h",		"+d,+e+*",	0x5820000b, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		MSA,	0 },
 {"sld.w",		"+d,+e+*",	0x5840000b, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		MSA,	0 },
 {"sld.d",		"+d,+e+*",	0x5860000b, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		MSA,	0 },
-{"sldi.b",		"+d,+e+o",	0x58000016, 0xffe0003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
-{"sldi.h",		"+d,+e+u",	0x58200016, 0xfff0003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
-{"sldi.w",		"+d,+e+v",	0x58300016, 0xfff8003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
-{"sldi.d",		"+d,+e+w",	0x58380016, 0xfffc003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
+{"sldi.b",		"+d,+e+o",	0x58000016, 0xfff0003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
+{"sldi.h",		"+d,+e+u",	0x58200016, 0xfff8003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
+{"sldi.w",		"+d,+e+v",	0x58300016, 0xfffc003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
+{"sldi.d",		"+d,+e+w",	0x58380016, 0xfffe003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
 {"splat.b",		"+d,+e+*",	0x5880000b, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"splat.h",		"+d,+e+*",	0x58a0000b, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"splat.w",		"+d,+e+*",	0x58c0000b, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"splat.d",		"+d,+e+*",	0x58e0000b, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
-{"splati.b",		"+d,+e+o",	0x58400016, 0xffe0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"splati.h",		"+d,+e+u",	0x58600016, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"splati.w",		"+d,+e+v",	0x58700016, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"splati.d",		"+d,+e+w",	0x58780016, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"splati.b",		"+d,+e+o",	0x58400016, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"splati.h",		"+d,+e+u",	0x58600016, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"splati.w",		"+d,+e+v",	0x58700016, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"splati.d",		"+d,+e+w",	0x58780016, 0xfffe003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
 {"pckev.b",		"+d,+e,+h",	0x5900000b, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"pckev.h",		"+d,+e,+h",	0x5920000b, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"pckev.w",		"+d,+e,+h",	0x5940000b, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
@@ -1704,22 +1704,22 @@ const struct mips_opcode micromips_opcodes[] =
 {"nlzc.h",		"+d,+e",	0x5b0d002e, 0xffff003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
 {"nlzc.w",		"+d,+e",	0x5b0e002e, 0xffff003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
 {"nlzc.d",		"+d,+e",	0x5b0f002e, 0xffff003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_s.b",		"+k,+e+o",	0x58800016, 0xffe0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_s.h",		"+k,+e+u",	0x58a00016, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_s.w",		"+k,+e+v",	0x58b00016, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_s.d",		"+k,+e+w",	0x58b80016, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA64,	0 },
-{"copy_u.b",		"+k,+e+o",	0x58c00016, 0xffe0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_u.h",		"+k,+e+u",	0x58e00016, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_u.w",		"+k,+e+v",	0x58f00016, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_u.d",		"+k,+e+w",	0x58f80016, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA64,	0 },
-{"insert.b",		"+d+o,d",	0x59000016, 0xffe0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insert.h",		"+d+u,d",	0x59200016, 0xfff0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insert.w",		"+d+v,d",	0x59300016, 0xfff8003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insert.d",		"+d+w,d",	0x59380016, 0xfffc003f,	MOD_1|RD_3,		0,		0,		MSA64,	0 },
-{"insve.b",		"+d+o,+e+&",	0x59400016, 0xffe0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insve.h",		"+d+u,+e+&",	0x59600016, 0xfff0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insve.w",		"+d+v,+e+&",	0x59700016, 0xfff8003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insve.d",		"+d+w,+e+&",	0x59780016, 0xfffc003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"copy_s.b",		"+k,+e+o",	0x58800016, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_s.h",		"+k,+e+u",	0x58a00016, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_s.w",		"+k,+e+v",	0x58b00016, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_s.d",		"+k,+e+w",	0x58b80016, 0xfffe003f,	WR_1|RD_2,		0,		0,		MSA64,	0 },
+{"copy_u.b",		"+k,+e+o",	0x58c00016, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_u.h",		"+k,+e+u",	0x58e00016, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_u.w",		"+k,+e+v",	0x58f00016, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_u.d",		"+k,+e+w",	0x58f80016, 0xfffe003f,	WR_1|RD_2,		0,		0,		MSA64,	0 },
+{"insert.b",		"+d+o,d",	0x59000016, 0xfff0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insert.h",		"+d+u,d",	0x59200016, 0xfff8003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insert.w",		"+d+v,d",	0x59300016, 0xfffc003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insert.d",		"+d+w,d",	0x59380016, 0xfffe003f,	MOD_1|RD_3,		0,		0,		MSA64,	0 },
+{"insve.b",		"+d+o,+e+&",	0x59400016, 0xfff0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insve.h",		"+d+u,+e+&",	0x59600016, 0xfff8003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insve.w",		"+d+v,+e+&",	0x59700016, 0xfffc003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insve.d",		"+d+w,+e+&",	0x59780016, 0xfffe003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
 {"bnz.b",		"+h,p",		0x83800000, 0xffe00000,	RD_1|CBD,		0,		0,		MSA,	0 },
 {"bnz.h",		"+h,p",		0x83a00000, 0xffe00000,	RD_1|CBD,		0,		0,		MSA,	0 },
 {"bnz.w",		"+h,p",		0x83c00000, 0xffe00000,	RD_1|CBD,		0,		0,		MSA,	0 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index cd43185..fd619f4 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -92,15 +92,15 @@ decode_mips_operand (const char *p)
 	case 'l': REG (5, 6, MSA_CTRL);
 	case 'm': REG (0, 0, R5900_ACC);
 	case 'n': REG (5, 11, MSA_CTRL);
-	case 'o': SPECIAL (5, 16, IMM_INDEX);
+	case 'o': SPECIAL (4, 16, IMM_INDEX);
 	case 'p': BIT (5, 6, 0);		/* (0 .. 31), 32-bit op */
 	case 'q': REG (0, 0, R5900_Q);
 	case 'r': REG (0, 0, R5900_R);
 	case 's': MSB (5, 11, 0, FALSE, 31);	/* (0 .. 31) */
 	case 't': REG (5, 16, COPRO);
-	case 'u': SPECIAL (4, 16, IMM_INDEX);
-	case 'v': SPECIAL (3, 16, IMM_INDEX);
-	case 'w': SPECIAL (2, 16, IMM_INDEX);
+	case 'u': SPECIAL (3, 16, IMM_INDEX);
+	case 'v': SPECIAL (2, 16, IMM_INDEX);
+	case 'w': SPECIAL (1, 16, IMM_INDEX);
 	case 'x': BIT (5, 16, 0);		/* (0 .. 31) */
 	case 'y': REG (0, 0, R5900_I);
 	case 'z': REG (5, 0, GP);
@@ -2853,18 +2853,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sld.h",		"+d,+e+*",	0x78200014, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		MSA,	0 },
 {"sld.w",		"+d,+e+*",	0x78400014, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		MSA,	0 },
 {"sld.d",		"+d,+e+*",	0x78600014, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		MSA,	0 },
-{"sldi.b",		"+d,+e+o",	0x78000019, 0xffe0003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
-{"sldi.h",		"+d,+e+u",	0x78200019, 0xfff0003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
-{"sldi.w",		"+d,+e+v",	0x78300019, 0xfff8003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
-{"sldi.d",		"+d,+e+w",	0x78380019, 0xfffc003f,	MOD_1|RD_2,		0,		0,		MSA,	0 },
+{"sldi.b",		"+d,+e+o",	0x78000019, 0xfff0003f, MOD_1|RD_2,		0,		0,		MSA,	0 },
+{"sldi.h",		"+d,+e+u",	0x78200019, 0xfff8003f, MOD_1|RD_2,		0,		0,		MSA,	0 },
+{"sldi.w",		"+d,+e+v",	0x78300019, 0xfffc003f, MOD_1|RD_2,		0,		0,		MSA,	0 },
+{"sldi.d",		"+d,+e+w",	0x78380019, 0xfffe003f, MOD_1|RD_2,		0,		0,		MSA,	0 },
 {"splat.b",		"+d,+e+*",	0x78800014, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"splat.h",		"+d,+e+*",	0x78a00014, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"splat.w",		"+d,+e+*",	0x78c00014, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"splat.d",		"+d,+e+*",	0x78e00014, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
-{"splati.b",		"+d,+e+o",	0x78400019, 0xffe0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"splati.h",		"+d,+e+u",	0x78600019, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"splati.w",		"+d,+e+v",	0x78700019, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"splati.d",		"+d,+e+w",	0x78780019, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"splati.b",		"+d,+e+o",	0x78400019, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"splati.h",		"+d,+e+u",	0x78600019, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"splati.w",		"+d,+e+v",	0x78700019, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"splati.d",		"+d,+e+w",	0x78780019, 0xfffe003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
 {"pckev.b",		"+d,+e,+h",	0x79000014, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"pckev.h",		"+d,+e,+h",	0x79200014, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
 {"pckev.w",		"+d,+e,+h",	0x79400014, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		MSA,	0 },
@@ -2956,22 +2956,22 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nlzc.h",		"+d,+e",	0x7b0d001e, 0xffff003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
 {"nlzc.w",		"+d,+e",	0x7b0e001e, 0xffff003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
 {"nlzc.d",		"+d,+e",	0x7b0f001e, 0xffff003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_s.b",		"+k,+e+o",	0x78800019, 0xffe0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_s.h",		"+k,+e+u",	0x78a00019, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_s.w",		"+k,+e+v",	0x78b00019, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_s.d",		"+k,+e+w",	0x78b80019, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA64,	0 },
-{"copy_u.b",		"+k,+e+o",	0x78c00019, 0xffe0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_u.h",		"+k,+e+u",	0x78e00019, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_u.w",		"+k,+e+v",	0x78f00019, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
-{"copy_u.d",		"+k,+e+w",	0x78f80019, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA64,	0 },
-{"insert.b",		"+d+o,d",	0x79000019, 0xffe0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insert.h",		"+d+u,d",	0x79200019, 0xfff0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insert.w",		"+d+v,d",	0x79300019, 0xfff8003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insert.d",		"+d+w,d",	0x79380019, 0xfffc003f,	MOD_1|RD_3,		0,		0,		MSA64,	0 },
-{"insve.b",		"+d+o,+e+&",	0x79400019, 0xffe0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insve.h",		"+d+u,+e+&",	0x79600019, 0xfff0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insve.w",		"+d+v,+e+&",	0x79700019, 0xfff8003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
-{"insve.d",		"+d+w,+e+&",	0x79780019, 0xfffc003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"copy_s.b",		"+k,+e+o",	0x78800019, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_s.h",		"+k,+e+u",	0x78a00019, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_s.w",		"+k,+e+v",	0x78b00019, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_s.d",		"+k,+e+w",	0x78b80019, 0xfffe003f,	WR_1|RD_2,		0,		0,		MSA64,	0 },
+{"copy_u.b",		"+k,+e+o",	0x78c00019, 0xfff0003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_u.h",		"+k,+e+u",	0x78e00019, 0xfff8003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_u.w",		"+k,+e+v",	0x78f00019, 0xfffc003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
+{"copy_u.d",		"+k,+e+w",	0x78f80019, 0xfffe003f,	WR_1|RD_2,		0,		0,		MSA64,	0 },
+{"insert.b",		"+d+o,d",	0x79000019, 0xfff0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insert.h",		"+d+u,d",	0x79200019, 0xfff8003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insert.w",		"+d+v,d",	0x79300019, 0xfffc003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insert.d",		"+d+w,d",	0x79380019, 0xfffe003f,	MOD_1|RD_3,		0,		0,		MSA64,	0 },
+{"insve.b",		"+d+o,+e+&",	0x79400019, 0xfff0003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insve.h",		"+d+u,+e+&",	0x79600019, 0xfff8003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insve.w",		"+d+v,+e+&",	0x79700019, 0xfffc003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
+{"insve.d",		"+d+w,+e+&",	0x79780019, 0xfffe003f,	MOD_1|RD_3,		0,		0,		MSA,	0 },
 {"bnz.b",		"+h,p",		0x47800000, 0xffe00000,	RD_1|CBD,		0,		0,		MSA,	0 },
 {"bnz.h",		"+h,p",		0x47a00000, 0xffe00000,	RD_1|CBD,		0,		0,		MSA,	0 },
 {"bnz.w",		"+h,p",		0x47c00000, 0xffe00000,	RD_1|CBD,		0,		0,		MSA,	0 },