diff options
| author | H.J. Lu <hjl.tools@gmail.com> | 2008-04-03 14:03:21 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2008-04-03 14:03:21 +0000 |
| commit | c0f3af977b0f28a0dc5a620110b8dcf9d8286f84 (patch) | |
| tree | 07edd0198461fb5ea1e7938a4dfe1b3a8d684fe1 | |
| parent | deae2a14a03a8cae07817ae03e4517fe4983d94e (diff) | |
| download | gdb-c0f3af977b0f28a0dc5a620110b8dcf9d8286f84.zip gdb-c0f3af977b0f28a0dc5a620110b8dcf9d8286f84.tar.gz gdb-c0f3af977b0f28a0dc5a620110b8dcf9d8286f84.tar.bz2 | |
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
61 files changed, 52103 insertions, 9586 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index b0e140a..3d6b8d8 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,6 +1,11 @@ +2008-04-03 H.J. Lu <hongjiu.lu@intel.com> + + * dwarf.c (dwarf_regnames_i386): Add AVX registers. + (dwarf_regnames_x86_64): Likewise. + 2008-03-27 Cary Coutant <ccoutant@google.com> - Add support for thin archives. + Add support for thin archives. * ar.c (make_thin_archive): New global flag. (map_over_members): Deal with full pathnames in thin archives. (usage, main): Add 'T' option for building thin archives. diff --git a/binutils/dwarf.c b/binutils/dwarf.c index cdc8d12..0fe58a1 100644 --- a/binutils/dwarf.c +++ b/binutils/dwarf.c @@ -3182,7 +3182,10 @@ static const char *const dwarf_regnames_i386[] = "mm4", "mm5", "mm6", "mm7", "fcw", "fsw", "mxcsr", "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, - "tr", "ldtr" + "tr", "ldtr", + NULL, NULL, NULL, + "ymm0", "ymm1", "ymm2", "ymm3", + "ymm4", "ymm5", "ymm6", "ymm7" }; static const char *const dwarf_regnames_x86_64[] = @@ -3204,7 +3207,12 @@ static const char *const dwarf_regnames_x86_64[] = "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, "fs.base", "gs.base", NULL, NULL, "tr", "ldtr", - "mxcsr", "fcw", "fsw" + "mxcsr", "fcw", "fsw", + NULL, NULL, NULL, + "ymm0", "ymm1", "ymm2", "ymm3", + "ymm4", "ymm5", "ymm6", "ymm7", + "ymm8", "ymm9", "ymm10", "ymm11", + "ymm12", "ymm13", "ymm14", "ymm15" }; static const char *const *dwarf_regnames; diff --git a/gas/ChangeLog b/gas/ChangeLog index d5a9d56..fae8cb0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,53 @@ +2008-04-03 H.J. Lu <hongjiu.lu@intel.com> + + * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. + + * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. + Document -msse2avx, .avx, .aes, .clmul and .fma. + + * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. + (vex_prefix): Likewise. + (sse2avx): Likewise. + (CPU_FLAGS_ARCH_MATCH): Likewise. + (CPU_FLAGS_64BIT_MATCH): Likewise. + (CPU_FLAGS_32BIT_MATCH): Likewise. + (CPU_FLAGS_PERFECT_MATCH): Likewise. + (regymm): Likewise. + (vex_imm4): Likewise. + (fits_in_imm4): Likewise. + (build_vex_prefix): Likewise. + (VEX_check_operands): Likewise. + (bad_implicit_operand): Likewise. + (OPTION_MSSE2AVX): Likewise. + (T_YMMWORD): Likewise. + (_i386_insn): Add vex. + (cpu_arch): Add .avx, .aes, .clmul and .fma. + (cpu_flags_match): Changed to take a pointer to const template. + Enable encoding SSE instructions with VEX prefix for -msse2avx. + (match_mem_size): Also check ymmword. + (operand_type_match): Clear ymmword. + (md_begin): Allow '_' in mnemonic. + (type_names): Add OPERAND_TYPE_VEX_IMM4. + (process_immext): Update assert. + (md_assemble): Don't call process_immext if sse2avx and immext + are true. Call build_vex_prefix if vex is true. + (parse_insn): Updated for cpu_flags_match. + (swap_operands): Handle 5 operands. + (match_template): Handle 5 operands. Updated for cpu_flags_match. + Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. + (process_suffix): Handle YMMWORD_MNEM_SUFFIX. + (check_byte_reg): Check regymm. + (process_operands): Duplicate the destination register for + -msse2avx if needed. + (build_modrm_byte): Updated for instructions with VEX encoding. + (output_insn): Output VEX prefix if needed. + (md_longopts): Add msse2avx. + (md_parse_option): Handle OPTION_MSSE2AVX. + (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. + (intel_e09): Support YMMWORD. + (intel_e11): Likewise. + (intel_get_token): Likewise. + 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Add attiny167. @@ -1,4 +1,9 @@ -*- text -*- +* New command line option -msse2avx for x86 target to encode SSE + instructions with VEX prefix. + +* Add Intel AES, CLMUL, AVX/FMA support for x86 target. + * New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU, -mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg, -mnaked-reg and -mold-gcc, for x86 targets. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 80a1ac8..e8e8031 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -81,6 +81,7 @@ #define LONG_MNEM_SUFFIX 'l' #define QWORD_MNEM_SUFFIX 'q' #define XMMWORD_MNEM_SUFFIX 'x' +#define YMMWORD_MNEM_SUFFIX 'y' /* Intel Syntax. Use a non-ascii letter since since it never appears in instructions. */ #define LONG_DOUBLE_MNEM_SUFFIX '\1' @@ -220,6 +221,16 @@ static void handle_large_common (int small ATTRIBUTE_UNUSED); static const char *default_arch = DEFAULT_ARCH; +/* VEX prefix. */ +typedef struct +{ + /* VEX prefix is either 2 byte or 3 byte. */ + unsigned char bytes[3]; + unsigned int length; + /* Destination or source register specifier. */ + const reg_entry *register_specifier; +} vex_prefix; + /* 'md_assemble ()' gathers together information and puts it into a i386_insn. */ @@ -285,6 +296,7 @@ struct _i386_insn rex_byte rex; sib_byte sib; drex_byte drex; + vex_prefix vex; }; typedef struct _i386_insn i386_insn; @@ -462,6 +474,9 @@ static i386_cpu_flags cpu_arch_isa_flags; larger than a byte offset. */ static unsigned int no_cond_jump_promotion = 0; +/* Encode SSE instructions with VEX prefix. */ +static unsigned int sse2avx; + /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ static symbolS *GOT_symbol; @@ -622,12 +637,20 @@ static const arch_entry cpu_arch[] = CPU_SSE4_2_FLAGS }, { ".sse4", PROCESSOR_UNKNOWN, CPU_SSE4_2_FLAGS }, + { ".avx", PROCESSOR_UNKNOWN, + CPU_AVX_FLAGS }, { ".vmx", PROCESSOR_UNKNOWN, CPU_VMX_FLAGS }, { ".smx", PROCESSOR_UNKNOWN, CPU_SMX_FLAGS }, { ".xsave", PROCESSOR_UNKNOWN, CPU_XSAVE_FLAGS }, + { ".aes", PROCESSOR_UNKNOWN, + CPU_AES_FLAGS }, + { ".clmul", PROCESSOR_UNKNOWN, + CPU_CLMUL_FLAGS }, + { ".fma", PROCESSOR_UNKNOWN, + CPU_FMA_FLAGS }, { ".3dnow", PROCESSOR_UNKNOWN, CPU_3DNOW_FLAGS }, { ".3dnowa", PROCESSOR_UNKNOWN, @@ -1176,29 +1199,45 @@ cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) return x; } -/* Return 3 if there is a perfect match, 2 if compatible with 64bit, - 1 if compatible with arch, 0 if there is no match. */ +#define CPU_FLAGS_ARCH_MATCH 0x1 +#define CPU_FLAGS_64BIT_MATCH 0x2 + +#define CPU_FLAGS_32BIT_MATCH CPU_FLAGS_ARCH_MATCH +#define CPU_FLAGS_PERFECT_MATCH \ + (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) + +/* Return CPU flags match bits. */ static int -cpu_flags_match (i386_cpu_flags x) +cpu_flags_match (const template *t) { - int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0; + i386_cpu_flags x = t->cpu_flags; + int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; x.bitfield.cpu64 = 0; x.bitfield.cpuno64 = 0; if (cpu_flags_all_zero (&x)) - overlap |= 1; + { + /* This instruction is available on all archs. */ + match |= CPU_FLAGS_32BIT_MATCH; + } else { + /* This instruction is available only on some archs. */ i386_cpu_flags cpu = cpu_arch_flags; cpu.bitfield.cpu64 = 0; cpu.bitfield.cpuno64 = 0; cpu = cpu_flags_and (x, cpu); - overlap |= cpu_flags_all_zero (&cpu) ? 0 : 1; + if (!cpu_flags_all_zero (&cpu)) + { + /* Check SSE2AVX */ + if (!t->opcode_modifier.sse2avx || sse2avx) + match |= CPU_FLAGS_32BIT_MATCH; + } } - return overlap; + return match; } static INLINE i386_operand_type @@ -1269,6 +1308,7 @@ static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; +static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; @@ -1278,6 +1318,7 @@ static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; +static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4; enum operand_type { @@ -1356,7 +1397,9 @@ match_mem_size (const template *t, unsigned int j) || (i.types[j].bitfield.tbyte && !t->operand_types[j].bitfield.tbyte) || (i.types[j].bitfield.xmmword - && !t->operand_types[j].bitfield.xmmword))); + && !t->operand_types[j].bitfield.xmmword) + || (i.types[j].bitfield.ymmword + && !t->operand_types[j].bitfield.ymmword))); } /* Return 1 if there is no size conflict on any operands for @@ -1437,6 +1480,7 @@ operand_type_match (i386_operand_type overlap, temp.bitfield.qword = 0; temp.bitfield.tbyte = 0; temp.bitfield.xmmword = 0; + temp.bitfield.ymmword = 0; if (operand_type_all_zero (&temp)) return 0; @@ -1548,6 +1592,12 @@ fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) #endif } /* fits_in_unsigned_long() */ +static INLINE int +fits_in_imm4 (offsetT num) +{ + return (num & 0xf) == num; +} + static i386_operand_type smallest_imm_type (offsetT num) { @@ -1991,6 +2041,7 @@ md_begin () operand_chars['?'] = '?'; #endif digit_chars['-'] = '-'; + mnemonic_chars['_'] = '_'; mnemonic_chars['-'] = '-'; mnemonic_chars['.'] = '.'; identifier_chars['_'] = '_'; @@ -2069,6 +2120,7 @@ pi (char *line, i386_insn *x) || x->types[i].bitfield.reg64 || x->types[i].bitfield.regmmx || x->types[i].bitfield.regxmm + || x->types[i].bitfield.regymm || x->types[i].bitfield.sreg2 || x->types[i].bitfield.sreg3 || x->types[i].bitfield.control @@ -2170,6 +2222,7 @@ const type_names[] = { OPERAND_TYPE_REGMMX, "rMMX" }, { OPERAND_TYPE_REGXMM, "rXMM" }, { OPERAND_TYPE_ESSEG, "es" }, + { OPERAND_TYPE_VEX_IMM4, "VEX i4" }, }; static void @@ -2395,6 +2448,102 @@ intel_float_operand (const char *mnemonic) return 1; } +/* Build the VEX prefix. */ + +static void +build_vex_prefix (void) +{ + unsigned int register_specifier; + unsigned int implied_prefix; + unsigned int vector_length; + + /* Check register specifier. */ + if (i.vex.register_specifier) + { + register_specifier = i.vex.register_specifier->reg_num; + if ((i.vex.register_specifier->reg_flags & RegRex)) + register_specifier += 8; + register_specifier = ~register_specifier & 0xf; + } + else + register_specifier = 0xf; + + vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0; + + switch ((i.tm.base_opcode >> 8) & 0xff) + { + case 0: + implied_prefix = 0; + break; + case DATA_PREFIX_OPCODE: + implied_prefix = 1; + break; + case REPE_PREFIX_OPCODE: + implied_prefix = 2; + break; + case REPNE_PREFIX_OPCODE: + implied_prefix = 3; + break; + default: + abort (); + } + + /* Use 2-byte VEX prefix if possible. */ + if (i.tm.opcode_modifier.vex0f + && (i.rex & (REX_W | REX_X | REX_B)) == 0) + { + /* 2-byte VEX prefix. */ + unsigned int r; + + i.vex.length = 2; + i.vex.bytes[0] = 0xc5; + + /* Check the REX.R bit. */ + r = (i.rex & REX_R) ? 0 : 1; + i.vex.bytes[1] = (r << 7 + | register_specifier << 3 + | vector_length << 2 + | implied_prefix); + } + else + { + /* 3-byte VEX prefix. */ + unsigned int m, w; + + if (i.tm.opcode_modifier.vex0f) + m = 0x1; + else if (i.tm.opcode_modifier.vex0f38) + m = 0x2; + else if (i.tm.opcode_modifier.vex0f3a) + m = 0x3; + else + abort (); + + i.vex.length = 3; + i.vex.bytes[0] = 0xc4; + + /* The high 3 bits of the second VEX byte are 1's compliment + of RXB bits from REX. */ + i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; + + /* Check the REX.W bit. */ + w = (i.rex & REX_W) ? 1 : 0; + if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1) + { + if (w) + abort (); + + if (i.tm.opcode_modifier.vexw1) + w = 1; + } + + i.vex.bytes[2] = (w << 7 + | register_specifier << 3 + | vector_length << 2 + | implied_prefix); + } +} + static void process_immext (void) { @@ -2417,18 +2566,20 @@ process_immext (void) i.operands = 0; } - /* These AMD 3DNow! and SSE2 Instructions have an opcode suffix + /* These AMD 3DNow! and SSE2 instructions have an opcode suffix which is coded in the same place as an 8-bit immediate field would be. Here we fake an 8-bit immediate operand from the opcode suffix stored in tm.extension_opcode. - SSE5 also uses this encoding, for some of its 3 argument - instructions. */ + SSE5 and AVX instructions also use this encoding, for some of + 3 argument instructions. */ assert (i.imm_operands == 0 && (i.operands <= 2 || (i.tm.cpu_flags.bitfield.cpusse5 - && i.operands <= 3))); + && i.operands <= 3) + || (i.tm.opcode_modifier.vex + && i.operands <= 4))); exp = &im_expressions[i.imm_operands++]; i.op[i.operands].imms = exp; @@ -2553,7 +2704,9 @@ md_assemble (char *line) || i.types[j].bitfield.floatacc) i.reg_operands--; - if (i.tm.opcode_modifier.immext) + /* ImmExt should be processed after SSE2AVX. */ + if (!i.tm.opcode_modifier.sse2avx + && i.tm.opcode_modifier.immext) process_immext (); /* For insns with operands there are more diddles to do to the opcode. */ @@ -2568,6 +2721,9 @@ md_assemble (char *line) as_warn (_("translating to `%sp'"), i.tm.name); } + if (i.tm.opcode_modifier.vex) + build_vex_prefix (); + /* Handle conversion of 'int $3' --> special int3 insn. */ if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) { @@ -2810,12 +2966,12 @@ parse_insn (char *line, char *mnemonic) supported = 0; for (t = current_templates->start; t < current_templates->end; ++t) { - supported |= cpu_flags_match (t->cpu_flags); - if (supported == 3) + supported |= cpu_flags_match (t); + if (supported == CPU_FLAGS_PERFECT_MATCH) goto skip; } - if (!(supported & 2)) + if (!(supported & CPU_FLAGS_64BIT_MATCH)) { as_bad (flag_code == CODE_64BIT ? _("`%s' is not supported in 64-bit mode") @@ -2823,7 +2979,7 @@ parse_insn (char *line, char *mnemonic) current_templates->start->name); return NULL; } - if (!(supported & 1)) + if (supported != CPU_FLAGS_PERFECT_MATCH) { as_bad (_("`%s' is not supported on `%s%s'"), current_templates->start->name, cpu_arch_name, @@ -3004,6 +3160,7 @@ swap_operands (void) { switch (i.operands) { + case 5: case 4: swap_2_operands (1, i.operands - 2); case 3: @@ -3245,12 +3402,36 @@ optimize_disp (void) } } +/* Check if operands are valid for the instrucrtion. Update VEX + operand types. */ + +static int +VEX_check_operands (const template *t) +{ + if (!t->opcode_modifier.vex) + return 0; + + /* Only check VEX_Imm4, which must be the first operand. */ + if (t->operand_types[0].bitfield.vex_imm4) + { + if (i.op[0].imms->X_op != O_constant + || !fits_in_imm4 (i.op[0].imms->X_add_number)) + return 1; + + /* Turn off Imm8 so that update_imm won't complain. */ + i.types[0] = vex_imm4; + } + + return 0; +} + static int match_template (void) { /* Points to template once we've found it. */ const template *t; i386_operand_type overlap0, overlap1, overlap2, overlap3; + i386_operand_type overlap4; unsigned int found_reverse_match; i386_opcode_modifier suffix_check; i386_operand_type operand_types [MAX_OPERANDS]; @@ -3259,8 +3440,8 @@ match_template (void) unsigned int found_cpu_match; unsigned int check_register; -#if MAX_OPERANDS != 4 -# error "MAX_OPERANDS must be 4." +#if MAX_OPERANDS != 5 +# error "MAX_OPERANDS must be 5." #endif found_reverse_match = 0; @@ -3289,7 +3470,8 @@ match_template (void) continue; /* Check processor support. */ - found_cpu_match = cpu_flags_match (t->cpu_flags) == 3; + found_cpu_match = (cpu_flags_match (t) + == CPU_FLAGS_PERFECT_MATCH); if (!found_cpu_match) continue; @@ -3330,9 +3512,11 @@ match_template (void) && !intel_float_operand (t->name)) : intel_float_operand (t->name) != 2) && ((!operand_types[0].bitfield.regmmx - && !operand_types[0].bitfield.regxmm) + && !operand_types[0].bitfield.regxmm + && !operand_types[0].bitfield.regymm) || (!operand_types[t->operands > 1].bitfield.regmmx - && !!operand_types[t->operands > 1].bitfield.regxmm)) + && !!operand_types[t->operands > 1].bitfield.regxmm + && !!operand_types[t->operands > 1].bitfield.regymm)) && (t->base_opcode != 0x0fc7 || t->extension_opcode != 1 /* cmpxchg8b */)) continue; @@ -3426,6 +3610,7 @@ match_template (void) continue; case 3: case 4: + case 5: overlap1 = operand_type_and (i.types[1], operand_types[1]); if (!operand_type_match (overlap0, i.types[0]) || !operand_type_match (overlap1, i.types[1]) @@ -3471,6 +3656,9 @@ match_template (void) /* Found a forward 2 operand match here. */ switch (t->operands) { + case 5: + overlap4 = operand_type_and (i.types[4], + operand_types[4]); case 4: overlap3 = operand_type_and (i.types[3], operand_types[3]); @@ -3482,6 +3670,15 @@ match_template (void) switch (t->operands) { + case 5: + if (!operand_type_match (overlap4, i.types[4]) + || !operand_type_register_match (overlap3, + i.types[3], + operand_types[3], + overlap4, + i.types[4], + operand_types[4])) + continue; case 4: if (!operand_type_match (overlap3, i.types[3]) || (check_register @@ -3517,6 +3714,11 @@ match_template (void) found_reverse_match = 0; continue; } + + /* Check if VEX operands are valid. */ + if (VEX_check_operands (t)) + continue; + /* We've found a match; break out of loop. */ break; } @@ -3700,9 +3902,10 @@ process_suffix (void) if (!check_word_reg ()) return 0; } - else if (i.suffix == XMMWORD_MNEM_SUFFIX) + else if (i.suffix == XMMWORD_MNEM_SUFFIX + || i.suffix == YMMWORD_MNEM_SUFFIX) { - /* Skip if the instruction has x suffix. match_template + /* Skip if the instruction has x/y suffix. match_template should check if it is a valid suffix. */ } else if (intel_syntax && i.tm.opcode_modifier.ignoresize) @@ -3789,7 +3992,8 @@ process_suffix (void) if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX - && i.suffix != XMMWORD_MNEM_SUFFIX) + && i.suffix != XMMWORD_MNEM_SUFFIX + && i.suffix != YMMWORD_MNEM_SUFFIX) { /* It's not a byte, select word/dword operation. */ if (i.tm.opcode_modifier.w) @@ -3916,6 +4120,7 @@ check_byte_reg (void) || i.types[op].bitfield.reg64 || i.types[op].bitfield.regmmx || i.types[op].bitfield.regxmm + || i.types[op].bitfield.regymm || i.types[op].bitfield.sreg2 || i.types[op].bitfield.sreg3 || i.types[op].bitfield.control @@ -4508,6 +4713,19 @@ process_drex (void) } static int +bad_implicit_operand (int xmm) +{ + const char *reg = xmm ? "xmm0" : "ymm0"; + if (intel_syntax) + as_bad (_("the last operand of `%s' must be `%s%s'"), + i.tm.name, register_prefix, reg); + else + as_bad (_("the first operand of `%s' must be `%s%s'"), + i.tm.name, register_prefix, reg); + return 0; +} + +static int process_operands (void) { /* Default segment register this instruction will use for memory @@ -4521,23 +4739,98 @@ process_operands (void) || i.tm.opcode_modifier.drexc) process_drex (); - if (i.tm.opcode_modifier.firstxmm0) + if (i.tm.opcode_modifier.sse2avx + && (i.tm.opcode_modifier.vexnds + || i.tm.opcode_modifier.vexndd)) { + unsigned int dup = i.operands; + unsigned int dest = dup - 1; unsigned int j; - /* The first operand is implicit and must be xmm0. */ + /* The destination must be an xmm register. */ assert (i.reg_operands - && operand_type_equal (&i.types[0], ®xmm)); - if (i.op[0].regs->reg_num != 0) + && MAX_OPERANDS > dup + && operand_type_equal (&i.types[dest], ®xmm)); + + if (i.tm.opcode_modifier.firstxmm0) { - if (intel_syntax) - as_bad (_("the last operand of `%s' must be `%sxmm0'"), - i.tm.name, register_prefix); + /* The first operand is implicit and must be xmm0. */ + assert (operand_type_equal (&i.types[0], ®xmm)); + if (i.op[0].regs->reg_num != 0) + return bad_implicit_operand (1); + + if (i.tm.opcode_modifier.vex3sources) + { + /* Keep xmm0 for instructions with VEX prefix and 3 + sources. */ + goto duplicate; + } else - as_bad (_("the first operand of `%s' must be `%sxmm0'"), - i.tm.name, register_prefix); - return 0; + { + /* We remove the first xmm0 and keep the number of + operands unchanged, which in fact duplicates the + destination. */ + for (j = 1; j < i.operands; j++) + { + i.op[j - 1] = i.op[j]; + i.types[j - 1] = i.types[j]; + i.tm.operand_types[j - 1] = i.tm.operand_types[j]; + } + } + } + else if (i.tm.opcode_modifier.implicit1stxmm0) + { + assert ((MAX_OPERANDS - 1) > dup + && i.tm.opcode_modifier.vex3sources); + + /* Add the implicit xmm0 for instructions with VEX prefix + and 3 sources. */ + for (j = i.operands; j > 0; j--) + { + i.op[j] = i.op[j - 1]; + i.types[j] = i.types[j - 1]; + i.tm.operand_types[j] = i.tm.operand_types[j - 1]; + } + i.op[0].regs + = (const reg_entry *) hash_find (reg_hash, "xmm0"); + i.types[0] = regxmm; + i.tm.operand_types[0] = regxmm; + + i.operands += 2; + i.reg_operands += 2; + i.tm.operands += 2; + + dup++; + dest++; + i.op[dup] = i.op[dest]; + i.types[dup] = i.types[dest]; + i.tm.operand_types[dup] = i.tm.operand_types[dest]; } + else + { +duplicate: + i.operands++; + i.reg_operands++; + i.tm.operands++; + + i.op[dup] = i.op[dest]; + i.types[dup] = i.types[dest]; + i.tm.operand_types[dup] = i.tm.operand_types[dest]; + } + + if (i.tm.opcode_modifier.immext) + process_immext (); + } + else if (i.tm.opcode_modifier.firstxmm0) + { + unsigned int j; + + /* The first operand is implicit and must be xmm0/ymm0. */ + assert (i.reg_operands + && (operand_type_equal (&i.types[0], ®xmm) + || operand_type_equal (&i.types[0], ®ymm))); + if (i.op[0].regs->reg_num != 0) + return bad_implicit_operand (i.types[0].bitfield.regxmm); for (j = 1; j < i.operands; j++) { @@ -4665,6 +4958,129 @@ static const seg_entry * build_modrm_byte (void) { const seg_entry *default_seg = 0; + unsigned int source, dest; + int vex_3_sources; + + /* The first operand of instructions with VEX prefix and 3 sources + must be VEX_Imm4. */ + vex_3_sources = i.tm.opcode_modifier.vex3sources; + if (vex_3_sources) + { + unsigned int nds, reg; + + if (i.tm.opcode_modifier.veximmext + && i.tm.opcode_modifier.immext) + { + dest = i.operands - 2; + assert (dest == 3); + } + else + dest = i.operands - 1; + nds = dest - 1; + + /* There are 2 kinds of instructions: + 1. 5 operands: one immediate operand and 4 register + operands or 3 register operands plus 1 memory operand. + It must have VexNDS and VexW0 or VexW1. The destination + must be either XMM or YMM register. + 2. 4 operands: 4 register operands or 3 register operands + plus 1 memory operand. It must have VexNDS and VexImmExt. */ + if (!((i.reg_operands == 4 + || (i.reg_operands == 3 && i.mem_operands == 1)) + && i.tm.opcode_modifier.vexnds + && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) + || operand_type_equal (&i.tm.operand_types[dest], ®ymm)) + && (operand_type_equal (&i.tm.operand_types[nds], ®xmm) + || operand_type_equal (&i.tm.operand_types[nds], ®ymm)) + && ((dest == 4 + && i.imm_operands == 1 + && i.types[0].bitfield.vex_imm4 + && (i.tm.opcode_modifier.vexw0 + || i.tm.opcode_modifier.vexw1)) + || (dest == 3 + && (i.imm_operands == 0 + || (i.imm_operands == 1 + && i.tm.opcode_modifier.immext)) + && i.tm.opcode_modifier.veximmext)))) + abort (); + + i.vex.register_specifier = i.op[nds].regs; + + if (i.imm_operands == 0) + { + /* When there is no immediate operand, generate an 8bit + immediate operand to encode the first operand. */ + expressionS *exp = &im_expressions[i.imm_operands++]; + i.op[i.operands].imms = exp; + i.types[i.operands] = imm8; + i.operands++; + /* If VexW1 is set, the first operand is the source and + the second operand is encoded in the immediate operand. */ + if (i.tm.opcode_modifier.vexw1) + { + source = 0; + reg = 1; + } + else + { + source = 1; + reg = 0; + } + assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm) + || operand_type_equal (&i.tm.operand_types[reg], + ®ymm)); + exp->X_op = O_constant; + exp->X_add_number + = ((i.op[reg].regs->reg_num + + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4); + } + else + { + unsigned int imm; + + if (i.tm.opcode_modifier.vexw0) + { + /* If VexW0 is set, the third operand is the source and + the second operand is encoded in the immediate + operand. */ + source = 2; + reg = 1; + } + else + { + /* VexW1 is set, the second operand is the source and + the third operand is encoded in the immediate + operand. */ + source = 1; + reg = 2; + } + + if (i.tm.opcode_modifier.immext) + { + /* When ImmExt is set, the immdiate byte is the last + operand. */ + imm = i.operands - 1; + source--; + reg--; + } + else + { + imm = 0; + + /* Turn on Imm8 so that output_imm will generate it. */ + i.types[imm].bitfield.imm8 = 1; + } + + assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm) + || operand_type_equal (&i.tm.operand_types[reg], + ®ymm)); + i.op[imm].imms->X_add_number + |= ((i.op[reg].regs->reg_num + + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4); + } + } + else + source = dest = 0; /* SSE5 4 operand instructions are encoded in such a way that one of the inputs must match the destination register. Process_drex hides @@ -4688,11 +5104,18 @@ build_modrm_byte (void) } /* i.reg_operands MUST be the number of real register operands; - implicit registers do not count. */ - else if (i.reg_operands == 2) + implicit registers do not count. If there are 3 register + operands, it must be a instruction with VexNDS. For a + instruction with VexNDD, the destination register is encoded + in VEX prefix. If there are 4 register operands, it must be + a instruction with VEX prefix and 3 sources. */ + else if (i.mem_operands == 0 + && ((i.reg_operands == 2 + && !i.tm.opcode_modifier.vexndd) + || (i.reg_operands == 3 + && i.tm.opcode_modifier.vexnds) + || (i.reg_operands == 4 && vex_3_sources))) { - unsigned int source, dest; - switch (i.operands) { case 2: @@ -4701,10 +5124,12 @@ build_modrm_byte (void) case 3: /* When there are 3 operands, one of them may be immediate, which may be the first or the last operand. Otherwise, - the first operand must be shift count register (cl). */ + the first operand must be shift count register (cl) or it + is an instruction with VexNDS. */ assert (i.imm_operands == 1 || (i.imm_operands == 0 - && i.types[0].bitfield.shiftcount)); + && (i.tm.opcode_modifier.vexnds + || i.types[0].bitfield.shiftcount))); if (operand_type_check (i.types[0], imm) || i.types[0].bitfield.shiftcount) source = 1; @@ -4714,17 +5139,53 @@ build_modrm_byte (void) case 4: /* When there are 4 operands, the first two must be 8bit immediate operands. The source operand will be the 3rd - one. */ - assert (i.imm_operands == 2 - && i.types[0].bitfield.imm8 - && i.types[1].bitfield.imm8); - source = 2; + one. + + For instructions with VexNDS, if the first operand + an imm8, the source operand is the 2nd one. If the last + operand is imm8, the source operand is the first one. */ + assert ((i.imm_operands == 2 + && i.types[0].bitfield.imm8 + && i.types[1].bitfield.imm8) + || (i.tm.opcode_modifier.vexnds + && i.imm_operands == 1 + && (i.types[0].bitfield.imm8 + || i.types[i.operands - 1].bitfield.imm8))); + if (i.tm.opcode_modifier.vexnds) + { + if (i.types[0].bitfield.imm8) + source = 1; + else + source = 0; + } + else + source = 2; + break; + case 5: break; default: abort (); } - dest = source + 1; + if (!vex_3_sources) + { + dest = source + 1; + + if (i.tm.opcode_modifier.vexnds) + { + /* For instructions with VexNDS, the register-only + source operand must be XMM or YMM register. It is + encoded in VEX prefix. */ + if ((dest + 1) >= i.operands + || (!operand_type_equal (&i.tm.operand_types[dest], + ®xmm) + && !operand_type_equal (&i.tm.operand_types[dest], + ®ymm))) + abort (); + i.vex.register_specifier = i.op[dest].regs; + dest++; + } + } i.rm.mode = 3; /* One of the register operands will be encoded in the i.tm.reg @@ -4763,6 +5224,8 @@ build_modrm_byte (void) } else { /* If it's not 2 reg operands... */ + unsigned int mem; + if (i.mem_operands) { unsigned int fake_zero_displacement = 0; @@ -4966,7 +5429,11 @@ build_modrm_byte (void) exp->X_add_symbol = (symbolS *) 0; exp->X_op_symbol = (symbolS *) 0; } + + mem = op; } + else + mem = ~0; /* Fill in i.rm.reg or i.rm.regmem field with register operand (if any) based on i.tm.extension_opcode. Again, we must be @@ -4989,6 +5456,8 @@ build_modrm_byte (void) } else { + unsigned int vex_reg = ~0; + for (op = 0; op < i.operands; op++) if (i.types[op].bitfield.reg8 || i.types[op].bitfield.reg16 @@ -4996,6 +5465,7 @@ build_modrm_byte (void) || i.types[op].bitfield.reg64 || i.types[op].bitfield.regmmx || i.types[op].bitfield.regxmm + || i.types[op].bitfield.regymm || i.types[op].bitfield.sreg2 || i.types[op].bitfield.sreg3 || i.types[op].bitfield.control @@ -5003,7 +5473,48 @@ build_modrm_byte (void) || i.types[op].bitfield.test) break; - assert (op < i.operands); + if (vex_3_sources) + op = dest; + else if (i.tm.opcode_modifier.vexnds) + { + /* For instructions with VexNDS, the register-only + source operand is encoded in VEX prefix. */ + assert (mem != (unsigned int) ~0); + + if (op > mem) + { + vex_reg = op++; + assert (op < i.operands); + } + else + { + vex_reg = op + 1; + assert (vex_reg < i.operands); + } + } + else if (i.tm.opcode_modifier.vexndd) + { + /* For instructions with VexNDD, there should be + no memory operand and the register destination + is encoded in VEX prefix. */ + assert (i.mem_operands == 0 + && (op + 2) == i.operands); + vex_reg = op + 1; + } + else + assert (op < i.operands); + + if (vex_reg != (unsigned int) ~0) + { + assert (i.reg_operands == 2); + + if (!operand_type_equal (&i.tm.operand_types[vex_reg], + & regxmm) + && !operand_type_equal (&i.tm.operand_types[vex_reg], + ®ymm)) + abort (); + i.vex.register_specifier = i.op[vex_reg].regs; + } /* If there is an extension opcode to put here, the register number must be put into the regmem field. */ @@ -5276,40 +5787,71 @@ output_insn (void) unsigned int j; unsigned int prefix; - switch (i.tm.opcode_length) + /* Since the VEX prefix contains the implicit prefix, we don't + need the explicit prefix. */ + if (!i.tm.opcode_modifier.vex) { - case 3: - if (i.tm.base_opcode & 0xff000000) - { - prefix = (i.tm.base_opcode >> 24) & 0xff; - goto check_prefix; - } - break; - case 2: - if ((i.tm.base_opcode & 0xff0000) != 0) + switch (i.tm.opcode_length) { - prefix = (i.tm.base_opcode >> 16) & 0xff; - if (i.tm.cpu_flags.bitfield.cpupadlock) + case 3: + if (i.tm.base_opcode & 0xff000000) { + prefix = (i.tm.base_opcode >> 24) & 0xff; + goto check_prefix; + } + break; + case 2: + if ((i.tm.base_opcode & 0xff0000) != 0) + { + prefix = (i.tm.base_opcode >> 16) & 0xff; + if (i.tm.cpu_flags.bitfield.cpupadlock) + { check_prefix: - if (prefix != REPE_PREFIX_OPCODE - || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) + if (prefix != REPE_PREFIX_OPCODE + || (i.prefix[LOCKREP_PREFIX] + != REPE_PREFIX_OPCODE)) + add_prefix (prefix); + } + else add_prefix (prefix); } - else - add_prefix (prefix); + break; + case 1: + break; + default: + abort (); } - break; - case 1: - break; - default: - abort (); + + /* The prefix bytes. */ + for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) + if (*q) + FRAG_APPEND_1_CHAR (*q); } - /* The prefix bytes. */ - for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) - if (*q) - FRAG_APPEND_1_CHAR (*q); + if (i.tm.opcode_modifier.vex) + { + for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) + if (*q) + switch (j) + { + case REX_PREFIX: + /* REX byte is encoded in VEX prefix. */ + break; + case SEG_PREFIX: + case ADDR_PREFIX: + FRAG_APPEND_1_CHAR (*q); + break; + default: + /* There should be no other prefixes for instructions + with VEX prefix. */ + abort (); + } + + /* Now the VEX prefix. */ + p = frag_more (i.vex.length); + for (j = 0; j < i.vex.length; j++) + p[j] = i.vex.bytes[j]; + } /* Now the opcode; be careful about word order here! */ if (i.tm.opcode_length == 1) @@ -7250,6 +7792,7 @@ const char *md_shortopts = "qn"; #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) +#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) struct option md_longopts[] = { @@ -7265,6 +7808,7 @@ struct option md_longopts[] = {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, + {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof (md_longopts); @@ -7454,6 +7998,10 @@ md_parse_option (int c, char *arg) old_gcc = 1; break; + case OPTION_MSSE2AVX: + sse2avx = 1; + break; + default: return 0; } @@ -7497,8 +8045,8 @@ md_show_usage (stream) generic32, generic64\n\ EXTENSION is combination of:\n\ mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\ - vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\ - abm, padlock\n")); + avx, vmx, smx, xsave, aes, clmul, fma, 3dnow,\n\ + 3dnowa, sse4a, sse5, svme, abm, padlock\n")); fprintf (stream, _("\ -mtune=CPU optimize for CPU, CPU is one of:\n\ i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ @@ -7506,6 +8054,8 @@ md_show_usage (stream) core, core2, k6, k6_2, athlon, k8, amdfam10,\n\ generic32, generic64\n")); fprintf (stream, _("\ + -msse2avx encode SSE instructions with VEX prefix\n")); + fprintf (stream, _("\ -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); fprintf (stream, _("\ -msyntax=[att|intel] use AT&T/Intel syntax\n")); @@ -7943,7 +8493,7 @@ tc_gen_reloc (section, fixp) constant digits [[ radixOverride ]] - dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD + dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD digits decdigit | digits decdigit @@ -8059,6 +8609,7 @@ tc_gen_reloc (section, fixp) | TBYTE | OWORD | XMMWORD + | YMMWORD | . | $ | register @@ -8111,6 +8662,7 @@ static struct intel_token cur_token, prev_token; #define T_ID 13 #define T_SHL 14 #define T_SHR 15 +#define T_YMMWORD 16 /* Prototypes for intel parser functions. */ static int intel_match_token (int); @@ -8516,6 +9068,12 @@ intel_e09 (void) i.types[this_operand].bitfield.xmmword = 1; } + else if (prev_token.code == T_YMMWORD) + { + suffix = YMMWORD_MNEM_SUFFIX; + i.types[this_operand].bitfield.ymmword = 1; + } + else { as_bad (_("Unknown operand modifier `%s'"), prev_token.str); @@ -8699,6 +9257,7 @@ intel_e10 (void) | TBYTE | OWORD | XMMWORD + | YMMWORD | $ | . | register @@ -8894,7 +9453,8 @@ intel_e11 (void) | QWORD | TBYTE | OWORD - | XMMWORD */ + | XMMWORD + | YMMWORD */ case T_BYTE: case T_WORD: case T_DWORD: @@ -8902,6 +9462,7 @@ intel_e11 (void) case T_QWORD: case T_TBYTE: case T_XMMWORD: + case T_YMMWORD: intel_match_token (cur_token.code); if (cur_token.code == T_PTR) @@ -9167,6 +9728,9 @@ intel_get_token (void) || strcasecmp (new_token.str, "OWORD") == 0) new_token.code = T_XMMWORD; + else if (strcasecmp (new_token.str, "YMMWORD") == 0) + new_token.code = T_YMMWORD; + else if (strcasecmp (new_token.str, "PTR") == 0) new_token.code = T_PTR; diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 7f01ea0..105330e 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -120,9 +120,13 @@ accept various extension mnemonics. For example, @code{sse4.1}, @code{sse4.2}, @code{sse4}, +@code{avx}, @code{vmx}, @code{smx}, @code{xsave}, +@code{aes}, +@code{clmul}, +@code{fma}, @code{3dnow}, @code{3dnowa}, @code{sse4a}, @@ -145,6 +149,12 @@ generated. Valid @var{CPU} values are identical to the processor list of @option{-march=@var{CPU}}. +@cindex @samp{-msse2avx} option, i386 +@cindex @samp{-msse2avx} option, x86-64 +@item -msse2avx +This option specifies that the assembler should encode SSE instructions +with VEX prefix. + @cindex @samp{-mmnemonic=} option, i386 @cindex @samp{-mmnemonic=} option, x86-64 @item -mmnemonic=@var{att} @@ -821,7 +831,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{generic32} @tab @samp{generic64} @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} -@item @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave} +@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave} +@item @samp{.aes} @tab @samp{.clmul} @tab @samp{.fma} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.svme} @tab @samp{.abm} @item @samp{.padlock} diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 52d2ab6..d7e72eb 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,59 @@ +2008-04-03 H.J. Lu <hongjiu.lu@intel.com> + + * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, + x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, + x86-64-avx-intel and x86-64-inval-avx. + + * gas/cfi/cfi-i386.s: Add tests for AVX register maps. + * gas/cfi/cfi-x86_64.s: Likewise. + + * gas/i386/aes.d: New. + * gas/i386/aes.s: Likewise. + * gas/i386/aes-intel.d: Likewise. + * gas/i386/avx.d: Likewise. + * gas/i386/avx.s: Likewise. + * gas/i386/avx-intel.d: Likewise. + * gas/i386/clmul.d: Likewise. + * gas/i386/clmul-intel.d: Likewise. + * gas/i386/clmul.s: Likewise. + * gas/i386/i386.exp: Likewise. + * gas/i386/inval-avx.l: Likewise. + * gas/i386/inval-avx.s: Likewise. + * gas/i386/sse2avx.d: Likewise. + * gas/i386/sse2avx.s: Likewise. + * gas/i386/x86-64-aes.d: Likewise. + * gas/i386/x86-64-aes.s: Likewise. + * gas/i386/x86-64-aes-intel.d: Likewise. + * gas/i386/x86-64-avx.d: Likewise. + * gas/i386/x86-64-avx.s: Likewise. + * gas/i386/x86-64-avx-intel.d: Likewise. + * gas/i386/x86-64-clmul.d: Likewise. + * gas/i386/x86-64-clmul-intel.d: Likewise. + * gas/i386/x86-64-clmul.s: Likewise. + * gas/i386/x86-64-inval-avx.l: Likewise. + * gas/i386/x86-64-inval-avx.s: Likewise. + * gas/i386/x86-64-sse2avx.d: Likewise. + * gas/i386/x86-64-sse2avx.s: Likewise. + + * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. + * gas/i386/x86-64-arch-2.s: Likewise. + + * gas/i386/rexw.s: Add AVX tests. + + * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. + + * gas/cfi/cfi-i386.d: Updated. + * gas/cfi/cfi-x86_64.d: Likewise. + * gas/i386/arch-10.d: Likewise. + * gas/i386/arch-10-1.l: Likewise. + * gas/i386/arch-10-2.l: Likewise. + * gas/i386/arch-10-3.l: Likewise. + * gas/i386/arch-10-4.l: Likewise. + * gas/i386/rexw.d: Likewise. + * gas/i386/x86-64-arch-2.d: Likewise. + * gas/i386/x86-64-opcode-inval.d: Likewise. + * gas/i386/x86-64-opcode-inval-intel.d: Likewise. + 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com> From Jie Zhang <jie.zhang@analog.com> diff --git a/gas/testsuite/gas/cfi/cfi-i386.d b/gas/testsuite/gas/cfi/cfi-i386.d index ef477d3..38470da 100644 --- a/gas/testsuite/gas/cfi/cfi-i386.d +++ b/gas/testsuite/gas/cfi/cfi-i386.d @@ -57,7 +57,7 @@ The section .eh_frame contains: DW_CFA_undefined: r8 \(eip\) DW_CFA_nop -000000a0 00000094 00000018 FDE cie=0000008c pc=00000044..00000071 +000000a0 000000ac 00000018 FDE cie=0000008c pc=00000044..00000079 DW_CFA_advance_loc: 1 to 00000045 DW_CFA_undefined: r0 \(eax\) DW_CFA_advance_loc: 1 to 00000046 @@ -146,7 +146,24 @@ The section .eh_frame contains: DW_CFA_undefined: r35 \(mm6\) DW_CFA_advance_loc: 1 to 00000070 DW_CFA_undefined: r36 \(mm7\) + DW_CFA_advance_loc: 1 to 00000071 + DW_CFA_undefined: r53 \(ymm0\) + DW_CFA_advance_loc: 1 to 00000072 + DW_CFA_undefined: r54 \(ymm1\) + DW_CFA_advance_loc: 1 to 00000073 + DW_CFA_undefined: r55 \(ymm2\) + DW_CFA_advance_loc: 1 to 00000074 + DW_CFA_undefined: r56 \(ymm3\) + DW_CFA_advance_loc: 1 to 00000075 + DW_CFA_undefined: r57 \(ymm4\) + DW_CFA_advance_loc: 1 to 00000076 + DW_CFA_undefined: r58 \(ymm5\) + DW_CFA_advance_loc: 1 to 00000077 + DW_CFA_undefined: r59 \(ymm6\) + DW_CFA_advance_loc: 1 to 00000078 + DW_CFA_undefined: r60 \(ymm7\) DW_CFA_nop DW_CFA_nop DW_CFA_nop +#pass diff --git a/gas/testsuite/gas/cfi/cfi-i386.s b/gas/testsuite/gas/cfi/cfi-i386.s index 9da0db1..29119db 100644 --- a/gas/testsuite/gas/cfi/cfi-i386.s +++ b/gas/testsuite/gas/cfi/cfi-i386.s @@ -162,4 +162,13 @@ func_all_registers: .cfi_undefined mm6 ; nop .cfi_undefined mm7 ; nop + .cfi_undefined ymm0 ; nop + .cfi_undefined ymm1 ; nop + .cfi_undefined ymm2 ; nop + .cfi_undefined ymm3 ; nop + .cfi_undefined ymm4 ; nop + .cfi_undefined ymm5 ; nop + .cfi_undefined ymm6 ; nop + .cfi_undefined ymm7 ; nop + .cfi_endproc diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.d b/gas/testsuite/gas/cfi/cfi-x86_64.d index 3fc7d53..0f6566b 100644 --- a/gas/testsuite/gas/cfi/cfi-x86_64.d +++ b/gas/testsuite/gas/cfi/cfi-x86_64.d @@ -94,7 +94,7 @@ The section .eh_frame contains: DW_CFA_undefined: r16 \(rip\) DW_CFA_nop -000000e8 000000cc 00000018 FDE cie=000000d4 pc=00000058..00000097 +000000e8 000000fc 00000018 FDE cie=000000d4 pc=00000058..000000a7 DW_CFA_advance_loc: 1 to 00000059 DW_CFA_undefined: r0 \(rax\) DW_CFA_advance_loc: 1 to 0000005a @@ -219,9 +219,42 @@ The section .eh_frame contains: DW_CFA_undefined: r47 \(mm6\) DW_CFA_advance_loc: 1 to 00000096 DW_CFA_undefined: r48 \(mm7\) + DW_CFA_advance_loc: 1 to 00000097 + DW_CFA_undefined: r70 \(ymm0\) + DW_CFA_advance_loc: 1 to 00000098 + DW_CFA_undefined: r71 \(ymm1\) + DW_CFA_advance_loc: 1 to 00000099 + DW_CFA_undefined: r72 \(ymm2\) + DW_CFA_advance_loc: 1 to 0000009a + DW_CFA_undefined: r73 \(ymm3\) + DW_CFA_advance_loc: 1 to 0000009b + DW_CFA_undefined: r74 \(ymm4\) + DW_CFA_advance_loc: 1 to 0000009c + DW_CFA_undefined: r75 \(ymm5\) + DW_CFA_advance_loc: 1 to 0000009d + DW_CFA_undefined: r76 \(ymm6\) + DW_CFA_advance_loc: 1 to 0000009e + DW_CFA_undefined: r77 \(ymm7\) + DW_CFA_advance_loc: 1 to 0000009f + DW_CFA_undefined: r78 \(ymm8\) + DW_CFA_advance_loc: 1 to 000000a0 + DW_CFA_undefined: r79 \(ymm9\) + DW_CFA_advance_loc: 1 to 000000a1 + DW_CFA_undefined: r80 \(ymm10\) + DW_CFA_advance_loc: 1 to 000000a2 + DW_CFA_undefined: r81 \(ymm11\) + DW_CFA_advance_loc: 1 to 000000a3 + DW_CFA_undefined: r82 \(ymm12\) + DW_CFA_advance_loc: 1 to 000000a4 + DW_CFA_undefined: r83 \(ymm13\) + DW_CFA_advance_loc: 1 to 000000a5 + DW_CFA_undefined: r84 \(ymm14\) + DW_CFA_advance_loc: 1 to 000000a6 + DW_CFA_undefined: r85 \(ymm15\) DW_CFA_nop DW_CFA_nop DW_CFA_nop DW_CFA_nop DW_CFA_nop +#pass diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.s b/gas/testsuite/gas/cfi/cfi-x86_64.s index 65c2aa2..4fbc4e1 100644 --- a/gas/testsuite/gas/cfi/cfi-x86_64.s +++ b/gas/testsuite/gas/cfi/cfi-x86_64.s @@ -211,4 +211,21 @@ func_all_registers: .cfi_undefined mm6 ; nop .cfi_undefined mm7 ; nop + .cfi_undefined ymm0 ; nop + .cfi_undefined ymm1 ; nop + .cfi_undefined ymm2 ; nop + .cfi_undefined ymm3 ; nop + .cfi_undefined ymm4 ; nop + .cfi_undefined ymm5 ; nop + .cfi_undefined ymm6 ; nop + .cfi_undefined ymm7 ; nop + .cfi_undefined ymm8 ; nop + .cfi_undefined ymm9 ; nop + .cfi_undefined ymm10 ; nop + .cfi_undefined ymm11 ; nop + .cfi_undefined ymm12 ; nop + .cfi_undefined ymm13 ; nop + .cfi_undefined ymm14 ; nop + .cfi_undefined ymm15 ; nop + .cfi_endproc diff --git a/gas/testsuite/gas/i386/aes-intel.d b/gas/testsuite/gas/i386/aes-intel.d new file mode 100644 index 0000000..78d42ec --- /dev/null +++ b/gas/testsuite/gas/i386/aes-intel.d @@ -0,0 +1,34 @@ +#source: aes.s +#objdump: -dw -Mintel +#name: i386 AES (Intel mode) + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist xmm0,XMMWORD PTR \[ecx\],0x8 +[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist xmm0,xmm1,0x8 +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist xmm0,XMMWORD PTR \[ecx\],0x8 +[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist xmm0,xmm1,0x8 +#pass diff --git a/gas/testsuite/gas/i386/aes.d b/gas/testsuite/gas/i386/aes.d new file mode 100644 index 0000000..5bbb9c9 --- /dev/null +++ b/gas/testsuite/gas/i386/aes.d @@ -0,0 +1,33 @@ +#objdump: -dw +#name: i386 AES + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist \$0x8,\(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist \$0x8,\(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist \$0x8,%xmm1,%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/aes.s b/gas/testsuite/gas/i386/aes.s new file mode 100644 index 0000000..3d570cb --- /dev/null +++ b/gas/testsuite/gas/i386/aes.s @@ -0,0 +1,30 @@ +# Check AES new instructions. + + .text +foo: + aesenc (%ecx),%xmm0 + aesenc %xmm1,%xmm0 + aesenclast (%ecx),%xmm0 + aesenclast %xmm1,%xmm0 + aesdec (%ecx),%xmm0 + aesdec %xmm1,%xmm0 + aesdeclast (%ecx),%xmm0 + aesdeclast %xmm1,%xmm0 + aesimc (%ecx),%xmm0 + aesimc %xmm1,%xmm0 + aeskeygenassist $8,(%ecx),%xmm0 + aeskeygenassist $8,%xmm1,%xmm0 + + .intel_syntax noprefix + aesenc xmm0,XMMWORD PTR [ecx] + aesenc xmm0,xmm1 + aesenclast xmm0,XMMWORD PTR [ecx] + aesenclast xmm0,xmm1 + aesdec xmm0,XMMWORD PTR [ecx] + aesdec xmm0,xmm1 + aesdeclast xmm0,XMMWORD PTR [ecx] + aesdeclast xmm0,xmm1 + aesimc xmm0,XMMWORD PTR [ecx] + aesimc xmm0,xmm1 + aeskeygenassist xmm0,XMMWORD PTR [ecx],8 + aeskeygenassist xmm0,xmm1,8 diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l index 8feaf90..af717c4 100644 --- a/gas/testsuite/gas/i386/arch-10-1.l +++ b/gas/testsuite/gas/i386/arch-10-1.l @@ -17,6 +17,10 @@ .*:34: Error: .* .*:36: Error: .* .*:38: Error: .* +.*:40: Error: .* +.*:42: Error: .* +.*:44: Error: .* +.*:46: Error: .* GAS LISTING .* @@ -39,23 +43,31 @@ GAS LISTING .* [ ]*16[ ]+phminposuw %xmm1,%xmm3 [ ]*17[ ]+\# SSE4\.2 [ ]*18[ ]+crc32 %ecx,%ebx -[ ]*19[ ]+\# VMX -[ ]*20[ ]+vmxoff -[ ]*21[ ]+\# SMX -[ ]*22[ ]+getsec -[ ]*23[ ]+\# Xsave -[ ]*24[ ]+xgetbv -[ ]*25[ ]+\# 3DNow -[ ]*26[ ]+pmulhrw %mm4,%mm3 -[ ]*27[ ]+\# 3DNow Extensions -[ ]*28[ ]+pswapd %mm4,%mm3 -[ ]*29[ ]+\# SSE4a -[ ]*30[ ]+insertq %xmm2,%xmm1 -[ ]*31[ ]+\# SVME -[ ]*32[ ]+vmload -[ ]*33[ ]+\# ABM -[ ]*34[ ]+lzcnt %ecx,%ebx -[ ]*35[ ]+\# SSE5 -[ ]*36[ ]+frczss %xmm2, %xmm1 -[ ]*37[ ]+\# PadLock -[ ]*38[ ]+xstorerng +[ ]*19[ ]+\# AVX +[ ]*20[ ]+vzeroall +[ ]*21[ ]+\# VMX +[ ]*22[ ]+vmxoff +[ ]*23[ ]+\# SMX +[ ]*24[ ]+getsec +[ ]*25[ ]+\# Xsave +[ ]*26[ ]+xgetbv +[ ]*27[ ]+\# AES +[ ]*28[ ]+aesenc \(%ecx\),%xmm0 +[ ]*29[ ]+\# CLMUL +[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0 +[ ]*31[ ]+\# FMA +[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*33[ ]+\# 3DNow +[ ]*34[ ]+pmulhrw %mm4,%mm3 +[ ]*35[ ]+\# 3DNow Extensions +[ ]*36[ ]+pswapd %mm4,%mm3 +[ ]*37[ ]+\# SSE4a +[ ]*38[ ]+insertq %xmm2,%xmm1 +[ ]*39[ ]+\# SVME +[ ]*40[ ]+vmload +[ ]*41[ ]+\# ABM +[ ]*42[ ]+lzcnt %ecx,%ebx +[ ]*43[ ]+\# SSE5 +[ ]*44[ ]+frczss %xmm2, %xmm1 +[ ]*45[ ]+\# PadLock +[ ]*46[ ]+xstorerng diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l index 430b0c2..714c099 100644 --- a/gas/testsuite/gas/i386/arch-10-2.l +++ b/gas/testsuite/gas/i386/arch-10-2.l @@ -16,6 +16,10 @@ .*:34: Error: .* .*:36: Error: .* .*:38: Error: .* +.*:40: Error: .* +.*:42: Error: .* +.*:44: Error: .* +.*:46: Error: .* GAS LISTING .* @@ -38,23 +42,31 @@ GAS LISTING .* [ ]*16[ ]+phminposuw %xmm1,%xmm3 [ ]*17[ ]+\# SSE4\.2 [ ]*18[ ]+crc32 %ecx,%ebx -[ ]*19[ ]+\# VMX -[ ]*20[ ]+vmxoff -[ ]*21[ ]+\# SMX -[ ]*22[ ]+getsec -[ ]*23[ ]+\# Xsave -[ ]*24[ ]+xgetbv -[ ]*25[ ]+\# 3DNow -[ ]*26[ ]+pmulhrw %mm4,%mm3 -[ ]*27[ ]+\# 3DNow Extensions -[ ]*28[ ]+pswapd %mm4,%mm3 -[ ]*29[ ]+\# SSE4a -[ ]*30[ ]+insertq %xmm2,%xmm1 -[ ]*31[ ]+\# SVME -[ ]*32[ ]+vmload -[ ]*33[ ]+\# ABM -[ ]*34[ ]+lzcnt %ecx,%ebx -[ ]*35[ ]+\# SSE5 -[ ]*36[ ]+frczss %xmm2, %xmm1 -[ ]*37[ ]+\# PadLock -[ ]*38[ ]+xstorerng +[ ]*19[ ]+\# AVX +[ ]*20[ ]+vzeroall +[ ]*21[ ]+\# VMX +[ ]*22[ ]+vmxoff +[ ]*23[ ]+\# SMX +[ ]*24[ ]+getsec +[ ]*25[ ]+\# Xsave +[ ]*26[ ]+xgetbv +[ ]*27[ ]+\# AES +[ ]*28[ ]+aesenc \(%ecx\),%xmm0 +[ ]*29[ ]+\# CLMUL +[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0 +[ ]*31[ ]+\# FMA +[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*33[ ]+\# 3DNow +[ ]*34[ ]+pmulhrw %mm4,%mm3 +[ ]*35[ ]+\# 3DNow Extensions +[ ]*36[ ]+pswapd %mm4,%mm3 +[ ]*37[ ]+\# SSE4a +[ ]*38[ ]+insertq %xmm2,%xmm1 +[ ]*39[ ]+\# SVME +[ ]*40[ ]+vmload +[ ]*41[ ]+\# ABM +[ ]*42[ ]+lzcnt %ecx,%ebx +[ ]*43[ ]+\# SSE5 +[ ]*44[ ]+frczss %xmm2, %xmm1 +[ ]*45[ ]+\# PadLock +[ ]*46[ ]+xstorerng diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l index f7320e5..3315a98 100644 --- a/gas/testsuite/gas/i386/arch-10-3.l +++ b/gas/testsuite/gas/i386/arch-10-3.l @@ -9,6 +9,10 @@ .*:34: Error: .* .*:36: Error: .* .*:38: Error: .* +.*:40: Error: .* +.*:42: Error: .* +.*:44: Error: .* +.*:46: Error: .* GAS LISTING .* @@ -34,23 +38,31 @@ GAS LISTING .* [ ]*17[ ]+\# SSE4\.2 [ ]*18[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx [ ]*18[ ]+D9 -[ ]*19[ ]+\# VMX -[ ]*20[ ]+vmxoff -[ ]*21[ ]+\# SMX -[ ]*22[ ]+getsec -[ ]*23[ ]+\# Xsave -[ ]*24[ ]+xgetbv -[ ]*25[ ]+\# 3DNow -[ ]*26[ ]+pmulhrw %mm4,%mm3 -[ ]*27[ ]+\# 3DNow Extensions -[ ]*28[ ]+pswapd %mm4,%mm3 -[ ]*29[ ]+\# SSE4a -[ ]*30[ ]+insertq %xmm2,%xmm1 -[ ]*31[ ]+\# SVME -[ ]*32[ ]+vmload -[ ]*33[ ]+\# ABM -[ ]*34[ ]+lzcnt %ecx,%ebx -[ ]*35[ ]+\# SSE5 -[ ]*36[ ]+frczss %xmm2, %xmm1 -[ ]*37[ ]+\# PadLock -[ ]*38[ ]+xstorerng +[ ]*19[ ]+\# AVX +[ ]*20[ ]+vzeroall +[ ]*21[ ]+\# VMX +[ ]*22[ ]+vmxoff +[ ]*23[ ]+\# SMX +[ ]*24[ ]+getsec +[ ]*25[ ]+\# Xsave +[ ]*26[ ]+xgetbv +[ ]*27[ ]+\# AES +[ ]*28[ ]+aesenc \(%ecx\),%xmm0 +[ ]*29[ ]+\# CLMUL +[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0 +[ ]*31[ ]+\# FMA +[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*33[ ]+\# 3DNow +[ ]*34[ ]+pmulhrw %mm4,%mm3 +[ ]*35[ ]+\# 3DNow Extensions +[ ]*36[ ]+pswapd %mm4,%mm3 +[ ]*37[ ]+\# SSE4a +[ ]*38[ ]+insertq %xmm2,%xmm1 +[ ]*39[ ]+\# SVME +[ ]*40[ ]+vmload +[ ]*41[ ]+\# ABM +[ ]*42[ ]+lzcnt %ecx,%ebx +[ ]*43[ ]+\# SSE5 +[ ]*44[ ]+frczss %xmm2, %xmm1 +[ ]*45[ ]+\# PadLock +[ ]*46[ ]+xstorerng diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l index 3cda861..eec46a3 100644 --- a/gas/testsuite/gas/i386/arch-10-4.l +++ b/gas/testsuite/gas/i386/arch-10-4.l @@ -1,5 +1,5 @@ .*: Assembler messages: -.*:24: Error: .* +.*:20: Error: .* .*:26: Error: .* .*:28: Error: .* .*:30: Error: .* @@ -7,6 +7,10 @@ .*:34: Error: .* .*:36: Error: .* .*:38: Error: .* +.*:40: Error: .* +.*:42: Error: .* +.*:44: Error: .* +.*:46: Error: .* GAS LISTING .* @@ -32,23 +36,31 @@ GAS LISTING .* [ ]*17[ ]+\# SSE4\.2 [ ]*18[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx [ ]*18[ ]+D9 -[ ]*19[ ]+\# VMX -[ ]*20[ ]+\?\?\?\? 0F01C4 vmxoff -[ ]*21[ ]+\# SMX -[ ]*22[ ]+\?\?\?\? 0F37 getsec -[ ]*23[ ]+\# Xsave -[ ]*24[ ]+xgetbv -[ ]*25[ ]+\# 3DNow -[ ]*26[ ]+pmulhrw %mm4,%mm3 -[ ]*27[ ]+\# 3DNow Extensions -[ ]*28[ ]+pswapd %mm4,%mm3 -[ ]*29[ ]+\# SSE4a -[ ]*30[ ]+insertq %xmm2,%xmm1 -[ ]*31[ ]+\# SVME -[ ]*32[ ]+vmload -[ ]*33[ ]+\# ABM -[ ]*34[ ]+lzcnt %ecx,%ebx -[ ]*35[ ]+\# SSE5 -[ ]*36[ ]+frczss %xmm2, %xmm1 -[ ]*37[ ]+\# PadLock -[ ]*38[ ]+xstorerng +[ ]*19[ ]+\# AVX +[ ]*20[ ]+vzeroall +[ ]*21[ ]+\# VMX +[ ]*22[ ]+\?\?\?\? 0F01C4 vmxoff +[ ]*23[ ]+\# SMX +[ ]*24[ ]+\?\?\?\? 0F37 getsec +[ ]*25[ ]+\# Xsave +[ ]*26[ ]+xgetbv +[ ]*27[ ]+\# AES +[ ]*28[ ]+aesenc \(%ecx\),%xmm0 +[ ]*29[ ]+\# CLMUL +[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0 +[ ]*31[ ]+\# FMA +[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*33[ ]+\# 3DNow +[ ]*34[ ]+pmulhrw %mm4,%mm3 +[ ]*35[ ]+\# 3DNow Extensions +[ ]*36[ ]+pswapd %mm4,%mm3 +[ ]*37[ ]+\# SSE4a +[ ]*38[ ]+insertq %xmm2,%xmm1 +[ ]*39[ ]+\# SVME +[ ]*40[ ]+vmload +[ ]*41[ ]+\# ABM +[ ]*42[ ]+lzcnt %ecx,%ebx +[ ]*43[ ]+\# SSE5 +[ ]*44[ ]+frczss %xmm2, %xmm1 +[ ]*45[ ]+\# PadLock +[ ]*46[ ]+xstorerng diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d index 81e6598..60b44d4 100644 --- a/gas/testsuite/gas/i386/arch-10.d +++ b/gas/testsuite/gas/i386/arch-10.d @@ -1,4 +1,4 @@ -#as: -march=i686+sse4+vmx+smx+xsave+sse5+3dnowa+svme+padlock +#as: -march=i686+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock #objdump: -dw #name: i386 arch 10 @@ -15,9 +15,13 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3 [ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3 [ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[a-f0-9]+: c5 fc 77 vzeroall [ ]*[a-f0-9]+: 0f 01 c4 vmxoff [ ]*[a-f0-9]+: 0f 37 getsec [ ]*[a-f0-9]+: 0f 01 d0 xgetbv +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 [ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3 [ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3 [ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1 diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s index e5e799d..afa3c3b 100644 --- a/gas/testsuite/gas/i386/arch-10.s +++ b/gas/testsuite/gas/i386/arch-10.s @@ -16,12 +16,20 @@ phaddw %xmm4,%xmm3 phminposuw %xmm1,%xmm3 # SSE4.2 crc32 %ecx,%ebx +# AVX +vzeroall # VMX vmxoff # SMX getsec # Xsave xgetbv +# AES +aesenc (%ecx),%xmm0 +# CLMUL +pclmulqdq $8,%xmm1,%xmm0 +# FMA +vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 # 3DNow pmulhrw %mm4,%mm3 # 3DNow Extensions diff --git a/gas/testsuite/gas/i386/avx-intel.d b/gas/testsuite/gas/i386/avx-intel.d new file mode 100644 index 0000000..8d8772d --- /dev/null +++ b/gas/testsuite/gas/i386/avx-intel.d @@ -0,0 +1,2759 @@ +#objdump: -dwMintel +#name: i386 AVX (Intel disassembly) +#source: avx.s + +.*: +file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: c5 fc 77 vzeroall +[ ]*[a-f0-9]+: c5 f8 77 vzeroupper +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 5d 2d 31 vmaskmovpd ymm6,ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd YMMWORD PTR \[ecx\],ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps ymm6,ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[ecx\],ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 58 11 vaddps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd d0 d4 vaddsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd d0 11 vaddsubpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cf d0 d4 vaddsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf d0 11 vaddsubps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 55 d4 vandnpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 55 11 vandnpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 55 d4 vandnps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 55 11 vandnps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 54 d4 vandpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 54 11 vandpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 54 d4 vandps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 54 11 vandps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 5e d4 vdivpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5e 11 vdivpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 5e d4 vdivps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5e 11 vdivps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 7c d4 vhaddpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 7c 11 vhaddpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cf 7c d4 vhaddps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf 7c 11 vhaddps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 7d d4 vhsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 7d 11 vhsubpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cf 7d d4 vhsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf 7d 11 vhsubps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 5f d4 vmaxpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5f 11 vmaxpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 5f d4 vmaxps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5f 11 vmaxps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 5d d4 vminpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5d 11 vminpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 5d d4 vminps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5d 11 vminps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 59 d4 vmulpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 59 11 vmulpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 59 d4 vmulps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 59 11 vmulps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 56 d4 vorpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 56 11 vorpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 56 d4 vorps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 56 11 vorps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 4d 0d d4 vpermilpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 4d 0d 11 vpermilpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 4d 0c d4 vpermilps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 4d 0c 11 vpermilps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 5c d4 vsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5c 11 vsubpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 5c d4 vsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5c 11 vsubps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 15 d4 vunpckhpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 15 11 vunpckhpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 15 d4 vunpckhps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 15 11 vunpckhps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 14 d4 vunpcklpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 14 11 vunpcklpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 14 d4 vunpcklps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 14 11 vunpcklps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 57 d4 vxorpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 57 11 vxorpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 57 d4 vxorps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 57 11 vxorps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 10 vcmpeq_ospd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 11 vcmplt_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 11 vcmplt_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 12 vcmple_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 12 vcmple_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 13 vcmpunord_spd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 13 vcmpunord_spd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 14 vcmpneq_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 14 vcmpneq_uspd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 15 vcmpnlt_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 15 vcmpnlt_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 16 vcmpnle_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 16 vcmpnle_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 17 vcmpord_spd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 17 vcmpord_spd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 18 vcmpeq_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 18 vcmpeq_uspd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 19 vcmpnge_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 19 vcmpnge_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1a vcmpngt_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1a vcmpngt_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1b vcmpfalse_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1b vcmpfalse_ospd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1c vcmpneq_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1c vcmpneq_ospd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1d vcmpge_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1d vcmpge_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1e vcmpgt_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1e vcmpgt_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1f vcmptrue_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 10 vcmpeq_osps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 11 vcmplt_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 11 vcmplt_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 12 vcmple_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 12 vcmple_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 13 vcmpunord_sps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 13 vcmpunord_sps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 14 vcmpneq_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 14 vcmpneq_usps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 15 vcmpnlt_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 15 vcmpnlt_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 16 vcmpnle_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 16 vcmpnle_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 17 vcmpord_sps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 17 vcmpord_sps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 18 vcmpeq_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 18 vcmpeq_usps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 19 vcmpnge_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 19 vcmpnge_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1a vcmpngt_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1a vcmpngt_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1b vcmpfalse_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1b vcmpfalse_osps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1c vcmpneq_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1c vcmpneq_osps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1d vcmpge_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1d vcmpge_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1e vcmpgt_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4 +[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2ps xmm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq xmm4,ymm4 +[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dq xmm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[ecx\] +[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd ymm7,ymm2,ymm6,ymm4,0xa +[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps ymm7,ymm2,ymm6,ymm4,0xa +[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa +[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 ymm6,ymm4,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 xmm4,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[ecx\],ymm4,0x64 +[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dq xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2ps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dq xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 0e f4 vtestps xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0e 21 vtestps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 0f f4 vtestpd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0f 21 vtestpd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu xmm4,\[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fe e6 e4 vcvtdq2pd ymm4,xmm4 +[ ]*[a-f0-9]+: c5 fe e6 21 vcvtdq2pd ymm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 5a e4 vcvtps2pd ymm4,xmm4 +[ ]*[a-f0-9]+: c5 fc 5a 21 vcvtps2pd ymm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 58 d4 vaddpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 58 39 vaddpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 58 d4 vaddps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 58 39 vaddps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d0 d4 vaddsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d0 39 vaddsubpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb d0 d4 vaddsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb d0 39 vaddsubps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 55 d4 vandnpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 55 39 vandnpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 55 d4 vandnps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 55 39 vandnps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 54 d4 vandpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 54 39 vandpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 54 d4 vandps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 54 39 vandps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 5e d4 vdivpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5e 39 vdivpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 5e d4 vdivps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5e 39 vdivps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 7c d4 vhaddpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 7c 39 vhaddpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 7c d4 vhaddps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 7c 39 vhaddps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 7d d4 vhsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 7d 39 vhsubpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 7d d4 vhsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 7d 39 vhsubps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 5f d4 vmaxpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5f 39 vmaxpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 5f d4 vmaxps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5f 39 vmaxps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 5d d4 vminpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5d 39 vminpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 5d d4 vminps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5d 39 vminps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 59 d4 vmulpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 59 39 vmulpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 59 d4 vmulps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 59 39 vmulps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 56 d4 vorpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 56 39 vorpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 56 d4 vorps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 56 39 vorps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 63 d4 vpacksswb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 63 39 vpacksswb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 6b d4 vpackssdw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6b 39 vpackssdw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 67 d4 vpackuswb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 67 39 vpackuswb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 2b d4 vpackusdw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 2b 39 vpackusdw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fc d4 vpaddb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fc 39 vpaddb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fd d4 vpaddw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fd 39 vpaddw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fe d4 vpaddd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fe 39 vpaddd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d4 d4 vpaddq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d4 39 vpaddq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ec d4 vpaddsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ec 39 vpaddsb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ed d4 vpaddsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ed 39 vpaddsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 dc d4 vpaddusb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 dc 39 vpaddusb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 dd d4 vpaddusw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 dd 39 vpaddusw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 db d4 vpand xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 db 39 vpand xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 df d4 vpandn xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 df 39 vpandn xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e0 d4 vpavgb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e0 39 vpavgb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e3 d4 vpavgw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e3 39 vpavgw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 74 d4 vpcmpeqb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 74 39 vpcmpeqb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 75 d4 vpcmpeqw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 75 39 vpcmpeqw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 76 d4 vpcmpeqd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 76 39 vpcmpeqd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 29 d4 vpcmpeqq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 29 39 vpcmpeqq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 64 d4 vpcmpgtb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 64 39 vpcmpgtb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 65 d4 vpcmpgtw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 65 39 vpcmpgtw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 66 d4 vpcmpgtd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 66 39 vpcmpgtd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 37 d4 vpcmpgtq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 37 39 vpcmpgtq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 0d d4 vpermilpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0d 39 vpermilpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 0c d4 vpermilps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0c 39 vpermilps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 01 d4 vphaddw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 01 39 vphaddw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 02 d4 vphaddd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 02 39 vphaddd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 03 d4 vphaddsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 03 39 vphaddsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 05 d4 vphsubw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 05 39 vphsubw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 06 d4 vphsubd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 06 39 vphsubd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 07 d4 vphsubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 07 39 vphsubsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f5 d4 vpmaddwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f5 39 vpmaddwd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 04 d4 vpmaddubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 04 39 vpmaddubsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3c d4 vpmaxsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3c 39 vpmaxsb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ee d4 vpmaxsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ee 39 vpmaxsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3d d4 vpmaxsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3d 39 vpmaxsd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 de d4 vpmaxub xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 de 39 vpmaxub xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3e d4 vpmaxuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3e 39 vpmaxuw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3f d4 vpmaxud xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3f 39 vpmaxud xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 38 d4 vpminsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 38 39 vpminsb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ea d4 vpminsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ea 39 vpminsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 39 d4 vpminsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 39 39 vpminsd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 da d4 vpminub xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 da 39 vpminub xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3a d4 vpminuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3a 39 vpminuw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3b d4 vpminud xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3b 39 vpminud xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e4 d4 vpmulhuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e4 39 vpmulhuw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 0b d4 vpmulhrsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0b 39 vpmulhrsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e5 d4 vpmulhw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e5 39 vpmulhw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d5 d4 vpmullw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d5 39 vpmullw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 40 d4 vpmulld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 40 39 vpmulld xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f4 d4 vpmuludq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f4 39 vpmuludq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 28 d4 vpmuldq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 28 39 vpmuldq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 eb d4 vpor xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 eb 39 vpor xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f6 d4 vpsadbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f6 39 vpsadbw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 00 d4 vpshufb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 00 39 vpshufb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 08 d4 vpsignb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 08 39 vpsignb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 09 d4 vpsignw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 09 39 vpsignw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 0a d4 vpsignd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0a 39 vpsignd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f1 d4 vpsllw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f1 39 vpsllw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f2 d4 vpslld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f2 39 vpslld xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f3 d4 vpsllq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f3 39 vpsllq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e1 d4 vpsraw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e1 39 vpsraw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e2 d4 vpsrad xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e2 39 vpsrad xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d1 d4 vpsrlw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d1 39 vpsrlw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d2 d4 vpsrld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d2 39 vpsrld xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d3 d4 vpsrlq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d3 39 vpsrlq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f8 d4 vpsubb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f8 39 vpsubb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f9 d4 vpsubw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f9 39 vpsubw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fa d4 vpsubd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fa 39 vpsubd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fb d4 vpsubq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fb 39 vpsubq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e8 d4 vpsubsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e8 39 vpsubsb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e9 d4 vpsubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e9 39 vpsubsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d8 d4 vpsubusb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d8 39 vpsubusb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d9 d4 vpsubusw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d9 39 vpsubusw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 68 d4 vpunpckhbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 68 39 vpunpckhbw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 69 d4 vpunpckhwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 69 39 vpunpckhwd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 6a d4 vpunpckhdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6a 39 vpunpckhdq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 6d d4 vpunpckhqdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6d 39 vpunpckhqdq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 60 d4 vpunpcklbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 60 39 vpunpcklbw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 61 d4 vpunpcklwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 61 39 vpunpcklwd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 62 d4 vpunpckldq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 62 39 vpunpckldq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 6c d4 vpunpcklqdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6c 39 vpunpcklqdq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ef d4 vpxor xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ef 39 vpxor xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 5c d4 vsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5c 39 vsubpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 5c d4 vsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5c 39 vsubps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 15 d4 vunpckhpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 15 39 vunpckhpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 15 d4 vunpckhps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 15 39 vunpckhps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 14 d4 vunpcklpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 14 39 vunpcklpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 14 d4 vunpcklps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 14 39 vunpcklps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 57 d4 vxorpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 57 39 vxorpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 57 d4 vxorps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 57 39 vxorps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 00 vcmpeqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 00 vcmpeqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 01 vcmpltpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 01 vcmpltpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 02 vcmplepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 02 vcmplepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 03 vcmpunordpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 03 vcmpunordpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 04 vcmpneqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 04 vcmpneqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 05 vcmpnltpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 05 vcmpnltpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 06 vcmpnlepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 06 vcmpnlepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 07 vcmpordpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 08 vcmpeq_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 08 vcmpeq_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 09 vcmpngepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 09 vcmpngepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0a vcmpngtpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0a vcmpngtpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0b vcmpfalsepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0b vcmpfalsepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0c vcmpneq_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0c vcmpneq_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0d vcmpgepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0d vcmpgepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0e vcmpgtpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0e vcmpgtpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0f vcmptruepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0f vcmptruepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 10 vcmpeq_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 10 vcmpeq_ospd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 11 vcmplt_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 11 vcmplt_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 12 vcmple_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 12 vcmple_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 13 vcmpunord_spd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 13 vcmpunord_spd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 14 vcmpneq_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 14 vcmpneq_uspd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 15 vcmpnlt_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 15 vcmpnlt_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 16 vcmpnle_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 16 vcmpnle_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 17 vcmpord_spd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 17 vcmpord_spd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 18 vcmpeq_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 18 vcmpeq_uspd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 19 vcmpnge_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 19 vcmpnge_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1a vcmpngt_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1a vcmpngt_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1b vcmpfalse_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1b vcmpfalse_ospd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1c vcmpneq_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1c vcmpneq_ospd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1d vcmpge_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1d vcmpge_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1e vcmpgt_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1e vcmpgt_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1f vcmptrue_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1f vcmptrue_uspd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 00 vcmpeqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 00 vcmpeqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 01 vcmpltps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 01 vcmpltps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 02 vcmpleps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 02 vcmpleps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 03 vcmpunordps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 03 vcmpunordps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 04 vcmpneqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 04 vcmpneqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 05 vcmpnltps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 05 vcmpnltps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 06 vcmpnleps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 06 vcmpnleps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 07 vcmpordps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 08 vcmpeq_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 08 vcmpeq_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 09 vcmpngeps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 09 vcmpngeps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0a vcmpngtps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0a vcmpngtps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0b vcmpfalseps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0b vcmpfalseps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0c vcmpneq_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0c vcmpneq_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0d vcmpgeps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0d vcmpgeps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0e vcmpgtps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0e vcmpgtps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0f vcmptrueps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0f vcmptrueps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 10 vcmpeq_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 10 vcmpeq_osps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 11 vcmplt_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 11 vcmplt_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 12 vcmple_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 12 vcmple_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 13 vcmpunord_sps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 13 vcmpunord_sps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 14 vcmpneq_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 14 vcmpneq_usps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 15 vcmpnlt_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 15 vcmpnlt_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 16 vcmpnle_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 16 vcmpnle_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 17 vcmpord_sps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 17 vcmpord_sps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 18 vcmpeq_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 18 vcmpeq_usps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 19 vcmpnge_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 19 vcmpnge_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1a vcmpngt_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1a vcmpngt_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1b vcmpfalse_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1b vcmpfalse_osps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1c vcmpneq_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1c vcmpneq_osps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1d vcmpge_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1d vcmpge_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1e vcmpgt_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[ecx\],xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[ecx\],xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd xmm7,xmm2,xmm6,xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa +[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps xmm7,xmm2,xmm6,xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa +[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa +[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si ecx,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si ecx,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd xmm6,xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps xmm6,xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd xmm6,xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 e9 6b fc 60 vfmaddsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6b 39 60 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6b 39 40 vfmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6f fc 60 vfmsubsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6f 39 60 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6f 39 40 vfmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7b fc 60 vfnmaddsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7b 39 60 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7b 39 40 vfnmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7f fc 60 vfnmsubsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7f 39 60 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7f 39 40 vfnmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5a 11 vcvtsd2ss xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5e d4 vdivsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5e 11 vdivsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5f d4 vmaxsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5f 11 vmaxsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5d d4 vminsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5d 11 vminsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 59 d4 vmulsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 59 11 vmulsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 51 d4 vsqrtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 51 11 vsqrtsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5c d4 vsubsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 10 vcmpeq_ossd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 11 vcmplt_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 11 vcmplt_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 12 vcmple_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 12 vcmple_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 13 vcmpunord_ssd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 13 vcmpunord_ssd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 14 vcmpneq_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 14 vcmpneq_ussd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 15 vcmpnlt_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 15 vcmpnlt_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 16 vcmpnle_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 16 vcmpnle_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 17 vcmpord_ssd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 17 vcmpord_ssd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 18 vcmpeq_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 18 vcmpeq_ussd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 19 vcmpnge_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 19 vcmpnge_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1a vcmpngt_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1a vcmpngt_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1b vcmpfalse_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1b vcmpfalse_ossd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1c vcmpneq_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1c vcmpneq_ossd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1d vcmpge_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1d vcmpge_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1e vcmpgt_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5a 11 vcvtss2sd xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5e d4 vdivss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5e 11 vdivss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5f d4 vmaxss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5f 11 vmaxss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5d d4 vminss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5d 11 vminss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 59 d4 vmulss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 59 11 vmulss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 53 d4 vrcpss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 53 11 vrcpss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 52 d4 vrsqrtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 52 11 vrsqrtss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 51 d4 vsqrtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 51 11 vsqrtss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5c d4 vsubss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 10 vcmpeq_osss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 11 vcmplt_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 11 vcmplt_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 12 vcmple_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 12 vcmple_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 13 vcmpunord_sss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 13 vcmpunord_sss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 14 vcmpneq_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 14 vcmpneq_usss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 15 vcmpnlt_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 15 vcmpnlt_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 16 vcmpnle_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 16 vcmpnle_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 17 vcmpord_sss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 17 vcmpord_sss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 18 vcmpeq_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 18 vcmpeq_usss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 19 vcmpnge_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 19 vcmpnge_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1a vcmpngt_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1a vcmpngt_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1b vcmpfalse_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1b vcmpfalse_osss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1c vcmpneq_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1c vcmpneq_osss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1d vcmpge_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1d vcmpge_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1e vcmpgt_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1e vcmpgt_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1f vcmptrue_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1f vcmptrue_usss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 7d 18 21 vbroadcastss ymm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 18 21 vbroadcastss xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd xmm4,ecx +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si ecx,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si ecx,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd xmm6,xmm4,ecx +[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss xmm6,xmm4,ecx +[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 e9 6a fc 60 vfmaddss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6a 39 60 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6a 39 40 vfmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6e fc 60 vfmsubss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6e 39 60 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6e 39 40 vfmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7a fc 60 vfnmaddss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7a 39 60 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7a 39 40 vfnmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7e fc 60 vfnmsubss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7e 39 60 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7e 39 40 vfnmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb ecx,xmm4 +[ ]*[a-f0-9]+: c5 c8 12 d4 vmovhlps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4 +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ff e6 f4 vcvtpd2dq xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fd 5a f4 vcvtpd2ps xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fd e6 f4 vcvttpd2dq xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f8 ae 15 34 12 00 00 vldmxcsr DWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 f9 6f 05 34 12 00 00 vmovdqa xmm0,XMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 f9 7f 05 34 12 00 00 vmovdqa XMMWORD PTR ds:0x1234,xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 05 34 12 00 00 vmovd DWORD PTR ds:0x1234,xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 05 34 12 00 00 vcvtsd2si eax,QWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 fe e6 05 34 12 00 00 vcvtdq2pd ymm0,XMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 fd 5a 05 34 12 00 00 vcvtpd2ps xmm0,YMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 f9 e0 3d 34 12 00 00 vpavgb xmm7,xmm0,XMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 64 vpextrb BYTE PTR ds:0x1234,xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 3d 34 12 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c4 e3 59 4a 35 34 12 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR ds:0x1234,xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR ds:0x1234,0x64 +[ ]*[a-f0-9]+: c5 fd 6f 05 34 12 00 00 vmovdqa ymm0,YMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 fd 7f 05 34 12 00 00 vmovdqa YMMWORD PTR ds:0x1234,ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3d 34 12 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 64 vroundpd ymm0,YMMWORD PTR ds:0x1234,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 64 vextractf128 XMMWORD PTR ds:0x1234,ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 35 34 12 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR ds:0x1234,ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr DWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 f9 6f 45 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 f9 7f 45 00 vmovdqa XMMWORD PTR \[ebp\+0x0\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 45 00 vmovd DWORD PTR \[ebp\+0x0\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 45 00 vcvtsd2si eax,QWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 fe e6 45 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 fd 5a 45 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 f9 e0 7d 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c4 e3 79 14 45 00 64 vpextrb BYTE PTR \[ebp\+0x0\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 7d 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c4 e3 59 4a 75 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+0x0\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x0\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 45 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 fd 7f 45 00 vmovdqa YMMWORD PTR \[ebp\+0x0\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 7d 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+0x0\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 64 vextractf128 XMMWORD PTR \[ebp\+0x0\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 75 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+0x0\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 14 24 vldmxcsr DWORD PTR \[esp\] +[ ]*[a-f0-9]+: c5 f9 6f 04 24 vmovdqa xmm0,XMMWORD PTR \[esp\] +[ ]*[a-f0-9]+: c5 f9 7f 04 24 vmovdqa XMMWORD PTR \[esp\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 04 24 vmovd DWORD PTR \[esp\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 04 24 vcvtsd2si eax,QWORD PTR \[esp\] +[ ]*[a-f0-9]+: c5 fe e6 04 24 vcvtdq2pd ymm0,XMMWORD PTR \[esp\] +[ ]*[a-f0-9]+: c5 fd 5a 04 24 vcvtpd2ps xmm0,YMMWORD PTR \[esp\] +[ ]*[a-f0-9]+: c5 f9 e0 3c 24 vpavgb xmm7,xmm0,XMMWORD PTR \[esp\] +[ ]*[a-f0-9]+: c4 e3 79 14 04 24 64 vpextrb BYTE PTR \[esp\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 3c 24 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\] +[ ]*[a-f0-9]+: c4 e3 59 4a 34 24 00 vblendvps xmm6,xmm4,XMMWORD PTR \[esp\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 24 64 vpinsrb xmm7,xmm0,BYTE PTR \[esp\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 04 24 vmovdqa ymm0,YMMWORD PTR \[esp\] +[ ]*[a-f0-9]+: c5 fd 7f 04 24 vmovdqa YMMWORD PTR \[esp\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 24 vpermilpd ymm7,ymm0,YMMWORD PTR \[esp\] +[ ]*[a-f0-9]+: c4 e3 7d 09 04 24 64 vroundpd ymm0,YMMWORD PTR \[esp\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 24 64 vextractf128 XMMWORD PTR \[esp\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 24 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 24 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[esp\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr DWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 85 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 85 99 00 00 00 vmovdqa XMMWORD PTR \[ebp\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 85 99 00 00 00 vmovd DWORD PTR \[ebp\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 85 99 00 00 00 vcvtsd2si eax,QWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 85 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 85 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bd 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 64 vpextrb BYTE PTR \[ebp\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bd 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b5 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 85 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 85 99 00 00 00 vmovdqa YMMWORD PTR \[ebp\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bd 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 64 vextractf128 XMMWORD PTR \[ebp\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b5 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 99 00 00 00 vldmxcsr DWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 04 25 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 04 25 99 00 00 00 vmovdqa XMMWORD PTR \[eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 04 25 99 00 00 00 vmovd DWORD PTR \[eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 04 25 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 04 25 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 04 25 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 3c 25 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 64 vpextrb BYTE PTR \[eiz\*1\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 3c 25 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a 34 25 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 04 25 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 04 25 99 00 00 00 vmovdqa YMMWORD PTR \[eiz\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 25 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 64 vextractf128 XMMWORD PTR \[eiz\*1\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 25 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eiz\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 14 65 99 00 00 00 vldmxcsr DWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 04 65 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 04 65 99 00 00 00 vmovdqa XMMWORD PTR \[eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 04 65 99 00 00 00 vmovd DWORD PTR \[eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 04 65 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 04 65 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 04 65 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 3c 65 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 64 vpextrb BYTE PTR \[eiz\*2\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 3c 65 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a 34 65 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 04 65 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 04 65 99 00 00 00 vmovdqa YMMWORD PTR \[eiz\*2\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 65 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 64 vextractf128 XMMWORD PTR \[eiz\*2\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 65 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eiz\*2\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 20 99 00 00 00 vldmxcsr DWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 20 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 20 99 00 00 00 vmovdqa XMMWORD PTR \[eax\+eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 20 99 00 00 00 vmovd DWORD PTR \[eax\+eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 20 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 20 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 20 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc 20 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 64 vpextrb BYTE PTR \[eax\+eiz\*1\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc 20 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 20 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 20 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 20 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 20 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 20 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 60 99 00 00 00 vldmxcsr DWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 60 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 60 99 00 00 00 vmovdqa XMMWORD PTR \[eax\+eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 60 99 00 00 00 vmovd DWORD PTR \[eax\+eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 60 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 60 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 60 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc 60 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 64 vpextrb BYTE PTR \[eax\+eiz\*2\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc 60 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 60 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 60 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 60 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 60 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 60 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 98 99 00 00 00 vldmxcsr DWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 98 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 98 99 00 00 00 vmovdqa XMMWORD PTR \[eax\+ebx\*4\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 98 99 00 00 00 vmovd DWORD PTR \[eax\+ebx\*4\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 98 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 98 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 98 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc 98 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 64 vpextrb BYTE PTR \[eax\+ebx\*4\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc 98 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 98 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+ebx\*4\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+ebx\*4\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 98 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 98 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 98 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 98 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 cc 99 00 00 00 vldmxcsr DWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 cc 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 cc 99 00 00 00 vmovdqa XMMWORD PTR \[esp\+ecx\*8\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 cc 99 00 00 00 vmovd DWORD PTR \[esp\+ecx\*8\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 cc 99 00 00 00 vcvtsd2si eax,QWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 cc 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 cc 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc cc 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 64 vpextrb BYTE PTR \[esp\+ecx\*8\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc cc 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 cc 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[esp\+ecx\*8\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[esp\+ecx\*8\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 cc 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 cc 99 00 00 00 vmovdqa YMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc cc 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 64 vextractf128 XMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 cc 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 15 99 00 00 00 vldmxcsr DWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 15 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 15 99 00 00 00 vmovdqa XMMWORD PTR \[ebp\+edx\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 15 99 00 00 00 vmovd DWORD PTR \[ebp\+edx\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 15 99 00 00 00 vcvtsd2si eax,QWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 15 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 15 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc 15 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 64 vpextrb BYTE PTR \[ebp\+edx\*1\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc 15 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 15 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+edx\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+edx\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 15 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 15 99 00 00 00 vmovdqa YMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 15 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 64 vextractf128 XMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 15 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f9 50 c0 vmovmskpd eax,xmm0 +[ ]*[a-f0-9]+: c5 c1 72 f0 64 vpslld xmm7,xmm0,0x64 +[ ]*[a-f0-9]+: c5 fc 50 c0 vmovmskps eax,ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 5d 2d 31 vmaskmovpd ymm6,ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd YMMWORD PTR \[ecx\],ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps ymm6,ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[ecx\],ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 58 11 vaddps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd d0 d4 vaddsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd d0 11 vaddsubpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cf d0 d4 vaddsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf d0 11 vaddsubps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 55 d4 vandnpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 55 11 vandnpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 55 d4 vandnps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 55 11 vandnps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 54 d4 vandpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 54 11 vandpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 54 d4 vandps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 54 11 vandps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 5e d4 vdivpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5e 11 vdivpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 5e d4 vdivps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5e 11 vdivps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 7c d4 vhaddpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 7c 11 vhaddpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cf 7c d4 vhaddps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf 7c 11 vhaddps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 7d d4 vhsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 7d 11 vhsubpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cf 7d d4 vhsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf 7d 11 vhsubps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 5f d4 vmaxpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5f 11 vmaxpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 5f d4 vmaxps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5f 11 vmaxps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 5d d4 vminpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5d 11 vminpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 5d d4 vminps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5d 11 vminps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 59 d4 vmulpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 59 11 vmulpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 59 d4 vmulps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 59 11 vmulps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 56 d4 vorpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 56 11 vorpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 56 d4 vorps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 56 11 vorps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 4d 0d d4 vpermilpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 4d 0d 11 vpermilpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 4d 0c d4 vpermilps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 4d 0c 11 vpermilps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 5c d4 vsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5c 11 vsubpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 5c d4 vsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5c 11 vsubps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 15 d4 vunpckhpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 15 11 vunpckhpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 15 d4 vunpckhps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 15 11 vunpckhps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 14 d4 vunpcklpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 14 11 vunpcklpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 14 d4 vunpcklps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 14 11 vunpcklps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd 57 d4 vxorpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 57 11 vxorpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc 57 d4 vxorps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 57 11 vxorps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 10 vcmpeq_ospd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 11 vcmplt_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 11 vcmplt_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 12 vcmple_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 12 vcmple_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 13 vcmpunord_spd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 13 vcmpunord_spd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 14 vcmpneq_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 14 vcmpneq_uspd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 15 vcmpnlt_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 15 vcmpnlt_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 16 vcmpnle_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 16 vcmpnle_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 17 vcmpord_spd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 17 vcmpord_spd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 18 vcmpeq_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 18 vcmpeq_uspd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 19 vcmpnge_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 19 vcmpnge_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1a vcmpngt_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1a vcmpngt_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1b vcmpfalse_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1b vcmpfalse_ospd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1c vcmpneq_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1c vcmpneq_ospd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1d vcmpge_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1d vcmpge_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1e vcmpgt_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1e vcmpgt_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1f vcmptrue_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 10 vcmpeq_osps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 11 vcmplt_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 11 vcmplt_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 12 vcmple_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 12 vcmple_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 13 vcmpunord_sps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 13 vcmpunord_sps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 14 vcmpneq_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 14 vcmpneq_usps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 15 vcmpnlt_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 15 vcmpnlt_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 16 vcmpnle_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 16 vcmpnle_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 17 vcmpord_sps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 17 vcmpord_sps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 18 vcmpeq_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 18 vcmpeq_usps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 19 vcmpnge_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 19 vcmpnge_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1a vcmpngt_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1a vcmpngt_uqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1b vcmpfalse_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1b vcmpfalse_osps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1c vcmpneq_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1c vcmpneq_osps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1d vcmpge_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1d vcmpge_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1e vcmpgt_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4 +[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2ps xmm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq xmm4,ymm4 +[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dq xmm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[ecx\] +[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd ymm7,ymm2,ymm6,ymm4,0xa +[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps ymm7,ymm2,ymm6,ymm4,0xa +[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa +[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 ymm6,ymm4,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 xmm4,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[ecx\],ymm4,0x64 +[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dq xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2ps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dq xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 0e f4 vtestps xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0e 21 vtestps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 0f f4 vtestpd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0f 21 vtestpd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu xmm4,\[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fe e6 e4 vcvtdq2pd ymm4,xmm4 +[ ]*[a-f0-9]+: c5 fe e6 21 vcvtdq2pd ymm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fc 5a e4 vcvtps2pd ymm4,xmm4 +[ ]*[a-f0-9]+: c5 fc 5a 21 vcvtps2pd ymm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 58 d4 vaddpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 58 39 vaddpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 58 d4 vaddps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 58 39 vaddps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d0 d4 vaddsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d0 39 vaddsubpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb d0 d4 vaddsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb d0 39 vaddsubps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 55 d4 vandnpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 55 39 vandnpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 55 d4 vandnps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 55 39 vandnps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 54 d4 vandpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 54 39 vandpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 54 d4 vandps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 54 39 vandps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 5e d4 vdivpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5e 39 vdivpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 5e d4 vdivps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5e 39 vdivps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 7c d4 vhaddpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 7c 39 vhaddpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 7c d4 vhaddps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 7c 39 vhaddps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 7d d4 vhsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 7d 39 vhsubpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 7d d4 vhsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 7d 39 vhsubps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 5f d4 vmaxpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5f 39 vmaxpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 5f d4 vmaxps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5f 39 vmaxps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 5d d4 vminpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5d 39 vminpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 5d d4 vminps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5d 39 vminps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 59 d4 vmulpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 59 39 vmulpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 59 d4 vmulps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 59 39 vmulps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 56 d4 vorpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 56 39 vorpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 56 d4 vorps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 56 39 vorps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 63 d4 vpacksswb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 63 39 vpacksswb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 6b d4 vpackssdw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6b 39 vpackssdw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 67 d4 vpackuswb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 67 39 vpackuswb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 2b d4 vpackusdw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 2b 39 vpackusdw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fc d4 vpaddb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fc 39 vpaddb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fd d4 vpaddw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fd 39 vpaddw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fe d4 vpaddd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fe 39 vpaddd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d4 d4 vpaddq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d4 39 vpaddq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ec d4 vpaddsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ec 39 vpaddsb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ed d4 vpaddsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ed 39 vpaddsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 dc d4 vpaddusb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 dc 39 vpaddusb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 dd d4 vpaddusw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 dd 39 vpaddusw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 db d4 vpand xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 db 39 vpand xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 df d4 vpandn xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 df 39 vpandn xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e0 d4 vpavgb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e0 39 vpavgb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e3 d4 vpavgw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e3 39 vpavgw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 74 d4 vpcmpeqb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 74 39 vpcmpeqb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 75 d4 vpcmpeqw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 75 39 vpcmpeqw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 76 d4 vpcmpeqd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 76 39 vpcmpeqd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 29 d4 vpcmpeqq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 29 39 vpcmpeqq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 64 d4 vpcmpgtb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 64 39 vpcmpgtb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 65 d4 vpcmpgtw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 65 39 vpcmpgtw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 66 d4 vpcmpgtd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 66 39 vpcmpgtd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 37 d4 vpcmpgtq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 37 39 vpcmpgtq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 0d d4 vpermilpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0d 39 vpermilpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 0c d4 vpermilps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0c 39 vpermilps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 01 d4 vphaddw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 01 39 vphaddw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 02 d4 vphaddd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 02 39 vphaddd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 03 d4 vphaddsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 03 39 vphaddsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 05 d4 vphsubw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 05 39 vphsubw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 06 d4 vphsubd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 06 39 vphsubd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 07 d4 vphsubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 07 39 vphsubsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f5 d4 vpmaddwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f5 39 vpmaddwd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 04 d4 vpmaddubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 04 39 vpmaddubsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3c d4 vpmaxsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3c 39 vpmaxsb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ee d4 vpmaxsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ee 39 vpmaxsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3d d4 vpmaxsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3d 39 vpmaxsd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 de d4 vpmaxub xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 de 39 vpmaxub xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3e d4 vpmaxuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3e 39 vpmaxuw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3f d4 vpmaxud xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3f 39 vpmaxud xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 38 d4 vpminsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 38 39 vpminsb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ea d4 vpminsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ea 39 vpminsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 39 d4 vpminsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 39 39 vpminsd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 da d4 vpminub xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 da 39 vpminub xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3a d4 vpminuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3a 39 vpminuw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 3b d4 vpminud xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3b 39 vpminud xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e4 d4 vpmulhuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e4 39 vpmulhuw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 0b d4 vpmulhrsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0b 39 vpmulhrsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e5 d4 vpmulhw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e5 39 vpmulhw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d5 d4 vpmullw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d5 39 vpmullw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 40 d4 vpmulld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 40 39 vpmulld xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f4 d4 vpmuludq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f4 39 vpmuludq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 28 d4 vpmuldq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 28 39 vpmuldq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 eb d4 vpor xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 eb 39 vpor xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f6 d4 vpsadbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f6 39 vpsadbw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 00 d4 vpshufb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 00 39 vpshufb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 08 d4 vpsignb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 08 39 vpsignb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 09 d4 vpsignw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 09 39 vpsignw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 49 0a d4 vpsignd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0a 39 vpsignd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f1 d4 vpsllw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f1 39 vpsllw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f2 d4 vpslld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f2 39 vpslld xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f3 d4 vpsllq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f3 39 vpsllq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e1 d4 vpsraw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e1 39 vpsraw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e2 d4 vpsrad xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e2 39 vpsrad xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d1 d4 vpsrlw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d1 39 vpsrlw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d2 d4 vpsrld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d2 39 vpsrld xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d3 d4 vpsrlq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d3 39 vpsrlq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f8 d4 vpsubb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f8 39 vpsubb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 f9 d4 vpsubw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f9 39 vpsubw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fa d4 vpsubd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fa 39 vpsubd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 fb d4 vpsubq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fb 39 vpsubq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e8 d4 vpsubsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e8 39 vpsubsb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 e9 d4 vpsubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e9 39 vpsubsw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d8 d4 vpsubusb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d8 39 vpsubusb xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 d9 d4 vpsubusw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d9 39 vpsubusw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 68 d4 vpunpckhbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 68 39 vpunpckhbw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 69 d4 vpunpckhwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 69 39 vpunpckhwd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 6a d4 vpunpckhdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6a 39 vpunpckhdq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 6d d4 vpunpckhqdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6d 39 vpunpckhqdq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 60 d4 vpunpcklbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 60 39 vpunpcklbw xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 61 d4 vpunpcklwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 61 39 vpunpcklwd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 62 d4 vpunpckldq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 62 39 vpunpckldq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 6c d4 vpunpcklqdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6c 39 vpunpcklqdq xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 ef d4 vpxor xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ef 39 vpxor xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 5c d4 vsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5c 39 vsubpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 5c d4 vsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5c 39 vsubps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 15 d4 vunpckhpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 15 39 vunpckhpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 15 d4 vunpckhps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 15 39 vunpckhps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 14 d4 vunpcklpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 14 39 vunpcklpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 14 d4 vunpcklps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 14 39 vunpcklps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 57 d4 vxorpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 57 39 vxorpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 57 d4 vxorps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 57 39 vxorps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 00 vcmpeqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 00 vcmpeqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 01 vcmpltpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 01 vcmpltpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 02 vcmplepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 02 vcmplepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 03 vcmpunordpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 03 vcmpunordpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 04 vcmpneqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 04 vcmpneqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 05 vcmpnltpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 05 vcmpnltpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 06 vcmpnlepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 06 vcmpnlepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 07 vcmpordpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 08 vcmpeq_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 08 vcmpeq_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 09 vcmpngepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 09 vcmpngepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0a vcmpngtpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0a vcmpngtpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0b vcmpfalsepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0b vcmpfalsepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0c vcmpneq_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0c vcmpneq_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0d vcmpgepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0d vcmpgepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0e vcmpgtpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0e vcmpgtpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0f vcmptruepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0f vcmptruepd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 10 vcmpeq_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 10 vcmpeq_ospd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 11 vcmplt_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 11 vcmplt_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 12 vcmple_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 12 vcmple_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 13 vcmpunord_spd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 13 vcmpunord_spd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 14 vcmpneq_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 14 vcmpneq_uspd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 15 vcmpnlt_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 15 vcmpnlt_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 16 vcmpnle_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 16 vcmpnle_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 17 vcmpord_spd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 17 vcmpord_spd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 18 vcmpeq_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 18 vcmpeq_uspd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 19 vcmpnge_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 19 vcmpnge_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1a vcmpngt_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1a vcmpngt_uqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1b vcmpfalse_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1b vcmpfalse_ospd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1c vcmpneq_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1c vcmpneq_ospd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1d vcmpge_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1d vcmpge_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1e vcmpgt_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1e vcmpgt_oqpd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1f vcmptrue_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1f vcmptrue_uspd xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 00 vcmpeqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 00 vcmpeqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 01 vcmpltps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 01 vcmpltps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 02 vcmpleps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 02 vcmpleps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 03 vcmpunordps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 03 vcmpunordps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 04 vcmpneqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 04 vcmpneqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 05 vcmpnltps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 05 vcmpnltps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 06 vcmpnleps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 06 vcmpnleps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 07 vcmpordps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 08 vcmpeq_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 08 vcmpeq_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 09 vcmpngeps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 09 vcmpngeps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0a vcmpngtps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0a vcmpngtps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0b vcmpfalseps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0b vcmpfalseps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0c vcmpneq_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0c vcmpneq_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0d vcmpgeps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0d vcmpgeps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0e vcmpgtps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0e vcmpgtps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0f vcmptrueps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0f vcmptrueps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 10 vcmpeq_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 10 vcmpeq_osps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 11 vcmplt_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 11 vcmplt_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 12 vcmple_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 12 vcmple_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 13 vcmpunord_sps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 13 vcmpunord_sps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 14 vcmpneq_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 14 vcmpneq_usps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 15 vcmpnlt_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 15 vcmpnlt_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 16 vcmpnle_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 16 vcmpnle_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 17 vcmpord_sps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 17 vcmpord_sps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 18 vcmpeq_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 18 vcmpeq_usps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 19 vcmpnge_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 19 vcmpnge_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1a vcmpngt_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1a vcmpngt_uqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1b vcmpfalse_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1b vcmpfalse_osps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1c vcmpneq_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1c vcmpneq_osps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1d vcmpge_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1d vcmpge_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1e vcmpgt_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[ecx\],xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[ecx\],xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd xmm7,xmm2,xmm6,xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa +[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps xmm7,xmm2,xmm6,xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa +[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa +[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si ecx,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si ecx,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd xmm6,xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps xmm6,xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd xmm6,xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 e9 6b fc 60 vfmaddsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6b 39 60 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6b 39 40 vfmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6f fc 60 vfmsubsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6f 39 60 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6f 39 40 vfmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7b fc 60 vfnmaddsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7b 39 60 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7b 39 40 vfnmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7f fc 60 vfnmsubsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7f 39 60 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7f 39 40 vfnmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5a 11 vcvtsd2ss xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5e d4 vdivsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5e 11 vdivsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5f d4 vmaxsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5f 11 vmaxsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5d d4 vminsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5d 11 vminsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 59 d4 vmulsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 59 11 vmulsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 51 d4 vsqrtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 51 11 vsqrtsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb 5c d4 vsubsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 10 vcmpeq_ossd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 11 vcmplt_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 11 vcmplt_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 12 vcmple_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 12 vcmple_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 13 vcmpunord_ssd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 13 vcmpunord_ssd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 14 vcmpneq_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 14 vcmpneq_ussd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 15 vcmpnlt_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 15 vcmpnlt_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 16 vcmpnle_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 16 vcmpnle_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 17 vcmpord_ssd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 17 vcmpord_ssd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 18 vcmpeq_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 18 vcmpeq_ussd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 19 vcmpnge_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 19 vcmpnge_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1a vcmpngt_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1a vcmpngt_uqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1b vcmpfalse_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1b vcmpfalse_ossd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1c vcmpneq_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1c vcmpneq_ossd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1d vcmpge_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1d vcmpge_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1e vcmpgt_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5a 11 vcvtss2sd xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5e d4 vdivss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5e 11 vdivss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5f d4 vmaxss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5f 11 vmaxss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5d d4 vminss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5d 11 vminss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 59 d4 vmulss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 59 11 vmulss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 53 d4 vrcpss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 53 11 vrcpss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 52 d4 vrsqrtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 52 11 vrsqrtss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 51 d4 vsqrtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 51 11 vsqrtss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca 5c d4 vsubss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 10 vcmpeq_osss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 11 vcmplt_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 11 vcmplt_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 12 vcmple_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 12 vcmple_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 13 vcmpunord_sss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 13 vcmpunord_sss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 14 vcmpneq_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 14 vcmpneq_usss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 15 vcmpnlt_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 15 vcmpnlt_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 16 vcmpnle_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 16 vcmpnle_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 17 vcmpord_sss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 17 vcmpord_sss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 18 vcmpeq_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 18 vcmpeq_usss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 19 vcmpnge_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 19 vcmpnge_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1a vcmpngt_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1a vcmpngt_uqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1b vcmpfalse_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1b vcmpfalse_osss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1c vcmpneq_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1c vcmpneq_osss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1d vcmpge_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1d vcmpge_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1e vcmpgt_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1e vcmpgt_oqss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1f vcmptrue_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1f vcmptrue_usss xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 7d 18 21 vbroadcastss ymm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 18 21 vbroadcastss xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd xmm4,ecx +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si ecx,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si ecx,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd xmm6,xmm4,ecx +[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss xmm6,xmm4,ecx +[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 e9 6a fc 60 vfmaddss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6a 39 60 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6a 39 40 vfmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6e fc 60 vfmsubss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6e 39 60 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 6e 39 40 vfmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7a fc 60 vfnmaddss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7a 39 60 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7a 39 40 vfnmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7e fc 60 vfnmsubss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7e 39 60 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e3 69 7e 39 40 vfnmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[ecx\] +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[ecx\] +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb ecx,xmm4 +[ ]*[a-f0-9]+: c5 c8 12 d4 vmovhlps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4 +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ff e6 f4 vcvtpd2dq xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fd 5a f4 vcvtpd2ps xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fd e6 f4 vcvttpd2dq xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f8 ae 15 34 12 00 00 vldmxcsr DWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 f9 6f 05 34 12 00 00 vmovdqa xmm0,XMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 f9 7f 05 34 12 00 00 vmovdqa XMMWORD PTR ds:0x1234,xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 05 34 12 00 00 vmovd DWORD PTR ds:0x1234,xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 05 34 12 00 00 vcvtsd2si eax,QWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 fe e6 05 34 12 00 00 vcvtdq2pd ymm0,XMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 fd 5a 05 34 12 00 00 vcvtpd2ps xmm0,YMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 f9 e0 3d 34 12 00 00 vpavgb xmm7,xmm0,XMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 64 vpextrb BYTE PTR ds:0x1234,xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 3d 34 12 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c4 e3 59 4a 35 34 12 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR ds:0x1234,xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR ds:0x1234,0x64 +[ ]*[a-f0-9]+: c5 fd 6f 05 34 12 00 00 vmovdqa ymm0,YMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c5 fd 7f 05 34 12 00 00 vmovdqa YMMWORD PTR ds:0x1234,ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3d 34 12 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR ds:0x1234 +[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 64 vroundpd ymm0,YMMWORD PTR ds:0x1234,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 64 vextractf128 XMMWORD PTR ds:0x1234,ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 35 34 12 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR ds:0x1234,ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr DWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 f9 6f 45 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 f9 7f 45 00 vmovdqa XMMWORD PTR \[ebp\+0x0\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 45 00 vmovd DWORD PTR \[ebp\+0x0\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 45 00 vcvtsd2si eax,QWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 fe e6 45 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 fd 5a 45 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 f9 e0 7d 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c4 e3 79 14 45 00 64 vpextrb BYTE PTR \[ebp\+0x0\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 7d 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c4 e3 59 4a 75 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+0x0\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x0\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 45 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c5 fd 7f 45 00 vmovdqa YMMWORD PTR \[ebp\+0x0\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 7d 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\] +[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+0x0\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 64 vextractf128 XMMWORD PTR \[ebp\+0x0\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 75 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+0x0\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr DWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 85 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 85 99 00 00 00 vmovdqa XMMWORD PTR \[ebp\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 85 99 00 00 00 vmovd DWORD PTR \[ebp\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 85 99 00 00 00 vcvtsd2si eax,QWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 85 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 85 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bd 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 64 vpextrb BYTE PTR \[ebp\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bd 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b5 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 85 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 85 99 00 00 00 vmovdqa YMMWORD PTR \[ebp\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bd 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 64 vextractf128 XMMWORD PTR \[ebp\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b5 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 99 00 00 00 vldmxcsr DWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 04 25 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 04 25 99 00 00 00 vmovdqa XMMWORD PTR \[eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 04 25 99 00 00 00 vmovd DWORD PTR \[eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 04 25 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 04 25 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 04 25 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 3c 25 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 64 vpextrb BYTE PTR \[eiz\*1\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 3c 25 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a 34 25 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 04 25 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 04 25 99 00 00 00 vmovdqa YMMWORD PTR \[eiz\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 25 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 64 vextractf128 XMMWORD PTR \[eiz\*1\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 25 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eiz\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 14 65 99 00 00 00 vldmxcsr DWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 04 65 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 04 65 99 00 00 00 vmovdqa XMMWORD PTR \[eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 04 65 99 00 00 00 vmovd DWORD PTR \[eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 04 65 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 04 65 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 04 65 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 3c 65 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 64 vpextrb BYTE PTR \[eiz\*2\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a 3c 65 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a 34 65 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 04 65 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 04 65 99 00 00 00 vmovdqa YMMWORD PTR \[eiz\*2\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 65 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 64 vextractf128 XMMWORD PTR \[eiz\*2\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 65 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eiz\*2\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 20 99 00 00 00 vldmxcsr DWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 20 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 20 99 00 00 00 vmovdqa XMMWORD PTR \[eax\+eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 20 99 00 00 00 vmovd DWORD PTR \[eax\+eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 20 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 20 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 20 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc 20 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 64 vpextrb BYTE PTR \[eax\+eiz\*1\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc 20 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 20 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+eiz\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 20 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 20 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 20 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 20 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 60 99 00 00 00 vldmxcsr DWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 60 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 60 99 00 00 00 vmovdqa XMMWORD PTR \[eax\+eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 60 99 00 00 00 vmovd DWORD PTR \[eax\+eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 60 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 60 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 60 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc 60 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 64 vpextrb BYTE PTR \[eax\+eiz\*2\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc 60 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 60 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+eiz\*2\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 60 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 60 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 60 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 60 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 98 99 00 00 00 vldmxcsr DWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 98 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 98 99 00 00 00 vmovdqa XMMWORD PTR \[eax\+ebx\*4\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 98 99 00 00 00 vmovd DWORD PTR \[eax\+ebx\*4\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 98 99 00 00 00 vcvtsd2si eax,QWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 98 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 98 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc 98 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 64 vpextrb BYTE PTR \[eax\+ebx\*4\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc 98 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 98 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+ebx\*4\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+ebx\*4\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 98 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 98 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 98 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 98 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 cc 99 00 00 00 vldmxcsr DWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 cc 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 cc 99 00 00 00 vmovdqa XMMWORD PTR \[esp\+ecx\*8\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 cc 99 00 00 00 vmovd DWORD PTR \[esp\+ecx\*8\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 cc 99 00 00 00 vcvtsd2si eax,QWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 cc 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 cc 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc cc 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 64 vpextrb BYTE PTR \[esp\+ecx\*8\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc cc 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 cc 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[esp\+ecx\*8\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[esp\+ecx\*8\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 cc 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 cc 99 00 00 00 vmovdqa YMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc cc 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 64 vextractf128 XMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 cc 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f8 ae 94 15 99 00 00 00 vldmxcsr DWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 6f 84 15 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 7f 84 15 99 00 00 00 vmovdqa XMMWORD PTR \[ebp\+edx\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 f9 7e 84 15 99 00 00 00 vmovd DWORD PTR \[ebp\+edx\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c5 fb 2d 84 15 99 00 00 00 vcvtsd2si eax,QWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fe e6 84 15 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 5a 84 15 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 f9 e0 bc 15 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 64 vpextrb BYTE PTR \[ebp\+edx\*1\+0x99\],xmm0,0x64 +[ ]*[a-f0-9]+: c5 fb 2a bc 15 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 59 4a b4 15 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+edx\*1\+0x99\],xmm0 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+edx\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 fd 6f 84 15 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c5 fd 7f 84 15 99 00 00 00 vmovdqa YMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 15 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\] +[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 64 vextractf128 XMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 15 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0 +[ ]*[a-f0-9]+: c5 f9 50 c0 vmovmskpd eax,xmm0 +[ ]*[a-f0-9]+: c5 c1 72 f0 64 vpslld xmm7,xmm0,0x64 +[ ]*[a-f0-9]+: c5 fc 50 c0 vmovmskps eax,ymm0 +#pass diff --git a/gas/testsuite/gas/i386/avx.d b/gas/testsuite/gas/i386/avx.d new file mode 100644 index 0000000..aa1083f --- /dev/null +++ b/gas/testsuite/gas/i386/avx.d @@ -0,0 +1,2758 @@ +#objdump: -dw +#name: i386 AVX + +.*: file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: c5 fc 77 vzeroall +[ ]*[a-f0-9]+: c5 f8 77 vzeroupper +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\) +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%ecx\) +[ ]*[a-f0-9]+: c4 e2 5d 2d 31 vmaskmovpd \(%ecx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd %ymm4,%ymm6,\(%ecx\) +[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps \(%ecx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%ecx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%ecx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%ecx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%ecx\),%ymm6 +[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 58 11 vaddps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd d0 d4 vaddsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd d0 11 vaddsubpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf d0 d4 vaddsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf d0 11 vaddsubps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 55 d4 vandnpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 55 11 vandnpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 55 d4 vandnps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 55 11 vandnps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 54 d4 vandpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 54 11 vandpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 54 d4 vandps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 54 11 vandps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5e d4 vdivpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5e 11 vdivpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5e d4 vdivps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5e 11 vdivps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7c d4 vhaddpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7c 11 vhaddpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7c d4 vhaddps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7c 11 vhaddps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7d d4 vhsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7d 11 vhsubpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7d d4 vhsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7d 11 vhsubps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5f d4 vmaxpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5f 11 vmaxpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5f d4 vmaxps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5f 11 vmaxps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5d d4 vminpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5d 11 vminpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5d d4 vminps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5d 11 vminps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 59 d4 vmulpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 59 11 vmulpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 59 d4 vmulps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 59 11 vmulps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 56 d4 vorpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 56 11 vorpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 56 d4 vorps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 56 11 vorps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0d d4 vpermilpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0d 11 vpermilpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0c d4 vpermilps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0c 11 vpermilps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5c d4 vsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5c 11 vsubpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5c d4 vsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5c 11 vsubps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 15 d4 vunpckhpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 15 11 vunpckhpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 15 d4 vunpckhps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 15 11 vunpckhps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 14 d4 vunpcklpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 14 11 vunpcklpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 14 d4 vunpcklps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 14 11 vunpcklps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 57 d4 vxorpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 57 11 vxorpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 57 d4 vxorps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 57 11 vxorps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 10 vcmpeq_ospd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 11 vcmplt_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 11 vcmplt_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 12 vcmple_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 12 vcmple_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 13 vcmpunord_spd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 13 vcmpunord_spd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 14 vcmpneq_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 14 vcmpneq_uspd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 15 vcmpnlt_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 15 vcmpnlt_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 16 vcmpnle_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 16 vcmpnle_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 17 vcmpord_spd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 17 vcmpord_spd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 18 vcmpeq_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 18 vcmpeq_uspd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 19 vcmpnge_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 19 vcmpnge_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1a vcmpngt_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1a vcmpngt_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1b vcmpfalse_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1b vcmpfalse_ospd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1c vcmpneq_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1c vcmpneq_ospd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1d vcmpge_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1d vcmpge_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1e vcmpgt_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1e vcmpgt_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1f vcmptrue_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 10 vcmpeq_osps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 11 vcmplt_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 11 vcmplt_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 12 vcmple_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 12 vcmple_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 13 vcmpunord_sps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 13 vcmpunord_sps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 14 vcmpneq_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 14 vcmpneq_usps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 15 vcmpnlt_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 15 vcmpnlt_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 16 vcmpnle_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 16 vcmpnle_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 17 vcmpord_sps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 17 vcmpord_sps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 18 vcmpeq_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 18 vcmpeq_usps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 19 vcmpnge_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 19 vcmpnge_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1a vcmpngt_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1a vcmpngt_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1b vcmpfalse_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1b vcmpfalse_osps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1c vcmpneq_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1c vcmpneq_osps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1d vcmpge_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1d vcmpge_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1e vcmpgt_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2psy \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dqy \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%ecx\),%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd \$0xa,%ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps \$0xa,%ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 \$0x64,%xmm4,%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%ecx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 \$0x64,%ymm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dqx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2psx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dqx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0e f4 vtestps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 0e 21 vtestps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0f f4 vtestpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 0f 21 vtestpd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fe e6 e4 vcvtdq2pd %xmm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe e6 21 vcvtdq2pd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 5a e4 vcvtps2pd %xmm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 5a 21 vcvtps2pd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 c9 58 d4 vaddpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 58 39 vaddpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 58 d4 vaddps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 58 39 vaddps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d0 d4 vaddsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d0 39 vaddsubpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb d0 d4 vaddsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb d0 39 vaddsubps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 55 d4 vandnpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 55 39 vandnpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 55 d4 vandnps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 55 39 vandnps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 54 d4 vandpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 54 39 vandpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 54 d4 vandps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 54 39 vandps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5e d4 vdivpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5e 39 vdivpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5e d4 vdivps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5e 39 vdivps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 7c d4 vhaddpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 7c 39 vhaddpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb 7c d4 vhaddps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 7c 39 vhaddps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 7d d4 vhsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 7d 39 vhsubpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb 7d d4 vhsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 7d 39 vhsubps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5f d4 vmaxpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5f 39 vmaxpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5f d4 vmaxps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5f 39 vmaxps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5d d4 vminpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5d 39 vminpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5d d4 vminps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5d 39 vminps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 59 d4 vmulpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 59 39 vmulpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 59 d4 vmulps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 59 39 vmulps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 56 d4 vorpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 56 39 vorpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 56 d4 vorps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 56 39 vorps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 63 d4 vpacksswb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 63 39 vpacksswb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6b d4 vpackssdw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6b 39 vpackssdw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 67 d4 vpackuswb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 67 39 vpackuswb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 2b d4 vpackusdw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 2b 39 vpackusdw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fc d4 vpaddb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fc 39 vpaddb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fd d4 vpaddw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fd 39 vpaddw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fe d4 vpaddd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fe 39 vpaddd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d4 d4 vpaddq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d4 39 vpaddq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ec d4 vpaddsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ec 39 vpaddsb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ed d4 vpaddsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ed 39 vpaddsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 dc d4 vpaddusb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 dc 39 vpaddusb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 dd d4 vpaddusw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 dd 39 vpaddusw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 db d4 vpand %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 db 39 vpand \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 df d4 vpandn %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 df 39 vpandn \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e0 d4 vpavgb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e0 39 vpavgb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e3 d4 vpavgw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e3 39 vpavgw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 74 d4 vpcmpeqb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 74 39 vpcmpeqb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 75 d4 vpcmpeqw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 75 39 vpcmpeqw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 76 d4 vpcmpeqd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 76 39 vpcmpeqd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 29 d4 vpcmpeqq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 29 39 vpcmpeqq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 64 d4 vpcmpgtb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 64 39 vpcmpgtb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 65 39 vpcmpgtw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 66 d4 vpcmpgtd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 66 39 vpcmpgtd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 37 d4 vpcmpgtq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 37 39 vpcmpgtq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0d d4 vpermilpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0d 39 vpermilpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0c d4 vpermilps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0c 39 vpermilps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 01 d4 vphaddw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 01 39 vphaddw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 02 d4 vphaddd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 02 39 vphaddd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 03 d4 vphaddsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 03 39 vphaddsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 05 d4 vphsubw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 05 39 vphsubw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 06 d4 vphsubd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 06 39 vphsubd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 07 d4 vphsubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 07 39 vphsubsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f5 39 vpmaddwd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 04 39 vpmaddubsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3c d4 vpmaxsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3c 39 vpmaxsb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ee d4 vpmaxsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ee 39 vpmaxsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3d d4 vpmaxsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3d 39 vpmaxsd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 de d4 vpmaxub %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 de 39 vpmaxub \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3e d4 vpmaxuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3e 39 vpmaxuw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3f d4 vpmaxud %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3f 39 vpmaxud \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 38 d4 vpminsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 38 39 vpminsb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ea d4 vpminsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ea 39 vpminsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 39 d4 vpminsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 39 39 vpminsd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 da d4 vpminub %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 da 39 vpminub \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3a d4 vpminuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3a 39 vpminuw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3b d4 vpminud %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3b 39 vpminud \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e4 d4 vpmulhuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e4 39 vpmulhuw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0b d4 vpmulhrsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0b 39 vpmulhrsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e5 d4 vpmulhw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e5 39 vpmulhw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d5 d4 vpmullw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d5 39 vpmullw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 40 d4 vpmulld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 40 39 vpmulld \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f4 d4 vpmuludq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f4 39 vpmuludq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 28 d4 vpmuldq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 28 39 vpmuldq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 eb d4 vpor %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 eb 39 vpor \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f6 d4 vpsadbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f6 39 vpsadbw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 00 d4 vpshufb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 00 39 vpshufb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 08 d4 vpsignb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 08 39 vpsignb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 09 d4 vpsignw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 09 39 vpsignw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0a d4 vpsignd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0a 39 vpsignd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f1 d4 vpsllw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f1 39 vpsllw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f2 d4 vpslld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f2 39 vpslld \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f3 d4 vpsllq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f3 39 vpsllq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e1 d4 vpsraw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e1 39 vpsraw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e2 d4 vpsrad %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e2 39 vpsrad \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d1 d4 vpsrlw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d1 39 vpsrlw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d2 d4 vpsrld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d2 39 vpsrld \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d3 d4 vpsrlq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d3 39 vpsrlq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f8 d4 vpsubb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f8 39 vpsubb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f9 d4 vpsubw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f9 39 vpsubw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fa d4 vpsubd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fa 39 vpsubd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fb d4 vpsubq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fb 39 vpsubq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e8 d4 vpsubsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e8 39 vpsubsb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e9 d4 vpsubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e9 39 vpsubsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d8 d4 vpsubusb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d8 39 vpsubusb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d9 d4 vpsubusw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d9 39 vpsubusw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 68 d4 vpunpckhbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 68 39 vpunpckhbw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 69 d4 vpunpckhwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 69 39 vpunpckhwd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6a d4 vpunpckhdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6a 39 vpunpckhdq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6d d4 vpunpckhqdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6d 39 vpunpckhqdq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 60 d4 vpunpcklbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 60 39 vpunpcklbw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 61 d4 vpunpcklwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 61 39 vpunpcklwd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 62 d4 vpunpckldq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 62 39 vpunpckldq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6c d4 vpunpcklqdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6c 39 vpunpcklqdq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ef d4 vpxor %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ef 39 vpxor \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5c d4 vsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5c 39 vsubpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5c d4 vsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5c 39 vsubps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 15 d4 vunpckhpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 15 39 vunpckhpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 15 d4 vunpckhps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 15 39 vunpckhps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 14 d4 vunpcklpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 14 39 vunpcklpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 14 d4 vunpcklps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 14 39 vunpcklps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 57 d4 vxorpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 57 39 vxorpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 57 d4 vxorps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 57 39 vxorps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 00 vcmpeqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 00 vcmpeqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 01 vcmpltpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 01 vcmpltpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 02 vcmplepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 02 vcmplepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 03 vcmpunordpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 03 vcmpunordpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 04 vcmpneqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 04 vcmpneqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 05 vcmpnltpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 05 vcmpnltpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 06 vcmpnlepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 06 vcmpnlepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 07 vcmpordpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 08 vcmpeq_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 08 vcmpeq_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 09 vcmpngepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 09 vcmpngepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0a vcmpngtpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0a vcmpngtpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0b vcmpfalsepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0b vcmpfalsepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0c vcmpneq_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0c vcmpneq_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0d vcmpgepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0d vcmpgepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0e vcmpgtpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0e vcmpgtpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0f vcmptruepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0f vcmptruepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 10 vcmpeq_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 10 vcmpeq_ospd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 11 vcmplt_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 11 vcmplt_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 12 vcmple_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 12 vcmple_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 13 vcmpunord_spd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 13 vcmpunord_spd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 14 vcmpneq_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 14 vcmpneq_uspd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 15 vcmpnlt_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 15 vcmpnlt_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 16 vcmpnle_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 16 vcmpnle_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 17 vcmpord_spd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 17 vcmpord_spd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 18 vcmpeq_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 18 vcmpeq_uspd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 19 vcmpnge_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 19 vcmpnge_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1a vcmpngt_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1a vcmpngt_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1b vcmpfalse_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1b vcmpfalse_ospd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1c vcmpneq_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1c vcmpneq_ospd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1d vcmpge_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1d vcmpge_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1e vcmpgt_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1e vcmpgt_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1f vcmptrue_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1f vcmptrue_uspd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 00 vcmpeqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 00 vcmpeqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 01 vcmpltps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 01 vcmpltps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 02 vcmpleps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 02 vcmpleps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 03 vcmpunordps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 03 vcmpunordps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 04 vcmpneqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 04 vcmpneqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 05 vcmpnltps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 05 vcmpnltps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 06 vcmpnleps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 06 vcmpnleps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 07 vcmpordps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 08 vcmpeq_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 08 vcmpeq_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 09 vcmpngeps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 09 vcmpngeps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0a vcmpngtps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0a vcmpngtps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0b vcmpfalseps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0b vcmpfalseps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0c vcmpneq_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0c vcmpneq_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0d vcmpgeps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0d vcmpgeps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0e vcmpgtps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0e vcmpgtps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0f vcmptrueps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0f vcmptrueps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 10 vcmpeq_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 10 vcmpeq_osps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 11 vcmplt_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 11 vcmplt_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 12 vcmple_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 12 vcmple_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 13 vcmpunord_sps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 13 vcmpunord_sps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 14 vcmpneq_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 14 vcmpneq_usps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 15 vcmpnlt_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 15 vcmpnlt_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 16 vcmpnle_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 16 vcmpnle_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 17 vcmpord_sps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 17 vcmpord_sps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 18 vcmpeq_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 18 vcmpeq_usps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 19 vcmpnge_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 19 vcmpnge_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1a vcmpngt_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1a vcmpngt_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1b vcmpfalse_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1b vcmpfalse_osps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1c vcmpneq_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1c vcmpneq_osps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1d vcmpge_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1d vcmpge_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1e vcmpgt_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%ecx\) +[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd \$0xa,%xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps \$0xa,%xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 e9 6b fc 60 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6b 39 60 vfmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6b 39 40 vfmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6f fc 60 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6f 39 60 vfmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6f 39 40 vfmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7b fc 60 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7b 39 60 vfnmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7b 39 40 vfnmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7f fc 60 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7f 39 60 vfnmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7f 39 40 vfnmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5a 11 vcvtsd2ss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5e d4 vdivsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5e 11 vdivsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5f d4 vmaxsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5f 11 vmaxsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5d d4 vminsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5d 11 vminsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 59 d4 vmulsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 59 11 vmulsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 51 d4 vsqrtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 51 11 vsqrtsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5c d4 vsubsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 10 vcmpeq_ossd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 11 vcmplt_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 11 vcmplt_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 12 vcmple_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 12 vcmple_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 13 vcmpunord_ssd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 13 vcmpunord_ssd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 14 vcmpneq_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 14 vcmpneq_ussd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 15 vcmpnlt_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 15 vcmpnlt_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 16 vcmpnle_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 16 vcmpnle_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 17 vcmpord_ssd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 17 vcmpord_ssd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 18 vcmpeq_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 18 vcmpeq_ussd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 19 vcmpnge_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 19 vcmpnge_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1a vcmpngt_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1a vcmpngt_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1b vcmpfalse_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1b vcmpfalse_ossd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1c vcmpneq_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1c vcmpneq_ossd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1d vcmpge_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1d vcmpge_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1e vcmpgt_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5a 11 vcvtss2sd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5e d4 vdivss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5e 11 vdivss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5f d4 vmaxss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5f 11 vmaxss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5d d4 vminss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5d 11 vminss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 59 d4 vmulss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 59 11 vmulss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 53 d4 vrcpss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 53 11 vrcpss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 52 d4 vrsqrtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 52 11 vrsqrtss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 51 d4 vsqrtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 51 11 vsqrtss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5c d4 vsubss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 10 vcmpeq_osss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 11 vcmplt_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 11 vcmplt_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 12 vcmple_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 12 vcmple_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 13 vcmpunord_sss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 13 vcmpunord_sss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 14 vcmpneq_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 14 vcmpneq_usss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 15 vcmpnlt_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 15 vcmpnlt_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 16 vcmpnle_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 16 vcmpnle_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 17 vcmpord_sss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 17 vcmpord_sss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 18 vcmpeq_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 18 vcmpeq_usss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 19 vcmpnge_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 19 vcmpnge_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1a vcmpngt_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1a vcmpngt_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1b vcmpfalse_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1b vcmpfalse_osss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1c vcmpneq_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1c vcmpneq_osss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1d vcmpge_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1d vcmpge_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1e vcmpgt_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1e vcmpgt_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1f vcmptrue_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1f vcmptrue_usss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 7d 18 21 vbroadcastss \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 18 21 vbroadcastss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd %ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss %ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 e9 6a fc 60 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6a 39 60 vfmaddss \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6a 39 40 vfmaddss %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6e fc 60 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6e 39 60 vfmsubss \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6e 39 40 vfmsubss %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7a fc 60 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7a 39 60 vfnmaddss \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7a 39 40 vfnmaddss %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7e fc 60 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7e 39 60 vfnmsubss \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7e 39 40 vfnmsubss %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c5 c8 12 d4 vmovhlps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 ff e6 f4 vcvtpd2dq %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fd 5a f4 vcvtpd2ps %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fd e6 f4 vcvttpd2dq %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 ae 15 34 12 00 00 vldmxcsr 0x1234 +[ ]*[a-f0-9]+: c5 f9 6f 05 34 12 00 00 vmovdqa 0x1234,%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 05 34 12 00 00 vmovdqa %xmm0,0x1234 +[ ]*[a-f0-9]+: c5 f9 7e 05 34 12 00 00 vmovd %xmm0,0x1234 +[ ]*[a-f0-9]+: c5 fb 2d 05 34 12 00 00 vcvtsd2si 0x1234,%eax +[ ]*[a-f0-9]+: c5 fe e6 05 34 12 00 00 vcvtdq2pd 0x1234,%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 05 34 12 00 00 vcvtpd2psy 0x1234,%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 3d 34 12 00 00 vpavgb 0x1234,%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 64 vpextrb \$0x64,%xmm0,0x1234 +[ ]*[a-f0-9]+: c5 fb 2a 3d 34 12 00 00 vcvtsi2sdl 0x1234,%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 35 34 12 00 00 00 vblendvps %xmm0,0x1234,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 64 vpinsrb \$0x64,0x1234,%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 05 34 12 00 00 vmovdqa 0x1234,%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 05 34 12 00 00 vmovdqa %ymm0,0x1234 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3d 34 12 00 00 vpermilpd 0x1234,%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 64 vroundpd \$0x64,0x1234,%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 64 vextractf128 \$0x64,%ymm0,0x1234 +[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 64 vperm2f128 \$0x64,0x1234,%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 35 34 12 00 00 00 vblendvpd %ymm0,0x1234,%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%ebp\) +[ ]*[a-f0-9]+: c5 f9 6f 45 00 vmovdqa 0x0\(%ebp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 45 00 vmovdqa %xmm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c5 f9 7e 45 00 vmovd %xmm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c5 fb 2d 45 00 vcvtsd2si 0x0\(%ebp\),%eax +[ ]*[a-f0-9]+: c5 fe e6 45 00 vcvtdq2pd 0x0\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 45 00 vcvtpd2psy 0x0\(%ebp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 7d 00 vpavgb 0x0\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 45 00 64 vpextrb \$0x64,%xmm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c5 fb 2a 7d 00 vcvtsi2sdl 0x0\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 75 00 00 vblendvps %xmm0,0x0\(%ebp\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 64 vpinsrb \$0x64,0x0\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 45 00 vmovdqa 0x0\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 45 00 vmovdqa %ymm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c4 e2 7d 0d 7d 00 vpermilpd 0x0\(%ebp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 64 vroundpd \$0x64,0x0\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 64 vextractf128 \$0x64,%ymm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 64 vperm2f128 \$0x64,0x0\(%ebp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 75 00 00 vblendvpd %ymm0,0x0\(%ebp\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 14 24 vldmxcsr \(%esp\) +[ ]*[a-f0-9]+: c5 f9 6f 04 24 vmovdqa \(%esp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 04 24 vmovdqa %xmm0,\(%esp\) +[ ]*[a-f0-9]+: c5 f9 7e 04 24 vmovd %xmm0,\(%esp\) +[ ]*[a-f0-9]+: c5 fb 2d 04 24 vcvtsd2si \(%esp\),%eax +[ ]*[a-f0-9]+: c5 fe e6 04 24 vcvtdq2pd \(%esp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 04 24 vcvtpd2psy \(%esp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 3c 24 vpavgb \(%esp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 04 24 64 vpextrb \$0x64,%xmm0,\(%esp\) +[ ]*[a-f0-9]+: c5 fb 2a 3c 24 vcvtsi2sdl \(%esp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 34 24 00 vblendvps %xmm0,\(%esp\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 24 64 vpinsrb \$0x64,\(%esp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 04 24 vmovdqa \(%esp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 04 24 vmovdqa %ymm0,\(%esp\) +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 24 vpermilpd \(%esp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 04 24 64 vroundpd \$0x64,\(%esp\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 24 64 vextractf128 \$0x64,%ymm0,\(%esp\) +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 24 64 vperm2f128 \$0x64,\(%esp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 24 00 vblendvpd %ymm0,\(%esp\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr 0x99\(%ebp\) +[ ]*[a-f0-9]+: c5 f9 6f 85 99 00 00 00 vmovdqa 0x99\(%ebp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 85 99 00 00 00 vmovdqa %xmm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c5 f9 7e 85 99 00 00 00 vmovd %xmm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c5 fb 2d 85 99 00 00 00 vcvtsd2si 0x99\(%ebp\),%eax +[ ]*[a-f0-9]+: c5 fe e6 85 99 00 00 00 vcvtdq2pd 0x99\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 85 99 00 00 00 vcvtpd2psy 0x99\(%ebp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bd 99 00 00 00 vpavgb 0x99\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c5 fb 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b5 99 00 00 00 00 vblendvps %xmm0,0x99\(%ebp\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 64 vpinsrb \$0x64,0x99\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 85 99 00 00 00 vmovdqa 0x99\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 85 99 00 00 00 vmovdqa %ymm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bd 99 00 00 00 vpermilpd 0x99\(%ebp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 64 vroundpd \$0x64,0x99\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%ebp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b5 99 00 00 00 00 vblendvpd %ymm0,0x99\(%ebp\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 99 00 00 00 vldmxcsr 0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c5 f9 6f 04 25 99 00 00 00 vmovdqa 0x99\(,%eiz,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 04 25 99 00 00 00 vmovdqa %xmm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c5 f9 7e 04 25 99 00 00 00 vmovd %xmm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c5 fb 2d 04 25 99 00 00 00 vcvtsd2si 0x99\(,%eiz,1\),%eax +[ ]*[a-f0-9]+: c5 fe e6 04 25 99 00 00 00 vcvtdq2pd 0x99\(,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 04 25 99 00 00 00 vcvtpd2psy 0x99\(,%eiz,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 3c 25 99 00 00 00 vpavgb 0x99\(,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c5 fb 2a 3c 25 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 34 25 99 00 00 00 00 vblendvps %xmm0,0x99\(,%eiz,1\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 64 vpinsrb \$0x64,0x99\(,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 04 25 99 00 00 00 vmovdqa 0x99\(,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 04 25 99 00 00 00 vmovdqa %ymm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 25 99 00 00 00 vpermilpd 0x99\(,%eiz,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 64 vroundpd \$0x64,0x99\(,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 64 vperm2f128 \$0x64,0x99\(,%eiz,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 25 99 00 00 00 00 vblendvpd %ymm0,0x99\(,%eiz,1\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 14 65 99 00 00 00 vldmxcsr 0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c5 f9 6f 04 65 99 00 00 00 vmovdqa 0x99\(,%eiz,2\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 04 65 99 00 00 00 vmovdqa %xmm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c5 f9 7e 04 65 99 00 00 00 vmovd %xmm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c5 fb 2d 04 65 99 00 00 00 vcvtsd2si 0x99\(,%eiz,2\),%eax +[ ]*[a-f0-9]+: c5 fe e6 04 65 99 00 00 00 vcvtdq2pd 0x99\(,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 04 65 99 00 00 00 vcvtpd2psy 0x99\(,%eiz,2\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 3c 65 99 00 00 00 vpavgb 0x99\(,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c5 fb 2a 3c 65 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 34 65 99 00 00 00 00 vblendvps %xmm0,0x99\(,%eiz,2\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 64 vpinsrb \$0x64,0x99\(,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 04 65 99 00 00 00 vmovdqa 0x99\(,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 04 65 99 00 00 00 vmovdqa %ymm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 65 99 00 00 00 vpermilpd 0x99\(,%eiz,2\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 64 vroundpd \$0x64,0x99\(,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 64 vperm2f128 \$0x64,0x99\(,%eiz,2\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 65 99 00 00 00 00 vblendvpd %ymm0,0x99\(,%eiz,2\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 20 99 00 00 00 vldmxcsr 0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c5 f9 6f 84 20 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 20 99 00 00 00 vmovdqa %xmm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c5 f9 7e 84 20 99 00 00 00 vmovd %xmm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c5 fb 2d 84 20 99 00 00 00 vcvtsd2si 0x99\(%eax,%eiz,1\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 20 99 00 00 00 vcvtdq2pd 0x99\(%eax,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 20 99 00 00 00 vcvtpd2psy 0x99\(%eax,%eiz,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc 20 99 00 00 00 vpavgb 0x99\(%eax,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c5 fb 2a bc 20 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 20 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%eiz,1\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 20 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 20 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 20 99 00 00 00 vpermilpd 0x99\(%eax,%eiz,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%eiz,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 20 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%eiz,1\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 60 99 00 00 00 vldmxcsr 0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c5 f9 6f 84 60 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,2\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 60 99 00 00 00 vmovdqa %xmm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c5 f9 7e 84 60 99 00 00 00 vmovd %xmm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c5 fb 2d 84 60 99 00 00 00 vcvtsd2si 0x99\(%eax,%eiz,2\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 60 99 00 00 00 vcvtdq2pd 0x99\(%eax,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 60 99 00 00 00 vcvtpd2psy 0x99\(%eax,%eiz,2\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc 60 99 00 00 00 vpavgb 0x99\(%eax,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c5 fb 2a bc 60 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 60 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%eiz,2\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 60 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 60 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 60 99 00 00 00 vpermilpd 0x99\(%eax,%eiz,2\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%eiz,2\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 60 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%eiz,2\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 98 99 00 00 00 vldmxcsr 0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c5 f9 6f 84 98 99 00 00 00 vmovdqa 0x99\(%eax,%ebx,4\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 98 99 00 00 00 vmovdqa %xmm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c5 f9 7e 84 98 99 00 00 00 vmovd %xmm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c5 fb 2d 84 98 99 00 00 00 vcvtsd2si 0x99\(%eax,%ebx,4\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 98 99 00 00 00 vcvtdq2pd 0x99\(%eax,%ebx,4\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 98 99 00 00 00 vcvtpd2psy 0x99\(%eax,%ebx,4\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc 98 99 00 00 00 vpavgb 0x99\(%eax,%ebx,4\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c5 fb 2a bc 98 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%ebx,4\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 98 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%ebx,4\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%ebx,4\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 98 99 00 00 00 vmovdqa 0x99\(%eax,%ebx,4\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 98 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 98 99 00 00 00 vpermilpd 0x99\(%eax,%ebx,4\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%ebx,4\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%ebx,4\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 98 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%ebx,4\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 cc 99 00 00 00 vldmxcsr 0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c5 f9 6f 84 cc 99 00 00 00 vmovdqa 0x99\(%esp,%ecx,8\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 cc 99 00 00 00 vmovdqa %xmm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c5 f9 7e 84 cc 99 00 00 00 vmovd %xmm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c5 fb 2d 84 cc 99 00 00 00 vcvtsd2si 0x99\(%esp,%ecx,8\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 cc 99 00 00 00 vcvtdq2pd 0x99\(%esp,%ecx,8\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 cc 99 00 00 00 vcvtpd2psy 0x99\(%esp,%ecx,8\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc cc 99 00 00 00 vpavgb 0x99\(%esp,%ecx,8\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c5 fb 2a bc cc 99 00 00 00 vcvtsi2sdl 0x99\(%esp,%ecx,8\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 cc 99 00 00 00 00 vblendvps %xmm0,0x99\(%esp,%ecx,8\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 64 vpinsrb \$0x64,0x99\(%esp,%ecx,8\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 cc 99 00 00 00 vmovdqa 0x99\(%esp,%ecx,8\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 cc 99 00 00 00 vmovdqa %ymm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc cc 99 00 00 00 vpermilpd 0x99\(%esp,%ecx,8\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 64 vroundpd \$0x64,0x99\(%esp,%ecx,8\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%esp,%ecx,8\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 cc 99 00 00 00 00 vblendvpd %ymm0,0x99\(%esp,%ecx,8\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 15 99 00 00 00 vldmxcsr 0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c5 f9 6f 84 15 99 00 00 00 vmovdqa 0x99\(%ebp,%edx,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 15 99 00 00 00 vmovdqa %xmm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c5 f9 7e 84 15 99 00 00 00 vmovd %xmm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c5 fb 2d 84 15 99 00 00 00 vcvtsd2si 0x99\(%ebp,%edx,1\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 15 99 00 00 00 vcvtdq2pd 0x99\(%ebp,%edx,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 15 99 00 00 00 vcvtpd2psy 0x99\(%ebp,%edx,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc 15 99 00 00 00 vpavgb 0x99\(%ebp,%edx,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c5 fb 2a bc 15 99 00 00 00 vcvtsi2sdl 0x99\(%ebp,%edx,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 15 99 00 00 00 00 vblendvps %xmm0,0x99\(%ebp,%edx,1\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 64 vpinsrb \$0x64,0x99\(%ebp,%edx,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 15 99 00 00 00 vmovdqa 0x99\(%ebp,%edx,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 15 99 00 00 00 vmovdqa %ymm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 15 99 00 00 00 vpermilpd 0x99\(%ebp,%edx,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 64 vroundpd \$0x64,0x99\(%ebp,%edx,1\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%ebp,%edx,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 15 99 00 00 00 00 vblendvpd %ymm0,0x99\(%ebp,%edx,1\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f9 50 c0 vmovmskpd %xmm0,%eax +[ ]*[a-f0-9]+: c5 c1 72 f0 64 vpslld \$0x64,%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fc 50 c0 vmovmskps %ymm0,%eax +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\) +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%ecx\) +[ ]*[a-f0-9]+: c4 e2 5d 2d 31 vmaskmovpd \(%ecx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd %ymm4,%ymm6,\(%ecx\) +[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps \(%ecx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%ecx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%ecx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%ecx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%ecx\),%ymm6 +[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 58 11 vaddps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd d0 d4 vaddsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd d0 11 vaddsubpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf d0 d4 vaddsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf d0 11 vaddsubps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 55 d4 vandnpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 55 11 vandnpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 55 d4 vandnps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 55 11 vandnps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 54 d4 vandpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 54 11 vandpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 54 d4 vandps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 54 11 vandps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5e d4 vdivpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5e 11 vdivpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5e d4 vdivps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5e 11 vdivps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7c d4 vhaddpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7c 11 vhaddpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7c d4 vhaddps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7c 11 vhaddps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7d d4 vhsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7d 11 vhsubpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7d d4 vhsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7d 11 vhsubps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5f d4 vmaxpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5f 11 vmaxpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5f d4 vmaxps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5f 11 vmaxps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5d d4 vminpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5d 11 vminpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5d d4 vminps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5d 11 vminps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 59 d4 vmulpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 59 11 vmulpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 59 d4 vmulps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 59 11 vmulps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 56 d4 vorpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 56 11 vorpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 56 d4 vorps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 56 11 vorps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0d d4 vpermilpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0d 11 vpermilpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0c d4 vpermilps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0c 11 vpermilps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5c d4 vsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5c 11 vsubpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5c d4 vsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5c 11 vsubps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 15 d4 vunpckhpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 15 11 vunpckhpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 15 d4 vunpckhps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 15 11 vunpckhps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 14 d4 vunpcklpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 14 11 vunpcklpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 14 d4 vunpcklps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 14 11 vunpcklps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 57 d4 vxorpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 57 11 vxorpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 57 d4 vxorps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 57 11 vxorps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 10 vcmpeq_ospd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 11 vcmplt_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 11 vcmplt_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 12 vcmple_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 12 vcmple_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 13 vcmpunord_spd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 13 vcmpunord_spd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 14 vcmpneq_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 14 vcmpneq_uspd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 15 vcmpnlt_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 15 vcmpnlt_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 16 vcmpnle_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 16 vcmpnle_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 17 vcmpord_spd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 17 vcmpord_spd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 18 vcmpeq_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 18 vcmpeq_uspd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 19 vcmpnge_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 19 vcmpnge_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1a vcmpngt_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1a vcmpngt_uqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1b vcmpfalse_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1b vcmpfalse_ospd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1c vcmpneq_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1c vcmpneq_ospd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1d vcmpge_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1d vcmpge_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1e vcmpgt_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1e vcmpgt_oqpd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1f vcmptrue_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 10 vcmpeq_osps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 11 vcmplt_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 11 vcmplt_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 12 vcmple_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 12 vcmple_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 13 vcmpunord_sps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 13 vcmpunord_sps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 14 vcmpneq_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 14 vcmpneq_usps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 15 vcmpnlt_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 15 vcmpnlt_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 16 vcmpnle_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 16 vcmpnle_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 17 vcmpord_sps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 17 vcmpord_sps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 18 vcmpeq_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 18 vcmpeq_usps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 19 vcmpnge_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 19 vcmpnge_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1a vcmpngt_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1a vcmpngt_uqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1b vcmpfalse_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1b vcmpfalse_osps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1c vcmpneq_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1c vcmpneq_osps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1d vcmpge_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1d vcmpge_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1e vcmpgt_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2psy \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dqy \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%ecx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%ecx\),%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd \$0xa,%ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps \$0xa,%ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 \$0x64,%xmm4,%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%ecx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 \$0x64,%ymm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dqx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2psx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dqx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0e f4 vtestps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 0e 21 vtestps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0f f4 vtestpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 0f 21 vtestpd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fe e6 e4 vcvtdq2pd %xmm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe e6 21 vcvtdq2pd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 5a e4 vcvtps2pd %xmm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 5a 21 vcvtps2pd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 c9 58 d4 vaddpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 58 39 vaddpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 58 d4 vaddps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 58 39 vaddps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d0 d4 vaddsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d0 39 vaddsubpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb d0 d4 vaddsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb d0 39 vaddsubps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 55 d4 vandnpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 55 39 vandnpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 55 d4 vandnps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 55 39 vandnps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 54 d4 vandpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 54 39 vandpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 54 d4 vandps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 54 39 vandps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5e d4 vdivpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5e 39 vdivpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5e d4 vdivps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5e 39 vdivps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 7c d4 vhaddpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 7c 39 vhaddpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb 7c d4 vhaddps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 7c 39 vhaddps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 7d d4 vhsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 7d 39 vhsubpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb 7d d4 vhsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 7d 39 vhsubps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5f d4 vmaxpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5f 39 vmaxpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5f d4 vmaxps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5f 39 vmaxps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5d d4 vminpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5d 39 vminpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5d d4 vminps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5d 39 vminps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 59 d4 vmulpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 59 39 vmulpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 59 d4 vmulps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 59 39 vmulps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 56 d4 vorpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 56 39 vorpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 56 d4 vorps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 56 39 vorps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 63 d4 vpacksswb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 63 39 vpacksswb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6b d4 vpackssdw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6b 39 vpackssdw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 67 d4 vpackuswb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 67 39 vpackuswb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 2b d4 vpackusdw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 2b 39 vpackusdw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fc d4 vpaddb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fc 39 vpaddb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fd d4 vpaddw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fd 39 vpaddw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fe d4 vpaddd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fe 39 vpaddd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d4 d4 vpaddq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d4 39 vpaddq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ec d4 vpaddsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ec 39 vpaddsb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ed d4 vpaddsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ed 39 vpaddsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 dc d4 vpaddusb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 dc 39 vpaddusb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 dd d4 vpaddusw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 dd 39 vpaddusw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 db d4 vpand %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 db 39 vpand \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 df d4 vpandn %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 df 39 vpandn \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e0 d4 vpavgb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e0 39 vpavgb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e3 d4 vpavgw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e3 39 vpavgw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 74 d4 vpcmpeqb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 74 39 vpcmpeqb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 75 d4 vpcmpeqw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 75 39 vpcmpeqw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 76 d4 vpcmpeqd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 76 39 vpcmpeqd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 29 d4 vpcmpeqq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 29 39 vpcmpeqq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 64 d4 vpcmpgtb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 64 39 vpcmpgtb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 65 39 vpcmpgtw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 66 d4 vpcmpgtd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 66 39 vpcmpgtd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 37 d4 vpcmpgtq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 37 39 vpcmpgtq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0d d4 vpermilpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0d 39 vpermilpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0c d4 vpermilps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0c 39 vpermilps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 01 d4 vphaddw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 01 39 vphaddw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 02 d4 vphaddd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 02 39 vphaddd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 03 d4 vphaddsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 03 39 vphaddsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 05 d4 vphsubw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 05 39 vphsubw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 06 d4 vphsubd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 06 39 vphsubd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 07 d4 vphsubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 07 39 vphsubsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f5 39 vpmaddwd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 04 39 vpmaddubsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3c d4 vpmaxsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3c 39 vpmaxsb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ee d4 vpmaxsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ee 39 vpmaxsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3d d4 vpmaxsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3d 39 vpmaxsd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 de d4 vpmaxub %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 de 39 vpmaxub \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3e d4 vpmaxuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3e 39 vpmaxuw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3f d4 vpmaxud %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3f 39 vpmaxud \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 38 d4 vpminsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 38 39 vpminsb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ea d4 vpminsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ea 39 vpminsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 39 d4 vpminsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 39 39 vpminsd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 da d4 vpminub %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 da 39 vpminub \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3a d4 vpminuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3a 39 vpminuw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3b d4 vpminud %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3b 39 vpminud \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e4 d4 vpmulhuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e4 39 vpmulhuw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0b d4 vpmulhrsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0b 39 vpmulhrsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e5 d4 vpmulhw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e5 39 vpmulhw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d5 d4 vpmullw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d5 39 vpmullw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 40 d4 vpmulld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 40 39 vpmulld \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f4 d4 vpmuludq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f4 39 vpmuludq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 28 d4 vpmuldq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 28 39 vpmuldq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 eb d4 vpor %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 eb 39 vpor \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f6 d4 vpsadbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f6 39 vpsadbw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 00 d4 vpshufb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 00 39 vpshufb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 08 d4 vpsignb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 08 39 vpsignb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 09 d4 vpsignw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 09 39 vpsignw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0a d4 vpsignd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0a 39 vpsignd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f1 d4 vpsllw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f1 39 vpsllw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f2 d4 vpslld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f2 39 vpslld \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f3 d4 vpsllq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f3 39 vpsllq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e1 d4 vpsraw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e1 39 vpsraw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e2 d4 vpsrad %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e2 39 vpsrad \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d1 d4 vpsrlw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d1 39 vpsrlw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d2 d4 vpsrld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d2 39 vpsrld \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d3 d4 vpsrlq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d3 39 vpsrlq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f8 d4 vpsubb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f8 39 vpsubb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f9 d4 vpsubw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f9 39 vpsubw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fa d4 vpsubd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fa 39 vpsubd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fb d4 vpsubq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fb 39 vpsubq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e8 d4 vpsubsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e8 39 vpsubsb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e9 d4 vpsubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e9 39 vpsubsw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d8 d4 vpsubusb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d8 39 vpsubusb \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d9 d4 vpsubusw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d9 39 vpsubusw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 68 d4 vpunpckhbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 68 39 vpunpckhbw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 69 d4 vpunpckhwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 69 39 vpunpckhwd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6a d4 vpunpckhdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6a 39 vpunpckhdq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6d d4 vpunpckhqdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6d 39 vpunpckhqdq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 60 d4 vpunpcklbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 60 39 vpunpcklbw \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 61 d4 vpunpcklwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 61 39 vpunpcklwd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 62 d4 vpunpckldq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 62 39 vpunpckldq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6c d4 vpunpcklqdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6c 39 vpunpcklqdq \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ef d4 vpxor %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ef 39 vpxor \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5c d4 vsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5c 39 vsubpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5c d4 vsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5c 39 vsubps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 15 d4 vunpckhpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 15 39 vunpckhpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 15 d4 vunpckhps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 15 39 vunpckhps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 14 d4 vunpcklpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 14 39 vunpcklpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 14 d4 vunpcklps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 14 39 vunpcklps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 57 d4 vxorpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 57 39 vxorpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 57 d4 vxorps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 57 39 vxorps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 00 vcmpeqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 00 vcmpeqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 01 vcmpltpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 01 vcmpltpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 02 vcmplepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 02 vcmplepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 03 vcmpunordpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 03 vcmpunordpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 04 vcmpneqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 04 vcmpneqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 05 vcmpnltpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 05 vcmpnltpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 06 vcmpnlepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 06 vcmpnlepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 07 vcmpordpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 08 vcmpeq_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 08 vcmpeq_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 09 vcmpngepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 09 vcmpngepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0a vcmpngtpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0a vcmpngtpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0b vcmpfalsepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0b vcmpfalsepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0c vcmpneq_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0c vcmpneq_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0d vcmpgepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0d vcmpgepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0e vcmpgtpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0e vcmpgtpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0f vcmptruepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0f vcmptruepd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 10 vcmpeq_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 10 vcmpeq_ospd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 11 vcmplt_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 11 vcmplt_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 12 vcmple_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 12 vcmple_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 13 vcmpunord_spd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 13 vcmpunord_spd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 14 vcmpneq_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 14 vcmpneq_uspd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 15 vcmpnlt_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 15 vcmpnlt_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 16 vcmpnle_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 16 vcmpnle_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 17 vcmpord_spd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 17 vcmpord_spd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 18 vcmpeq_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 18 vcmpeq_uspd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 19 vcmpnge_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 19 vcmpnge_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1a vcmpngt_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1a vcmpngt_uqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1b vcmpfalse_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1b vcmpfalse_ospd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1c vcmpneq_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1c vcmpneq_ospd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1d vcmpge_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1d vcmpge_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1e vcmpgt_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1e vcmpgt_oqpd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1f vcmptrue_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1f vcmptrue_uspd \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 00 vcmpeqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 00 vcmpeqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 01 vcmpltps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 01 vcmpltps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 02 vcmpleps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 02 vcmpleps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 03 vcmpunordps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 03 vcmpunordps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 04 vcmpneqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 04 vcmpneqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 05 vcmpnltps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 05 vcmpnltps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 06 vcmpnleps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 06 vcmpnleps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 07 vcmpordps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 08 vcmpeq_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 08 vcmpeq_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 09 vcmpngeps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 09 vcmpngeps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0a vcmpngtps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0a vcmpngtps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0b vcmpfalseps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0b vcmpfalseps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0c vcmpneq_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0c vcmpneq_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0d vcmpgeps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0d vcmpgeps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0e vcmpgtps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0e vcmpgtps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0f vcmptrueps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0f vcmptrueps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 10 vcmpeq_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 10 vcmpeq_osps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 11 vcmplt_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 11 vcmplt_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 12 vcmple_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 12 vcmple_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 13 vcmpunord_sps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 13 vcmpunord_sps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 14 vcmpneq_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 14 vcmpneq_usps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 15 vcmpnlt_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 15 vcmpnlt_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 16 vcmpnle_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 16 vcmpnle_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 17 vcmpord_sps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 17 vcmpord_sps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 18 vcmpeq_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 18 vcmpeq_usps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 19 vcmpnge_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 19 vcmpnge_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1a vcmpngt_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1a vcmpngt_uqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1b vcmpfalse_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1b vcmpfalse_osps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1c vcmpneq_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1c vcmpneq_osps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1d vcmpge_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1d vcmpge_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1e vcmpgt_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%ecx\) +[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd \$0xa,%xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps \$0xa,%xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 e9 6b fc 60 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6b 39 60 vfmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6b 39 40 vfmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6f fc 60 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6f 39 60 vfmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6f 39 40 vfmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7b fc 60 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7b 39 60 vfnmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7b 39 40 vfnmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7f fc 60 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7f 39 60 vfnmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7f 39 40 vfnmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5a 11 vcvtsd2ss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5e d4 vdivsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5e 11 vdivsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5f d4 vmaxsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5f 11 vmaxsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5d d4 vminsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5d 11 vminsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 59 d4 vmulsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 59 11 vmulsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 51 d4 vsqrtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 51 11 vsqrtsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5c d4 vsubsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 10 vcmpeq_ossd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 11 vcmplt_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 11 vcmplt_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 12 vcmple_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 12 vcmple_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 13 vcmpunord_ssd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 13 vcmpunord_ssd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 14 vcmpneq_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 14 vcmpneq_ussd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 15 vcmpnlt_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 15 vcmpnlt_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 16 vcmpnle_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 16 vcmpnle_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 17 vcmpord_ssd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 17 vcmpord_ssd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 18 vcmpeq_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 18 vcmpeq_ussd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 19 vcmpnge_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 19 vcmpnge_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1a vcmpngt_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1a vcmpngt_uqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1b vcmpfalse_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1b vcmpfalse_ossd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1c vcmpneq_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1c vcmpneq_ossd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1d vcmpge_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1d vcmpge_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1e vcmpgt_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5a 11 vcvtss2sd \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5e d4 vdivss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5e 11 vdivss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5f d4 vmaxss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5f 11 vmaxss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5d d4 vminss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5d 11 vminss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 59 d4 vmulss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 59 11 vmulss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 53 d4 vrcpss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 53 11 vrcpss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 52 d4 vrsqrtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 52 11 vrsqrtss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 51 d4 vsqrtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 51 11 vsqrtss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5c d4 vsubss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 10 vcmpeq_osss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 11 vcmplt_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 11 vcmplt_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 12 vcmple_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 12 vcmple_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 13 vcmpunord_sss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 13 vcmpunord_sss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 14 vcmpneq_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 14 vcmpneq_usss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 15 vcmpnlt_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 15 vcmpnlt_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 16 vcmpnle_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 16 vcmpnle_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 17 vcmpord_sss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 17 vcmpord_sss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 18 vcmpeq_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 18 vcmpeq_usss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 19 vcmpnge_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 19 vcmpnge_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1a vcmpngt_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1a vcmpngt_uqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1b vcmpfalse_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1b vcmpfalse_osss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1c vcmpneq_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1c vcmpneq_osss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1d vcmpge_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1d vcmpge_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1e vcmpgt_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1e vcmpgt_oqss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1f vcmptrue_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1f vcmptrue_usss \(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 7d 18 21 vbroadcastss \(%ecx\),%ymm4 +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 18 21 vbroadcastss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd %ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss %ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%ecx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 e9 6a fc 60 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6a 39 60 vfmaddss \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6a 39 40 vfmaddss %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6e fc 60 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6e 39 60 vfmsubss \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6e 39 40 vfmsubss %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7a fc 60 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7a 39 60 vfnmaddss \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7a 39 40 vfnmaddss %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7e fc 60 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7e 39 60 vfnmsubss \(%ecx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7e 39 40 vfnmsubss %xmm4,\(%ecx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c5 c8 12 d4 vmovhlps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 ff e6 f4 vcvtpd2dq %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fd 5a f4 vcvtpd2ps %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fd e6 f4 vcvttpd2dq %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 ae 15 34 12 00 00 vldmxcsr 0x1234 +[ ]*[a-f0-9]+: c5 f9 6f 05 34 12 00 00 vmovdqa 0x1234,%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 05 34 12 00 00 vmovdqa %xmm0,0x1234 +[ ]*[a-f0-9]+: c5 f9 7e 05 34 12 00 00 vmovd %xmm0,0x1234 +[ ]*[a-f0-9]+: c5 fb 2d 05 34 12 00 00 vcvtsd2si 0x1234,%eax +[ ]*[a-f0-9]+: c5 fe e6 05 34 12 00 00 vcvtdq2pd 0x1234,%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 05 34 12 00 00 vcvtpd2psy 0x1234,%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 3d 34 12 00 00 vpavgb 0x1234,%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 64 vpextrb \$0x64,%xmm0,0x1234 +[ ]*[a-f0-9]+: c5 fb 2a 3d 34 12 00 00 vcvtsi2sdl 0x1234,%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 35 34 12 00 00 00 vblendvps %xmm0,0x1234,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 64 vpinsrb \$0x64,0x1234,%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 05 34 12 00 00 vmovdqa 0x1234,%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 05 34 12 00 00 vmovdqa %ymm0,0x1234 +[ ]*[a-f0-9]+: c4 e2 7d 0d 3d 34 12 00 00 vpermilpd 0x1234,%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 64 vroundpd \$0x64,0x1234,%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 64 vextractf128 \$0x64,%ymm0,0x1234 +[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 64 vperm2f128 \$0x64,0x1234,%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 35 34 12 00 00 00 vblendvpd %ymm0,0x1234,%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%ebp\) +[ ]*[a-f0-9]+: c5 f9 6f 45 00 vmovdqa 0x0\(%ebp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 45 00 vmovdqa %xmm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c5 f9 7e 45 00 vmovd %xmm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c5 fb 2d 45 00 vcvtsd2si 0x0\(%ebp\),%eax +[ ]*[a-f0-9]+: c5 fe e6 45 00 vcvtdq2pd 0x0\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 45 00 vcvtpd2psy 0x0\(%ebp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 7d 00 vpavgb 0x0\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 45 00 64 vpextrb \$0x64,%xmm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c5 fb 2a 7d 00 vcvtsi2sdl 0x0\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 75 00 00 vblendvps %xmm0,0x0\(%ebp\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 64 vpinsrb \$0x64,0x0\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 45 00 vmovdqa 0x0\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 45 00 vmovdqa %ymm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c4 e2 7d 0d 7d 00 vpermilpd 0x0\(%ebp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 64 vroundpd \$0x64,0x0\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 64 vextractf128 \$0x64,%ymm0,0x0\(%ebp\) +[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 64 vperm2f128 \$0x64,0x0\(%ebp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 75 00 00 vblendvpd %ymm0,0x0\(%ebp\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr 0x99\(%ebp\) +[ ]*[a-f0-9]+: c5 f9 6f 85 99 00 00 00 vmovdqa 0x99\(%ebp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 85 99 00 00 00 vmovdqa %xmm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c5 f9 7e 85 99 00 00 00 vmovd %xmm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c5 fb 2d 85 99 00 00 00 vcvtsd2si 0x99\(%ebp\),%eax +[ ]*[a-f0-9]+: c5 fe e6 85 99 00 00 00 vcvtdq2pd 0x99\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 85 99 00 00 00 vcvtpd2psy 0x99\(%ebp\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bd 99 00 00 00 vpavgb 0x99\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c5 fb 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b5 99 00 00 00 00 vblendvps %xmm0,0x99\(%ebp\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 64 vpinsrb \$0x64,0x99\(%ebp\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 85 99 00 00 00 vmovdqa 0x99\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 85 99 00 00 00 vmovdqa %ymm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bd 99 00 00 00 vpermilpd 0x99\(%ebp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 64 vroundpd \$0x64,0x99\(%ebp\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%ebp\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%ebp\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b5 99 00 00 00 00 vblendvpd %ymm0,0x99\(%ebp\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 99 00 00 00 vldmxcsr 0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c5 f9 6f 04 25 99 00 00 00 vmovdqa 0x99\(,%eiz,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 04 25 99 00 00 00 vmovdqa %xmm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c5 f9 7e 04 25 99 00 00 00 vmovd %xmm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c5 fb 2d 04 25 99 00 00 00 vcvtsd2si 0x99\(,%eiz,1\),%eax +[ ]*[a-f0-9]+: c5 fe e6 04 25 99 00 00 00 vcvtdq2pd 0x99\(,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 04 25 99 00 00 00 vcvtpd2psy 0x99\(,%eiz,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 3c 25 99 00 00 00 vpavgb 0x99\(,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c5 fb 2a 3c 25 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 34 25 99 00 00 00 00 vblendvps %xmm0,0x99\(,%eiz,1\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 64 vpinsrb \$0x64,0x99\(,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 04 25 99 00 00 00 vmovdqa 0x99\(,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 04 25 99 00 00 00 vmovdqa %ymm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 25 99 00 00 00 vpermilpd 0x99\(,%eiz,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 64 vroundpd \$0x64,0x99\(,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(,%eiz,1\) +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 64 vperm2f128 \$0x64,0x99\(,%eiz,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 25 99 00 00 00 00 vblendvpd %ymm0,0x99\(,%eiz,1\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 14 65 99 00 00 00 vldmxcsr 0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c5 f9 6f 04 65 99 00 00 00 vmovdqa 0x99\(,%eiz,2\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 04 65 99 00 00 00 vmovdqa %xmm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c5 f9 7e 04 65 99 00 00 00 vmovd %xmm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c5 fb 2d 04 65 99 00 00 00 vcvtsd2si 0x99\(,%eiz,2\),%eax +[ ]*[a-f0-9]+: c5 fe e6 04 65 99 00 00 00 vcvtdq2pd 0x99\(,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 04 65 99 00 00 00 vcvtpd2psy 0x99\(,%eiz,2\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 3c 65 99 00 00 00 vpavgb 0x99\(,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c5 fb 2a 3c 65 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a 34 65 99 00 00 00 00 vblendvps %xmm0,0x99\(,%eiz,2\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 64 vpinsrb \$0x64,0x99\(,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 04 65 99 00 00 00 vmovdqa 0x99\(,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 04 65 99 00 00 00 vmovdqa %ymm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 65 99 00 00 00 vpermilpd 0x99\(,%eiz,2\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 64 vroundpd \$0x64,0x99\(,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(,%eiz,2\) +[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 64 vperm2f128 \$0x64,0x99\(,%eiz,2\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b 34 65 99 00 00 00 00 vblendvpd %ymm0,0x99\(,%eiz,2\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 20 99 00 00 00 vldmxcsr 0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c5 f9 6f 84 20 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 20 99 00 00 00 vmovdqa %xmm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c5 f9 7e 84 20 99 00 00 00 vmovd %xmm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c5 fb 2d 84 20 99 00 00 00 vcvtsd2si 0x99\(%eax,%eiz,1\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 20 99 00 00 00 vcvtdq2pd 0x99\(%eax,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 20 99 00 00 00 vcvtpd2psy 0x99\(%eax,%eiz,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc 20 99 00 00 00 vpavgb 0x99\(%eax,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c5 fb 2a bc 20 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 20 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%eiz,1\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%eiz,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 20 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 20 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 20 99 00 00 00 vpermilpd 0x99\(%eax,%eiz,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%eiz,1\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%eiz,1\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%eiz,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 20 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%eiz,1\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 60 99 00 00 00 vldmxcsr 0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c5 f9 6f 84 60 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,2\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 60 99 00 00 00 vmovdqa %xmm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c5 f9 7e 84 60 99 00 00 00 vmovd %xmm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c5 fb 2d 84 60 99 00 00 00 vcvtsd2si 0x99\(%eax,%eiz,2\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 60 99 00 00 00 vcvtdq2pd 0x99\(%eax,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 60 99 00 00 00 vcvtpd2psy 0x99\(%eax,%eiz,2\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc 60 99 00 00 00 vpavgb 0x99\(%eax,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c5 fb 2a bc 60 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 60 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%eiz,2\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%eiz,2\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 60 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 60 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 60 99 00 00 00 vpermilpd 0x99\(%eax,%eiz,2\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%eiz,2\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%eiz,2\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%eiz,2\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 60 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%eiz,2\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 98 99 00 00 00 vldmxcsr 0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c5 f9 6f 84 98 99 00 00 00 vmovdqa 0x99\(%eax,%ebx,4\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 98 99 00 00 00 vmovdqa %xmm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c5 f9 7e 84 98 99 00 00 00 vmovd %xmm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c5 fb 2d 84 98 99 00 00 00 vcvtsd2si 0x99\(%eax,%ebx,4\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 98 99 00 00 00 vcvtdq2pd 0x99\(%eax,%ebx,4\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 98 99 00 00 00 vcvtpd2psy 0x99\(%eax,%ebx,4\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc 98 99 00 00 00 vpavgb 0x99\(%eax,%ebx,4\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c5 fb 2a bc 98 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%ebx,4\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 98 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%ebx,4\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%ebx,4\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 98 99 00 00 00 vmovdqa 0x99\(%eax,%ebx,4\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 98 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 98 99 00 00 00 vpermilpd 0x99\(%eax,%ebx,4\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%ebx,4\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%ebx,4\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%ebx,4\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 98 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%ebx,4\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 cc 99 00 00 00 vldmxcsr 0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c5 f9 6f 84 cc 99 00 00 00 vmovdqa 0x99\(%esp,%ecx,8\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 cc 99 00 00 00 vmovdqa %xmm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c5 f9 7e 84 cc 99 00 00 00 vmovd %xmm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c5 fb 2d 84 cc 99 00 00 00 vcvtsd2si 0x99\(%esp,%ecx,8\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 cc 99 00 00 00 vcvtdq2pd 0x99\(%esp,%ecx,8\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 cc 99 00 00 00 vcvtpd2psy 0x99\(%esp,%ecx,8\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc cc 99 00 00 00 vpavgb 0x99\(%esp,%ecx,8\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c5 fb 2a bc cc 99 00 00 00 vcvtsi2sdl 0x99\(%esp,%ecx,8\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 cc 99 00 00 00 00 vblendvps %xmm0,0x99\(%esp,%ecx,8\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 64 vpinsrb \$0x64,0x99\(%esp,%ecx,8\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 cc 99 00 00 00 vmovdqa 0x99\(%esp,%ecx,8\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 cc 99 00 00 00 vmovdqa %ymm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc cc 99 00 00 00 vpermilpd 0x99\(%esp,%ecx,8\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 64 vroundpd \$0x64,0x99\(%esp,%ecx,8\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%esp,%ecx,8\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%esp,%ecx,8\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 cc 99 00 00 00 00 vblendvpd %ymm0,0x99\(%esp,%ecx,8\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f8 ae 94 15 99 00 00 00 vldmxcsr 0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c5 f9 6f 84 15 99 00 00 00 vmovdqa 0x99\(%ebp,%edx,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 7f 84 15 99 00 00 00 vmovdqa %xmm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c5 f9 7e 84 15 99 00 00 00 vmovd %xmm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c5 fb 2d 84 15 99 00 00 00 vcvtsd2si 0x99\(%ebp,%edx,1\),%eax +[ ]*[a-f0-9]+: c5 fe e6 84 15 99 00 00 00 vcvtdq2pd 0x99\(%ebp,%edx,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 5a 84 15 99 00 00 00 vcvtpd2psy 0x99\(%ebp,%edx,1\),%xmm0 +[ ]*[a-f0-9]+: c5 f9 e0 bc 15 99 00 00 00 vpavgb 0x99\(%ebp,%edx,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c5 fb 2a bc 15 99 00 00 00 vcvtsi2sdl 0x99\(%ebp,%edx,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c4 e3 59 4a b4 15 99 00 00 00 00 vblendvps %xmm0,0x99\(%ebp,%edx,1\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 64 vpinsrb \$0x64,0x99\(%ebp,%edx,1\),%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fd 6f 84 15 99 00 00 00 vmovdqa 0x99\(%ebp,%edx,1\),%ymm0 +[ ]*[a-f0-9]+: c5 fd 7f 84 15 99 00 00 00 vmovdqa %ymm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c4 e2 7d 0d bc 15 99 00 00 00 vpermilpd 0x99\(%ebp,%edx,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 64 vroundpd \$0x64,0x99\(%ebp,%edx,1\),%ymm0 +[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%ebp,%edx,1\) +[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%ebp,%edx,1\),%ymm0,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 4b b4 15 99 00 00 00 00 vblendvpd %ymm0,0x99\(%ebp,%edx,1\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c5 f9 50 c0 vmovmskpd %xmm0,%eax +[ ]*[a-f0-9]+: c5 c1 72 f0 64 vpslld \$0x64,%xmm0,%xmm7 +[ ]*[a-f0-9]+: c5 fc 50 c0 vmovmskps %ymm0,%eax +#pass diff --git a/gas/testsuite/gas/i386/avx.s b/gas/testsuite/gas/i386/avx.s new file mode 100644 index 0000000..bfb8a0f --- /dev/null +++ b/gas/testsuite/gas/i386/avx.s @@ -0,0 +1,3042 @@ +# Check AVX instructions + + .allow_index_reg + .text +_start: +# Tests for op + vzeroall + vzeroupper + +# Tests for op mem64 + vldmxcsr (%ecx) + vstmxcsr (%ecx) + +# Tests for op mem256, mask, ymm +# Tests for op ymm, mask, mem256 + vmaskmovpd (%ecx),%ymm4,%ymm6 + vmaskmovpd %ymm4,%ymm6,(%ecx) + vmaskmovps (%ecx),%ymm4,%ymm6 + vmaskmovps %ymm4,%ymm6,(%ecx) + +# Tests for op imm8, ymm/mem256, ymm + vpermilpd $100,%ymm6,%ymm2 + vpermilpd $100,(%ecx),%ymm6 + vpermilps $100,%ymm6,%ymm2 + vpermilps $100,(%ecx),%ymm6 + vroundpd $100,%ymm6,%ymm2 + vroundpd $100,(%ecx),%ymm6 + vroundps $100,%ymm6,%ymm2 + vroundps $100,(%ecx),%ymm6 + +# Tests for op ymm/mem256, ymm, ymm + vaddpd %ymm4,%ymm6,%ymm2 + vaddpd (%ecx),%ymm6,%ymm2 + vaddps %ymm4,%ymm6,%ymm2 + vaddps (%ecx),%ymm6,%ymm2 + vaddsubpd %ymm4,%ymm6,%ymm2 + vaddsubpd (%ecx),%ymm6,%ymm2 + vaddsubps %ymm4,%ymm6,%ymm2 + vaddsubps (%ecx),%ymm6,%ymm2 + vandnpd %ymm4,%ymm6,%ymm2 + vandnpd (%ecx),%ymm6,%ymm2 + vandnps %ymm4,%ymm6,%ymm2 + vandnps (%ecx),%ymm6,%ymm2 + vandpd %ymm4,%ymm6,%ymm2 + vandpd (%ecx),%ymm6,%ymm2 + vandps %ymm4,%ymm6,%ymm2 + vandps (%ecx),%ymm6,%ymm2 + vdivpd %ymm4,%ymm6,%ymm2 + vdivpd (%ecx),%ymm6,%ymm2 + vdivps %ymm4,%ymm6,%ymm2 + vdivps (%ecx),%ymm6,%ymm2 + vhaddpd %ymm4,%ymm6,%ymm2 + vhaddpd (%ecx),%ymm6,%ymm2 + vhaddps %ymm4,%ymm6,%ymm2 + vhaddps (%ecx),%ymm6,%ymm2 + vhsubpd %ymm4,%ymm6,%ymm2 + vhsubpd (%ecx),%ymm6,%ymm2 + vhsubps %ymm4,%ymm6,%ymm2 + vhsubps (%ecx),%ymm6,%ymm2 + vmaxpd %ymm4,%ymm6,%ymm2 + vmaxpd (%ecx),%ymm6,%ymm2 + vmaxps %ymm4,%ymm6,%ymm2 + vmaxps (%ecx),%ymm6,%ymm2 + vminpd %ymm4,%ymm6,%ymm2 + vminpd (%ecx),%ymm6,%ymm2 + vminps %ymm4,%ymm6,%ymm2 + vminps (%ecx),%ymm6,%ymm2 + vmulpd %ymm4,%ymm6,%ymm2 + vmulpd (%ecx),%ymm6,%ymm2 + vmulps %ymm4,%ymm6,%ymm2 + vmulps (%ecx),%ymm6,%ymm2 + vorpd %ymm4,%ymm6,%ymm2 + vorpd (%ecx),%ymm6,%ymm2 + vorps %ymm4,%ymm6,%ymm2 + vorps (%ecx),%ymm6,%ymm2 + vpermilpd %ymm4,%ymm6,%ymm2 + vpermilpd (%ecx),%ymm6,%ymm2 + vpermilps %ymm4,%ymm6,%ymm2 + vpermilps (%ecx),%ymm6,%ymm2 + vsubpd %ymm4,%ymm6,%ymm2 + vsubpd (%ecx),%ymm6,%ymm2 + vsubps %ymm4,%ymm6,%ymm2 + vsubps (%ecx),%ymm6,%ymm2 + vunpckhpd %ymm4,%ymm6,%ymm2 + vunpckhpd (%ecx),%ymm6,%ymm2 + vunpckhps %ymm4,%ymm6,%ymm2 + vunpckhps (%ecx),%ymm6,%ymm2 + vunpcklpd %ymm4,%ymm6,%ymm2 + vunpcklpd (%ecx),%ymm6,%ymm2 + vunpcklps %ymm4,%ymm6,%ymm2 + vunpcklps (%ecx),%ymm6,%ymm2 + vxorpd %ymm4,%ymm6,%ymm2 + vxorpd (%ecx),%ymm6,%ymm2 + vxorps %ymm4,%ymm6,%ymm2 + vxorps (%ecx),%ymm6,%ymm2 + vcmpeqpd %ymm4,%ymm6,%ymm2 + vcmpeqpd (%ecx),%ymm6,%ymm2 + vcmpltpd %ymm4,%ymm6,%ymm2 + vcmpltpd (%ecx),%ymm6,%ymm2 + vcmplepd %ymm4,%ymm6,%ymm2 + vcmplepd (%ecx),%ymm6,%ymm2 + vcmpunordpd %ymm4,%ymm6,%ymm2 + vcmpunordpd (%ecx),%ymm6,%ymm2 + vcmpneqpd %ymm4,%ymm6,%ymm2 + vcmpneqpd (%ecx),%ymm6,%ymm2 + vcmpnltpd %ymm4,%ymm6,%ymm2 + vcmpnltpd (%ecx),%ymm6,%ymm2 + vcmpnlepd %ymm4,%ymm6,%ymm2 + vcmpnlepd (%ecx),%ymm6,%ymm2 + vcmpordpd %ymm4,%ymm6,%ymm2 + vcmpordpd (%ecx),%ymm6,%ymm2 + vcmpeq_uqpd %ymm4,%ymm6,%ymm2 + vcmpeq_uqpd (%ecx),%ymm6,%ymm2 + vcmpngepd %ymm4,%ymm6,%ymm2 + vcmpngepd (%ecx),%ymm6,%ymm2 + vcmpngtpd %ymm4,%ymm6,%ymm2 + vcmpngtpd (%ecx),%ymm6,%ymm2 + vcmpfalsepd %ymm4,%ymm6,%ymm2 + vcmpfalsepd (%ecx),%ymm6,%ymm2 + vcmpneq_oqpd %ymm4,%ymm6,%ymm2 + vcmpneq_oqpd (%ecx),%ymm6,%ymm2 + vcmpgepd %ymm4,%ymm6,%ymm2 + vcmpgepd (%ecx),%ymm6,%ymm2 + vcmpgtpd %ymm4,%ymm6,%ymm2 + vcmpgtpd (%ecx),%ymm6,%ymm2 + vcmptruepd %ymm4,%ymm6,%ymm2 + vcmptruepd (%ecx),%ymm6,%ymm2 + vcmpeq_ospd %ymm4,%ymm6,%ymm2 + vcmpeq_ospd (%ecx),%ymm6,%ymm2 + vcmplt_oqpd %ymm4,%ymm6,%ymm2 + vcmplt_oqpd (%ecx),%ymm6,%ymm2 + vcmple_oqpd %ymm4,%ymm6,%ymm2 + vcmple_oqpd (%ecx),%ymm6,%ymm2 + vcmpunord_spd %ymm4,%ymm6,%ymm2 + vcmpunord_spd (%ecx),%ymm6,%ymm2 + vcmpneq_uspd %ymm4,%ymm6,%ymm2 + vcmpneq_uspd (%ecx),%ymm6,%ymm2 + vcmpnlt_uqpd %ymm4,%ymm6,%ymm2 + vcmpnlt_uqpd (%ecx),%ymm6,%ymm2 + vcmpnle_uqpd %ymm4,%ymm6,%ymm2 + vcmpnle_uqpd (%ecx),%ymm6,%ymm2 + vcmpord_spd %ymm4,%ymm6,%ymm2 + vcmpord_spd (%ecx),%ymm6,%ymm2 + vcmpeq_uspd %ymm4,%ymm6,%ymm2 + vcmpeq_uspd (%ecx),%ymm6,%ymm2 + vcmpnge_uqpd %ymm4,%ymm6,%ymm2 + vcmpnge_uqpd (%ecx),%ymm6,%ymm2 + vcmpngt_uqpd %ymm4,%ymm6,%ymm2 + vcmpngt_uqpd (%ecx),%ymm6,%ymm2 + vcmpfalse_ospd %ymm4,%ymm6,%ymm2 + vcmpfalse_ospd (%ecx),%ymm6,%ymm2 + vcmpneq_ospd %ymm4,%ymm6,%ymm2 + vcmpneq_ospd (%ecx),%ymm6,%ymm2 + vcmpge_oqpd %ymm4,%ymm6,%ymm2 + vcmpge_oqpd (%ecx),%ymm6,%ymm2 + vcmpgt_oqpd %ymm4,%ymm6,%ymm2 + vcmpgt_oqpd (%ecx),%ymm6,%ymm2 + vcmptrue_uspd %ymm4,%ymm6,%ymm2 + vcmptrue_uspd (%ecx),%ymm6,%ymm2 + vcmpeqps %ymm4,%ymm6,%ymm2 + vcmpeqps (%ecx),%ymm6,%ymm2 + vcmpltps %ymm4,%ymm6,%ymm2 + vcmpltps (%ecx),%ymm6,%ymm2 + vcmpleps %ymm4,%ymm6,%ymm2 + vcmpleps (%ecx),%ymm6,%ymm2 + vcmpunordps %ymm4,%ymm6,%ymm2 + vcmpunordps (%ecx),%ymm6,%ymm2 + vcmpneqps %ymm4,%ymm6,%ymm2 + vcmpneqps (%ecx),%ymm6,%ymm2 + vcmpnltps %ymm4,%ymm6,%ymm2 + vcmpnltps (%ecx),%ymm6,%ymm2 + vcmpnleps %ymm4,%ymm6,%ymm2 + vcmpnleps (%ecx),%ymm6,%ymm2 + vcmpordps %ymm4,%ymm6,%ymm2 + vcmpordps (%ecx),%ymm6,%ymm2 + vcmpeq_uqps %ymm4,%ymm6,%ymm2 + vcmpeq_uqps (%ecx),%ymm6,%ymm2 + vcmpngeps %ymm4,%ymm6,%ymm2 + vcmpngeps (%ecx),%ymm6,%ymm2 + vcmpngtps %ymm4,%ymm6,%ymm2 + vcmpngtps (%ecx),%ymm6,%ymm2 + vcmpfalseps %ymm4,%ymm6,%ymm2 + vcmpfalseps (%ecx),%ymm6,%ymm2 + vcmpneq_oqps %ymm4,%ymm6,%ymm2 + vcmpneq_oqps (%ecx),%ymm6,%ymm2 + vcmpgeps %ymm4,%ymm6,%ymm2 + vcmpgeps (%ecx),%ymm6,%ymm2 + vcmpgtps %ymm4,%ymm6,%ymm2 + vcmpgtps (%ecx),%ymm6,%ymm2 + vcmptrueps %ymm4,%ymm6,%ymm2 + vcmptrueps (%ecx),%ymm6,%ymm2 + vcmpeq_osps %ymm4,%ymm6,%ymm2 + vcmpeq_osps (%ecx),%ymm6,%ymm2 + vcmplt_oqps %ymm4,%ymm6,%ymm2 + vcmplt_oqps (%ecx),%ymm6,%ymm2 + vcmple_oqps %ymm4,%ymm6,%ymm2 + vcmple_oqps (%ecx),%ymm6,%ymm2 + vcmpunord_sps %ymm4,%ymm6,%ymm2 + vcmpunord_sps (%ecx),%ymm6,%ymm2 + vcmpneq_usps %ymm4,%ymm6,%ymm2 + vcmpneq_usps (%ecx),%ymm6,%ymm2 + vcmpnlt_uqps %ymm4,%ymm6,%ymm2 + vcmpnlt_uqps (%ecx),%ymm6,%ymm2 + vcmpnle_uqps %ymm4,%ymm6,%ymm2 + vcmpnle_uqps (%ecx),%ymm6,%ymm2 + vcmpord_sps %ymm4,%ymm6,%ymm2 + vcmpord_sps (%ecx),%ymm6,%ymm2 + vcmpeq_usps %ymm4,%ymm6,%ymm2 + vcmpeq_usps (%ecx),%ymm6,%ymm2 + vcmpnge_uqps %ymm4,%ymm6,%ymm2 + vcmpnge_uqps (%ecx),%ymm6,%ymm2 + vcmpngt_uqps %ymm4,%ymm6,%ymm2 + vcmpngt_uqps (%ecx),%ymm6,%ymm2 + vcmpfalse_osps %ymm4,%ymm6,%ymm2 + vcmpfalse_osps (%ecx),%ymm6,%ymm2 + vcmpneq_osps %ymm4,%ymm6,%ymm2 + vcmpneq_osps (%ecx),%ymm6,%ymm2 + vcmpge_oqps %ymm4,%ymm6,%ymm2 + vcmpge_oqps (%ecx),%ymm6,%ymm2 + vcmpgt_oqps %ymm4,%ymm6,%ymm2 + vcmpgt_oqps (%ecx),%ymm6,%ymm2 + vcmptrue_usps %ymm4,%ymm6,%ymm2 + vcmptrue_usps (%ecx),%ymm6,%ymm2 + +# Tests for op ymm/mem256, xmm + vcvtpd2dqy %ymm4,%xmm4 + vcvtpd2dqy (%ecx),%xmm4 + vcvtpd2psy %ymm4,%xmm4 + vcvtpd2psy (%ecx),%xmm4 + vcvttpd2dqy %ymm4,%xmm4 + vcvttpd2dqy (%ecx),%xmm4 + +# Tests for op ymm/mem256, ymm + vcvtdq2ps %ymm4,%ymm4 + vcvtdq2ps (%ecx),%ymm4 + vcvtps2dq %ymm4,%ymm4 + vcvtps2dq (%ecx),%ymm4 + vcvttps2dq %ymm4,%ymm4 + vcvttps2dq (%ecx),%ymm4 + vmovapd %ymm4,%ymm4 + vmovapd (%ecx),%ymm4 + vmovaps %ymm4,%ymm4 + vmovaps (%ecx),%ymm4 + vmovdqa %ymm4,%ymm4 + vmovdqa (%ecx),%ymm4 + vmovdqu %ymm4,%ymm4 + vmovdqu (%ecx),%ymm4 + vmovddup %ymm4,%ymm4 + vmovddup (%ecx),%ymm4 + vmovshdup %ymm4,%ymm4 + vmovshdup (%ecx),%ymm4 + vmovsldup %ymm4,%ymm4 + vmovsldup (%ecx),%ymm4 + vmovupd %ymm4,%ymm4 + vmovupd (%ecx),%ymm4 + vmovups %ymm4,%ymm4 + vmovups (%ecx),%ymm4 + vptest %ymm4,%ymm4 + vptest (%ecx),%ymm4 + vrcpps %ymm4,%ymm4 + vrcpps (%ecx),%ymm4 + vrsqrtps %ymm4,%ymm4 + vrsqrtps (%ecx),%ymm4 + vsqrtpd %ymm4,%ymm4 + vsqrtpd (%ecx),%ymm4 + vsqrtps %ymm4,%ymm4 + vsqrtps (%ecx),%ymm4 + vtestpd %ymm4,%ymm4 + vtestpd (%ecx),%ymm4 + vtestps %ymm4,%ymm4 + vtestps (%ecx),%ymm4 + +# Tests for op mem256, ymm + vlddqu (%ecx),%ymm4 + +# Tests for op imm8, ymm/mem256, ymm, ymm + vblendpd $100,%ymm4,%ymm6,%ymm2 + vblendpd $100,(%ecx),%ymm6,%ymm2 + vblendps $100,%ymm4,%ymm6,%ymm2 + vblendps $100,(%ecx),%ymm6,%ymm2 + vcmppd $100,%ymm4,%ymm6,%ymm2 + vcmppd $100,(%ecx),%ymm6,%ymm2 + vcmpps $100,%ymm4,%ymm6,%ymm2 + vcmpps $100,(%ecx),%ymm6,%ymm2 + vdpps $100,%ymm4,%ymm6,%ymm2 + vdpps $100,(%ecx),%ymm6,%ymm2 + vperm2f128 $100,%ymm4,%ymm6,%ymm2 + vperm2f128 $100,(%ecx),%ymm6,%ymm2 + vshufpd $100,%ymm4,%ymm6,%ymm2 + vshufpd $100,(%ecx),%ymm6,%ymm2 + vshufps $100,%ymm4,%ymm6,%ymm2 + vshufps $100,(%ecx),%ymm6,%ymm2 + +# Tests for op ymm, ymm/mem256, ymm, ymm + vblendvpd %ymm4,%ymm6,%ymm2,%ymm7 + vblendvpd %ymm4,(%ecx),%ymm2,%ymm7 + vblendvps %ymm4,%ymm6,%ymm2,%ymm7 + vblendvps %ymm4,(%ecx),%ymm2,%ymm7 + +# Tests for op ymm/mem256, ymm, ymm, ymm +# Tests for op ymm, ymm/mem256, ymm, ymm + vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 + vfmaddpd (%ecx),%ymm6,%ymm2,%ymm7 + vfmaddps %ymm4,%ymm6,%ymm2,%ymm7 + vfmaddps (%ecx),%ymm6,%ymm2,%ymm7 + vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7 + vfmaddsubpd (%ecx),%ymm6,%ymm2,%ymm7 + vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7 + vfmaddsubps (%ecx),%ymm6,%ymm2,%ymm7 + vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7 + vfmsubaddpd (%ecx),%ymm6,%ymm2,%ymm7 + vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7 + vfmsubaddps (%ecx),%ymm6,%ymm2,%ymm7 + vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7 + vfmsubpd (%ecx),%ymm6,%ymm2,%ymm7 + vfmsubps %ymm4,%ymm6,%ymm2,%ymm7 + vfmsubps (%ecx),%ymm6,%ymm2,%ymm7 + vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7 + vfnmaddpd (%ecx),%ymm6,%ymm2,%ymm7 + vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7 + vfnmaddps (%ecx),%ymm6,%ymm2,%ymm7 + vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7 + vfnmsubpd (%ecx),%ymm6,%ymm2,%ymm7 + vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7 + vfnmsubps (%ecx),%ymm6,%ymm2,%ymm7 + vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7 + vpermilmo2pd (%ecx),%ymm6,%ymm2,%ymm7 + vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7 + vpermilmz2pd (%ecx),%ymm6,%ymm2,%ymm7 + vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7 + vpermiltd2pd (%ecx),%ymm6,%ymm2,%ymm7 + vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7 + vpermilmo2ps (%ecx),%ymm6,%ymm2,%ymm7 + vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7 + vpermilmz2ps (%ecx),%ymm6,%ymm2,%ymm7 + vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7 + vpermiltd2ps (%ecx),%ymm6,%ymm2,%ymm7 + +# Tests for op imm4, ymm/mem256, ymm, ymm, ymm +# Tests for op imm4, ymm, ymm/mem256, ymm, ymm + vpermil2pd $10,%ymm4,%ymm6,%ymm2,%ymm7 + vpermil2pd $10,(%ecx),%ymm6,%ymm2,%ymm7 + vpermil2ps $10,%ymm4,%ymm6,%ymm2,%ymm7 + vpermil2ps $10,(%ecx),%ymm6,%ymm2,%ymm7 + +# Tests for op imm8, xmm/mem128, ymm, ymm + vinsertf128 $100,%xmm4,%ymm4,%ymm6 + vinsertf128 $100,(%ecx),%ymm4,%ymm6 + +# Tests for op imm8, ymm, xmm/mem128 + vextractf128 $100,%ymm4,%xmm4 + vextractf128 $100,%ymm4,(%ecx) + +# Tests for op xmm/mem128, xmm +# Tests for op mem128, ymm + vbroadcastf128 (%ecx),%ymm4 + +# Tests for op xmm/mem128, xmm + vcvtdq2ps %xmm4,%xmm6 + vcvtdq2ps (%ecx),%xmm4 + vcvtpd2dqx %xmm4,%xmm6 + vcvtpd2dqx (%ecx),%xmm4 + vcvtpd2psx %xmm4,%xmm6 + vcvtpd2psx (%ecx),%xmm4 + vcvtps2dq %xmm4,%xmm6 + vcvtps2dq (%ecx),%xmm4 + vcvttpd2dqx %xmm4,%xmm6 + vcvttpd2dqx (%ecx),%xmm4 + vcvttps2dq %xmm4,%xmm6 + vcvttps2dq (%ecx),%xmm4 + vmovapd %xmm4,%xmm6 + vmovapd (%ecx),%xmm4 + vmovaps %xmm4,%xmm6 + vmovaps (%ecx),%xmm4 + vmovdqa %xmm4,%xmm6 + vmovdqa (%ecx),%xmm4 + vmovdqu %xmm4,%xmm6 + vmovdqu (%ecx),%xmm4 + vmovshdup %xmm4,%xmm6 + vmovshdup (%ecx),%xmm4 + vmovsldup %xmm4,%xmm6 + vmovsldup (%ecx),%xmm4 + vmovupd %xmm4,%xmm6 + vmovupd (%ecx),%xmm4 + vmovups %xmm4,%xmm6 + vmovups (%ecx),%xmm4 + vpabsb %xmm4,%xmm6 + vpabsb (%ecx),%xmm4 + vpabsw %xmm4,%xmm6 + vpabsw (%ecx),%xmm4 + vpabsd %xmm4,%xmm6 + vpabsd (%ecx),%xmm4 + vphminposuw %xmm4,%xmm6 + vphminposuw (%ecx),%xmm4 + vptest %xmm4,%xmm6 + vptest (%ecx),%xmm4 + vtestps %xmm4,%xmm6 + vtestps (%ecx),%xmm4 + vtestpd %xmm4,%xmm6 + vtestpd (%ecx),%xmm4 + vrcpps %xmm4,%xmm6 + vrcpps (%ecx),%xmm4 + vrsqrtps %xmm4,%xmm6 + vrsqrtps (%ecx),%xmm4 + vsqrtpd %xmm4,%xmm6 + vsqrtpd (%ecx),%xmm4 + vsqrtps %xmm4,%xmm6 + vsqrtps (%ecx),%xmm4 + +# Tests for op xmm, xmm/mem128 + vmovapd %xmm4,%xmm6 + vmovapd %xmm4,(%ecx) + vmovaps %xmm4,%xmm6 + vmovaps %xmm4,(%ecx) + vmovdqa %xmm4,%xmm6 + vmovdqa %xmm4,(%ecx) + vmovdqu %xmm4,%xmm6 + vmovdqu %xmm4,(%ecx) + vmovupd %xmm4,%xmm6 + vmovupd %xmm4,(%ecx) + vmovups %xmm4,%xmm6 + vmovups %xmm4,(%ecx) + +# Tests for op mem128, xmm + vlddqu (%ecx),%xmm4 + vmovntdqa (%ecx),%xmm4 + +# Tests for op xmm, mem128 + vmovntdq %xmm4,(%ecx) + vmovntpd %xmm4,(%ecx) + vmovntps %xmm4,(%ecx) + +# Tests for op xmm/mem128, ymm + vcvtdq2pd %xmm4,%ymm4 + vcvtdq2pd (%ecx),%ymm4 + vcvtps2pd %xmm4,%ymm4 + vcvtps2pd (%ecx),%ymm4 + +# Tests for op xmm/mem128, xmm, xmm + vaddpd %xmm4,%xmm6,%xmm2 + vaddpd (%ecx),%xmm6,%xmm7 + vaddps %xmm4,%xmm6,%xmm2 + vaddps (%ecx),%xmm6,%xmm7 + vaddsubpd %xmm4,%xmm6,%xmm2 + vaddsubpd (%ecx),%xmm6,%xmm7 + vaddsubps %xmm4,%xmm6,%xmm2 + vaddsubps (%ecx),%xmm6,%xmm7 + vandnpd %xmm4,%xmm6,%xmm2 + vandnpd (%ecx),%xmm6,%xmm7 + vandnps %xmm4,%xmm6,%xmm2 + vandnps (%ecx),%xmm6,%xmm7 + vandpd %xmm4,%xmm6,%xmm2 + vandpd (%ecx),%xmm6,%xmm7 + vandps %xmm4,%xmm6,%xmm2 + vandps (%ecx),%xmm6,%xmm7 + vdivpd %xmm4,%xmm6,%xmm2 + vdivpd (%ecx),%xmm6,%xmm7 + vdivps %xmm4,%xmm6,%xmm2 + vdivps (%ecx),%xmm6,%xmm7 + vhaddpd %xmm4,%xmm6,%xmm2 + vhaddpd (%ecx),%xmm6,%xmm7 + vhaddps %xmm4,%xmm6,%xmm2 + vhaddps (%ecx),%xmm6,%xmm7 + vhsubpd %xmm4,%xmm6,%xmm2 + vhsubpd (%ecx),%xmm6,%xmm7 + vhsubps %xmm4,%xmm6,%xmm2 + vhsubps (%ecx),%xmm6,%xmm7 + vmaxpd %xmm4,%xmm6,%xmm2 + vmaxpd (%ecx),%xmm6,%xmm7 + vmaxps %xmm4,%xmm6,%xmm2 + vmaxps (%ecx),%xmm6,%xmm7 + vminpd %xmm4,%xmm6,%xmm2 + vminpd (%ecx),%xmm6,%xmm7 + vminps %xmm4,%xmm6,%xmm2 + vminps (%ecx),%xmm6,%xmm7 + vmulpd %xmm4,%xmm6,%xmm2 + vmulpd (%ecx),%xmm6,%xmm7 + vmulps %xmm4,%xmm6,%xmm2 + vmulps (%ecx),%xmm6,%xmm7 + vorpd %xmm4,%xmm6,%xmm2 + vorpd (%ecx),%xmm6,%xmm7 + vorps %xmm4,%xmm6,%xmm2 + vorps (%ecx),%xmm6,%xmm7 + vpacksswb %xmm4,%xmm6,%xmm2 + vpacksswb (%ecx),%xmm6,%xmm7 + vpackssdw %xmm4,%xmm6,%xmm2 + vpackssdw (%ecx),%xmm6,%xmm7 + vpackuswb %xmm4,%xmm6,%xmm2 + vpackuswb (%ecx),%xmm6,%xmm7 + vpackusdw %xmm4,%xmm6,%xmm2 + vpackusdw (%ecx),%xmm6,%xmm7 + vpaddb %xmm4,%xmm6,%xmm2 + vpaddb (%ecx),%xmm6,%xmm7 + vpaddw %xmm4,%xmm6,%xmm2 + vpaddw (%ecx),%xmm6,%xmm7 + vpaddd %xmm4,%xmm6,%xmm2 + vpaddd (%ecx),%xmm6,%xmm7 + vpaddq %xmm4,%xmm6,%xmm2 + vpaddq (%ecx),%xmm6,%xmm7 + vpaddsb %xmm4,%xmm6,%xmm2 + vpaddsb (%ecx),%xmm6,%xmm7 + vpaddsw %xmm4,%xmm6,%xmm2 + vpaddsw (%ecx),%xmm6,%xmm7 + vpaddusb %xmm4,%xmm6,%xmm2 + vpaddusb (%ecx),%xmm6,%xmm7 + vpaddusw %xmm4,%xmm6,%xmm2 + vpaddusw (%ecx),%xmm6,%xmm7 + vpand %xmm4,%xmm6,%xmm2 + vpand (%ecx),%xmm6,%xmm7 + vpandn %xmm4,%xmm6,%xmm2 + vpandn (%ecx),%xmm6,%xmm7 + vpavgb %xmm4,%xmm6,%xmm2 + vpavgb (%ecx),%xmm6,%xmm7 + vpavgw %xmm4,%xmm6,%xmm2 + vpavgw (%ecx),%xmm6,%xmm7 + vpcmpeqb %xmm4,%xmm6,%xmm2 + vpcmpeqb (%ecx),%xmm6,%xmm7 + vpcmpeqw %xmm4,%xmm6,%xmm2 + vpcmpeqw (%ecx),%xmm6,%xmm7 + vpcmpeqd %xmm4,%xmm6,%xmm2 + vpcmpeqd (%ecx),%xmm6,%xmm7 + vpcmpeqq %xmm4,%xmm6,%xmm2 + vpcmpeqq (%ecx),%xmm6,%xmm7 + vpcmpgtb %xmm4,%xmm6,%xmm2 + vpcmpgtb (%ecx),%xmm6,%xmm7 + vpcmpgtw %xmm4,%xmm6,%xmm2 + vpcmpgtw (%ecx),%xmm6,%xmm7 + vpcmpgtd %xmm4,%xmm6,%xmm2 + vpcmpgtd (%ecx),%xmm6,%xmm7 + vpcmpgtq %xmm4,%xmm6,%xmm2 + vpcmpgtq (%ecx),%xmm6,%xmm7 + vpermilpd %xmm4,%xmm6,%xmm2 + vpermilpd (%ecx),%xmm6,%xmm7 + vpermilps %xmm4,%xmm6,%xmm2 + vpermilps (%ecx),%xmm6,%xmm7 + vphaddw %xmm4,%xmm6,%xmm2 + vphaddw (%ecx),%xmm6,%xmm7 + vphaddd %xmm4,%xmm6,%xmm2 + vphaddd (%ecx),%xmm6,%xmm7 + vphaddsw %xmm4,%xmm6,%xmm2 + vphaddsw (%ecx),%xmm6,%xmm7 + vphsubw %xmm4,%xmm6,%xmm2 + vphsubw (%ecx),%xmm6,%xmm7 + vphsubd %xmm4,%xmm6,%xmm2 + vphsubd (%ecx),%xmm6,%xmm7 + vphsubsw %xmm4,%xmm6,%xmm2 + vphsubsw (%ecx),%xmm6,%xmm7 + vpmaddwd %xmm4,%xmm6,%xmm2 + vpmaddwd (%ecx),%xmm6,%xmm7 + vpmaddubsw %xmm4,%xmm6,%xmm2 + vpmaddubsw (%ecx),%xmm6,%xmm7 + vpmaxsb %xmm4,%xmm6,%xmm2 + vpmaxsb (%ecx),%xmm6,%xmm7 + vpmaxsw %xmm4,%xmm6,%xmm2 + vpmaxsw (%ecx),%xmm6,%xmm7 + vpmaxsd %xmm4,%xmm6,%xmm2 + vpmaxsd (%ecx),%xmm6,%xmm7 + vpmaxub %xmm4,%xmm6,%xmm2 + vpmaxub (%ecx),%xmm6,%xmm7 + vpmaxuw %xmm4,%xmm6,%xmm2 + vpmaxuw (%ecx),%xmm6,%xmm7 + vpmaxud %xmm4,%xmm6,%xmm2 + vpmaxud (%ecx),%xmm6,%xmm7 + vpminsb %xmm4,%xmm6,%xmm2 + vpminsb (%ecx),%xmm6,%xmm7 + vpminsw %xmm4,%xmm6,%xmm2 + vpminsw (%ecx),%xmm6,%xmm7 + vpminsd %xmm4,%xmm6,%xmm2 + vpminsd (%ecx),%xmm6,%xmm7 + vpminub %xmm4,%xmm6,%xmm2 + vpminub (%ecx),%xmm6,%xmm7 + vpminuw %xmm4,%xmm6,%xmm2 + vpminuw (%ecx),%xmm6,%xmm7 + vpminud %xmm4,%xmm6,%xmm2 + vpminud (%ecx),%xmm6,%xmm7 + vpmulhuw %xmm4,%xmm6,%xmm2 + vpmulhuw (%ecx),%xmm6,%xmm7 + vpmulhrsw %xmm4,%xmm6,%xmm2 + vpmulhrsw (%ecx),%xmm6,%xmm7 + vpmulhw %xmm4,%xmm6,%xmm2 + vpmulhw (%ecx),%xmm6,%xmm7 + vpmullw %xmm4,%xmm6,%xmm2 + vpmullw (%ecx),%xmm6,%xmm7 + vpmulld %xmm4,%xmm6,%xmm2 + vpmulld (%ecx),%xmm6,%xmm7 + vpmuludq %xmm4,%xmm6,%xmm2 + vpmuludq (%ecx),%xmm6,%xmm7 + vpmuldq %xmm4,%xmm6,%xmm2 + vpmuldq (%ecx),%xmm6,%xmm7 + vpor %xmm4,%xmm6,%xmm2 + vpor (%ecx),%xmm6,%xmm7 + vpsadbw %xmm4,%xmm6,%xmm2 + vpsadbw (%ecx),%xmm6,%xmm7 + vpshufb %xmm4,%xmm6,%xmm2 + vpshufb (%ecx),%xmm6,%xmm7 + vpsignb %xmm4,%xmm6,%xmm2 + vpsignb (%ecx),%xmm6,%xmm7 + vpsignw %xmm4,%xmm6,%xmm2 + vpsignw (%ecx),%xmm6,%xmm7 + vpsignd %xmm4,%xmm6,%xmm2 + vpsignd (%ecx),%xmm6,%xmm7 + vpsllw %xmm4,%xmm6,%xmm2 + vpsllw (%ecx),%xmm6,%xmm7 + vpslld %xmm4,%xmm6,%xmm2 + vpslld (%ecx),%xmm6,%xmm7 + vpsllq %xmm4,%xmm6,%xmm2 + vpsllq (%ecx),%xmm6,%xmm7 + vpsraw %xmm4,%xmm6,%xmm2 + vpsraw (%ecx),%xmm6,%xmm7 + vpsrad %xmm4,%xmm6,%xmm2 + vpsrad (%ecx),%xmm6,%xmm7 + vpsrlw %xmm4,%xmm6,%xmm2 + vpsrlw (%ecx),%xmm6,%xmm7 + vpsrld %xmm4,%xmm6,%xmm2 + vpsrld (%ecx),%xmm6,%xmm7 + vpsrlq %xmm4,%xmm6,%xmm2 + vpsrlq (%ecx),%xmm6,%xmm7 + vpsubb %xmm4,%xmm6,%xmm2 + vpsubb (%ecx),%xmm6,%xmm7 + vpsubw %xmm4,%xmm6,%xmm2 + vpsubw (%ecx),%xmm6,%xmm7 + vpsubd %xmm4,%xmm6,%xmm2 + vpsubd (%ecx),%xmm6,%xmm7 + vpsubq %xmm4,%xmm6,%xmm2 + vpsubq (%ecx),%xmm6,%xmm7 + vpsubsb %xmm4,%xmm6,%xmm2 + vpsubsb (%ecx),%xmm6,%xmm7 + vpsubsw %xmm4,%xmm6,%xmm2 + vpsubsw (%ecx),%xmm6,%xmm7 + vpsubusb %xmm4,%xmm6,%xmm2 + vpsubusb (%ecx),%xmm6,%xmm7 + vpsubusw %xmm4,%xmm6,%xmm2 + vpsubusw (%ecx),%xmm6,%xmm7 + vpunpckhbw %xmm4,%xmm6,%xmm2 + vpunpckhbw (%ecx),%xmm6,%xmm7 + vpunpckhwd %xmm4,%xmm6,%xmm2 + vpunpckhwd (%ecx),%xmm6,%xmm7 + vpunpckhdq %xmm4,%xmm6,%xmm2 + vpunpckhdq (%ecx),%xmm6,%xmm7 + vpunpckhqdq %xmm4,%xmm6,%xmm2 + vpunpckhqdq (%ecx),%xmm6,%xmm7 + vpunpcklbw %xmm4,%xmm6,%xmm2 + vpunpcklbw (%ecx),%xmm6,%xmm7 + vpunpcklwd %xmm4,%xmm6,%xmm2 + vpunpcklwd (%ecx),%xmm6,%xmm7 + vpunpckldq %xmm4,%xmm6,%xmm2 + vpunpckldq (%ecx),%xmm6,%xmm7 + vpunpcklqdq %xmm4,%xmm6,%xmm2 + vpunpcklqdq (%ecx),%xmm6,%xmm7 + vpxor %xmm4,%xmm6,%xmm2 + vpxor (%ecx),%xmm6,%xmm7 + vsubpd %xmm4,%xmm6,%xmm2 + vsubpd (%ecx),%xmm6,%xmm7 + vsubps %xmm4,%xmm6,%xmm2 + vsubps (%ecx),%xmm6,%xmm7 + vunpckhpd %xmm4,%xmm6,%xmm2 + vunpckhpd (%ecx),%xmm6,%xmm7 + vunpckhps %xmm4,%xmm6,%xmm2 + vunpckhps (%ecx),%xmm6,%xmm7 + vunpcklpd %xmm4,%xmm6,%xmm2 + vunpcklpd (%ecx),%xmm6,%xmm7 + vunpcklps %xmm4,%xmm6,%xmm2 + vunpcklps (%ecx),%xmm6,%xmm7 + vxorpd %xmm4,%xmm6,%xmm2 + vxorpd (%ecx),%xmm6,%xmm7 + vxorps %xmm4,%xmm6,%xmm2 + vxorps (%ecx),%xmm6,%xmm7 + vcmpeqpd %xmm4,%xmm6,%xmm2 + vcmpeqpd (%ecx),%xmm6,%xmm7 + vcmpltpd %xmm4,%xmm6,%xmm2 + vcmpltpd (%ecx),%xmm6,%xmm7 + vcmplepd %xmm4,%xmm6,%xmm2 + vcmplepd (%ecx),%xmm6,%xmm7 + vcmpunordpd %xmm4,%xmm6,%xmm2 + vcmpunordpd (%ecx),%xmm6,%xmm7 + vcmpneqpd %xmm4,%xmm6,%xmm2 + vcmpneqpd (%ecx),%xmm6,%xmm7 + vcmpnltpd %xmm4,%xmm6,%xmm2 + vcmpnltpd (%ecx),%xmm6,%xmm7 + vcmpnlepd %xmm4,%xmm6,%xmm2 + vcmpnlepd (%ecx),%xmm6,%xmm7 + vcmpordpd %xmm4,%xmm6,%xmm2 + vcmpordpd (%ecx),%xmm6,%xmm7 + vcmpeq_uqpd %xmm4,%xmm6,%xmm2 + vcmpeq_uqpd (%ecx),%xmm6,%xmm7 + vcmpngepd %xmm4,%xmm6,%xmm2 + vcmpngepd (%ecx),%xmm6,%xmm7 + vcmpngtpd %xmm4,%xmm6,%xmm2 + vcmpngtpd (%ecx),%xmm6,%xmm7 + vcmpfalsepd %xmm4,%xmm6,%xmm2 + vcmpfalsepd (%ecx),%xmm6,%xmm7 + vcmpneq_oqpd %xmm4,%xmm6,%xmm2 + vcmpneq_oqpd (%ecx),%xmm6,%xmm7 + vcmpgepd %xmm4,%xmm6,%xmm2 + vcmpgepd (%ecx),%xmm6,%xmm7 + vcmpgtpd %xmm4,%xmm6,%xmm2 + vcmpgtpd (%ecx),%xmm6,%xmm7 + vcmptruepd %xmm4,%xmm6,%xmm2 + vcmptruepd (%ecx),%xmm6,%xmm7 + vcmpeq_ospd %xmm4,%xmm6,%xmm2 + vcmpeq_ospd (%ecx),%xmm6,%xmm7 + vcmplt_oqpd %xmm4,%xmm6,%xmm2 + vcmplt_oqpd (%ecx),%xmm6,%xmm7 + vcmple_oqpd %xmm4,%xmm6,%xmm2 + vcmple_oqpd (%ecx),%xmm6,%xmm7 + vcmpunord_spd %xmm4,%xmm6,%xmm2 + vcmpunord_spd (%ecx),%xmm6,%xmm7 + vcmpneq_uspd %xmm4,%xmm6,%xmm2 + vcmpneq_uspd (%ecx),%xmm6,%xmm7 + vcmpnlt_uqpd %xmm4,%xmm6,%xmm2 + vcmpnlt_uqpd (%ecx),%xmm6,%xmm7 + vcmpnle_uqpd %xmm4,%xmm6,%xmm2 + vcmpnle_uqpd (%ecx),%xmm6,%xmm7 + vcmpord_spd %xmm4,%xmm6,%xmm2 + vcmpord_spd (%ecx),%xmm6,%xmm7 + vcmpeq_uspd %xmm4,%xmm6,%xmm2 + vcmpeq_uspd (%ecx),%xmm6,%xmm7 + vcmpnge_uqpd %xmm4,%xmm6,%xmm2 + vcmpnge_uqpd (%ecx),%xmm6,%xmm7 + vcmpngt_uqpd %xmm4,%xmm6,%xmm2 + vcmpngt_uqpd (%ecx),%xmm6,%xmm7 + vcmpfalse_ospd %xmm4,%xmm6,%xmm2 + vcmpfalse_ospd (%ecx),%xmm6,%xmm7 + vcmpneq_ospd %xmm4,%xmm6,%xmm2 + vcmpneq_ospd (%ecx),%xmm6,%xmm7 + vcmpge_oqpd %xmm4,%xmm6,%xmm2 + vcmpge_oqpd (%ecx),%xmm6,%xmm7 + vcmpgt_oqpd %xmm4,%xmm6,%xmm2 + vcmpgt_oqpd (%ecx),%xmm6,%xmm7 + vcmptrue_uspd %xmm4,%xmm6,%xmm2 + vcmptrue_uspd (%ecx),%xmm6,%xmm7 + vcmpeqps %xmm4,%xmm6,%xmm2 + vcmpeqps (%ecx),%xmm6,%xmm7 + vcmpltps %xmm4,%xmm6,%xmm2 + vcmpltps (%ecx),%xmm6,%xmm7 + vcmpleps %xmm4,%xmm6,%xmm2 + vcmpleps (%ecx),%xmm6,%xmm7 + vcmpunordps %xmm4,%xmm6,%xmm2 + vcmpunordps (%ecx),%xmm6,%xmm7 + vcmpneqps %xmm4,%xmm6,%xmm2 + vcmpneqps (%ecx),%xmm6,%xmm7 + vcmpnltps %xmm4,%xmm6,%xmm2 + vcmpnltps (%ecx),%xmm6,%xmm7 + vcmpnleps %xmm4,%xmm6,%xmm2 + vcmpnleps (%ecx),%xmm6,%xmm7 + vcmpordps %xmm4,%xmm6,%xmm2 + vcmpordps (%ecx),%xmm6,%xmm7 + vcmpeq_uqps %xmm4,%xmm6,%xmm2 + vcmpeq_uqps (%ecx),%xmm6,%xmm7 + vcmpngeps %xmm4,%xmm6,%xmm2 + vcmpngeps (%ecx),%xmm6,%xmm7 + vcmpngtps %xmm4,%xmm6,%xmm2 + vcmpngtps (%ecx),%xmm6,%xmm7 + vcmpfalseps %xmm4,%xmm6,%xmm2 + vcmpfalseps (%ecx),%xmm6,%xmm7 + vcmpneq_oqps %xmm4,%xmm6,%xmm2 + vcmpneq_oqps (%ecx),%xmm6,%xmm7 + vcmpgeps %xmm4,%xmm6,%xmm2 + vcmpgeps (%ecx),%xmm6,%xmm7 + vcmpgtps %xmm4,%xmm6,%xmm2 + vcmpgtps (%ecx),%xmm6,%xmm7 + vcmptrueps %xmm4,%xmm6,%xmm2 + vcmptrueps (%ecx),%xmm6,%xmm7 + vcmpeq_osps %xmm4,%xmm6,%xmm2 + vcmpeq_osps (%ecx),%xmm6,%xmm7 + vcmplt_oqps %xmm4,%xmm6,%xmm2 + vcmplt_oqps (%ecx),%xmm6,%xmm7 + vcmple_oqps %xmm4,%xmm6,%xmm2 + vcmple_oqps (%ecx),%xmm6,%xmm7 + vcmpunord_sps %xmm4,%xmm6,%xmm2 + vcmpunord_sps (%ecx),%xmm6,%xmm7 + vcmpneq_usps %xmm4,%xmm6,%xmm2 + vcmpneq_usps (%ecx),%xmm6,%xmm7 + vcmpnlt_uqps %xmm4,%xmm6,%xmm2 + vcmpnlt_uqps (%ecx),%xmm6,%xmm7 + vcmpnle_uqps %xmm4,%xmm6,%xmm2 + vcmpnle_uqps (%ecx),%xmm6,%xmm7 + vcmpord_sps %xmm4,%xmm6,%xmm2 + vcmpord_sps (%ecx),%xmm6,%xmm7 + vcmpeq_usps %xmm4,%xmm6,%xmm2 + vcmpeq_usps (%ecx),%xmm6,%xmm7 + vcmpnge_uqps %xmm4,%xmm6,%xmm2 + vcmpnge_uqps (%ecx),%xmm6,%xmm7 + vcmpngt_uqps %xmm4,%xmm6,%xmm2 + vcmpngt_uqps (%ecx),%xmm6,%xmm7 + vcmpfalse_osps %xmm4,%xmm6,%xmm2 + vcmpfalse_osps (%ecx),%xmm6,%xmm7 + vcmpneq_osps %xmm4,%xmm6,%xmm2 + vcmpneq_osps (%ecx),%xmm6,%xmm7 + vcmpge_oqps %xmm4,%xmm6,%xmm2 + vcmpge_oqps (%ecx),%xmm6,%xmm7 + vcmpgt_oqps %xmm4,%xmm6,%xmm2 + vcmpgt_oqps (%ecx),%xmm6,%xmm7 + vcmptrue_usps %xmm4,%xmm6,%xmm2 + vcmptrue_usps (%ecx),%xmm6,%xmm7 + +# Tests for op mem128, xmm, xmm + vmaskmovps (%ecx),%xmm4,%xmm6 + vmaskmovpd (%ecx),%xmm4,%xmm6 + +# Tests for op imm8, xmm/mem128, xmm + vpcmpestri $100,%xmm4,%xmm6 + vpcmpestri $100,(%ecx),%xmm6 + vpcmpestrm $100,%xmm4,%xmm6 + vpcmpestrm $100,(%ecx),%xmm6 + vpcmpistri $100,%xmm4,%xmm6 + vpcmpistri $100,(%ecx),%xmm6 + vpcmpistrm $100,%xmm4,%xmm6 + vpcmpistrm $100,(%ecx),%xmm6 + vpermilpd $100,%xmm4,%xmm6 + vpermilpd $100,(%ecx),%xmm6 + vpermilps $100,%xmm4,%xmm6 + vpermilps $100,(%ecx),%xmm6 + vpshufd $100,%xmm4,%xmm6 + vpshufd $100,(%ecx),%xmm6 + vpshufhw $100,%xmm4,%xmm6 + vpshufhw $100,(%ecx),%xmm6 + vpshuflw $100,%xmm4,%xmm6 + vpshuflw $100,(%ecx),%xmm6 + vroundpd $100,%xmm4,%xmm6 + vroundpd $100,(%ecx),%xmm6 + vroundps $100,%xmm4,%xmm6 + vroundps $100,(%ecx),%xmm6 + +# Tests for op xmm, xmm, mem128 + vmaskmovps %xmm4,%xmm6,(%ecx) + vmaskmovpd %xmm4,%xmm6,(%ecx) + +# Tests for op imm8, xmm/mem128, xmm, xmm + vblendpd $100,%xmm4,%xmm6,%xmm2 + vblendpd $100,(%ecx),%xmm6,%xmm2 + vblendps $100,%xmm4,%xmm6,%xmm2 + vblendps $100,(%ecx),%xmm6,%xmm2 + vcmppd $100,%xmm4,%xmm6,%xmm2 + vcmppd $100,(%ecx),%xmm6,%xmm2 + vcmpps $100,%xmm4,%xmm6,%xmm2 + vcmpps $100,(%ecx),%xmm6,%xmm2 + vdppd $100,%xmm4,%xmm6,%xmm2 + vdppd $100,(%ecx),%xmm6,%xmm2 + vdpps $100,%xmm4,%xmm6,%xmm2 + vdpps $100,(%ecx),%xmm6,%xmm2 + vmpsadbw $100,%xmm4,%xmm6,%xmm2 + vmpsadbw $100,(%ecx),%xmm6,%xmm2 + vpalignr $100,%xmm4,%xmm6,%xmm2 + vpalignr $100,(%ecx),%xmm6,%xmm2 + vpblendw $100,%xmm4,%xmm6,%xmm2 + vpblendw $100,(%ecx),%xmm6,%xmm2 + vshufpd $100,%xmm4,%xmm6,%xmm2 + vshufpd $100,(%ecx),%xmm6,%xmm2 + vshufps $100,%xmm4,%xmm6,%xmm2 + vshufps $100,(%ecx),%xmm6,%xmm2 + +# Tests for op xmm, xmm/mem128, xmm, xmm + vblendvpd %xmm4,%xmm6,%xmm2,%xmm7 + vblendvpd %xmm4,(%ecx),%xmm2,%xmm7 + vblendvps %xmm4,%xmm6,%xmm2,%xmm7 + vblendvps %xmm4,(%ecx),%xmm2,%xmm7 + vpblendvb %xmm4,%xmm6,%xmm2,%xmm7 + vpblendvb %xmm4,(%ecx),%xmm2,%xmm7 + +# Tests for op xmm/mem128, xmm, xmm, xmm +# Tests for op xmm, xmm/mem128, xmm, xmm + vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddpd (%ecx),%xmm6,%xmm2,%xmm7 + vfmaddpd %xmm4,(%ecx),%xmm2,%xmm7 + vfmaddps %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddps (%ecx),%xmm6,%xmm2,%xmm7 + vfmaddps %xmm4,(%ecx),%xmm2,%xmm7 + vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddsubpd (%ecx),%xmm6,%xmm2,%xmm7 + vfmaddsubpd %xmm4,(%ecx),%xmm2,%xmm7 + vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddsubps (%ecx),%xmm6,%xmm2,%xmm7 + vfmaddsubps %xmm4,(%ecx),%xmm2,%xmm7 + vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubaddpd (%ecx),%xmm6,%xmm2,%xmm7 + vfmsubaddpd %xmm4,(%ecx),%xmm2,%xmm7 + vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubaddps (%ecx),%xmm6,%xmm2,%xmm7 + vfmsubaddps %xmm4,(%ecx),%xmm2,%xmm7 + vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubpd (%ecx),%xmm6,%xmm2,%xmm7 + vfmsubpd %xmm4,(%ecx),%xmm2,%xmm7 + vfmsubps %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubps (%ecx),%xmm6,%xmm2,%xmm7 + vfmsubps %xmm4,(%ecx),%xmm2,%xmm7 + vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7 + vfnmaddpd (%ecx),%xmm6,%xmm2,%xmm7 + vfnmaddpd %xmm4,(%ecx),%xmm2,%xmm7 + vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7 + vfnmaddps (%ecx),%xmm6,%xmm2,%xmm7 + vfnmaddps %xmm4,(%ecx),%xmm2,%xmm7 + vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7 + vfnmsubpd (%ecx),%xmm6,%xmm2,%xmm7 + vfnmsubpd %xmm4,(%ecx),%xmm2,%xmm7 + vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7 + vfnmsubps (%ecx),%xmm6,%xmm2,%xmm7 + vfnmsubps %xmm4,(%ecx),%xmm2,%xmm7 + vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7 + vpermilmo2pd (%ecx),%xmm6,%xmm2,%xmm7 + vpermilmo2pd %xmm4,(%ecx),%xmm2,%xmm7 + vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7 + vpermilmz2pd (%ecx),%xmm6,%xmm2,%xmm7 + vpermilmz2pd %xmm4,(%ecx),%xmm2,%xmm7 + vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7 + vpermiltd2pd (%ecx),%xmm6,%xmm2,%xmm7 + vpermiltd2pd %xmm4,(%ecx),%xmm2,%xmm7 + vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7 + vpermilmo2ps (%ecx),%xmm6,%xmm2,%xmm7 + vpermilmo2ps %xmm4,(%ecx),%xmm2,%xmm7 + vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7 + vpermilmz2ps (%ecx),%xmm6,%xmm2,%xmm7 + vpermilmz2ps %xmm4,(%ecx),%xmm2,%xmm7 + vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7 + vpermiltd2ps (%ecx),%xmm6,%xmm2,%xmm7 + vpermiltd2ps %xmm4,(%ecx),%xmm2,%xmm7 + +# Tests for op imm4, xmm/mem128, xmm, xmm, xmm +# Tests for op imm4, xmm, xmm/mem128, xmm, xmm + vpermil2pd $10,%xmm4,%xmm6,%xmm2,%xmm7 + vpermil2pd $10,(%ecx),%xmm6,%xmm2,%xmm7 + vpermil2pd $10,%xmm4,(%ecx),%xmm2,%xmm7 + vpermil2ps $10,%xmm4,%xmm6,%xmm2,%xmm7 + vpermil2ps $10,(%ecx),%xmm6,%xmm2,%xmm7 + vpermil2ps $10,%xmm4,(%ecx),%xmm2,%xmm7 + +# Tests for op mem64, ymm + vbroadcastsd (%ecx),%ymm4 + +# Tests for op xmm/mem64, xmm + vcomisd %xmm4,%xmm6 + vcomisd (%ecx),%xmm4 + vcvtdq2pd %xmm4,%xmm6 + vcvtdq2pd (%ecx),%xmm4 + vcvtps2pd %xmm4,%xmm6 + vcvtps2pd (%ecx),%xmm4 + vmovddup %xmm4,%xmm6 + vmovddup (%ecx),%xmm4 + vpmovsxbw %xmm4,%xmm6 + vpmovsxbw (%ecx),%xmm4 + vpmovsxwd %xmm4,%xmm6 + vpmovsxwd (%ecx),%xmm4 + vpmovsxdq %xmm4,%xmm6 + vpmovsxdq (%ecx),%xmm4 + vpmovzxbw %xmm4,%xmm6 + vpmovzxbw (%ecx),%xmm4 + vpmovzxwd %xmm4,%xmm6 + vpmovzxwd (%ecx),%xmm4 + vpmovzxdq %xmm4,%xmm6 + vpmovzxdq (%ecx),%xmm4 + vucomisd %xmm4,%xmm6 + vucomisd (%ecx),%xmm4 + +# Tests for op mem64, xmm + vmovsd (%ecx),%xmm4 + +# Tests for op xmm, mem64 + vmovlpd %xmm4,(%ecx) + vmovlps %xmm4,(%ecx) + vmovhpd %xmm4,(%ecx) + vmovhps %xmm4,(%ecx) + vmovsd %xmm4,(%ecx) + +# Tests for op xmm, regq/mem64 +# Tests for op regq/mem64, xmm + vmovq %xmm4,(%ecx) + vmovq (%ecx),%xmm4 + +# Tests for op xmm/mem64, regl + vcvtsd2si %xmm4,%ecx + vcvtsd2si (%ecx),%ecx + vcvttsd2si %xmm4,%ecx + vcvttsd2si (%ecx),%ecx + +# Tests for op mem64, xmm, xmm + vmovlpd (%ecx),%xmm4,%xmm6 + vmovlps (%ecx),%xmm4,%xmm6 + vmovhpd (%ecx),%xmm4,%xmm6 + vmovhps (%ecx),%xmm4,%xmm6 + +# Tests for op imm8, xmm/mem64, xmm, xmm + vcmpsd $100,%xmm4,%xmm6,%xmm2 + vcmpsd $100,(%ecx),%xmm6,%xmm2 + vroundsd $100,%xmm4,%xmm6,%xmm2 + vroundsd $100,(%ecx),%xmm6,%xmm2 + +# Tests for op xmm/mem64, xmm, xmm, xmm +# Tests for op xmm, xmm/mem64, xmm, xmm + vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddsd (%ecx),%xmm6,%xmm2,%xmm7 + vfmaddsd %xmm4,(%ecx),%xmm2,%xmm7 + vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubsd (%ecx),%xmm6,%xmm2,%xmm7 + vfmsubsd %xmm4,(%ecx),%xmm2,%xmm7 + vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7 + vfnmaddsd (%ecx),%xmm6,%xmm2,%xmm7 + vfnmaddsd %xmm4,(%ecx),%xmm2,%xmm7 + vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7 + vfnmsubsd (%ecx),%xmm6,%xmm2,%xmm7 + vfnmsubsd %xmm4,(%ecx),%xmm2,%xmm7 + +# Tests for op xmm/mem64, xmm, xmm + vaddsd %xmm4,%xmm6,%xmm2 + vaddsd (%ecx),%xmm6,%xmm2 + vcvtsd2ss %xmm4,%xmm6,%xmm2 + vcvtsd2ss (%ecx),%xmm6,%xmm2 + vdivsd %xmm4,%xmm6,%xmm2 + vdivsd (%ecx),%xmm6,%xmm2 + vmaxsd %xmm4,%xmm6,%xmm2 + vmaxsd (%ecx),%xmm6,%xmm2 + vminsd %xmm4,%xmm6,%xmm2 + vminsd (%ecx),%xmm6,%xmm2 + vmulsd %xmm4,%xmm6,%xmm2 + vmulsd (%ecx),%xmm6,%xmm2 + vsqrtsd %xmm4,%xmm6,%xmm2 + vsqrtsd (%ecx),%xmm6,%xmm2 + vsubsd %xmm4,%xmm6,%xmm2 + vsubsd (%ecx),%xmm6,%xmm2 + vcmpeqsd %xmm4,%xmm6,%xmm2 + vcmpeqsd (%ecx),%xmm6,%xmm2 + vcmpltsd %xmm4,%xmm6,%xmm2 + vcmpltsd (%ecx),%xmm6,%xmm2 + vcmplesd %xmm4,%xmm6,%xmm2 + vcmplesd (%ecx),%xmm6,%xmm2 + vcmpunordsd %xmm4,%xmm6,%xmm2 + vcmpunordsd (%ecx),%xmm6,%xmm2 + vcmpneqsd %xmm4,%xmm6,%xmm2 + vcmpneqsd (%ecx),%xmm6,%xmm2 + vcmpnltsd %xmm4,%xmm6,%xmm2 + vcmpnltsd (%ecx),%xmm6,%xmm2 + vcmpnlesd %xmm4,%xmm6,%xmm2 + vcmpnlesd (%ecx),%xmm6,%xmm2 + vcmpordsd %xmm4,%xmm6,%xmm2 + vcmpordsd (%ecx),%xmm6,%xmm2 + vcmpeq_uqsd %xmm4,%xmm6,%xmm2 + vcmpeq_uqsd (%ecx),%xmm6,%xmm2 + vcmpngesd %xmm4,%xmm6,%xmm2 + vcmpngesd (%ecx),%xmm6,%xmm2 + vcmpngtsd %xmm4,%xmm6,%xmm2 + vcmpngtsd (%ecx),%xmm6,%xmm2 + vcmpfalsesd %xmm4,%xmm6,%xmm2 + vcmpfalsesd (%ecx),%xmm6,%xmm2 + vcmpneq_oqsd %xmm4,%xmm6,%xmm2 + vcmpneq_oqsd (%ecx),%xmm6,%xmm2 + vcmpgesd %xmm4,%xmm6,%xmm2 + vcmpgesd (%ecx),%xmm6,%xmm2 + vcmpgtsd %xmm4,%xmm6,%xmm2 + vcmpgtsd (%ecx),%xmm6,%xmm2 + vcmptruesd %xmm4,%xmm6,%xmm2 + vcmptruesd (%ecx),%xmm6,%xmm2 + vcmpeq_ossd %xmm4,%xmm6,%xmm2 + vcmpeq_ossd (%ecx),%xmm6,%xmm2 + vcmplt_oqsd %xmm4,%xmm6,%xmm2 + vcmplt_oqsd (%ecx),%xmm6,%xmm2 + vcmple_oqsd %xmm4,%xmm6,%xmm2 + vcmple_oqsd (%ecx),%xmm6,%xmm2 + vcmpunord_ssd %xmm4,%xmm6,%xmm2 + vcmpunord_ssd (%ecx),%xmm6,%xmm2 + vcmpneq_ussd %xmm4,%xmm6,%xmm2 + vcmpneq_ussd (%ecx),%xmm6,%xmm2 + vcmpnlt_uqsd %xmm4,%xmm6,%xmm2 + vcmpnlt_uqsd (%ecx),%xmm6,%xmm2 + vcmpnle_uqsd %xmm4,%xmm6,%xmm2 + vcmpnle_uqsd (%ecx),%xmm6,%xmm2 + vcmpord_ssd %xmm4,%xmm6,%xmm2 + vcmpord_ssd (%ecx),%xmm6,%xmm2 + vcmpeq_ussd %xmm4,%xmm6,%xmm2 + vcmpeq_ussd (%ecx),%xmm6,%xmm2 + vcmpnge_uqsd %xmm4,%xmm6,%xmm2 + vcmpnge_uqsd (%ecx),%xmm6,%xmm2 + vcmpngt_uqsd %xmm4,%xmm6,%xmm2 + vcmpngt_uqsd (%ecx),%xmm6,%xmm2 + vcmpfalse_ossd %xmm4,%xmm6,%xmm2 + vcmpfalse_ossd (%ecx),%xmm6,%xmm2 + vcmpneq_ossd %xmm4,%xmm6,%xmm2 + vcmpneq_ossd (%ecx),%xmm6,%xmm2 + vcmpge_oqsd %xmm4,%xmm6,%xmm2 + vcmpge_oqsd (%ecx),%xmm6,%xmm2 + vcmpgt_oqsd %xmm4,%xmm6,%xmm2 + vcmpgt_oqsd (%ecx),%xmm6,%xmm2 + vcmptrue_ussd %xmm4,%xmm6,%xmm2 + vcmptrue_ussd (%ecx),%xmm6,%xmm2 + +# Tests for op xmm/mem32, xmm, xmm + vaddss %xmm4,%xmm6,%xmm2 + vaddss (%ecx),%xmm6,%xmm2 + vcvtss2sd %xmm4,%xmm6,%xmm2 + vcvtss2sd (%ecx),%xmm6,%xmm2 + vdivss %xmm4,%xmm6,%xmm2 + vdivss (%ecx),%xmm6,%xmm2 + vmaxss %xmm4,%xmm6,%xmm2 + vmaxss (%ecx),%xmm6,%xmm2 + vminss %xmm4,%xmm6,%xmm2 + vminss (%ecx),%xmm6,%xmm2 + vmulss %xmm4,%xmm6,%xmm2 + vmulss (%ecx),%xmm6,%xmm2 + vrcpss %xmm4,%xmm6,%xmm2 + vrcpss (%ecx),%xmm6,%xmm2 + vrsqrtss %xmm4,%xmm6,%xmm2 + vrsqrtss (%ecx),%xmm6,%xmm2 + vsqrtss %xmm4,%xmm6,%xmm2 + vsqrtss (%ecx),%xmm6,%xmm2 + vsubss %xmm4,%xmm6,%xmm2 + vsubss (%ecx),%xmm6,%xmm2 + vcmpeqss %xmm4,%xmm6,%xmm2 + vcmpeqss (%ecx),%xmm6,%xmm2 + vcmpltss %xmm4,%xmm6,%xmm2 + vcmpltss (%ecx),%xmm6,%xmm2 + vcmpless %xmm4,%xmm6,%xmm2 + vcmpless (%ecx),%xmm6,%xmm2 + vcmpunordss %xmm4,%xmm6,%xmm2 + vcmpunordss (%ecx),%xmm6,%xmm2 + vcmpneqss %xmm4,%xmm6,%xmm2 + vcmpneqss (%ecx),%xmm6,%xmm2 + vcmpnltss %xmm4,%xmm6,%xmm2 + vcmpnltss (%ecx),%xmm6,%xmm2 + vcmpnless %xmm4,%xmm6,%xmm2 + vcmpnless (%ecx),%xmm6,%xmm2 + vcmpordss %xmm4,%xmm6,%xmm2 + vcmpordss (%ecx),%xmm6,%xmm2 + vcmpeq_uqss %xmm4,%xmm6,%xmm2 + vcmpeq_uqss (%ecx),%xmm6,%xmm2 + vcmpngess %xmm4,%xmm6,%xmm2 + vcmpngess (%ecx),%xmm6,%xmm2 + vcmpngtss %xmm4,%xmm6,%xmm2 + vcmpngtss (%ecx),%xmm6,%xmm2 + vcmpfalsess %xmm4,%xmm6,%xmm2 + vcmpfalsess (%ecx),%xmm6,%xmm2 + vcmpneq_oqss %xmm4,%xmm6,%xmm2 + vcmpneq_oqss (%ecx),%xmm6,%xmm2 + vcmpgess %xmm4,%xmm6,%xmm2 + vcmpgess (%ecx),%xmm6,%xmm2 + vcmpgtss %xmm4,%xmm6,%xmm2 + vcmpgtss (%ecx),%xmm6,%xmm2 + vcmptruess %xmm4,%xmm6,%xmm2 + vcmptruess (%ecx),%xmm6,%xmm2 + vcmpeq_osss %xmm4,%xmm6,%xmm2 + vcmpeq_osss (%ecx),%xmm6,%xmm2 + vcmplt_oqss %xmm4,%xmm6,%xmm2 + vcmplt_oqss (%ecx),%xmm6,%xmm2 + vcmple_oqss %xmm4,%xmm6,%xmm2 + vcmple_oqss (%ecx),%xmm6,%xmm2 + vcmpunord_sss %xmm4,%xmm6,%xmm2 + vcmpunord_sss (%ecx),%xmm6,%xmm2 + vcmpneq_usss %xmm4,%xmm6,%xmm2 + vcmpneq_usss (%ecx),%xmm6,%xmm2 + vcmpnlt_uqss %xmm4,%xmm6,%xmm2 + vcmpnlt_uqss (%ecx),%xmm6,%xmm2 + vcmpnle_uqss %xmm4,%xmm6,%xmm2 + vcmpnle_uqss (%ecx),%xmm6,%xmm2 + vcmpord_sss %xmm4,%xmm6,%xmm2 + vcmpord_sss (%ecx),%xmm6,%xmm2 + vcmpeq_usss %xmm4,%xmm6,%xmm2 + vcmpeq_usss (%ecx),%xmm6,%xmm2 + vcmpnge_uqss %xmm4,%xmm6,%xmm2 + vcmpnge_uqss (%ecx),%xmm6,%xmm2 + vcmpngt_uqss %xmm4,%xmm6,%xmm2 + vcmpngt_uqss (%ecx),%xmm6,%xmm2 + vcmpfalse_osss %xmm4,%xmm6,%xmm2 + vcmpfalse_osss (%ecx),%xmm6,%xmm2 + vcmpneq_osss %xmm4,%xmm6,%xmm2 + vcmpneq_osss (%ecx),%xmm6,%xmm2 + vcmpge_oqss %xmm4,%xmm6,%xmm2 + vcmpge_oqss (%ecx),%xmm6,%xmm2 + vcmpgt_oqss %xmm4,%xmm6,%xmm2 + vcmpgt_oqss (%ecx),%xmm6,%xmm2 + vcmptrue_usss %xmm4,%xmm6,%xmm2 + vcmptrue_usss (%ecx),%xmm6,%xmm2 + +# Tests for op mem32, ymm + vbroadcastss (%ecx),%ymm4 + +# Tests for op xmm/mem32, xmm + vcomiss %xmm4,%xmm6 + vcomiss (%ecx),%xmm4 + vpmovsxbd %xmm4,%xmm6 + vpmovsxbd (%ecx),%xmm4 + vpmovsxwq %xmm4,%xmm6 + vpmovsxwq (%ecx),%xmm4 + vpmovzxbd %xmm4,%xmm6 + vpmovzxbd (%ecx),%xmm4 + vpmovzxwq %xmm4,%xmm6 + vpmovzxwq (%ecx),%xmm4 + vucomiss %xmm4,%xmm6 + vucomiss (%ecx),%xmm4 + +# Tests for op mem32, xmm + vbroadcastss (%ecx),%xmm4 + vmovss (%ecx),%xmm4 + +# Tests for op xmm, mem32 + vmovss %xmm4,(%ecx) + +# Tests for op xmm, regl/mem32 +# Tests for op regl/mem32, xmm + vmovd %xmm4,%ecx + vmovd %xmm4,(%ecx) + vmovd %ecx,%xmm4 + vmovd (%ecx),%xmm4 + +# Tests for op xmm/mem32, regl + vcvtss2si %xmm4,%ecx + vcvtss2si (%ecx),%ecx + vcvttss2si %xmm4,%ecx + vcvttss2si (%ecx),%ecx + +# Tests for op imm8, xmm, regq/mem32 + vextractps $100,%xmm4,(%ecx) +# Tests for op imm8, xmm, regl/mem32 + vpextrd $100,%xmm4,%ecx + vpextrd $100,%xmm4,(%ecx) + vextractps $100,%xmm4,%ecx + vextractps $100,%xmm4,(%ecx) + +# Tests for op regl/mem32, xmm, xmm + vcvtsi2sd %ecx,%xmm4,%xmm6 + vcvtsi2sd (%ecx),%xmm4,%xmm6 + vcvtsi2ss %ecx,%xmm4,%xmm6 + vcvtsi2ss (%ecx),%xmm4,%xmm6 + +# Tests for op imm8, xmm/mem32, xmm, xmm + vcmpss $100,%xmm4,%xmm6,%xmm2 + vcmpss $100,(%ecx),%xmm6,%xmm2 + vinsertps $100,%xmm4,%xmm6,%xmm2 + vinsertps $100,(%ecx),%xmm6,%xmm2 + vroundss $100,%xmm4,%xmm6,%xmm2 + vroundss $100,(%ecx),%xmm6,%xmm2 + +# Tests for op xmm/mem32, xmm, xmm, xmm +# Tests for op xmm, xmm/mem32, xmm, xmm + vfmaddss %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddss (%ecx),%xmm6,%xmm2,%xmm7 + vfmaddss %xmm4,(%ecx),%xmm2,%xmm7 + vfmsubss %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubss (%ecx),%xmm6,%xmm2,%xmm7 + vfmsubss %xmm4,(%ecx),%xmm2,%xmm7 + vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7 + vfnmaddss (%ecx),%xmm6,%xmm2,%xmm7 + vfnmaddss %xmm4,(%ecx),%xmm2,%xmm7 + vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7 + vfnmsubss (%ecx),%xmm6,%xmm2,%xmm7 + vfnmsubss %xmm4,(%ecx),%xmm2,%xmm7 + +# Tests for op xmm/m16, xmm + vpmovsxbq %xmm4,%xmm6 + vpmovsxbq (%ecx),%xmm4 + vpmovzxbq %xmm4,%xmm6 + vpmovzxbq (%ecx),%xmm4 + +# Tests for op imm8, xmm, regl/mem16 + vpextrw $100,%xmm4,%ecx + vpextrw $100,%xmm4,(%ecx) + +# Tests for op imm8, xmm, regq/mem16 + vpextrw $100,%xmm4,(%ecx) + +# Tests for op imm8, regl/mem16, xmm, xmm + vpinsrw $100,%ecx,%xmm4,%xmm6 + vpinsrw $100,(%ecx),%xmm4,%xmm6 + + +# Tests for op imm8, xmm, regl/mem8 + vpextrb $100,%xmm4,%ecx + vpextrb $100,%xmm4,(%ecx) + +# Tests for op imm8, regl/mem8, xmm, xmm + vpinsrb $100,%ecx,%xmm4,%xmm6 + vpinsrb $100,(%ecx),%xmm4,%xmm6 + +# Tests for op imm8, xmm, regq/mem8 + vpextrb $100,%xmm4,(%ecx) + +# Tests for op imm8, regl/mem8, xmm, xmm + vpinsrb $100,%ecx,%xmm4,%xmm6 + vpinsrb $100,(%ecx),%xmm4,%xmm6 + +# Tests for op xmm, xmm + vmaskmovdqu %xmm4,%xmm6 + vmovq %xmm4,%xmm6 + +# Tests for op xmm, regl + vmovmskpd %xmm4,%ecx + vmovmskps %xmm4,%ecx + vpmovmskb %xmm4,%ecx +# Tests for op xmm, xmm, xmm + vmovhlps %xmm4,%xmm6,%xmm2 + vmovlhps %xmm4,%xmm6,%xmm2 + vmovsd %xmm4,%xmm6,%xmm2 + vmovss %xmm4,%xmm6,%xmm2 + +# Tests for op imm8, xmm, xmm + vpslld $100,%xmm4,%xmm6 + vpslldq $100,%xmm4,%xmm6 + vpsllq $100,%xmm4,%xmm6 + vpsllw $100,%xmm4,%xmm6 + vpsrad $100,%xmm4,%xmm6 + vpsraw $100,%xmm4,%xmm6 + vpsrld $100,%xmm4,%xmm6 + vpsrldq $100,%xmm4,%xmm6 + vpsrlq $100,%xmm4,%xmm6 + vpsrlw $100,%xmm4,%xmm6 + +# Tests for op imm8, xmm, regl + vpextrw $100,%xmm4,%ecx + +# Tests for op ymm, regl + vmovmskpd %ymm4,%ecx + vmovmskps %ymm4,%ecx + +# Tests for op ymm, regq + + +# Default instructions without suffixes. + vcvtpd2dq %xmm4,%xmm6 + vcvtpd2dq %ymm4,%xmm6 + vcvtpd2ps %xmm4,%xmm6 + vcvtpd2ps %ymm4,%xmm6 + vcvttpd2dq %xmm4,%xmm6 + vcvttpd2dq %ymm4,%xmm6 + +#Tests with different memory and register operands. + vldmxcsr 0x1234 + vmovdqa 0x1234,%xmm0 + vmovdqa %xmm0,0x1234 + vmovd %xmm0,0x1234 + vcvtsd2si 0x1234,%eax + vcvtdq2pd 0x1234,%ymm0 + vcvtpd2psy 0x1234,%xmm0 + vpavgb 0x1234,%xmm0,%xmm7 + vpextrb $100,%xmm0,0x1234 + vcvtsi2sdl 0x1234,%xmm0,%xmm7 + vblendvps %xmm0,0x1234,%xmm4,%xmm6 + vpinsrb $100,0x1234,%xmm0,%xmm7 + vmovdqa 0x1234,%ymm0 + vmovdqa %ymm0,0x1234 + vpermilpd 0x1234,%ymm0,%ymm7 + vroundpd $100,0x1234,%ymm0 + vextractf128 $100,%ymm0,0x1234 + vperm2f128 $100,0x1234,%ymm0,%ymm7 + vblendvpd %ymm0,0x1234,%ymm4,%ymm6 + vldmxcsr (%ebp) + vmovdqa (%ebp),%xmm0 + vmovdqa %xmm0,(%ebp) + vmovd %xmm0,(%ebp) + vcvtsd2si (%ebp),%eax + vcvtdq2pd (%ebp),%ymm0 + vcvtpd2psy (%ebp),%xmm0 + vpavgb (%ebp),%xmm0,%xmm7 + vpextrb $100,%xmm0,(%ebp) + vcvtsi2sdl (%ebp),%xmm0,%xmm7 + vblendvps %xmm0,(%ebp),%xmm4,%xmm6 + vpinsrb $100,(%ebp),%xmm0,%xmm7 + vmovdqa (%ebp),%ymm0 + vmovdqa %ymm0,(%ebp) + vpermilpd (%ebp),%ymm0,%ymm7 + vroundpd $100,(%ebp),%ymm0 + vextractf128 $100,%ymm0,(%ebp) + vperm2f128 $100,(%ebp),%ymm0,%ymm7 + vblendvpd %ymm0,(%ebp),%ymm4,%ymm6 + vldmxcsr (%esp) + vmovdqa (%esp),%xmm0 + vmovdqa %xmm0,(%esp) + vmovd %xmm0,(%esp) + vcvtsd2si (%esp),%eax + vcvtdq2pd (%esp),%ymm0 + vcvtpd2psy (%esp),%xmm0 + vpavgb (%esp),%xmm0,%xmm7 + vpextrb $100,%xmm0,(%esp) + vcvtsi2sdl (%esp),%xmm0,%xmm7 + vblendvps %xmm0,(%esp),%xmm4,%xmm6 + vpinsrb $100,(%esp),%xmm0,%xmm7 + vmovdqa (%esp),%ymm0 + vmovdqa %ymm0,(%esp) + vpermilpd (%esp),%ymm0,%ymm7 + vroundpd $100,(%esp),%ymm0 + vextractf128 $100,%ymm0,(%esp) + vperm2f128 $100,(%esp),%ymm0,%ymm7 + vblendvpd %ymm0,(%esp),%ymm4,%ymm6 + vldmxcsr 0x99(%ebp) + vmovdqa 0x99(%ebp),%xmm0 + vmovdqa %xmm0,0x99(%ebp) + vmovd %xmm0,0x99(%ebp) + vcvtsd2si 0x99(%ebp),%eax + vcvtdq2pd 0x99(%ebp),%ymm0 + vcvtpd2psy 0x99(%ebp),%xmm0 + vpavgb 0x99(%ebp),%xmm0,%xmm7 + vpextrb $100,%xmm0,0x99(%ebp) + vcvtsi2sdl 0x99(%ebp),%xmm0,%xmm7 + vblendvps %xmm0,0x99(%ebp),%xmm4,%xmm6 + vpinsrb $100,0x99(%ebp),%xmm0,%xmm7 + vmovdqa 0x99(%ebp),%ymm0 + vmovdqa %ymm0,0x99(%ebp) + vpermilpd 0x99(%ebp),%ymm0,%ymm7 + vroundpd $100,0x99(%ebp),%ymm0 + vextractf128 $100,%ymm0,0x99(%ebp) + vperm2f128 $100,0x99(%ebp),%ymm0,%ymm7 + vblendvpd %ymm0,0x99(%ebp),%ymm4,%ymm6 + vldmxcsr 0x99(,%eiz) + vmovdqa 0x99(,%eiz),%xmm0 + vmovdqa %xmm0,0x99(,%eiz) + vmovd %xmm0,0x99(,%eiz) + vcvtsd2si 0x99(,%eiz),%eax + vcvtdq2pd 0x99(,%eiz),%ymm0 + vcvtpd2psy 0x99(,%eiz),%xmm0 + vpavgb 0x99(,%eiz),%xmm0,%xmm7 + vpextrb $100,%xmm0,0x99(,%eiz) + vcvtsi2sdl 0x99(,%eiz),%xmm0,%xmm7 + vblendvps %xmm0,0x99(,%eiz),%xmm4,%xmm6 + vpinsrb $100,0x99(,%eiz),%xmm0,%xmm7 + vmovdqa 0x99(,%eiz),%ymm0 + vmovdqa %ymm0,0x99(,%eiz) + vpermilpd 0x99(,%eiz),%ymm0,%ymm7 + vroundpd $100,0x99(,%eiz),%ymm0 + vextractf128 $100,%ymm0,0x99(,%eiz) + vperm2f128 $100,0x99(,%eiz),%ymm0,%ymm7 + vblendvpd %ymm0,0x99(,%eiz),%ymm4,%ymm6 + vldmxcsr 0x99(,%eiz,2) + vmovdqa 0x99(,%eiz,2),%xmm0 + vmovdqa %xmm0,0x99(,%eiz,2) + vmovd %xmm0,0x99(,%eiz,2) + vcvtsd2si 0x99(,%eiz,2),%eax + vcvtdq2pd 0x99(,%eiz,2),%ymm0 + vcvtpd2psy 0x99(,%eiz,2),%xmm0 + vpavgb 0x99(,%eiz,2),%xmm0,%xmm7 + vpextrb $100,%xmm0,0x99(,%eiz,2) + vcvtsi2sdl 0x99(,%eiz,2),%xmm0,%xmm7 + vblendvps %xmm0,0x99(,%eiz,2),%xmm4,%xmm6 + vpinsrb $100,0x99(,%eiz,2),%xmm0,%xmm7 + vmovdqa 0x99(,%eiz,2),%ymm0 + vmovdqa %ymm0,0x99(,%eiz,2) + vpermilpd 0x99(,%eiz,2),%ymm0,%ymm7 + vroundpd $100,0x99(,%eiz,2),%ymm0 + vextractf128 $100,%ymm0,0x99(,%eiz,2) + vperm2f128 $100,0x99(,%eiz,2),%ymm0,%ymm7 + vblendvpd %ymm0,0x99(,%eiz,2),%ymm4,%ymm6 + vldmxcsr 0x99(%eax,%eiz) + vmovdqa 0x99(%eax,%eiz),%xmm0 + vmovdqa %xmm0,0x99(%eax,%eiz) + vmovd %xmm0,0x99(%eax,%eiz) + vcvtsd2si 0x99(%eax,%eiz),%eax + vcvtdq2pd 0x99(%eax,%eiz),%ymm0 + vcvtpd2psy 0x99(%eax,%eiz),%xmm0 + vpavgb 0x99(%eax,%eiz),%xmm0,%xmm7 + vpextrb $100,%xmm0,0x99(%eax,%eiz) + vcvtsi2sdl 0x99(%eax,%eiz),%xmm0,%xmm7 + vblendvps %xmm0,0x99(%eax,%eiz),%xmm4,%xmm6 + vpinsrb $100,0x99(%eax,%eiz),%xmm0,%xmm7 + vmovdqa 0x99(%eax,%eiz),%ymm0 + vmovdqa %ymm0,0x99(%eax,%eiz) + vpermilpd 0x99(%eax,%eiz),%ymm0,%ymm7 + vroundpd $100,0x99(%eax,%eiz),%ymm0 + vextractf128 $100,%ymm0,0x99(%eax,%eiz) + vperm2f128 $100,0x99(%eax,%eiz),%ymm0,%ymm7 + vblendvpd %ymm0,0x99(%eax,%eiz),%ymm4,%ymm6 + vldmxcsr 0x99(%eax,%eiz,2) + vmovdqa 0x99(%eax,%eiz,2),%xmm0 + vmovdqa %xmm0,0x99(%eax,%eiz,2) + vmovd %xmm0,0x99(%eax,%eiz,2) + vcvtsd2si 0x99(%eax,%eiz,2),%eax + vcvtdq2pd 0x99(%eax,%eiz,2),%ymm0 + vcvtpd2psy 0x99(%eax,%eiz,2),%xmm0 + vpavgb 0x99(%eax,%eiz,2),%xmm0,%xmm7 + vpextrb $100,%xmm0,0x99(%eax,%eiz,2) + vcvtsi2sdl 0x99(%eax,%eiz,2),%xmm0,%xmm7 + vblendvps %xmm0,0x99(%eax,%eiz,2),%xmm4,%xmm6 + vpinsrb $100,0x99(%eax,%eiz,2),%xmm0,%xmm7 + vmovdqa 0x99(%eax,%eiz,2),%ymm0 + vmovdqa %ymm0,0x99(%eax,%eiz,2) + vpermilpd 0x99(%eax,%eiz,2),%ymm0,%ymm7 + vroundpd $100,0x99(%eax,%eiz,2),%ymm0 + vextractf128 $100,%ymm0,0x99(%eax,%eiz,2) + vperm2f128 $100,0x99(%eax,%eiz,2),%ymm0,%ymm7 + vblendvpd %ymm0,0x99(%eax,%eiz,2),%ymm4,%ymm6 + vldmxcsr 0x99(%eax,%ebx,4) + vmovdqa 0x99(%eax,%ebx,4),%xmm0 + vmovdqa %xmm0,0x99(%eax,%ebx,4) + vmovd %xmm0,0x99(%eax,%ebx,4) + vcvtsd2si 0x99(%eax,%ebx,4),%eax + vcvtdq2pd 0x99(%eax,%ebx,4),%ymm0 + vcvtpd2psy 0x99(%eax,%ebx,4),%xmm0 + vpavgb 0x99(%eax,%ebx,4),%xmm0,%xmm7 + vpextrb $100,%xmm0,0x99(%eax,%ebx,4) + vcvtsi2sdl 0x99(%eax,%ebx,4),%xmm0,%xmm7 + vblendvps %xmm0,0x99(%eax,%ebx,4),%xmm4,%xmm6 + vpinsrb $100,0x99(%eax,%ebx,4),%xmm0,%xmm7 + vmovdqa 0x99(%eax,%ebx,4),%ymm0 + vmovdqa %ymm0,0x99(%eax,%ebx,4) + vpermilpd 0x99(%eax,%ebx,4),%ymm0,%ymm7 + vroundpd $100,0x99(%eax,%ebx,4),%ymm0 + vextractf128 $100,%ymm0,0x99(%eax,%ebx,4) + vperm2f128 $100,0x99(%eax,%ebx,4),%ymm0,%ymm7 + vblendvpd %ymm0,0x99(%eax,%ebx,4),%ymm4,%ymm6 + vldmxcsr 0x99(%esp,%ecx,8) + vmovdqa 0x99(%esp,%ecx,8),%xmm0 + vmovdqa %xmm0,0x99(%esp,%ecx,8) + vmovd %xmm0,0x99(%esp,%ecx,8) + vcvtsd2si 0x99(%esp,%ecx,8),%eax + vcvtdq2pd 0x99(%esp,%ecx,8),%ymm0 + vcvtpd2psy 0x99(%esp,%ecx,8),%xmm0 + vpavgb 0x99(%esp,%ecx,8),%xmm0,%xmm7 + vpextrb $100,%xmm0,0x99(%esp,%ecx,8) + vcvtsi2sdl 0x99(%esp,%ecx,8),%xmm0,%xmm7 + vblendvps %xmm0,0x99(%esp,%ecx,8),%xmm4,%xmm6 + vpinsrb $100,0x99(%esp,%ecx,8),%xmm0,%xmm7 + vmovdqa 0x99(%esp,%ecx,8),%ymm0 + vmovdqa %ymm0,0x99(%esp,%ecx,8) + vpermilpd 0x99(%esp,%ecx,8),%ymm0,%ymm7 + vroundpd $100,0x99(%esp,%ecx,8),%ymm0 + vextractf128 $100,%ymm0,0x99(%esp,%ecx,8) + vperm2f128 $100,0x99(%esp,%ecx,8),%ymm0,%ymm7 + vblendvpd %ymm0,0x99(%esp,%ecx,8),%ymm4,%ymm6 + vldmxcsr 0x99(%ebp,%edx,1) + vmovdqa 0x99(%ebp,%edx,1),%xmm0 + vmovdqa %xmm0,0x99(%ebp,%edx,1) + vmovd %xmm0,0x99(%ebp,%edx,1) + vcvtsd2si 0x99(%ebp,%edx,1),%eax + vcvtdq2pd 0x99(%ebp,%edx,1),%ymm0 + vcvtpd2psy 0x99(%ebp,%edx,1),%xmm0 + vpavgb 0x99(%ebp,%edx,1),%xmm0,%xmm7 + vpextrb $100,%xmm0,0x99(%ebp,%edx,1) + vcvtsi2sdl 0x99(%ebp,%edx,1),%xmm0,%xmm7 + vblendvps %xmm0,0x99(%ebp,%edx,1),%xmm4,%xmm6 + vpinsrb $100,0x99(%ebp,%edx,1),%xmm0,%xmm7 + vmovdqa 0x99(%ebp,%edx,1),%ymm0 + vmovdqa %ymm0,0x99(%ebp,%edx,1) + vpermilpd 0x99(%ebp,%edx,1),%ymm0,%ymm7 + vroundpd $100,0x99(%ebp,%edx,1),%ymm0 + vextractf128 $100,%ymm0,0x99(%ebp,%edx,1) + vperm2f128 $100,0x99(%ebp,%edx,1),%ymm0,%ymm7 + vblendvpd %ymm0,0x99(%ebp,%edx,1),%ymm4,%ymm6 +# Tests for all register operands. + vmovmskpd %xmm0,%eax + vpslld $100,%xmm0,%xmm7 + vmovmskps %ymm0,%eax + + .intel_syntax noprefix +# Tests for op mem64 + vldmxcsr DWORD PTR [ecx] + vstmxcsr DWORD PTR [ecx] + +# Tests for op mem256, mask, ymm +# Tests for op ymm, mask, mem256 + vmaskmovpd ymm6,ymm4,YMMWORD PTR [ecx] + vmaskmovpd YMMWORD PTR [ecx],ymm6,ymm4 + vmaskmovps ymm6,ymm4,YMMWORD PTR [ecx] + vmaskmovps YMMWORD PTR [ecx],ymm6,ymm4 + +# Tests for op imm8, ymm/mem256, ymm + vpermilpd ymm2,ymm6,100 + vpermilpd ymm6,YMMWORD PTR [ecx],100 + vpermilps ymm2,ymm6,100 + vpermilps ymm6,YMMWORD PTR [ecx],100 + vroundpd ymm2,ymm6,100 + vroundpd ymm6,YMMWORD PTR [ecx],100 + vroundps ymm2,ymm6,100 + vroundps ymm6,YMMWORD PTR [ecx],100 + +# Tests for op ymm/mem256, ymm, ymm + vaddpd ymm2,ymm6,ymm4 + vaddpd ymm2,ymm6,YMMWORD PTR [ecx] + vaddps ymm2,ymm6,ymm4 + vaddps ymm2,ymm6,YMMWORD PTR [ecx] + vaddsubpd ymm2,ymm6,ymm4 + vaddsubpd ymm2,ymm6,YMMWORD PTR [ecx] + vaddsubps ymm2,ymm6,ymm4 + vaddsubps ymm2,ymm6,YMMWORD PTR [ecx] + vandnpd ymm2,ymm6,ymm4 + vandnpd ymm2,ymm6,YMMWORD PTR [ecx] + vandnps ymm2,ymm6,ymm4 + vandnps ymm2,ymm6,YMMWORD PTR [ecx] + vandpd ymm2,ymm6,ymm4 + vandpd ymm2,ymm6,YMMWORD PTR [ecx] + vandps ymm2,ymm6,ymm4 + vandps ymm2,ymm6,YMMWORD PTR [ecx] + vdivpd ymm2,ymm6,ymm4 + vdivpd ymm2,ymm6,YMMWORD PTR [ecx] + vdivps ymm2,ymm6,ymm4 + vdivps ymm2,ymm6,YMMWORD PTR [ecx] + vhaddpd ymm2,ymm6,ymm4 + vhaddpd ymm2,ymm6,YMMWORD PTR [ecx] + vhaddps ymm2,ymm6,ymm4 + vhaddps ymm2,ymm6,YMMWORD PTR [ecx] + vhsubpd ymm2,ymm6,ymm4 + vhsubpd ymm2,ymm6,YMMWORD PTR [ecx] + vhsubps ymm2,ymm6,ymm4 + vhsubps ymm2,ymm6,YMMWORD PTR [ecx] + vmaxpd ymm2,ymm6,ymm4 + vmaxpd ymm2,ymm6,YMMWORD PTR [ecx] + vmaxps ymm2,ymm6,ymm4 + vmaxps ymm2,ymm6,YMMWORD PTR [ecx] + vminpd ymm2,ymm6,ymm4 + vminpd ymm2,ymm6,YMMWORD PTR [ecx] + vminps ymm2,ymm6,ymm4 + vminps ymm2,ymm6,YMMWORD PTR [ecx] + vmulpd ymm2,ymm6,ymm4 + vmulpd ymm2,ymm6,YMMWORD PTR [ecx] + vmulps ymm2,ymm6,ymm4 + vmulps ymm2,ymm6,YMMWORD PTR [ecx] + vorpd ymm2,ymm6,ymm4 + vorpd ymm2,ymm6,YMMWORD PTR [ecx] + vorps ymm2,ymm6,ymm4 + vorps ymm2,ymm6,YMMWORD PTR [ecx] + vpermilpd ymm2,ymm6,ymm4 + vpermilpd ymm2,ymm6,YMMWORD PTR [ecx] + vpermilps ymm2,ymm6,ymm4 + vpermilps ymm2,ymm6,YMMWORD PTR [ecx] + vsubpd ymm2,ymm6,ymm4 + vsubpd ymm2,ymm6,YMMWORD PTR [ecx] + vsubps ymm2,ymm6,ymm4 + vsubps ymm2,ymm6,YMMWORD PTR [ecx] + vunpckhpd ymm2,ymm6,ymm4 + vunpckhpd ymm2,ymm6,YMMWORD PTR [ecx] + vunpckhps ymm2,ymm6,ymm4 + vunpckhps ymm2,ymm6,YMMWORD PTR [ecx] + vunpcklpd ymm2,ymm6,ymm4 + vunpcklpd ymm2,ymm6,YMMWORD PTR [ecx] + vunpcklps ymm2,ymm6,ymm4 + vunpcklps ymm2,ymm6,YMMWORD PTR [ecx] + vxorpd ymm2,ymm6,ymm4 + vxorpd ymm2,ymm6,YMMWORD PTR [ecx] + vxorps ymm2,ymm6,ymm4 + vxorps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpeqpd ymm2,ymm6,ymm4 + vcmpeqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpltpd ymm2,ymm6,ymm4 + vcmpltpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmplepd ymm2,ymm6,ymm4 + vcmplepd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpunordpd ymm2,ymm6,ymm4 + vcmpunordpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpneqpd ymm2,ymm6,ymm4 + vcmpneqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnltpd ymm2,ymm6,ymm4 + vcmpnltpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnlepd ymm2,ymm6,ymm4 + vcmpnlepd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpordpd ymm2,ymm6,ymm4 + vcmpordpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpeq_uqpd ymm2,ymm6,ymm4 + vcmpeq_uqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpngepd ymm2,ymm6,ymm4 + vcmpngepd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpngtpd ymm2,ymm6,ymm4 + vcmpngtpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpfalsepd ymm2,ymm6,ymm4 + vcmpfalsepd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpneq_oqpd ymm2,ymm6,ymm4 + vcmpneq_oqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpgepd ymm2,ymm6,ymm4 + vcmpgepd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpgtpd ymm2,ymm6,ymm4 + vcmpgtpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmptruepd ymm2,ymm6,ymm4 + vcmptruepd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpeq_ospd ymm2,ymm6,ymm4 + vcmpeq_ospd ymm2,ymm6,YMMWORD PTR [ecx] + vcmplt_oqpd ymm2,ymm6,ymm4 + vcmplt_oqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmple_oqpd ymm2,ymm6,ymm4 + vcmple_oqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpunord_spd ymm2,ymm6,ymm4 + vcmpunord_spd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpneq_uspd ymm2,ymm6,ymm4 + vcmpneq_uspd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnlt_uqpd ymm2,ymm6,ymm4 + vcmpnlt_uqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnle_uqpd ymm2,ymm6,ymm4 + vcmpnle_uqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpord_spd ymm2,ymm6,ymm4 + vcmpord_spd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpeq_uspd ymm2,ymm6,ymm4 + vcmpeq_uspd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnge_uqpd ymm2,ymm6,ymm4 + vcmpnge_uqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpngt_uqpd ymm2,ymm6,ymm4 + vcmpngt_uqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpfalse_ospd ymm2,ymm6,ymm4 + vcmpfalse_ospd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpneq_ospd ymm2,ymm6,ymm4 + vcmpneq_ospd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpge_oqpd ymm2,ymm6,ymm4 + vcmpge_oqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpgt_oqpd ymm2,ymm6,ymm4 + vcmpgt_oqpd ymm2,ymm6,YMMWORD PTR [ecx] + vcmptrue_uspd ymm2,ymm6,ymm4 + vcmptrue_uspd ymm2,ymm6,YMMWORD PTR [ecx] + vcmpeqps ymm2,ymm6,ymm4 + vcmpeqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpltps ymm2,ymm6,ymm4 + vcmpltps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpleps ymm2,ymm6,ymm4 + vcmpleps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpunordps ymm2,ymm6,ymm4 + vcmpunordps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpneqps ymm2,ymm6,ymm4 + vcmpneqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnltps ymm2,ymm6,ymm4 + vcmpnltps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnleps ymm2,ymm6,ymm4 + vcmpnleps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpordps ymm2,ymm6,ymm4 + vcmpordps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpeq_uqps ymm2,ymm6,ymm4 + vcmpeq_uqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpngeps ymm2,ymm6,ymm4 + vcmpngeps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpngtps ymm2,ymm6,ymm4 + vcmpngtps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpfalseps ymm2,ymm6,ymm4 + vcmpfalseps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpneq_oqps ymm2,ymm6,ymm4 + vcmpneq_oqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpgeps ymm2,ymm6,ymm4 + vcmpgeps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpgtps ymm2,ymm6,ymm4 + vcmpgtps ymm2,ymm6,YMMWORD PTR [ecx] + vcmptrueps ymm2,ymm6,ymm4 + vcmptrueps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpeq_osps ymm2,ymm6,ymm4 + vcmpeq_osps ymm2,ymm6,YMMWORD PTR [ecx] + vcmplt_oqps ymm2,ymm6,ymm4 + vcmplt_oqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmple_oqps ymm2,ymm6,ymm4 + vcmple_oqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpunord_sps ymm2,ymm6,ymm4 + vcmpunord_sps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpneq_usps ymm2,ymm6,ymm4 + vcmpneq_usps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnlt_uqps ymm2,ymm6,ymm4 + vcmpnlt_uqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnle_uqps ymm2,ymm6,ymm4 + vcmpnle_uqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpord_sps ymm2,ymm6,ymm4 + vcmpord_sps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpeq_usps ymm2,ymm6,ymm4 + vcmpeq_usps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpnge_uqps ymm2,ymm6,ymm4 + vcmpnge_uqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpngt_uqps ymm2,ymm6,ymm4 + vcmpngt_uqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpfalse_osps ymm2,ymm6,ymm4 + vcmpfalse_osps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpneq_osps ymm2,ymm6,ymm4 + vcmpneq_osps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpge_oqps ymm2,ymm6,ymm4 + vcmpge_oqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmpgt_oqps ymm2,ymm6,ymm4 + vcmpgt_oqps ymm2,ymm6,YMMWORD PTR [ecx] + vcmptrue_usps ymm2,ymm6,ymm4 + vcmptrue_usps ymm2,ymm6,YMMWORD PTR [ecx] + +# Tests for op ymm/mem256, xmm + vcvtpd2dq xmm4,ymm4 + vcvtpd2dq xmm4,YMMWORD PTR [ecx] + vcvtpd2ps xmm4,ymm4 + vcvtpd2ps xmm4,YMMWORD PTR [ecx] + vcvttpd2dq xmm4,ymm4 + vcvttpd2dq xmm4,YMMWORD PTR [ecx] + +# Tests for op ymm/mem256, ymm + vcvtdq2ps ymm4,ymm4 + vcvtdq2ps ymm4,YMMWORD PTR [ecx] + vcvtps2dq ymm4,ymm4 + vcvtps2dq ymm4,YMMWORD PTR [ecx] + vcvttps2dq ymm4,ymm4 + vcvttps2dq ymm4,YMMWORD PTR [ecx] + vmovapd ymm4,ymm4 + vmovapd ymm4,YMMWORD PTR [ecx] + vmovaps ymm4,ymm4 + vmovaps ymm4,YMMWORD PTR [ecx] + vmovdqa ymm4,ymm4 + vmovdqa ymm4,YMMWORD PTR [ecx] + vmovdqu ymm4,ymm4 + vmovdqu ymm4,YMMWORD PTR [ecx] + vmovddup ymm4,ymm4 + vmovddup ymm4,YMMWORD PTR [ecx] + vmovshdup ymm4,ymm4 + vmovshdup ymm4,YMMWORD PTR [ecx] + vmovsldup ymm4,ymm4 + vmovsldup ymm4,YMMWORD PTR [ecx] + vmovupd ymm4,ymm4 + vmovupd ymm4,YMMWORD PTR [ecx] + vmovups ymm4,ymm4 + vmovups ymm4,YMMWORD PTR [ecx] + vptest ymm4,ymm4 + vptest ymm4,YMMWORD PTR [ecx] + vrcpps ymm4,ymm4 + vrcpps ymm4,YMMWORD PTR [ecx] + vrsqrtps ymm4,ymm4 + vrsqrtps ymm4,YMMWORD PTR [ecx] + vsqrtpd ymm4,ymm4 + vsqrtpd ymm4,YMMWORD PTR [ecx] + vsqrtps ymm4,ymm4 + vsqrtps ymm4,YMMWORD PTR [ecx] + vtestpd ymm4,ymm4 + vtestpd ymm4,YMMWORD PTR [ecx] + vtestps ymm4,ymm4 + vtestps ymm4,YMMWORD PTR [ecx] + +# Tests for op mem256, ymm + vlddqu ymm4,YMMWORD PTR [ecx] + +# Tests for op imm8, ymm/mem256, ymm, ymm + vblendpd ymm2,ymm6,ymm4,100 + vblendpd ymm2,ymm6,YMMWORD PTR [ecx],100 + vblendps ymm2,ymm6,ymm4,100 + vblendps ymm2,ymm6,YMMWORD PTR [ecx],100 + vcmppd ymm2,ymm6,ymm4,100 + vcmppd ymm2,ymm6,YMMWORD PTR [ecx],100 + vcmpps ymm2,ymm6,ymm4,100 + vcmpps ymm2,ymm6,YMMWORD PTR [ecx],100 + vdpps ymm2,ymm6,ymm4,100 + vdpps ymm2,ymm6,YMMWORD PTR [ecx],100 + vperm2f128 ymm2,ymm6,ymm4,100 + vperm2f128 ymm2,ymm6,YMMWORD PTR [ecx],100 + vshufpd ymm2,ymm6,ymm4,100 + vshufpd ymm2,ymm6,YMMWORD PTR [ecx],100 + vshufps ymm2,ymm6,ymm4,100 + vshufps ymm2,ymm6,YMMWORD PTR [ecx],100 + +# Tests for op ymm, ymm/mem256, ymm, ymm + vblendvpd ymm7,ymm2,ymm6,ymm4 + vblendvpd ymm7,ymm2,YMMWORD PTR [ecx],ymm4 + vblendvps ymm7,ymm2,ymm6,ymm4 + vblendvps ymm7,ymm2,YMMWORD PTR [ecx],ymm4 + +# Tests for op ymm/mem256, ymm, ymm, ymm +# Tests for op ymm, ymm/mem256, ymm, ymm + vfmaddpd ymm7,ymm2,ymm6,ymm4 + vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfmaddps ymm7,ymm2,ymm6,ymm4 + vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfmaddsubpd ymm7,ymm2,ymm6,ymm4 + vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfmaddsubps ymm7,ymm2,ymm6,ymm4 + vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfmsubaddpd ymm7,ymm2,ymm6,ymm4 + vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfmsubaddps ymm7,ymm2,ymm6,ymm4 + vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfmsubpd ymm7,ymm2,ymm6,ymm4 + vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfmsubps ymm7,ymm2,ymm6,ymm4 + vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfnmaddpd ymm7,ymm2,ymm6,ymm4 + vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfnmaddps ymm7,ymm2,ymm6,ymm4 + vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfnmsubpd ymm7,ymm2,ymm6,ymm4 + vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vfnmsubps ymm7,ymm2,ymm6,ymm4 + vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vpermilmo2pd ymm7,ymm2,ymm6,ymm4 + vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vpermilmz2pd ymm7,ymm2,ymm6,ymm4 + vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vpermiltd2pd ymm7,ymm2,ymm6,ymm4 + vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vpermilmo2ps ymm7,ymm2,ymm6,ymm4 + vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vpermilmz2ps ymm7,ymm2,ymm6,ymm4 + vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + vpermiltd2ps ymm7,ymm2,ymm6,ymm4 + vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR [ecx] + +# Tests for op imm4, ymm/mem256, ymm, ymm, ymm +# Tests for op imm4, ymm, ymm/mem256, ymm, ymm + vpermil2pd ymm7,ymm2,ymm6,ymm4,10 + vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR [ecx],10 + vpermil2ps ymm7,ymm2,ymm6,ymm4,10 + vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR [ecx],10 + +# Tests for op imm8, xmm/mem128, ymm, ymm + vinsertf128 ymm6,ymm4,xmm4,100 + vinsertf128 ymm6,ymm4,XMMWORD PTR [ecx],100 + +# Tests for op imm8, ymm, xmm/mem128 + vextractf128 xmm4,ymm4,100 + vextractf128 XMMWORD PTR [ecx],ymm4,100 + +# Tests for op xmm/mem128, xmm +# Tests for op mem128, ymm + vbroadcastf128 ymm4,XMMWORD PTR [ecx] + +# Tests for op xmm/mem128, xmm + vcvtdq2ps xmm6,xmm4 + vcvtdq2ps xmm4,XMMWORD PTR [ecx] + vcvtpd2dq xmm6,xmm4 + vcvtpd2dq xmm4,XMMWORD PTR [ecx] + vcvtpd2ps xmm6,xmm4 + vcvtpd2ps xmm4,XMMWORD PTR [ecx] + vcvtps2dq xmm6,xmm4 + vcvtps2dq xmm4,XMMWORD PTR [ecx] + vcvttpd2dq xmm6,xmm4 + vcvttpd2dq xmm4,XMMWORD PTR [ecx] + vcvttps2dq xmm6,xmm4 + vcvttps2dq xmm4,XMMWORD PTR [ecx] + vmovapd xmm6,xmm4 + vmovapd xmm4,XMMWORD PTR [ecx] + vmovaps xmm6,xmm4 + vmovaps xmm4,XMMWORD PTR [ecx] + vmovdqa xmm6,xmm4 + vmovdqa xmm4,XMMWORD PTR [ecx] + vmovdqu xmm6,xmm4 + vmovdqu xmm4,XMMWORD PTR [ecx] + vmovshdup xmm6,xmm4 + vmovshdup xmm4,XMMWORD PTR [ecx] + vmovsldup xmm6,xmm4 + vmovsldup xmm4,XMMWORD PTR [ecx] + vmovupd xmm6,xmm4 + vmovupd xmm4,XMMWORD PTR [ecx] + vmovups xmm6,xmm4 + vmovups xmm4,XMMWORD PTR [ecx] + vpabsb xmm6,xmm4 + vpabsb xmm4,XMMWORD PTR [ecx] + vpabsw xmm6,xmm4 + vpabsw xmm4,XMMWORD PTR [ecx] + vpabsd xmm6,xmm4 + vpabsd xmm4,XMMWORD PTR [ecx] + vphminposuw xmm6,xmm4 + vphminposuw xmm4,XMMWORD PTR [ecx] + vptest xmm6,xmm4 + vptest xmm4,XMMWORD PTR [ecx] + vtestps xmm6,xmm4 + vtestps xmm4,XMMWORD PTR [ecx] + vtestpd xmm6,xmm4 + vtestpd xmm4,XMMWORD PTR [ecx] + vrcpps xmm6,xmm4 + vrcpps xmm4,XMMWORD PTR [ecx] + vrsqrtps xmm6,xmm4 + vrsqrtps xmm4,XMMWORD PTR [ecx] + vsqrtpd xmm6,xmm4 + vsqrtpd xmm4,XMMWORD PTR [ecx] + vsqrtps xmm6,xmm4 + vsqrtps xmm4,XMMWORD PTR [ecx] + +# Tests for op xmm, xmm/mem128 + vmovapd xmm6,xmm4 + vmovapd XMMWORD PTR [ecx],xmm4 + vmovaps xmm6,xmm4 + vmovaps XMMWORD PTR [ecx],xmm4 + vmovdqa xmm6,xmm4 + vmovdqa XMMWORD PTR [ecx],xmm4 + vmovdqu xmm6,xmm4 + vmovdqu XMMWORD PTR [ecx],xmm4 + vmovupd xmm6,xmm4 + vmovupd XMMWORD PTR [ecx],xmm4 + vmovups xmm6,xmm4 + vmovups XMMWORD PTR [ecx],xmm4 + +# Tests for op mem128, xmm + vlddqu xmm4,XMMWORD PTR [ecx] + vmovntdqa xmm4,XMMWORD PTR [ecx] + +# Tests for op xmm, mem128 + vmovntdq XMMWORD PTR [ecx],xmm4 + vmovntpd XMMWORD PTR [ecx],xmm4 + vmovntps XMMWORD PTR [ecx],xmm4 + +# Tests for op xmm/mem128, ymm + vcvtdq2pd ymm4,xmm4 + vcvtdq2pd ymm4,XMMWORD PTR [ecx] + vcvtps2pd ymm4,xmm4 + vcvtps2pd ymm4,XMMWORD PTR [ecx] + +# Tests for op xmm/mem128, xmm, xmm + vaddpd xmm2,xmm6,xmm4 + vaddpd xmm7,xmm6,XMMWORD PTR [ecx] + vaddps xmm2,xmm6,xmm4 + vaddps xmm7,xmm6,XMMWORD PTR [ecx] + vaddsubpd xmm2,xmm6,xmm4 + vaddsubpd xmm7,xmm6,XMMWORD PTR [ecx] + vaddsubps xmm2,xmm6,xmm4 + vaddsubps xmm7,xmm6,XMMWORD PTR [ecx] + vandnpd xmm2,xmm6,xmm4 + vandnpd xmm7,xmm6,XMMWORD PTR [ecx] + vandnps xmm2,xmm6,xmm4 + vandnps xmm7,xmm6,XMMWORD PTR [ecx] + vandpd xmm2,xmm6,xmm4 + vandpd xmm7,xmm6,XMMWORD PTR [ecx] + vandps xmm2,xmm6,xmm4 + vandps xmm7,xmm6,XMMWORD PTR [ecx] + vdivpd xmm2,xmm6,xmm4 + vdivpd xmm7,xmm6,XMMWORD PTR [ecx] + vdivps xmm2,xmm6,xmm4 + vdivps xmm7,xmm6,XMMWORD PTR [ecx] + vhaddpd xmm2,xmm6,xmm4 + vhaddpd xmm7,xmm6,XMMWORD PTR [ecx] + vhaddps xmm2,xmm6,xmm4 + vhaddps xmm7,xmm6,XMMWORD PTR [ecx] + vhsubpd xmm2,xmm6,xmm4 + vhsubpd xmm7,xmm6,XMMWORD PTR [ecx] + vhsubps xmm2,xmm6,xmm4 + vhsubps xmm7,xmm6,XMMWORD PTR [ecx] + vmaxpd xmm2,xmm6,xmm4 + vmaxpd xmm7,xmm6,XMMWORD PTR [ecx] + vmaxps xmm2,xmm6,xmm4 + vmaxps xmm7,xmm6,XMMWORD PTR [ecx] + vminpd xmm2,xmm6,xmm4 + vminpd xmm7,xmm6,XMMWORD PTR [ecx] + vminps xmm2,xmm6,xmm4 + vminps xmm7,xmm6,XMMWORD PTR [ecx] + vmulpd xmm2,xmm6,xmm4 + vmulpd xmm7,xmm6,XMMWORD PTR [ecx] + vmulps xmm2,xmm6,xmm4 + vmulps xmm7,xmm6,XMMWORD PTR [ecx] + vorpd xmm2,xmm6,xmm4 + vorpd xmm7,xmm6,XMMWORD PTR [ecx] + vorps xmm2,xmm6,xmm4 + vorps xmm7,xmm6,XMMWORD PTR [ecx] + vpacksswb xmm2,xmm6,xmm4 + vpacksswb xmm7,xmm6,XMMWORD PTR [ecx] + vpackssdw xmm2,xmm6,xmm4 + vpackssdw xmm7,xmm6,XMMWORD PTR [ecx] + vpackuswb xmm2,xmm6,xmm4 + vpackuswb xmm7,xmm6,XMMWORD PTR [ecx] + vpackusdw xmm2,xmm6,xmm4 + vpackusdw xmm7,xmm6,XMMWORD PTR [ecx] + vpaddb xmm2,xmm6,xmm4 + vpaddb xmm7,xmm6,XMMWORD PTR [ecx] + vpaddw xmm2,xmm6,xmm4 + vpaddw xmm7,xmm6,XMMWORD PTR [ecx] + vpaddd xmm2,xmm6,xmm4 + vpaddd xmm7,xmm6,XMMWORD PTR [ecx] + vpaddq xmm2,xmm6,xmm4 + vpaddq xmm7,xmm6,XMMWORD PTR [ecx] + vpaddsb xmm2,xmm6,xmm4 + vpaddsb xmm7,xmm6,XMMWORD PTR [ecx] + vpaddsw xmm2,xmm6,xmm4 + vpaddsw xmm7,xmm6,XMMWORD PTR [ecx] + vpaddusb xmm2,xmm6,xmm4 + vpaddusb xmm7,xmm6,XMMWORD PTR [ecx] + vpaddusw xmm2,xmm6,xmm4 + vpaddusw xmm7,xmm6,XMMWORD PTR [ecx] + vpand xmm2,xmm6,xmm4 + vpand xmm7,xmm6,XMMWORD PTR [ecx] + vpandn xmm2,xmm6,xmm4 + vpandn xmm7,xmm6,XMMWORD PTR [ecx] + vpavgb xmm2,xmm6,xmm4 + vpavgb xmm7,xmm6,XMMWORD PTR [ecx] + vpavgw xmm2,xmm6,xmm4 + vpavgw xmm7,xmm6,XMMWORD PTR [ecx] + vpcmpeqb xmm2,xmm6,xmm4 + vpcmpeqb xmm7,xmm6,XMMWORD PTR [ecx] + vpcmpeqw xmm2,xmm6,xmm4 + vpcmpeqw xmm7,xmm6,XMMWORD PTR [ecx] + vpcmpeqd xmm2,xmm6,xmm4 + vpcmpeqd xmm7,xmm6,XMMWORD PTR [ecx] + vpcmpeqq xmm2,xmm6,xmm4 + vpcmpeqq xmm7,xmm6,XMMWORD PTR [ecx] + vpcmpgtb xmm2,xmm6,xmm4 + vpcmpgtb xmm7,xmm6,XMMWORD PTR [ecx] + vpcmpgtw xmm2,xmm6,xmm4 + vpcmpgtw xmm7,xmm6,XMMWORD PTR [ecx] + vpcmpgtd xmm2,xmm6,xmm4 + vpcmpgtd xmm7,xmm6,XMMWORD PTR [ecx] + vpcmpgtq xmm2,xmm6,xmm4 + vpcmpgtq xmm7,xmm6,XMMWORD PTR [ecx] + vpermilpd xmm2,xmm6,xmm4 + vpermilpd xmm7,xmm6,XMMWORD PTR [ecx] + vpermilps xmm2,xmm6,xmm4 + vpermilps xmm7,xmm6,XMMWORD PTR [ecx] + vphaddw xmm2,xmm6,xmm4 + vphaddw xmm7,xmm6,XMMWORD PTR [ecx] + vphaddd xmm2,xmm6,xmm4 + vphaddd xmm7,xmm6,XMMWORD PTR [ecx] + vphaddsw xmm2,xmm6,xmm4 + vphaddsw xmm7,xmm6,XMMWORD PTR [ecx] + vphsubw xmm2,xmm6,xmm4 + vphsubw xmm7,xmm6,XMMWORD PTR [ecx] + vphsubd xmm2,xmm6,xmm4 + vphsubd xmm7,xmm6,XMMWORD PTR [ecx] + vphsubsw xmm2,xmm6,xmm4 + vphsubsw xmm7,xmm6,XMMWORD PTR [ecx] + vpmaddwd xmm2,xmm6,xmm4 + vpmaddwd xmm7,xmm6,XMMWORD PTR [ecx] + vpmaddubsw xmm2,xmm6,xmm4 + vpmaddubsw xmm7,xmm6,XMMWORD PTR [ecx] + vpmaxsb xmm2,xmm6,xmm4 + vpmaxsb xmm7,xmm6,XMMWORD PTR [ecx] + vpmaxsw xmm2,xmm6,xmm4 + vpmaxsw xmm7,xmm6,XMMWORD PTR [ecx] + vpmaxsd xmm2,xmm6,xmm4 + vpmaxsd xmm7,xmm6,XMMWORD PTR [ecx] + vpmaxub xmm2,xmm6,xmm4 + vpmaxub xmm7,xmm6,XMMWORD PTR [ecx] + vpmaxuw xmm2,xmm6,xmm4 + vpmaxuw xmm7,xmm6,XMMWORD PTR [ecx] + vpmaxud xmm2,xmm6,xmm4 + vpmaxud xmm7,xmm6,XMMWORD PTR [ecx] + vpminsb xmm2,xmm6,xmm4 + vpminsb xmm7,xmm6,XMMWORD PTR [ecx] + vpminsw xmm2,xmm6,xmm4 + vpminsw xmm7,xmm6,XMMWORD PTR [ecx] + vpminsd xmm2,xmm6,xmm4 + vpminsd xmm7,xmm6,XMMWORD PTR [ecx] + vpminub xmm2,xmm6,xmm4 + vpminub xmm7,xmm6,XMMWORD PTR [ecx] + vpminuw xmm2,xmm6,xmm4 + vpminuw xmm7,xmm6,XMMWORD PTR [ecx] + vpminud xmm2,xmm6,xmm4 + vpminud xmm7,xmm6,XMMWORD PTR [ecx] + vpmulhuw xmm2,xmm6,xmm4 + vpmulhuw xmm7,xmm6,XMMWORD PTR [ecx] + vpmulhrsw xmm2,xmm6,xmm4 + vpmulhrsw xmm7,xmm6,XMMWORD PTR [ecx] + vpmulhw xmm2,xmm6,xmm4 + vpmulhw xmm7,xmm6,XMMWORD PTR [ecx] + vpmullw xmm2,xmm6,xmm4 + vpmullw xmm7,xmm6,XMMWORD PTR [ecx] + vpmulld xmm2,xmm6,xmm4 + vpmulld xmm7,xmm6,XMMWORD PTR [ecx] + vpmuludq xmm2,xmm6,xmm4 + vpmuludq xmm7,xmm6,XMMWORD PTR [ecx] + vpmuldq xmm2,xmm6,xmm4 + vpmuldq xmm7,xmm6,XMMWORD PTR [ecx] + vpor xmm2,xmm6,xmm4 + vpor xmm7,xmm6,XMMWORD PTR [ecx] + vpsadbw xmm2,xmm6,xmm4 + vpsadbw xmm7,xmm6,XMMWORD PTR [ecx] + vpshufb xmm2,xmm6,xmm4 + vpshufb xmm7,xmm6,XMMWORD PTR [ecx] + vpsignb xmm2,xmm6,xmm4 + vpsignb xmm7,xmm6,XMMWORD PTR [ecx] + vpsignw xmm2,xmm6,xmm4 + vpsignw xmm7,xmm6,XMMWORD PTR [ecx] + vpsignd xmm2,xmm6,xmm4 + vpsignd xmm7,xmm6,XMMWORD PTR [ecx] + vpsllw xmm2,xmm6,xmm4 + vpsllw xmm7,xmm6,XMMWORD PTR [ecx] + vpslld xmm2,xmm6,xmm4 + vpslld xmm7,xmm6,XMMWORD PTR [ecx] + vpsllq xmm2,xmm6,xmm4 + vpsllq xmm7,xmm6,XMMWORD PTR [ecx] + vpsraw xmm2,xmm6,xmm4 + vpsraw xmm7,xmm6,XMMWORD PTR [ecx] + vpsrad xmm2,xmm6,xmm4 + vpsrad xmm7,xmm6,XMMWORD PTR [ecx] + vpsrlw xmm2,xmm6,xmm4 + vpsrlw xmm7,xmm6,XMMWORD PTR [ecx] + vpsrld xmm2,xmm6,xmm4 + vpsrld xmm7,xmm6,XMMWORD PTR [ecx] + vpsrlq xmm2,xmm6,xmm4 + vpsrlq xmm7,xmm6,XMMWORD PTR [ecx] + vpsubb xmm2,xmm6,xmm4 + vpsubb xmm7,xmm6,XMMWORD PTR [ecx] + vpsubw xmm2,xmm6,xmm4 + vpsubw xmm7,xmm6,XMMWORD PTR [ecx] + vpsubd xmm2,xmm6,xmm4 + vpsubd xmm7,xmm6,XMMWORD PTR [ecx] + vpsubq xmm2,xmm6,xmm4 + vpsubq xmm7,xmm6,XMMWORD PTR [ecx] + vpsubsb xmm2,xmm6,xmm4 + vpsubsb xmm7,xmm6,XMMWORD PTR [ecx] + vpsubsw xmm2,xmm6,xmm4 + vpsubsw xmm7,xmm6,XMMWORD PTR [ecx] + vpsubusb xmm2,xmm6,xmm4 + vpsubusb xmm7,xmm6,XMMWORD PTR [ecx] + vpsubusw xmm2,xmm6,xmm4 + vpsubusw xmm7,xmm6,XMMWORD PTR [ecx] + vpunpckhbw xmm2,xmm6,xmm4 + vpunpckhbw xmm7,xmm6,XMMWORD PTR [ecx] + vpunpckhwd xmm2,xmm6,xmm4 + vpunpckhwd xmm7,xmm6,XMMWORD PTR [ecx] + vpunpckhdq xmm2,xmm6,xmm4 + vpunpckhdq xmm7,xmm6,XMMWORD PTR [ecx] + vpunpckhqdq xmm2,xmm6,xmm4 + vpunpckhqdq xmm7,xmm6,XMMWORD PTR [ecx] + vpunpcklbw xmm2,xmm6,xmm4 + vpunpcklbw xmm7,xmm6,XMMWORD PTR [ecx] + vpunpcklwd xmm2,xmm6,xmm4 + vpunpcklwd xmm7,xmm6,XMMWORD PTR [ecx] + vpunpckldq xmm2,xmm6,xmm4 + vpunpckldq xmm7,xmm6,XMMWORD PTR [ecx] + vpunpcklqdq xmm2,xmm6,xmm4 + vpunpcklqdq xmm7,xmm6,XMMWORD PTR [ecx] + vpxor xmm2,xmm6,xmm4 + vpxor xmm7,xmm6,XMMWORD PTR [ecx] + vsubpd xmm2,xmm6,xmm4 + vsubpd xmm7,xmm6,XMMWORD PTR [ecx] + vsubps xmm2,xmm6,xmm4 + vsubps xmm7,xmm6,XMMWORD PTR [ecx] + vunpckhpd xmm2,xmm6,xmm4 + vunpckhpd xmm7,xmm6,XMMWORD PTR [ecx] + vunpckhps xmm2,xmm6,xmm4 + vunpckhps xmm7,xmm6,XMMWORD PTR [ecx] + vunpcklpd xmm2,xmm6,xmm4 + vunpcklpd xmm7,xmm6,XMMWORD PTR [ecx] + vunpcklps xmm2,xmm6,xmm4 + vunpcklps xmm7,xmm6,XMMWORD PTR [ecx] + vxorpd xmm2,xmm6,xmm4 + vxorpd xmm7,xmm6,XMMWORD PTR [ecx] + vxorps xmm2,xmm6,xmm4 + vxorps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpeqpd xmm2,xmm6,xmm4 + vcmpeqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpltpd xmm2,xmm6,xmm4 + vcmpltpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmplepd xmm2,xmm6,xmm4 + vcmplepd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpunordpd xmm2,xmm6,xmm4 + vcmpunordpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpneqpd xmm2,xmm6,xmm4 + vcmpneqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnltpd xmm2,xmm6,xmm4 + vcmpnltpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnlepd xmm2,xmm6,xmm4 + vcmpnlepd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpordpd xmm2,xmm6,xmm4 + vcmpordpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpeq_uqpd xmm2,xmm6,xmm4 + vcmpeq_uqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpngepd xmm2,xmm6,xmm4 + vcmpngepd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpngtpd xmm2,xmm6,xmm4 + vcmpngtpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpfalsepd xmm2,xmm6,xmm4 + vcmpfalsepd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpneq_oqpd xmm2,xmm6,xmm4 + vcmpneq_oqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpgepd xmm2,xmm6,xmm4 + vcmpgepd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpgtpd xmm2,xmm6,xmm4 + vcmpgtpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmptruepd xmm2,xmm6,xmm4 + vcmptruepd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpeq_ospd xmm2,xmm6,xmm4 + vcmpeq_ospd xmm7,xmm6,XMMWORD PTR [ecx] + vcmplt_oqpd xmm2,xmm6,xmm4 + vcmplt_oqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmple_oqpd xmm2,xmm6,xmm4 + vcmple_oqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpunord_spd xmm2,xmm6,xmm4 + vcmpunord_spd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpneq_uspd xmm2,xmm6,xmm4 + vcmpneq_uspd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnlt_uqpd xmm2,xmm6,xmm4 + vcmpnlt_uqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnle_uqpd xmm2,xmm6,xmm4 + vcmpnle_uqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpord_spd xmm2,xmm6,xmm4 + vcmpord_spd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpeq_uspd xmm2,xmm6,xmm4 + vcmpeq_uspd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnge_uqpd xmm2,xmm6,xmm4 + vcmpnge_uqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpngt_uqpd xmm2,xmm6,xmm4 + vcmpngt_uqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpfalse_ospd xmm2,xmm6,xmm4 + vcmpfalse_ospd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpneq_ospd xmm2,xmm6,xmm4 + vcmpneq_ospd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpge_oqpd xmm2,xmm6,xmm4 + vcmpge_oqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpgt_oqpd xmm2,xmm6,xmm4 + vcmpgt_oqpd xmm7,xmm6,XMMWORD PTR [ecx] + vcmptrue_uspd xmm2,xmm6,xmm4 + vcmptrue_uspd xmm7,xmm6,XMMWORD PTR [ecx] + vcmpeqps xmm2,xmm6,xmm4 + vcmpeqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpltps xmm2,xmm6,xmm4 + vcmpltps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpleps xmm2,xmm6,xmm4 + vcmpleps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpunordps xmm2,xmm6,xmm4 + vcmpunordps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpneqps xmm2,xmm6,xmm4 + vcmpneqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnltps xmm2,xmm6,xmm4 + vcmpnltps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnleps xmm2,xmm6,xmm4 + vcmpnleps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpordps xmm2,xmm6,xmm4 + vcmpordps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpeq_uqps xmm2,xmm6,xmm4 + vcmpeq_uqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpngeps xmm2,xmm6,xmm4 + vcmpngeps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpngtps xmm2,xmm6,xmm4 + vcmpngtps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpfalseps xmm2,xmm6,xmm4 + vcmpfalseps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpneq_oqps xmm2,xmm6,xmm4 + vcmpneq_oqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpgeps xmm2,xmm6,xmm4 + vcmpgeps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpgtps xmm2,xmm6,xmm4 + vcmpgtps xmm7,xmm6,XMMWORD PTR [ecx] + vcmptrueps xmm2,xmm6,xmm4 + vcmptrueps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpeq_osps xmm2,xmm6,xmm4 + vcmpeq_osps xmm7,xmm6,XMMWORD PTR [ecx] + vcmplt_oqps xmm2,xmm6,xmm4 + vcmplt_oqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmple_oqps xmm2,xmm6,xmm4 + vcmple_oqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpunord_sps xmm2,xmm6,xmm4 + vcmpunord_sps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpneq_usps xmm2,xmm6,xmm4 + vcmpneq_usps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnlt_uqps xmm2,xmm6,xmm4 + vcmpnlt_uqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnle_uqps xmm2,xmm6,xmm4 + vcmpnle_uqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpord_sps xmm2,xmm6,xmm4 + vcmpord_sps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpeq_usps xmm2,xmm6,xmm4 + vcmpeq_usps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpnge_uqps xmm2,xmm6,xmm4 + vcmpnge_uqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpngt_uqps xmm2,xmm6,xmm4 + vcmpngt_uqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpfalse_osps xmm2,xmm6,xmm4 + vcmpfalse_osps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpneq_osps xmm2,xmm6,xmm4 + vcmpneq_osps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpge_oqps xmm2,xmm6,xmm4 + vcmpge_oqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmpgt_oqps xmm2,xmm6,xmm4 + vcmpgt_oqps xmm7,xmm6,XMMWORD PTR [ecx] + vcmptrue_usps xmm2,xmm6,xmm4 + vcmptrue_usps xmm7,xmm6,XMMWORD PTR [ecx] + +# Tests for op mem128, xmm, xmm + vmaskmovps xmm6,xmm4,XMMWORD PTR [ecx] + vmaskmovpd xmm6,xmm4,XMMWORD PTR [ecx] + +# Tests for op imm8, xmm/mem128, xmm + vpcmpestri xmm6,xmm4,100 + vpcmpestri xmm6,XMMWORD PTR [ecx],100 + vpcmpestrm xmm6,xmm4,100 + vpcmpestrm xmm6,XMMWORD PTR [ecx],100 + vpcmpistri xmm6,xmm4,100 + vpcmpistri xmm6,XMMWORD PTR [ecx],100 + vpcmpistrm xmm6,xmm4,100 + vpcmpistrm xmm6,XMMWORD PTR [ecx],100 + vpermilpd xmm6,xmm4,100 + vpermilpd xmm6,XMMWORD PTR [ecx],100 + vpermilps xmm6,xmm4,100 + vpermilps xmm6,XMMWORD PTR [ecx],100 + vpshufd xmm6,xmm4,100 + vpshufd xmm6,XMMWORD PTR [ecx],100 + vpshufhw xmm6,xmm4,100 + vpshufhw xmm6,XMMWORD PTR [ecx],100 + vpshuflw xmm6,xmm4,100 + vpshuflw xmm6,XMMWORD PTR [ecx],100 + vroundpd xmm6,xmm4,100 + vroundpd xmm6,XMMWORD PTR [ecx],100 + vroundps xmm6,xmm4,100 + vroundps xmm6,XMMWORD PTR [ecx],100 + +# Tests for op xmm, xmm, mem128 + vmaskmovps XMMWORD PTR [ecx],xmm6,xmm4 + vmaskmovpd XMMWORD PTR [ecx],xmm6,xmm4 + +# Tests for op imm8, xmm/mem128, xmm, xmm + vblendpd xmm2,xmm6,xmm4,100 + vblendpd xmm2,xmm6,XMMWORD PTR [ecx],100 + vblendps xmm2,xmm6,xmm4,100 + vblendps xmm2,xmm6,XMMWORD PTR [ecx],100 + vcmppd xmm2,xmm6,xmm4,100 + vcmppd xmm2,xmm6,XMMWORD PTR [ecx],100 + vcmpps xmm2,xmm6,xmm4,100 + vcmpps xmm2,xmm6,XMMWORD PTR [ecx],100 + vdppd xmm2,xmm6,xmm4,100 + vdppd xmm2,xmm6,XMMWORD PTR [ecx],100 + vdpps xmm2,xmm6,xmm4,100 + vdpps xmm2,xmm6,XMMWORD PTR [ecx],100 + vmpsadbw xmm2,xmm6,xmm4,100 + vmpsadbw xmm2,xmm6,XMMWORD PTR [ecx],100 + vpalignr xmm2,xmm6,xmm4,100 + vpalignr xmm2,xmm6,XMMWORD PTR [ecx],100 + vpblendw xmm2,xmm6,xmm4,100 + vpblendw xmm2,xmm6,XMMWORD PTR [ecx],100 + vshufpd xmm2,xmm6,xmm4,100 + vshufpd xmm2,xmm6,XMMWORD PTR [ecx],100 + vshufps xmm2,xmm6,xmm4,100 + vshufps xmm2,xmm6,XMMWORD PTR [ecx],100 + +# Tests for op xmm, xmm/mem128, xmm, xmm + vblendvpd xmm7,xmm2,xmm6,xmm4 + vblendvpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vblendvps xmm7,xmm2,xmm6,xmm4 + vblendvps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vpblendvb xmm7,xmm2,xmm6,xmm4 + vpblendvb xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + +# Tests for op xmm/mem128, xmm, xmm, xmm +# Tests for op xmm, xmm/mem128, xmm, xmm + vfmaddpd xmm7,xmm2,xmm6,xmm4 + vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfmaddpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfmaddps xmm7,xmm2,xmm6,xmm4 + vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfmaddps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfmaddsubpd xmm7,xmm2,xmm6,xmm4 + vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfmaddsubpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfmaddsubps xmm7,xmm2,xmm6,xmm4 + vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfmaddsubps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfmsubaddpd xmm7,xmm2,xmm6,xmm4 + vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfmsubaddpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfmsubaddps xmm7,xmm2,xmm6,xmm4 + vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfmsubaddps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfmsubpd xmm7,xmm2,xmm6,xmm4 + vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfmsubpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfmsubps xmm7,xmm2,xmm6,xmm4 + vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfmsubps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfnmaddpd xmm7,xmm2,xmm6,xmm4 + vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfnmaddpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfnmaddps xmm7,xmm2,xmm6,xmm4 + vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfnmaddps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfnmsubpd xmm7,xmm2,xmm6,xmm4 + vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfnmsubpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vfnmsubps xmm7,xmm2,xmm6,xmm4 + vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vfnmsubps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vpermilmo2pd xmm7,xmm2,xmm6,xmm4 + vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vpermilmo2pd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vpermilmz2pd xmm7,xmm2,xmm6,xmm4 + vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vpermilmz2pd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vpermiltd2pd xmm7,xmm2,xmm6,xmm4 + vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vpermiltd2pd xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vpermilmo2ps xmm7,xmm2,xmm6,xmm4 + vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vpermilmo2ps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vpermilmz2ps xmm7,xmm2,xmm6,xmm4 + vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vpermilmz2ps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + vpermiltd2ps xmm7,xmm2,xmm6,xmm4 + vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR [ecx] + vpermiltd2ps xmm7,xmm2,XMMWORD PTR [ecx],xmm4 + +# Tests for op imm4, xmm/mem128, xmm, xmm, xmm +# Tests for op imm4, xmm, xmm/mem128, xmm, xmm + vpermil2pd xmm7,xmm2,xmm6,xmm4,10 + vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR [ecx],10 + vpermil2pd xmm7,xmm2,XMMWORD PTR [ecx],xmm4,10 + vpermil2ps xmm7,xmm2,xmm6,xmm4,10 + vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR [ecx],10 + vpermil2ps xmm7,xmm2,XMMWORD PTR [ecx],xmm4,10 + +# Tests for op mem64, ymm + vbroadcastsd ymm4,QWORD PTR [ecx] + +# Tests for op xmm/mem64, xmm + vcomisd xmm6,xmm4 + vcomisd xmm4,QWORD PTR [ecx] + vcvtdq2pd xmm6,xmm4 + vcvtdq2pd xmm4,QWORD PTR [ecx] + vcvtps2pd xmm6,xmm4 + vcvtps2pd xmm4,QWORD PTR [ecx] + vmovddup xmm6,xmm4 + vmovddup xmm4,QWORD PTR [ecx] + vpmovsxbw xmm6,xmm4 + vpmovsxbw xmm4,QWORD PTR [ecx] + vpmovsxwd xmm6,xmm4 + vpmovsxwd xmm4,QWORD PTR [ecx] + vpmovsxdq xmm6,xmm4 + vpmovsxdq xmm4,QWORD PTR [ecx] + vpmovzxbw xmm6,xmm4 + vpmovzxbw xmm4,QWORD PTR [ecx] + vpmovzxwd xmm6,xmm4 + vpmovzxwd xmm4,QWORD PTR [ecx] + vpmovzxdq xmm6,xmm4 + vpmovzxdq xmm4,QWORD PTR [ecx] + vucomisd xmm6,xmm4 + vucomisd xmm4,QWORD PTR [ecx] + +# Tests for op mem64, xmm + vmovsd xmm4,QWORD PTR [ecx] + +# Tests for op xmm, mem64 + vmovlpd QWORD PTR [ecx],xmm4 + vmovlps QWORD PTR [ecx],xmm4 + vmovhpd QWORD PTR [ecx],xmm4 + vmovhps QWORD PTR [ecx],xmm4 + vmovsd QWORD PTR [ecx],xmm4 + +# Tests for op xmm, regq/mem64 +# Tests for op regq/mem64, xmm + vmovq QWORD PTR [ecx],xmm4 + vmovq xmm4,QWORD PTR [ecx] + +# Tests for op xmm/mem64, regl + vcvtsd2si ecx,xmm4 + vcvtsd2si ecx,QWORD PTR [ecx] + vcvttsd2si ecx,xmm4 + vcvttsd2si ecx,QWORD PTR [ecx] + +# Tests for op mem64, xmm, xmm + vmovlpd xmm6,xmm4,QWORD PTR [ecx] + vmovlps xmm6,xmm4,QWORD PTR [ecx] + vmovhpd xmm6,xmm4,QWORD PTR [ecx] + vmovhps xmm6,xmm4,QWORD PTR [ecx] + +# Tests for op imm8, xmm/mem64, xmm, xmm + vcmpsd xmm2,xmm6,xmm4,100 + vcmpsd xmm2,xmm6,QWORD PTR [ecx],100 + vroundsd xmm2,xmm6,xmm4,100 + vroundsd xmm2,xmm6,QWORD PTR [ecx],100 + +# Tests for op xmm/mem64, xmm, xmm, xmm +# Tests for op xmm, xmm/mem64, xmm, xmm + vfmaddsd xmm7,xmm2,xmm6,xmm4 + vfmaddsd xmm7,xmm2,xmm6,QWORD PTR [ecx] + vfmaddsd xmm7,xmm2,QWORD PTR [ecx],xmm4 + vfmsubsd xmm7,xmm2,xmm6,xmm4 + vfmsubsd xmm7,xmm2,xmm6,QWORD PTR [ecx] + vfmsubsd xmm7,xmm2,QWORD PTR [ecx],xmm4 + vfnmaddsd xmm7,xmm2,xmm6,xmm4 + vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR [ecx] + vfnmaddsd xmm7,xmm2,QWORD PTR [ecx],xmm4 + vfnmsubsd xmm7,xmm2,xmm6,xmm4 + vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR [ecx] + vfnmsubsd xmm7,xmm2,QWORD PTR [ecx],xmm4 + +# Tests for op xmm/mem64, xmm, xmm + vaddsd xmm2,xmm6,xmm4 + vaddsd xmm2,xmm6,QWORD PTR [ecx] + vcvtsd2ss xmm2,xmm6,xmm4 + vcvtsd2ss xmm2,xmm6,QWORD PTR [ecx] + vdivsd xmm2,xmm6,xmm4 + vdivsd xmm2,xmm6,QWORD PTR [ecx] + vmaxsd xmm2,xmm6,xmm4 + vmaxsd xmm2,xmm6,QWORD PTR [ecx] + vminsd xmm2,xmm6,xmm4 + vminsd xmm2,xmm6,QWORD PTR [ecx] + vmulsd xmm2,xmm6,xmm4 + vmulsd xmm2,xmm6,QWORD PTR [ecx] + vsqrtsd xmm2,xmm6,xmm4 + vsqrtsd xmm2,xmm6,QWORD PTR [ecx] + vsubsd xmm2,xmm6,xmm4 + vsubsd xmm2,xmm6,QWORD PTR [ecx] + vcmpeqsd xmm2,xmm6,xmm4 + vcmpeqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpltsd xmm2,xmm6,xmm4 + vcmpltsd xmm2,xmm6,QWORD PTR [ecx] + vcmplesd xmm2,xmm6,xmm4 + vcmplesd xmm2,xmm6,QWORD PTR [ecx] + vcmpunordsd xmm2,xmm6,xmm4 + vcmpunordsd xmm2,xmm6,QWORD PTR [ecx] + vcmpneqsd xmm2,xmm6,xmm4 + vcmpneqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpnltsd xmm2,xmm6,xmm4 + vcmpnltsd xmm2,xmm6,QWORD PTR [ecx] + vcmpnlesd xmm2,xmm6,xmm4 + vcmpnlesd xmm2,xmm6,QWORD PTR [ecx] + vcmpordsd xmm2,xmm6,xmm4 + vcmpordsd xmm2,xmm6,QWORD PTR [ecx] + vcmpeq_uqsd xmm2,xmm6,xmm4 + vcmpeq_uqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpngesd xmm2,xmm6,xmm4 + vcmpngesd xmm2,xmm6,QWORD PTR [ecx] + vcmpngtsd xmm2,xmm6,xmm4 + vcmpngtsd xmm2,xmm6,QWORD PTR [ecx] + vcmpfalsesd xmm2,xmm6,xmm4 + vcmpfalsesd xmm2,xmm6,QWORD PTR [ecx] + vcmpneq_oqsd xmm2,xmm6,xmm4 + vcmpneq_oqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpgesd xmm2,xmm6,xmm4 + vcmpgesd xmm2,xmm6,QWORD PTR [ecx] + vcmpgtsd xmm2,xmm6,xmm4 + vcmpgtsd xmm2,xmm6,QWORD PTR [ecx] + vcmptruesd xmm2,xmm6,xmm4 + vcmptruesd xmm2,xmm6,QWORD PTR [ecx] + vcmpeq_ossd xmm2,xmm6,xmm4 + vcmpeq_ossd xmm2,xmm6,QWORD PTR [ecx] + vcmplt_oqsd xmm2,xmm6,xmm4 + vcmplt_oqsd xmm2,xmm6,QWORD PTR [ecx] + vcmple_oqsd xmm2,xmm6,xmm4 + vcmple_oqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpunord_ssd xmm2,xmm6,xmm4 + vcmpunord_ssd xmm2,xmm6,QWORD PTR [ecx] + vcmpneq_ussd xmm2,xmm6,xmm4 + vcmpneq_ussd xmm2,xmm6,QWORD PTR [ecx] + vcmpnlt_uqsd xmm2,xmm6,xmm4 + vcmpnlt_uqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpnle_uqsd xmm2,xmm6,xmm4 + vcmpnle_uqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpord_ssd xmm2,xmm6,xmm4 + vcmpord_ssd xmm2,xmm6,QWORD PTR [ecx] + vcmpeq_ussd xmm2,xmm6,xmm4 + vcmpeq_ussd xmm2,xmm6,QWORD PTR [ecx] + vcmpnge_uqsd xmm2,xmm6,xmm4 + vcmpnge_uqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpngt_uqsd xmm2,xmm6,xmm4 + vcmpngt_uqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpfalse_ossd xmm2,xmm6,xmm4 + vcmpfalse_ossd xmm2,xmm6,QWORD PTR [ecx] + vcmpneq_ossd xmm2,xmm6,xmm4 + vcmpneq_ossd xmm2,xmm6,QWORD PTR [ecx] + vcmpge_oqsd xmm2,xmm6,xmm4 + vcmpge_oqsd xmm2,xmm6,QWORD PTR [ecx] + vcmpgt_oqsd xmm2,xmm6,xmm4 + vcmpgt_oqsd xmm2,xmm6,QWORD PTR [ecx] + vcmptrue_ussd xmm2,xmm6,xmm4 + vcmptrue_ussd xmm2,xmm6,QWORD PTR [ecx] + +# Tests for op xmm/mem32, xmm, xmm + vaddss xmm2,xmm6,xmm4 + vaddss xmm2,xmm6,DWORD PTR [ecx] + vcvtss2sd xmm2,xmm6,xmm4 + vcvtss2sd xmm2,xmm6,DWORD PTR [ecx] + vdivss xmm2,xmm6,xmm4 + vdivss xmm2,xmm6,DWORD PTR [ecx] + vmaxss xmm2,xmm6,xmm4 + vmaxss xmm2,xmm6,DWORD PTR [ecx] + vminss xmm2,xmm6,xmm4 + vminss xmm2,xmm6,DWORD PTR [ecx] + vmulss xmm2,xmm6,xmm4 + vmulss xmm2,xmm6,DWORD PTR [ecx] + vrcpss xmm2,xmm6,xmm4 + vrcpss xmm2,xmm6,DWORD PTR [ecx] + vrsqrtss xmm2,xmm6,xmm4 + vrsqrtss xmm2,xmm6,DWORD PTR [ecx] + vsqrtss xmm2,xmm6,xmm4 + vsqrtss xmm2,xmm6,DWORD PTR [ecx] + vsubss xmm2,xmm6,xmm4 + vsubss xmm2,xmm6,DWORD PTR [ecx] + vcmpeqss xmm2,xmm6,xmm4 + vcmpeqss xmm2,xmm6,DWORD PTR [ecx] + vcmpltss xmm2,xmm6,xmm4 + vcmpltss xmm2,xmm6,DWORD PTR [ecx] + vcmpless xmm2,xmm6,xmm4 + vcmpless xmm2,xmm6,DWORD PTR [ecx] + vcmpunordss xmm2,xmm6,xmm4 + vcmpunordss xmm2,xmm6,DWORD PTR [ecx] + vcmpneqss xmm2,xmm6,xmm4 + vcmpneqss xmm2,xmm6,DWORD PTR [ecx] + vcmpnltss xmm2,xmm6,xmm4 + vcmpnltss xmm2,xmm6,DWORD PTR [ecx] + vcmpnless xmm2,xmm6,xmm4 + vcmpnless xmm2,xmm6,DWORD PTR [ecx] + vcmpordss xmm2,xmm6,xmm4 + vcmpordss xmm2,xmm6,DWORD PTR [ecx] + vcmpeq_uqss xmm2,xmm6,xmm4 + vcmpeq_uqss xmm2,xmm6,DWORD PTR [ecx] + vcmpngess xmm2,xmm6,xmm4 + vcmpngess xmm2,xmm6,DWORD PTR [ecx] + vcmpngtss xmm2,xmm6,xmm4 + vcmpngtss xmm2,xmm6,DWORD PTR [ecx] + vcmpfalsess xmm2,xmm6,xmm4 + vcmpfalsess xmm2,xmm6,DWORD PTR [ecx] + vcmpneq_oqss xmm2,xmm6,xmm4 + vcmpneq_oqss xmm2,xmm6,DWORD PTR [ecx] + vcmpgess xmm2,xmm6,xmm4 + vcmpgess xmm2,xmm6,DWORD PTR [ecx] + vcmpgtss xmm2,xmm6,xmm4 + vcmpgtss xmm2,xmm6,DWORD PTR [ecx] + vcmptruess xmm2,xmm6,xmm4 + vcmptruess xmm2,xmm6,DWORD PTR [ecx] + vcmpeq_osss xmm2,xmm6,xmm4 + vcmpeq_osss xmm2,xmm6,DWORD PTR [ecx] + vcmplt_oqss xmm2,xmm6,xmm4 + vcmplt_oqss xmm2,xmm6,DWORD PTR [ecx] + vcmple_oqss xmm2,xmm6,xmm4 + vcmple_oqss xmm2,xmm6,DWORD PTR [ecx] + vcmpunord_sss xmm2,xmm6,xmm4 + vcmpunord_sss xmm2,xmm6,DWORD PTR [ecx] + vcmpneq_usss xmm2,xmm6,xmm4 + vcmpneq_usss xmm2,xmm6,DWORD PTR [ecx] + vcmpnlt_uqss xmm2,xmm6,xmm4 + vcmpnlt_uqss xmm2,xmm6,DWORD PTR [ecx] + vcmpnle_uqss xmm2,xmm6,xmm4 + vcmpnle_uqss xmm2,xmm6,DWORD PTR [ecx] + vcmpord_sss xmm2,xmm6,xmm4 + vcmpord_sss xmm2,xmm6,DWORD PTR [ecx] + vcmpeq_usss xmm2,xmm6,xmm4 + vcmpeq_usss xmm2,xmm6,DWORD PTR [ecx] + vcmpnge_uqss xmm2,xmm6,xmm4 + vcmpnge_uqss xmm2,xmm6,DWORD PTR [ecx] + vcmpngt_uqss xmm2,xmm6,xmm4 + vcmpngt_uqss xmm2,xmm6,DWORD PTR [ecx] + vcmpfalse_osss xmm2,xmm6,xmm4 + vcmpfalse_osss xmm2,xmm6,DWORD PTR [ecx] + vcmpneq_osss xmm2,xmm6,xmm4 + vcmpneq_osss xmm2,xmm6,DWORD PTR [ecx] + vcmpge_oqss xmm2,xmm6,xmm4 + vcmpge_oqss xmm2,xmm6,DWORD PTR [ecx] + vcmpgt_oqss xmm2,xmm6,xmm4 + vcmpgt_oqss xmm2,xmm6,DWORD PTR [ecx] + vcmptrue_usss xmm2,xmm6,xmm4 + vcmptrue_usss xmm2,xmm6,DWORD PTR [ecx] + +# Tests for op mem32, ymm + vbroadcastss ymm4,DWORD PTR [ecx] + +# Tests for op xmm/mem32, xmm + vcomiss xmm6,xmm4 + vcomiss xmm4,DWORD PTR [ecx] + vpmovsxbd xmm6,xmm4 + vpmovsxbd xmm4,DWORD PTR [ecx] + vpmovsxwq xmm6,xmm4 + vpmovsxwq xmm4,DWORD PTR [ecx] + vpmovzxbd xmm6,xmm4 + vpmovzxbd xmm4,DWORD PTR [ecx] + vpmovzxwq xmm6,xmm4 + vpmovzxwq xmm4,DWORD PTR [ecx] + vucomiss xmm6,xmm4 + vucomiss xmm4,DWORD PTR [ecx] + +# Tests for op mem32, xmm + vbroadcastss xmm4,DWORD PTR [ecx] + vmovss xmm4,DWORD PTR [ecx] + +# Tests for op xmm, mem32 + vmovss DWORD PTR [ecx],xmm4 + +# Tests for op xmm, regl/mem32 +# Tests for op regl/mem32, xmm + vmovd ecx,xmm4 + vmovd DWORD PTR [ecx],xmm4 + vmovd xmm4,ecx + vmovd xmm4,DWORD PTR [ecx] + +# Tests for op xmm/mem32, regl + vcvtss2si ecx,xmm4 + vcvtss2si ecx,DWORD PTR [ecx] + vcvttss2si ecx,xmm4 + vcvttss2si ecx,DWORD PTR [ecx] + +# Tests for op imm8, xmm, regq/mem32 + vextractps DWORD PTR [ecx],xmm4,100 +# Tests for op imm8, xmm, regl/mem32 + vpextrd ecx,xmm4,100 + vpextrd DWORD PTR [ecx],xmm4,100 + vextractps ecx,xmm4,100 + vextractps DWORD PTR [ecx],xmm4,100 + +# Tests for op regl/mem32, xmm, xmm + vcvtsi2sd xmm6,xmm4,ecx + vcvtsi2sd xmm6,xmm4,DWORD PTR [ecx] + vcvtsi2ss xmm6,xmm4,ecx + vcvtsi2ss xmm6,xmm4,DWORD PTR [ecx] + +# Tests for op imm8, xmm/mem32, xmm, xmm + vcmpss xmm2,xmm6,xmm4,100 + vcmpss xmm2,xmm6,DWORD PTR [ecx],100 + vinsertps xmm2,xmm6,xmm4,100 + vinsertps xmm2,xmm6,DWORD PTR [ecx],100 + vroundss xmm2,xmm6,xmm4,100 + vroundss xmm2,xmm6,DWORD PTR [ecx],100 + +# Tests for op xmm/mem32, xmm, xmm, xmm +# Tests for op xmm, xmm/mem32, xmm, xmm + vfmaddss xmm7,xmm2,xmm6,xmm4 + vfmaddss xmm7,xmm2,xmm6,DWORD PTR [ecx] + vfmaddss xmm7,xmm2,DWORD PTR [ecx],xmm4 + vfmsubss xmm7,xmm2,xmm6,xmm4 + vfmsubss xmm7,xmm2,xmm6,DWORD PTR [ecx] + vfmsubss xmm7,xmm2,DWORD PTR [ecx],xmm4 + vfnmaddss xmm7,xmm2,xmm6,xmm4 + vfnmaddss xmm7,xmm2,xmm6,DWORD PTR [ecx] + vfnmaddss xmm7,xmm2,DWORD PTR [ecx],xmm4 + vfnmsubss xmm7,xmm2,xmm6,xmm4 + vfnmsubss xmm7,xmm2,xmm6,DWORD PTR [ecx] + vfnmsubss xmm7,xmm2,DWORD PTR [ecx],xmm4 + +# Tests for op xmm/m16, xmm + vpmovsxbq xmm6,xmm4 + vpmovsxbq xmm4,WORD PTR [ecx] + vpmovzxbq xmm6,xmm4 + vpmovzxbq xmm4,WORD PTR [ecx] + +# Tests for op imm8, xmm, regl/mem16 + vpextrw ecx,xmm4,100 + vpextrw WORD PTR [ecx],xmm4,100 + +# Tests for op imm8, xmm, regq/mem16 + vpextrw WORD PTR [ecx],xmm4,100 + +# Tests for op imm8, regl/mem16, xmm, xmm + vpinsrw xmm6,xmm4,ecx,100 + vpinsrw xmm6,xmm4,WORD PTR [ecx],100 + + +# Tests for op imm8, xmm, regl/mem8 + vpextrb ecx,xmm4,100 + vpextrb BYTE PTR [ecx],xmm4,100 + +# Tests for op imm8, regl/mem8, xmm, xmm + vpinsrb xmm6,xmm4,ecx,100 + vpinsrb xmm6,xmm4,BYTE PTR [ecx],100 + +# Tests for op imm8, xmm, regq/mem8 + vpextrb BYTE PTR [ecx],xmm4,100 + +# Tests for op imm8, regl/mem8, xmm, xmm + vpinsrb xmm6,xmm4,ecx,100 + vpinsrb xmm6,xmm4,BYTE PTR [ecx],100 + +# Tests for op xmm, xmm + vmaskmovdqu xmm6,xmm4 + vmovq xmm6,xmm4 + +# Tests for op xmm, regl + vmovmskpd ecx,xmm4 + vmovmskps ecx,xmm4 + vpmovmskb ecx,xmm4 +# Tests for op xmm, xmm, xmm + vmovhlps xmm2,xmm6,xmm4 + vmovlhps xmm2,xmm6,xmm4 + vmovsd xmm2,xmm6,xmm4 + vmovss xmm2,xmm6,xmm4 + +# Tests for op imm8, xmm, xmm + vpslld xmm6,xmm4,100 + vpslldq xmm6,xmm4,100 + vpsllq xmm6,xmm4,100 + vpsllw xmm6,xmm4,100 + vpsrad xmm6,xmm4,100 + vpsraw xmm6,xmm4,100 + vpsrld xmm6,xmm4,100 + vpsrldq xmm6,xmm4,100 + vpsrlq xmm6,xmm4,100 + vpsrlw xmm6,xmm4,100 + +# Tests for op imm8, xmm, regl + vpextrw ecx,xmm4,100 + +# Tests for op ymm, regl + vmovmskpd ecx,ymm4 + vmovmskps ecx,ymm4 + +# Tests for op ymm, regq + + +# Default instructions without suffixes. + vcvtpd2dq xmm6,xmm4 + vcvtpd2dq xmm6,ymm4 + vcvtpd2ps xmm6,xmm4 + vcvtpd2ps xmm6,ymm4 + vcvttpd2dq xmm6,xmm4 + vcvttpd2dq xmm6,ymm4 + +#Tests with different memory and register operands. + vldmxcsr DWORD PTR ds:0x1234 + vmovdqa xmm0,XMMWORD PTR ds:0x1234 + vmovdqa XMMWORD PTR ds:0x1234,xmm0 + vmovd DWORD PTR ds:0x1234,xmm0 + vcvtsd2si eax,QWORD PTR ds:0x1234 + vcvtdq2pd ymm0,XMMWORD PTR ds:0x1234 + vcvtpd2ps xmm0,YMMWORD PTR ds:0x1234 + vpavgb xmm7,xmm0,XMMWORD PTR ds:0x1234 + vpextrb ds:0x1234,xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234 + vblendvps xmm6,xmm4,XMMWORD PTR ds:0x1234,xmm0 + vpinsrb xmm7,xmm0,ds:0x1234,100 + vmovdqa ymm0,YMMWORD PTR ds:0x1234 + vmovdqa YMMWORD PTR ds:0x1234,ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR ds:0x1234 + vroundpd ymm0,YMMWORD PTR ds:0x1234,100 + vextractf128 XMMWORD PTR ds:0x1234,ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,100 + vblendvpd ymm6,ymm4,YMMWORD PTR ds:0x1234,ymm0 + vldmxcsr DWORD PTR [ebp] + vmovdqa xmm0,XMMWORD PTR [ebp] + vmovdqa XMMWORD PTR [ebp],xmm0 + vmovd DWORD PTR [ebp],xmm0 + vcvtsd2si eax,QWORD PTR [ebp] + vcvtdq2pd ymm0,XMMWORD PTR [ebp] + vcvtpd2ps xmm0,YMMWORD PTR [ebp] + vpavgb xmm7,xmm0,XMMWORD PTR [ebp] + vpextrb [ebp],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp] + vblendvps xmm6,xmm4,XMMWORD PTR [ebp],xmm0 + vpinsrb xmm7,xmm0,[ebp],100 + vmovdqa ymm0,YMMWORD PTR [ebp] + vmovdqa YMMWORD PTR [ebp],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [ebp] + vroundpd ymm0,YMMWORD PTR [ebp],100 + vextractf128 XMMWORD PTR [ebp],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [ebp],ymm0 + vldmxcsr DWORD PTR [ebp+0x99] + vmovdqa xmm0,XMMWORD PTR [ebp+0x99] + vmovdqa XMMWORD PTR [ebp+0x99],xmm0 + vmovd DWORD PTR [ebp+0x99],xmm0 + vcvtsd2si eax,QWORD PTR [ebp+0x99] + vcvtdq2pd ymm0,XMMWORD PTR [ebp+0x99] + vcvtpd2ps xmm0,YMMWORD PTR [ebp+0x99] + vpavgb xmm7,xmm0,XMMWORD PTR [ebp+0x99] + vpextrb [ebp+0x99],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp+0x99] + vblendvps xmm6,xmm4,XMMWORD PTR [ebp+0x99],xmm0 + vpinsrb xmm7,xmm0,[ebp+0x99],100 + vmovdqa ymm0,YMMWORD PTR [ebp+0x99] + vmovdqa YMMWORD PTR [ebp+0x99],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [ebp+0x99] + vroundpd ymm0,YMMWORD PTR [ebp+0x99],100 + vextractf128 XMMWORD PTR [ebp+0x99],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp+0x99],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [ebp+0x99],ymm0 + vldmxcsr DWORD PTR [eiz*1+0x99] + vmovdqa xmm0,XMMWORD PTR [eiz*1+0x99] + vmovdqa XMMWORD PTR [eiz*1+0x99],xmm0 + vmovd DWORD PTR [eiz*1+0x99],xmm0 + vcvtsd2si eax,QWORD PTR [eiz*1+0x99] + vcvtdq2pd ymm0,XMMWORD PTR [eiz*1+0x99] + vcvtpd2ps xmm0,YMMWORD PTR [eiz*1+0x99] + vpavgb xmm7,xmm0,XMMWORD PTR [eiz*1+0x99] + vpextrb [eiz*1+0x99],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [eiz*1+0x99] + vblendvps xmm6,xmm4,XMMWORD PTR [eiz*1+0x99],xmm0 + vpinsrb xmm7,xmm0,[eiz*1+0x99],100 + vmovdqa ymm0,YMMWORD PTR [eiz*1+0x99] + vmovdqa YMMWORD PTR [eiz*1+0x99],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [eiz*1+0x99] + vroundpd ymm0,YMMWORD PTR [eiz*1+0x99],100 + vextractf128 XMMWORD PTR [eiz*1+0x99],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [eiz*1+0x99],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [eiz*1+0x99],ymm0 + vldmxcsr DWORD PTR [eiz*2+0x99] + vmovdqa xmm0,XMMWORD PTR [eiz*2+0x99] + vmovdqa XMMWORD PTR [eiz*2+0x99],xmm0 + vmovd DWORD PTR [eiz*2+0x99],xmm0 + vcvtsd2si eax,QWORD PTR [eiz*2+0x99] + vcvtdq2pd ymm0,XMMWORD PTR [eiz*2+0x99] + vcvtpd2ps xmm0,YMMWORD PTR [eiz*2+0x99] + vpavgb xmm7,xmm0,XMMWORD PTR [eiz*2+0x99] + vpextrb [eiz*2+0x99],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [eiz*2+0x99] + vblendvps xmm6,xmm4,XMMWORD PTR [eiz*2+0x99],xmm0 + vpinsrb xmm7,xmm0,[eiz*2+0x99],100 + vmovdqa ymm0,YMMWORD PTR [eiz*2+0x99] + vmovdqa YMMWORD PTR [eiz*2+0x99],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [eiz*2+0x99] + vroundpd ymm0,YMMWORD PTR [eiz*2+0x99],100 + vextractf128 XMMWORD PTR [eiz*2+0x99],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [eiz*2+0x99],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [eiz*2+0x99],ymm0 + vldmxcsr DWORD PTR [eax+eiz*1+0x99] + vmovdqa xmm0,XMMWORD PTR [eax+eiz*1+0x99] + vmovdqa XMMWORD PTR [eax+eiz*1+0x99],xmm0 + vmovd DWORD PTR [eax+eiz*1+0x99],xmm0 + vcvtsd2si eax,QWORD PTR [eax+eiz*1+0x99] + vcvtdq2pd ymm0,XMMWORD PTR [eax+eiz*1+0x99] + vcvtpd2ps xmm0,YMMWORD PTR [eax+eiz*1+0x99] + vpavgb xmm7,xmm0,XMMWORD PTR [eax+eiz*1+0x99] + vpextrb [eax+eiz*1+0x99],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+eiz*1+0x99] + vblendvps xmm6,xmm4,XMMWORD PTR [eax+eiz*1+0x99],xmm0 + vpinsrb xmm7,xmm0,[eax+eiz*1+0x99],100 + vmovdqa ymm0,YMMWORD PTR [eax+eiz*1+0x99] + vmovdqa YMMWORD PTR [eax+eiz*1+0x99],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [eax+eiz*1+0x99] + vroundpd ymm0,YMMWORD PTR [eax+eiz*1+0x99],100 + vextractf128 XMMWORD PTR [eax+eiz*1+0x99],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+eiz*1+0x99],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [eax+eiz*1+0x99],ymm0 + vldmxcsr DWORD PTR [eax+eiz*2+0x99] + vmovdqa xmm0,XMMWORD PTR [eax+eiz*2+0x99] + vmovdqa XMMWORD PTR [eax+eiz*2+0x99],xmm0 + vmovd DWORD PTR [eax+eiz*2+0x99],xmm0 + vcvtsd2si eax,QWORD PTR [eax+eiz*2+0x99] + vcvtdq2pd ymm0,XMMWORD PTR [eax+eiz*2+0x99] + vcvtpd2ps xmm0,YMMWORD PTR [eax+eiz*2+0x99] + vpavgb xmm7,xmm0,XMMWORD PTR [eax+eiz*2+0x99] + vpextrb [eax+eiz*2+0x99],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+eiz*2+0x99] + vblendvps xmm6,xmm4,XMMWORD PTR [eax+eiz*2+0x99],xmm0 + vpinsrb xmm7,xmm0,[eax+eiz*2+0x99],100 + vmovdqa ymm0,YMMWORD PTR [eax+eiz*2+0x99] + vmovdqa YMMWORD PTR [eax+eiz*2+0x99],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [eax+eiz*2+0x99] + vroundpd ymm0,YMMWORD PTR [eax+eiz*2+0x99],100 + vextractf128 XMMWORD PTR [eax+eiz*2+0x99],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+eiz*2+0x99],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [eax+eiz*2+0x99],ymm0 + vldmxcsr DWORD PTR [eax+ebx*4+0x99] + vmovdqa xmm0,XMMWORD PTR [eax+ebx*4+0x99] + vmovdqa XMMWORD PTR [eax+ebx*4+0x99],xmm0 + vmovd DWORD PTR [eax+ebx*4+0x99],xmm0 + vcvtsd2si eax,QWORD PTR [eax+ebx*4+0x99] + vcvtdq2pd ymm0,XMMWORD PTR [eax+ebx*4+0x99] + vcvtpd2ps xmm0,YMMWORD PTR [eax+ebx*4+0x99] + vpavgb xmm7,xmm0,XMMWORD PTR [eax+ebx*4+0x99] + vpextrb [eax+ebx*4+0x99],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+ebx*4+0x99] + vblendvps xmm6,xmm4,XMMWORD PTR [eax+ebx*4+0x99],xmm0 + vpinsrb xmm7,xmm0,[eax+ebx*4+0x99],100 + vmovdqa ymm0,YMMWORD PTR [eax+ebx*4+0x99] + vmovdqa YMMWORD PTR [eax+ebx*4+0x99],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [eax+ebx*4+0x99] + vroundpd ymm0,YMMWORD PTR [eax+ebx*4+0x99],100 + vextractf128 XMMWORD PTR [eax+ebx*4+0x99],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+ebx*4+0x99],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [eax+ebx*4+0x99],ymm0 + vldmxcsr DWORD PTR [esp+ecx*8+0x99] + vmovdqa xmm0,XMMWORD PTR [esp+ecx*8+0x99] + vmovdqa XMMWORD PTR [esp+ecx*8+0x99],xmm0 + vmovd DWORD PTR [esp+ecx*8+0x99],xmm0 + vcvtsd2si eax,QWORD PTR [esp+ecx*8+0x99] + vcvtdq2pd ymm0,XMMWORD PTR [esp+ecx*8+0x99] + vcvtpd2ps xmm0,YMMWORD PTR [esp+ecx*8+0x99] + vpavgb xmm7,xmm0,XMMWORD PTR [esp+ecx*8+0x99] + vpextrb [esp+ecx*8+0x99],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [esp+ecx*8+0x99] + vblendvps xmm6,xmm4,XMMWORD PTR [esp+ecx*8+0x99],xmm0 + vpinsrb xmm7,xmm0,[esp+ecx*8+0x99],100 + vmovdqa ymm0,YMMWORD PTR [esp+ecx*8+0x99] + vmovdqa YMMWORD PTR [esp+ecx*8+0x99],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [esp+ecx*8+0x99] + vroundpd ymm0,YMMWORD PTR [esp+ecx*8+0x99],100 + vextractf128 XMMWORD PTR [esp+ecx*8+0x99],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [esp+ecx*8+0x99],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [esp+ecx*8+0x99],ymm0 + vldmxcsr DWORD PTR [ebp+edx*1+0x99] + vmovdqa xmm0,XMMWORD PTR [ebp+edx*1+0x99] + vmovdqa XMMWORD PTR [ebp+edx*1+0x99],xmm0 + vmovd DWORD PTR [ebp+edx*1+0x99],xmm0 + vcvtsd2si eax,QWORD PTR [ebp+edx*1+0x99] + vcvtdq2pd ymm0,XMMWORD PTR [ebp+edx*1+0x99] + vcvtpd2ps xmm0,YMMWORD PTR [ebp+edx*1+0x99] + vpavgb xmm7,xmm0,XMMWORD PTR [ebp+edx*1+0x99] + vpextrb [ebp+edx*1+0x99],xmm0,100 + vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp+edx*1+0x99] + vblendvps xmm6,xmm4,XMMWORD PTR [ebp+edx*1+0x99],xmm0 + vpinsrb xmm7,xmm0,[ebp+edx*1+0x99],100 + vmovdqa ymm0,YMMWORD PTR [ebp+edx*1+0x99] + vmovdqa YMMWORD PTR [ebp+edx*1+0x99],ymm0 + vpermilpd ymm7,ymm0,YMMWORD PTR [ebp+edx*1+0x99] + vroundpd ymm0,YMMWORD PTR [ebp+edx*1+0x99],100 + vextractf128 XMMWORD PTR [ebp+edx*1+0x99],ymm0,100 + vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp+edx*1+0x99],100 + vblendvpd ymm6,ymm4,YMMWORD PTR [ebp+edx*1+0x99],ymm0 +# Tests for all register operands. + vmovmskpd eax,xmm0 + vpslld xmm7,xmm0,100 + vmovmskps eax,ymm0 diff --git a/gas/testsuite/gas/i386/clmul-intel.d b/gas/testsuite/gas/i386/clmul-intel.d new file mode 100644 index 0000000..cd29bb4 --- /dev/null +++ b/gas/testsuite/gas/i386/clmul-intel.d @@ -0,0 +1,30 @@ +#source: clmul.s +#objdump: -dw -Mintel +#name: i386 CLMUL (Intel mode) + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq xmm0,XMMWORD PTR \[ecx\],0x8 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq xmm0,xmm1,0x8 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq xmm0,XMMWORD PTR \[ecx\],0x8 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq xmm0,xmm1,0x8 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq xmm0,XMMWORD PTR \[ecx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq xmm0,xmm1 +#pass diff --git a/gas/testsuite/gas/i386/clmul.d b/gas/testsuite/gas/i386/clmul.d new file mode 100644 index 0000000..be1a549 --- /dev/null +++ b/gas/testsuite/gas/i386/clmul.d @@ -0,0 +1,29 @@ +#objdump: -dw +#name: i386 CLMUL + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq \$0x8,\(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq \$0x8,\(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq %xmm1,%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/clmul.s b/gas/testsuite/gas/i386/clmul.s new file mode 100644 index 0000000..b77d558 --- /dev/null +++ b/gas/testsuite/gas/i386/clmul.s @@ -0,0 +1,26 @@ +# Check CLMUL new instructions. + + .text +foo: + pclmulqdq $8,(%ecx),%xmm0 + pclmulqdq $8,%xmm1,%xmm0 + pclmullqlqdq (%ecx),%xmm0 + pclmullqlqdq %xmm1,%xmm0 + pclmulhqlqdq (%ecx),%xmm0 + pclmulhqlqdq %xmm1,%xmm0 + pclmullqhqdq (%ecx),%xmm0 + pclmullqhqdq %xmm1,%xmm0 + pclmulhqhqdq (%ecx),%xmm0 + pclmulhqhqdq %xmm1,%xmm0 + + .intel_syntax noprefix + pclmulqdq xmm0,XMMWORD PTR [ecx],8 + pclmulqdq xmm0,xmm1,8 + pclmullqlqdq xmm0,XMMWORD PTR [ecx] + pclmullqlqdq xmm0,xmm1 + pclmulhqlqdq xmm0,XMMWORD PTR [ecx] + pclmulhqlqdq xmm0,xmm1 + pclmullqhqdq xmm0,XMMWORD PTR [ecx] + pclmullqhqdq xmm0,xmm1 + pclmulhqhqdq xmm0,XMMWORD PTR [ecx] + pclmulhqhqdq xmm0,xmm1 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 30459e9..4111fe5 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -116,6 +116,14 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "arch-12" run_dump_test "xsave" run_dump_test "xsave-intel" + run_dump_test "aes" + run_dump_test "aes-intel" + run_dump_test "clmul" + run_dump_test "clmul-intel" + run_dump_test "avx" + run_dump_test "avx-intel" + run_dump_test "sse2avx" + run_list_test "inval-avx" "-al" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. @@ -234,6 +242,14 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-arch-2" run_dump_test "x86-64-xsave" run_dump_test "x86-64-xsave-intel" + run_dump_test "x86-64-aes" + run_dump_test "x86-64-aes-intel" + run_dump_test "x86-64-clmul" + run_dump_test "x86-64-clmul-intel" + run_dump_test "x86-64-avx" + run_dump_test "x86-64-avx-intel" + run_dump_test "x86-64-sse2avx" + run_list_test "x86-64-inval-avx" "-al" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/inval-avx.l b/gas/testsuite/gas/i386/inval-avx.l new file mode 100644 index 0000000..796b1e4 --- /dev/null +++ b/gas/testsuite/gas/i386/inval-avx.l @@ -0,0 +1,109 @@ +.*: Assembler messages: +.*:4: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* +.*:10: Error: .* +.*:11: Error: .* +.*:12: Error: .* +.*:13: Error: .* +.*:14: Error: .* +.*:15: Error: .* +.*:16: Error: .* +.*:17: Error: .* +.*:18: Error: .* +.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* +.*:22: Error: .* +.*:23: Error: .* +.*:24: Error: .* +.*:25: Error: .* +.*:26: Error: .* +.*:27: Error: .* +.*:28: Error: .* +.*:31: Error: .* +.*:32: Error: .* +.*:33: Error: .* +.*:34: Error: .* +.*:35: Error: .* +.*:36: Error: .* +.*:37: Error: .* +.*:38: Error: .* +.*:39: Error: .* +.*:40: Error: .* +.*:41: Error: .* +.*:42: Error: .* +.*:43: Error: .* +.*:44: Error: .* +.*:45: Error: .* +.*:46: Error: .* +.*:47: Error: .* +.*:48: Error: .* +.*:49: Error: .* +.*:50: Error: .* +.*:51: Error: .* +.*:52: Error: .* +.*:53: Error: .* +.*:54: Error: .* +.*:55: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\# Check illegal AVX instructions +[ ]*2[ ]+\.text +[ ]*3[ ]+_start: +[ ]*4[ ]+vcvtpd2dq \(%ecx\),%xmm2 +[ ]*5[ ]+vcvtpd2ps \(%ecx\),%xmm2 +[ ]*6[ ]+vcvttpd2dq \(%ecx\),%xmm2 +[ ]*7[ ]+vfmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*8[ ]+vfmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*9[ ]+vfmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*10[ ]+vfmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*11[ ]+vfmaddsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*12[ ]+vfmaddsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*13[ ]+vfmsubaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*14[ ]+vfmsubaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*15[ ]+vfmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*16[ ]+vfmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*17[ ]+vfmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*18[ ]+vfmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*19[ ]+vfnmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*20[ ]+vfnmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*21[ ]+vfnmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*22[ ]+vfnmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*23[ ]+vfnmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*24[ ]+vfnmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*25[ ]+vfnmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*26[ ]+vfnmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*27[ ]+vpermil2pd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*28[ ]+vpermil2ps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*29[ ]+ +[ ]*30[ ]+\.intel_syntax noprefix +[ ]*31[ ]+vcvtpd2dq xmm2,\[ecx\] +[ ]*32[ ]+vcvtpd2ps xmm2,\[ecx\] +[ ]*33[ ]+vcvttpd2dq xmm2,\[ecx\] +[ ]*34[ ]+vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*35[ ]+vfmaddps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*36[ ]+vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*37[ ]+vfmaddss xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*38[ ]+vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*39[ ]+vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*40[ ]+vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*41[ ]+vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*42[ ]+vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*43[ ]+vfmsubps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*44[ ]+vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*45[ ]+vfmsubss xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*46[ ]+vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*47[ ]+vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*48[ ]+vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*49[ ]+vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*50[ ]+vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*51[ ]+vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*52[ ]+vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*53[ ]+vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*54[ ]+vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*55[ ]+vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10 diff --git a/gas/testsuite/gas/i386/inval-avx.s b/gas/testsuite/gas/i386/inval-avx.s new file mode 100644 index 0000000..bf42a8d --- /dev/null +++ b/gas/testsuite/gas/i386/inval-avx.s @@ -0,0 +1,55 @@ +# Check illegal AVX instructions + .text +_start: + vcvtpd2dq (%ecx),%xmm2 + vcvtpd2ps (%ecx),%xmm2 + vcvttpd2dq (%ecx),%xmm2 + vfmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddsubps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubaddps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3 + vpermil2pd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vpermil2ps $17,%xmm4,%xmm2,%xmm1,%xmm3 + + .intel_syntax noprefix + vcvtpd2dq xmm2,[ecx] + vcvtpd2ps xmm2,[ecx] + vcvttpd2dq xmm2,[ecx] + vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddps xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddss xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubps xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubss xmm3,xmm1,xmm2,xmm4,0x10 + vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10 + vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10 + vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10 + vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10 + vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10 + vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10 + vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10 + vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10 + vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10 + vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10 diff --git a/gas/testsuite/gas/i386/rexw.d b/gas/testsuite/gas/i386/rexw.d index acd3056..84240f3 100644 --- a/gas/testsuite/gas/i386/rexw.d +++ b/gas/testsuite/gas/i386/rexw.d @@ -17,6 +17,14 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f c4 c1 00 pinsrw \$0x0,%ecx,%mm0 [ ]*[a-f0-9]+: 0f d7 c5 pmovmskb %mm5,%eax [ ]*[a-f0-9]+: 66 0f d7 c5 pmovmskb %xmm5,%eax +[ ]*[a-f0-9]+: c4 e3 79 17 c1 00 vextractps \$0x0,%xmm0,%ecx +[ ]*[a-f0-9]+: c5 f9 50 ca vmovmskpd %xmm2,%ecx +[ ]*[a-f0-9]+: c5 f8 50 ca vmovmskps %xmm2,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 c1 00 vpextrb \$0x0,%xmm0,%ecx +[ ]*[a-f0-9]+: c5 f9 c5 c8 00 vpextrw \$0x0,%xmm0,%ecx +[ ]*[a-f0-9]+: c4 e3 79 20 c1 00 vpinsrb \$0x0,%ecx,%xmm0,%xmm0 +[ ]*[a-f0-9]+: c5 f9 c4 c1 00 vpinsrw \$0x0,%ecx,%xmm0,%xmm0 +[ ]*[a-f0-9]+: c5 f9 d7 c5 vpmovmskb %xmm5,%eax [ ]*[a-f0-9]+: 66 0f 3a 17 c1 00 extractps \$0x0,%xmm0,%ecx [ ]*[a-f0-9]+: 66 0f 50 ca movmskpd %xmm2,%ecx [ ]*[a-f0-9]+: 0f 50 ca movmskps %xmm2,%ecx @@ -28,4 +36,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f c4 c1 00 pinsrw \$0x0,%ecx,%xmm0 [ ]*[a-f0-9]+: 0f d7 cd pmovmskb %mm5,%ecx [ ]*[a-f0-9]+: 66 0f d7 cd pmovmskb %xmm5,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 c1 00 vextractps \$0x0,%xmm0,%ecx +[ ]*[a-f0-9]+: c5 f9 50 ca vmovmskpd %xmm2,%ecx +[ ]*[a-f0-9]+: c5 f8 50 ca vmovmskps %xmm2,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 c1 00 vpextrb \$0x0,%xmm0,%ecx +[ ]*[a-f0-9]+: c5 f9 c5 c8 00 vpextrw \$0x0,%xmm0,%ecx +[ ]*[a-f0-9]+: c4 e3 79 20 c1 00 vpinsrb \$0x0,%ecx,%xmm0,%xmm0 +[ ]*[a-f0-9]+: c5 f9 c4 c1 00 vpinsrw \$0x0,%ecx,%xmm0,%xmm0 +[ ]*[a-f0-9]+: c5 f9 d7 cd vpmovmskb %xmm5,%ecx #pass diff --git a/gas/testsuite/gas/i386/rexw.s b/gas/testsuite/gas/i386/rexw.s index 882273d..0c931c7 100644 --- a/gas/testsuite/gas/i386/rexw.s +++ b/gas/testsuite/gas/i386/rexw.s @@ -14,6 +14,16 @@ foo: pmovmskb %mm5,%rax pmovmskb %xmm5,%rax +# AVX instructions + vextractps $0x0,%xmm0,%rcx + vmovmskpd %xmm2,%rcx + vmovmskps %xmm2,%rcx + vpextrb $0x0,%xmm0,%rcx + vpextrw $0x0,%xmm0,%rcx + vpinsrb $0x0,%rcx,%xmm0,%xmm0 + vpinsrw $0x0,%rcx,%xmm0,%xmm0 + vpmovmskb %xmm5,%rax + .intel_syntax noprefix extractps rcx,xmm0,0x0 movmskpd rcx,xmm2 @@ -26,3 +36,13 @@ foo: pinsrw xmm0,rcx,0x0 pmovmskb rcx,mm5 pmovmskb rcx,xmm5 + +# AVX instructions + vextractps rcx,xmm0,0x0 + vmovmskpd rcx,xmm2 + vmovmskps rcx,xmm2 + vpextrb rcx,xmm0,0x0 + vpextrw rcx,xmm0,0x0 + vpinsrb xmm0,xmm0,rcx,0x0 + vpinsrw xmm0,xmm0,rcx,0x0 + vpmovmskb rcx,xmm5 diff --git a/gas/testsuite/gas/i386/sse2avx.d b/gas/testsuite/gas/i386/sse2avx.d new file mode 100644 index 0000000..ecca20e --- /dev/null +++ b/gas/testsuite/gas/i386/sse2avx.d @@ -0,0 +1,566 @@ +#as: -msse2avx +#objdump: -dw +#name: i386 SSE with AVX encoding + +.*: file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\) +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%ecx\) +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dqx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2psx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dqx \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 c9 58 f4 vaddpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 58 31 vaddpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 58 f4 vaddps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 58 31 vaddps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d0 f4 vaddsubpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d0 31 vaddsubpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb d0 f4 vaddsubps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb d0 31 vaddsubps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 55 f4 vandnpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 55 31 vandnpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 55 f4 vandnps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 55 31 vandnps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 54 f4 vandpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 54 31 vandpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 54 f4 vandps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 54 31 vandps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5e f4 vdivpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5e 31 vdivpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5e f4 vdivps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5e 31 vdivps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 7c f4 vhaddpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 7c 31 vhaddpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 7c f4 vhaddps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 7c 31 vhaddps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 7d f4 vhsubpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 7d 31 vhsubpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 7d f4 vhsubps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 7d 31 vhsubps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5f f4 vmaxpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5f 31 vmaxpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5f f4 vmaxps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5f 31 vmaxps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5d f4 vminpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5d 31 vminpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5d f4 vminps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5d 31 vminps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 59 f4 vmulpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 59 31 vmulpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 59 f4 vmulps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 59 31 vmulps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 56 f4 vorpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 56 31 vorpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 56 f4 vorps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 56 31 vorps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 63 f4 vpacksswb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 63 31 vpacksswb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6b f4 vpackssdw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6b 31 vpackssdw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 67 f4 vpackuswb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 67 31 vpackuswb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 2b f4 vpackusdw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 2b 31 vpackusdw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fc f4 vpaddb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fc 31 vpaddb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fd f4 vpaddw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fd 31 vpaddw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fe f4 vpaddd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fe 31 vpaddd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d4 f4 vpaddq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d4 31 vpaddq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ec f4 vpaddsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ec 31 vpaddsb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ed f4 vpaddsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ed 31 vpaddsw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 dc f4 vpaddusb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 dc 31 vpaddusb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 dd f4 vpaddusw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 dd 31 vpaddusw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 db f4 vpand %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 db 31 vpand \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 df f4 vpandn %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 df 31 vpandn \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e0 f4 vpavgb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e0 31 vpavgb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e3 f4 vpavgw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e3 31 vpavgw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 74 f4 vpcmpeqb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 74 31 vpcmpeqb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 75 f4 vpcmpeqw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 75 31 vpcmpeqw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 76 f4 vpcmpeqd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 76 31 vpcmpeqd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 29 f4 vpcmpeqq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 29 31 vpcmpeqq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 64 f4 vpcmpgtb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 64 31 vpcmpgtb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 65 f4 vpcmpgtw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 65 31 vpcmpgtw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 66 f4 vpcmpgtd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 66 31 vpcmpgtd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 37 f4 vpcmpgtq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 37 31 vpcmpgtq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 01 f4 vphaddw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 01 31 vphaddw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 02 f4 vphaddd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 02 31 vphaddd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 03 f4 vphaddsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 03 31 vphaddsw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 05 f4 vphsubw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 05 31 vphsubw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 06 f4 vphsubd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 06 31 vphsubd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 07 f4 vphsubsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 07 31 vphsubsw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f5 f4 vpmaddwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f5 31 vpmaddwd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 04 f4 vpmaddubsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 04 31 vpmaddubsw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3c f4 vpmaxsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3c 31 vpmaxsb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ee f4 vpmaxsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ee 31 vpmaxsw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3d f4 vpmaxsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3d 31 vpmaxsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 de f4 vpmaxub %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 de 31 vpmaxub \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3e f4 vpmaxuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3e 31 vpmaxuw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3f f4 vpmaxud %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3f 31 vpmaxud \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 38 f4 vpminsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 38 31 vpminsb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ea f4 vpminsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ea 31 vpminsw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 39 f4 vpminsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 39 31 vpminsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 da f4 vpminub %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 da 31 vpminub \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3a f4 vpminuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3a 31 vpminuw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3b f4 vpminud %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3b 31 vpminud \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e4 f4 vpmulhuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e4 31 vpmulhuw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 0b f4 vpmulhrsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 0b 31 vpmulhrsw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e5 f4 vpmulhw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e5 31 vpmulhw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d5 f4 vpmullw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d5 31 vpmullw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 40 f4 vpmulld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 40 31 vpmulld \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f4 f4 vpmuludq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f4 31 vpmuludq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 28 f4 vpmuldq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 28 31 vpmuldq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 eb f4 vpor %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 eb 31 vpor \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f6 f4 vpsadbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f6 31 vpsadbw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 00 f4 vpshufb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 00 31 vpshufb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 08 f4 vpsignb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 08 31 vpsignb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 09 f4 vpsignw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 09 31 vpsignw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 0a f4 vpsignd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 0a 31 vpsignd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f1 f4 vpsllw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f1 31 vpsllw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f2 f4 vpslld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f2 31 vpslld \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f3 f4 vpsllq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f3 31 vpsllq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e1 f4 vpsraw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e1 31 vpsraw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e2 f4 vpsrad %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e2 31 vpsrad \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d1 f4 vpsrlw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d1 31 vpsrlw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d2 f4 vpsrld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d2 31 vpsrld \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d3 f4 vpsrlq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d3 31 vpsrlq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f8 f4 vpsubb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f8 31 vpsubb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f9 f4 vpsubw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f9 31 vpsubw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fa f4 vpsubd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fa 31 vpsubd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fb f4 vpsubq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fb 31 vpsubq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e8 f4 vpsubsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e8 31 vpsubsb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e9 f4 vpsubsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e9 31 vpsubsw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d8 f4 vpsubusb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d8 31 vpsubusb \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d9 f4 vpsubusw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d9 31 vpsubusw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 68 f4 vpunpckhbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 68 31 vpunpckhbw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 69 f4 vpunpckhwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 69 31 vpunpckhwd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6a f4 vpunpckhdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6a 31 vpunpckhdq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6d f4 vpunpckhqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6d 31 vpunpckhqdq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 60 f4 vpunpcklbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 60 31 vpunpcklbw \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 61 f4 vpunpcklwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 61 31 vpunpcklwd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 62 f4 vpunpckldq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 62 31 vpunpckldq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6c f4 vpunpcklqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6c 31 vpunpcklqdq \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ef f4 vpxor %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ef 31 vpxor \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5c f4 vsubpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5c 31 vsubpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5c f4 vsubps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5c 31 vsubps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 15 f4 vunpckhpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 15 31 vunpckhpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 15 f4 vunpckhps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 15 31 vunpckhps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 14 f4 vunpcklpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 14 31 vunpcklpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 14 f4 vunpcklps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 14 31 vunpcklps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 57 f4 vxorpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 57 31 vxorpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 57 f4 vxorps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 57 31 vxorps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 00 vcmpeqpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 00 vcmpeqpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 00 vcmpeqps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 00 vcmpeqps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 01 vcmpltpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 01 vcmpltpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 01 vcmpltps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 01 vcmpltps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 02 vcmplepd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 02 vcmplepd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 02 vcmpleps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 02 vcmpleps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 03 vcmpunordpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 03 vcmpunordpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 03 vcmpunordps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 03 vcmpunordps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 04 vcmpneqpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 04 vcmpneqpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 04 vcmpneqps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 04 vcmpneqps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 05 vcmpnltpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 05 vcmpnltpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 05 vcmpnltps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 05 vcmpnltps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 06 vcmpnlepd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 06 vcmpnlepd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 06 vcmpnleps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 06 vcmpnleps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 07 vcmpordpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 07 vcmpordpd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 07 vcmpordps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 07 vcmpordps \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%ecx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0d f4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0d 31 64 vblendpd \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0c f4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0c 31 64 vblendps \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 64 vcmppd \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 64 vcmpps \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 41 f4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 41 31 64 vdppd \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 40 f4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 40 31 64 vdpps \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 42 f4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 42 31 64 vmpsadbw \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0f f4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0f 31 64 vpalignr \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0e f4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0e 31 64 vpblendw \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c6 f4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c6 31 64 vshufpd \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c6 f4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c6 31 64 vshufps \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4b f4 00 vblendvpd %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4b 31 00 vblendvpd %xmm0,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4b f4 00 vblendvpd %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4b 31 00 vblendvpd %xmm0,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4a f4 00 vblendvps %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4a 31 00 vblendvps %xmm0,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4a f4 00 vblendvps %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4a 31 00 vblendvps %xmm0,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 d9 12 21 vmovlpd \(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d8 12 21 vmovlps \(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 16 21 vmovhpd \(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d8 16 21 vmovhps \(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 cb c2 f4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 64 vcmpsd \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0b f4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0b 31 64 vroundsd \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 58 f4 vaddsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 58 31 vaddsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5a f4 vcvtsd2ss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5a 31 vcvtsd2ss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5e f4 vdivsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5e 31 vdivsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5f f4 vmaxsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5f 31 vmaxsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5d f4 vminsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5d 31 vminsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 59 f4 vmulsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 59 31 vmulsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 51 f4 vsqrtsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 51 31 vsqrtsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5c f4 vsubsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5c 31 vsubsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 00 vcmpeqsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 00 vcmpeqsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 01 vcmpltsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 01 vcmpltsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 02 vcmplesd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 02 vcmplesd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 03 vcmpunordsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 03 vcmpunordsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 04 vcmpneqsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 04 vcmpneqsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 05 vcmpnltsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 05 vcmpnltsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 06 vcmpnlesd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 06 vcmpnlesd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 07 vcmpordsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 07 vcmpordsd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 58 f4 vaddss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 58 31 vaddss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5a f4 vcvtss2sd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5a 31 vcvtss2sd \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5e f4 vdivss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5e 31 vdivss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5f f4 vmaxss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5f 31 vmaxss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5d f4 vminss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5d 31 vminss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 59 f4 vmulss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 59 31 vmulss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 53 f4 vrcpss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 53 31 vrcpss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 52 f4 vrsqrtss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 52 31 vrsqrtss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 51 f4 vsqrtss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 51 31 vsqrtss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5c f4 vsubss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5c 31 vsubss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 00 vcmpeqss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 00 vcmpeqss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 01 vcmpltss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 01 vcmpltss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 02 vcmpless %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 02 vcmpless \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 03 vcmpunordss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 03 vcmpunordss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 04 vcmpneqss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 04 vcmpneqss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 05 vcmpnltss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 05 vcmpnltss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 06 vcmpnless %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 06 vcmpnless \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 07 vcmpordss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 07 vcmpordss \(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%ecx\),%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 db 2a e1 vcvtsi2sd %ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 db 2a 21 vcvtsi2sdl \(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 da 2a e1 vcvtsi2ss %ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 da 2a 21 vcvtsi2ssl \(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 ca c2 f4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 64 vcmpss \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 21 f4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 21 31 64 vinsertps \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0a f4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0a 31 64 vroundss \$0x64,\(%ecx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%ecx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c5 d9 c4 e1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 c4 21 64 vpinsrw \$0x64,\(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 59 20 e1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 59 20 21 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\) +[ ]*[a-f0-9]+: c4 e3 59 20 e1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 59 20 21 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c5 c8 12 f4 vmovhlps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 16 f4 vmovlhps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 d9 72 f4 64 vpslld \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +#pass diff --git a/gas/testsuite/gas/i386/sse2avx.s b/gas/testsuite/gas/i386/sse2avx.s new file mode 100644 index 0000000..1dccd94 --- /dev/null +++ b/gas/testsuite/gas/i386/sse2avx.s @@ -0,0 +1,642 @@ +# Check SSE to AVX instructions + + .allow_index_reg + .text +_start: +# Tests for op mem64 + ldmxcsr (%ecx) + stmxcsr (%ecx) + +# Tests for op xmm/mem128, xmm + cvtdq2ps %xmm4,%xmm6 + cvtdq2ps (%ecx),%xmm4 + cvtpd2dq %xmm4,%xmm6 + cvtpd2dq (%ecx),%xmm4 + cvtpd2ps %xmm4,%xmm6 + cvtpd2ps (%ecx),%xmm4 + cvtps2dq %xmm4,%xmm6 + cvtps2dq (%ecx),%xmm4 + cvttpd2dq %xmm4,%xmm6 + cvttpd2dq (%ecx),%xmm4 + cvttps2dq %xmm4,%xmm6 + cvttps2dq (%ecx),%xmm4 + movapd %xmm4,%xmm6 + movapd (%ecx),%xmm4 + movaps %xmm4,%xmm6 + movaps (%ecx),%xmm4 + movdqa %xmm4,%xmm6 + movdqa (%ecx),%xmm4 + movdqu %xmm4,%xmm6 + movdqu (%ecx),%xmm4 + movshdup %xmm4,%xmm6 + movshdup (%ecx),%xmm4 + movsldup %xmm4,%xmm6 + movsldup (%ecx),%xmm4 + movupd %xmm4,%xmm6 + movupd (%ecx),%xmm4 + movups %xmm4,%xmm6 + movups (%ecx),%xmm4 + pabsb %xmm4,%xmm6 + pabsb (%ecx),%xmm4 + pabsw %xmm4,%xmm6 + pabsw (%ecx),%xmm4 + pabsd %xmm4,%xmm6 + pabsd (%ecx),%xmm4 + phminposuw %xmm4,%xmm6 + phminposuw (%ecx),%xmm4 + ptest %xmm4,%xmm6 + ptest (%ecx),%xmm4 + rcpps %xmm4,%xmm6 + rcpps (%ecx),%xmm4 + rsqrtps %xmm4,%xmm6 + rsqrtps (%ecx),%xmm4 + sqrtpd %xmm4,%xmm6 + sqrtpd (%ecx),%xmm4 + sqrtps %xmm4,%xmm6 + sqrtps (%ecx),%xmm4 + +# Tests for op xmm, xmm/mem128 + movapd %xmm4,%xmm6 + movapd %xmm4,(%ecx) + movaps %xmm4,%xmm6 + movaps %xmm4,(%ecx) + movdqa %xmm4,%xmm6 + movdqa %xmm4,(%ecx) + movdqu %xmm4,%xmm6 + movdqu %xmm4,(%ecx) + movupd %xmm4,%xmm6 + movupd %xmm4,(%ecx) + movups %xmm4,%xmm6 + movups %xmm4,(%ecx) + +# Tests for op mem128, xmm + lddqu (%ecx),%xmm4 + movntdqa (%ecx),%xmm4 + +# Tests for op xmm, mem128 + movntdq %xmm4,(%ecx) + movntpd %xmm4,(%ecx) + movntps %xmm4,(%ecx) + +# Tests for op xmm/mem128, xmm[, xmm] + addpd %xmm4,%xmm6 + addpd (%ecx),%xmm6 + addps %xmm4,%xmm6 + addps (%ecx),%xmm6 + addsubpd %xmm4,%xmm6 + addsubpd (%ecx),%xmm6 + addsubps %xmm4,%xmm6 + addsubps (%ecx),%xmm6 + andnpd %xmm4,%xmm6 + andnpd (%ecx),%xmm6 + andnps %xmm4,%xmm6 + andnps (%ecx),%xmm6 + andpd %xmm4,%xmm6 + andpd (%ecx),%xmm6 + andps %xmm4,%xmm6 + andps (%ecx),%xmm6 + divpd %xmm4,%xmm6 + divpd (%ecx),%xmm6 + divps %xmm4,%xmm6 + divps (%ecx),%xmm6 + haddpd %xmm4,%xmm6 + haddpd (%ecx),%xmm6 + haddps %xmm4,%xmm6 + haddps (%ecx),%xmm6 + hsubpd %xmm4,%xmm6 + hsubpd (%ecx),%xmm6 + hsubps %xmm4,%xmm6 + hsubps (%ecx),%xmm6 + maxpd %xmm4,%xmm6 + maxpd (%ecx),%xmm6 + maxps %xmm4,%xmm6 + maxps (%ecx),%xmm6 + minpd %xmm4,%xmm6 + minpd (%ecx),%xmm6 + minps %xmm4,%xmm6 + minps (%ecx),%xmm6 + mulpd %xmm4,%xmm6 + mulpd (%ecx),%xmm6 + mulps %xmm4,%xmm6 + mulps (%ecx),%xmm6 + orpd %xmm4,%xmm6 + orpd (%ecx),%xmm6 + orps %xmm4,%xmm6 + orps (%ecx),%xmm6 + packsswb %xmm4,%xmm6 + packsswb (%ecx),%xmm6 + packssdw %xmm4,%xmm6 + packssdw (%ecx),%xmm6 + packuswb %xmm4,%xmm6 + packuswb (%ecx),%xmm6 + packusdw %xmm4,%xmm6 + packusdw (%ecx),%xmm6 + paddb %xmm4,%xmm6 + paddb (%ecx),%xmm6 + paddw %xmm4,%xmm6 + paddw (%ecx),%xmm6 + paddd %xmm4,%xmm6 + paddd (%ecx),%xmm6 + paddq %xmm4,%xmm6 + paddq (%ecx),%xmm6 + paddsb %xmm4,%xmm6 + paddsb (%ecx),%xmm6 + paddsw %xmm4,%xmm6 + paddsw (%ecx),%xmm6 + paddusb %xmm4,%xmm6 + paddusb (%ecx),%xmm6 + paddusw %xmm4,%xmm6 + paddusw (%ecx),%xmm6 + pand %xmm4,%xmm6 + pand (%ecx),%xmm6 + pandn %xmm4,%xmm6 + pandn (%ecx),%xmm6 + pavgb %xmm4,%xmm6 + pavgb (%ecx),%xmm6 + pavgw %xmm4,%xmm6 + pavgw (%ecx),%xmm6 + pcmpeqb %xmm4,%xmm6 + pcmpeqb (%ecx),%xmm6 + pcmpeqw %xmm4,%xmm6 + pcmpeqw (%ecx),%xmm6 + pcmpeqd %xmm4,%xmm6 + pcmpeqd (%ecx),%xmm6 + pcmpeqq %xmm4,%xmm6 + pcmpeqq (%ecx),%xmm6 + pcmpgtb %xmm4,%xmm6 + pcmpgtb (%ecx),%xmm6 + pcmpgtw %xmm4,%xmm6 + pcmpgtw (%ecx),%xmm6 + pcmpgtd %xmm4,%xmm6 + pcmpgtd (%ecx),%xmm6 + pcmpgtq %xmm4,%xmm6 + pcmpgtq (%ecx),%xmm6 + phaddw %xmm4,%xmm6 + phaddw (%ecx),%xmm6 + phaddd %xmm4,%xmm6 + phaddd (%ecx),%xmm6 + phaddsw %xmm4,%xmm6 + phaddsw (%ecx),%xmm6 + phsubw %xmm4,%xmm6 + phsubw (%ecx),%xmm6 + phsubd %xmm4,%xmm6 + phsubd (%ecx),%xmm6 + phsubsw %xmm4,%xmm6 + phsubsw (%ecx),%xmm6 + pmaddwd %xmm4,%xmm6 + pmaddwd (%ecx),%xmm6 + pmaddubsw %xmm4,%xmm6 + pmaddubsw (%ecx),%xmm6 + pmaxsb %xmm4,%xmm6 + pmaxsb (%ecx),%xmm6 + pmaxsw %xmm4,%xmm6 + pmaxsw (%ecx),%xmm6 + pmaxsd %xmm4,%xmm6 + pmaxsd (%ecx),%xmm6 + pmaxub %xmm4,%xmm6 + pmaxub (%ecx),%xmm6 + pmaxuw %xmm4,%xmm6 + pmaxuw (%ecx),%xmm6 + pmaxud %xmm4,%xmm6 + pmaxud (%ecx),%xmm6 + pminsb %xmm4,%xmm6 + pminsb (%ecx),%xmm6 + pminsw %xmm4,%xmm6 + pminsw (%ecx),%xmm6 + pminsd %xmm4,%xmm6 + pminsd (%ecx),%xmm6 + pminub %xmm4,%xmm6 + pminub (%ecx),%xmm6 + pminuw %xmm4,%xmm6 + pminuw (%ecx),%xmm6 + pminud %xmm4,%xmm6 + pminud (%ecx),%xmm6 + pmulhuw %xmm4,%xmm6 + pmulhuw (%ecx),%xmm6 + pmulhrsw %xmm4,%xmm6 + pmulhrsw (%ecx),%xmm6 + pmulhw %xmm4,%xmm6 + pmulhw (%ecx),%xmm6 + pmullw %xmm4,%xmm6 + pmullw (%ecx),%xmm6 + pmulld %xmm4,%xmm6 + pmulld (%ecx),%xmm6 + pmuludq %xmm4,%xmm6 + pmuludq (%ecx),%xmm6 + pmuldq %xmm4,%xmm6 + pmuldq (%ecx),%xmm6 + por %xmm4,%xmm6 + por (%ecx),%xmm6 + psadbw %xmm4,%xmm6 + psadbw (%ecx),%xmm6 + pshufb %xmm4,%xmm6 + pshufb (%ecx),%xmm6 + psignb %xmm4,%xmm6 + psignb (%ecx),%xmm6 + psignw %xmm4,%xmm6 + psignw (%ecx),%xmm6 + psignd %xmm4,%xmm6 + psignd (%ecx),%xmm6 + psllw %xmm4,%xmm6 + psllw (%ecx),%xmm6 + pslld %xmm4,%xmm6 + pslld (%ecx),%xmm6 + psllq %xmm4,%xmm6 + psllq (%ecx),%xmm6 + psraw %xmm4,%xmm6 + psraw (%ecx),%xmm6 + psrad %xmm4,%xmm6 + psrad (%ecx),%xmm6 + psrlw %xmm4,%xmm6 + psrlw (%ecx),%xmm6 + psrld %xmm4,%xmm6 + psrld (%ecx),%xmm6 + psrlq %xmm4,%xmm6 + psrlq (%ecx),%xmm6 + psubb %xmm4,%xmm6 + psubb (%ecx),%xmm6 + psubw %xmm4,%xmm6 + psubw (%ecx),%xmm6 + psubd %xmm4,%xmm6 + psubd (%ecx),%xmm6 + psubq %xmm4,%xmm6 + psubq (%ecx),%xmm6 + psubsb %xmm4,%xmm6 + psubsb (%ecx),%xmm6 + psubsw %xmm4,%xmm6 + psubsw (%ecx),%xmm6 + psubusb %xmm4,%xmm6 + psubusb (%ecx),%xmm6 + psubusw %xmm4,%xmm6 + psubusw (%ecx),%xmm6 + punpckhbw %xmm4,%xmm6 + punpckhbw (%ecx),%xmm6 + punpckhwd %xmm4,%xmm6 + punpckhwd (%ecx),%xmm6 + punpckhdq %xmm4,%xmm6 + punpckhdq (%ecx),%xmm6 + punpckhqdq %xmm4,%xmm6 + punpckhqdq (%ecx),%xmm6 + punpcklbw %xmm4,%xmm6 + punpcklbw (%ecx),%xmm6 + punpcklwd %xmm4,%xmm6 + punpcklwd (%ecx),%xmm6 + punpckldq %xmm4,%xmm6 + punpckldq (%ecx),%xmm6 + punpcklqdq %xmm4,%xmm6 + punpcklqdq (%ecx),%xmm6 + pxor %xmm4,%xmm6 + pxor (%ecx),%xmm6 + subpd %xmm4,%xmm6 + subpd (%ecx),%xmm6 + subps %xmm4,%xmm6 + subps (%ecx),%xmm6 + unpckhpd %xmm4,%xmm6 + unpckhpd (%ecx),%xmm6 + unpckhps %xmm4,%xmm6 + unpckhps (%ecx),%xmm6 + unpcklpd %xmm4,%xmm6 + unpcklpd (%ecx),%xmm6 + unpcklps %xmm4,%xmm6 + unpcklps (%ecx),%xmm6 + xorpd %xmm4,%xmm6 + xorpd (%ecx),%xmm6 + xorps %xmm4,%xmm6 + xorps (%ecx),%xmm6 + cmpeqpd %xmm4,%xmm6 + cmpeqpd (%ecx),%xmm6 + cmpeqps %xmm4,%xmm6 + cmpeqps (%ecx),%xmm6 + cmpltpd %xmm4,%xmm6 + cmpltpd (%ecx),%xmm6 + cmpltps %xmm4,%xmm6 + cmpltps (%ecx),%xmm6 + cmplepd %xmm4,%xmm6 + cmplepd (%ecx),%xmm6 + cmpleps %xmm4,%xmm6 + cmpleps (%ecx),%xmm6 + cmpunordpd %xmm4,%xmm6 + cmpunordpd (%ecx),%xmm6 + cmpunordps %xmm4,%xmm6 + cmpunordps (%ecx),%xmm6 + cmpneqpd %xmm4,%xmm6 + cmpneqpd (%ecx),%xmm6 + cmpneqps %xmm4,%xmm6 + cmpneqps (%ecx),%xmm6 + cmpnltpd %xmm4,%xmm6 + cmpnltpd (%ecx),%xmm6 + cmpnltps %xmm4,%xmm6 + cmpnltps (%ecx),%xmm6 + cmpnlepd %xmm4,%xmm6 + cmpnlepd (%ecx),%xmm6 + cmpnleps %xmm4,%xmm6 + cmpnleps (%ecx),%xmm6 + cmpordpd %xmm4,%xmm6 + cmpordpd (%ecx),%xmm6 + cmpordps %xmm4,%xmm6 + cmpordps (%ecx),%xmm6 + +# Tests for op imm8, xmm/mem128, xmm + pcmpestri $100,%xmm4,%xmm6 + pcmpestri $100,(%ecx),%xmm6 + pcmpestrm $100,%xmm4,%xmm6 + pcmpestrm $100,(%ecx),%xmm6 + pcmpistri $100,%xmm4,%xmm6 + pcmpistri $100,(%ecx),%xmm6 + pcmpistrm $100,%xmm4,%xmm6 + pcmpistrm $100,(%ecx),%xmm6 + pshufd $100,%xmm4,%xmm6 + pshufd $100,(%ecx),%xmm6 + pshufhw $100,%xmm4,%xmm6 + pshufhw $100,(%ecx),%xmm6 + pshuflw $100,%xmm4,%xmm6 + pshuflw $100,(%ecx),%xmm6 + roundpd $100,%xmm4,%xmm6 + roundpd $100,(%ecx),%xmm6 + roundps $100,%xmm4,%xmm6 + roundps $100,(%ecx),%xmm6 + +# Tests for op imm8, xmm/mem128, xmm[, xmm] + blendpd $100,%xmm4,%xmm6 + blendpd $100,(%ecx),%xmm6 + blendps $100,%xmm4,%xmm6 + blendps $100,(%ecx),%xmm6 + cmppd $100,%xmm4,%xmm6 + cmppd $100,(%ecx),%xmm6 + cmpps $100,%xmm4,%xmm6 + cmpps $100,(%ecx),%xmm6 + dppd $100,%xmm4,%xmm6 + dppd $100,(%ecx),%xmm6 + dpps $100,%xmm4,%xmm6 + dpps $100,(%ecx),%xmm6 + mpsadbw $100,%xmm4,%xmm6 + mpsadbw $100,(%ecx),%xmm6 + palignr $100,%xmm4,%xmm6 + palignr $100,(%ecx),%xmm6 + pblendw $100,%xmm4,%xmm6 + pblendw $100,(%ecx),%xmm6 + shufpd $100,%xmm4,%xmm6 + shufpd $100,(%ecx),%xmm6 + shufps $100,%xmm4,%xmm6 + shufps $100,(%ecx),%xmm6 + +# Tests for op xmm0, xmm/mem128, xmm[, xmm] + blendvpd %xmm0,%xmm4,%xmm6 + blendvpd %xmm0,(%ecx),%xmm6 + blendvpd %xmm4,%xmm6 + blendvpd (%ecx),%xmm6 + blendvps %xmm0,%xmm4,%xmm6 + blendvps %xmm0,(%ecx),%xmm6 + blendvps %xmm4,%xmm6 + blendvps (%ecx),%xmm6 + pblendvb %xmm0,%xmm4,%xmm6 + pblendvb %xmm0,(%ecx),%xmm6 + pblendvb %xmm4,%xmm6 + pblendvb (%ecx),%xmm6 + +# Tests for op xmm/mem64, xmm + comisd %xmm4,%xmm6 + comisd (%ecx),%xmm4 + cvtdq2pd %xmm4,%xmm6 + cvtdq2pd (%ecx),%xmm4 + cvtps2pd %xmm4,%xmm6 + cvtps2pd (%ecx),%xmm4 + movddup %xmm4,%xmm6 + movddup (%ecx),%xmm4 + pmovsxbw %xmm4,%xmm6 + pmovsxbw (%ecx),%xmm4 + pmovsxwd %xmm4,%xmm6 + pmovsxwd (%ecx),%xmm4 + pmovsxdq %xmm4,%xmm6 + pmovsxdq (%ecx),%xmm4 + pmovzxbw %xmm4,%xmm6 + pmovzxbw (%ecx),%xmm4 + pmovzxwd %xmm4,%xmm6 + pmovzxwd (%ecx),%xmm4 + pmovzxdq %xmm4,%xmm6 + pmovzxdq (%ecx),%xmm4 + ucomisd %xmm4,%xmm6 + ucomisd (%ecx),%xmm4 + +# Tests for op mem64, xmm + movsd (%ecx),%xmm4 + +# Tests for op xmm, mem64 + movlpd %xmm4,(%ecx) + movlps %xmm4,(%ecx) + movhpd %xmm4,(%ecx) + movhps %xmm4,(%ecx) + movsd %xmm4,(%ecx) + +# Tests for op xmm, regq/mem64 +# Tests for op regq/mem64, xmm + movq %xmm4,(%ecx) + movq (%ecx),%xmm4 + +# Tests for op xmm/mem64, regl + cvtsd2si %xmm4,%ecx + cvtsd2si (%ecx),%ecx + cvttsd2si %xmm4,%ecx + cvttsd2si (%ecx),%ecx + +# Tests for op mem64, xmm[, xmm] + movlpd (%ecx),%xmm4 + movlps (%ecx),%xmm4 + movhpd (%ecx),%xmm4 + movhps (%ecx),%xmm4 + +# Tests for op imm8, xmm/mem64, xmm[, xmm] + cmpsd $100,%xmm4,%xmm6 + cmpsd $100,(%ecx),%xmm6 + roundsd $100,%xmm4,%xmm6 + roundsd $100,(%ecx),%xmm6 + +# Tests for op xmm/mem64, xmm[, xmm] + addsd %xmm4,%xmm6 + addsd (%ecx),%xmm6 + cvtsd2ss %xmm4,%xmm6 + cvtsd2ss (%ecx),%xmm6 + divsd %xmm4,%xmm6 + divsd (%ecx),%xmm6 + maxsd %xmm4,%xmm6 + maxsd (%ecx),%xmm6 + minsd %xmm4,%xmm6 + minsd (%ecx),%xmm6 + mulsd %xmm4,%xmm6 + mulsd (%ecx),%xmm6 + sqrtsd %xmm4,%xmm6 + sqrtsd (%ecx),%xmm6 + subsd %xmm4,%xmm6 + subsd (%ecx),%xmm6 + cmpeqsd %xmm4,%xmm6 + cmpeqsd (%ecx),%xmm6 + cmpltsd %xmm4,%xmm6 + cmpltsd (%ecx),%xmm6 + cmplesd %xmm4,%xmm6 + cmplesd (%ecx),%xmm6 + cmpunordsd %xmm4,%xmm6 + cmpunordsd (%ecx),%xmm6 + cmpneqsd %xmm4,%xmm6 + cmpneqsd (%ecx),%xmm6 + cmpnltsd %xmm4,%xmm6 + cmpnltsd (%ecx),%xmm6 + cmpnlesd %xmm4,%xmm6 + cmpnlesd (%ecx),%xmm6 + cmpordsd %xmm4,%xmm6 + cmpordsd (%ecx),%xmm6 + +# Tests for op xmm/mem32, xmm[, xmm] + addss %xmm4,%xmm6 + addss (%ecx),%xmm6 + cvtss2sd %xmm4,%xmm6 + cvtss2sd (%ecx),%xmm6 + divss %xmm4,%xmm6 + divss (%ecx),%xmm6 + maxss %xmm4,%xmm6 + maxss (%ecx),%xmm6 + minss %xmm4,%xmm6 + minss (%ecx),%xmm6 + mulss %xmm4,%xmm6 + mulss (%ecx),%xmm6 + rcpss %xmm4,%xmm6 + rcpss (%ecx),%xmm6 + rsqrtss %xmm4,%xmm6 + rsqrtss (%ecx),%xmm6 + sqrtss %xmm4,%xmm6 + sqrtss (%ecx),%xmm6 + subss %xmm4,%xmm6 + subss (%ecx),%xmm6 + cmpeqss %xmm4,%xmm6 + cmpeqss (%ecx),%xmm6 + cmpltss %xmm4,%xmm6 + cmpltss (%ecx),%xmm6 + cmpless %xmm4,%xmm6 + cmpless (%ecx),%xmm6 + cmpunordss %xmm4,%xmm6 + cmpunordss (%ecx),%xmm6 + cmpneqss %xmm4,%xmm6 + cmpneqss (%ecx),%xmm6 + cmpnltss %xmm4,%xmm6 + cmpnltss (%ecx),%xmm6 + cmpnless %xmm4,%xmm6 + cmpnless (%ecx),%xmm6 + cmpordss %xmm4,%xmm6 + cmpordss (%ecx),%xmm6 + +# Tests for op xmm/mem32, xmm + comiss %xmm4,%xmm6 + comiss (%ecx),%xmm4 + pmovsxbd %xmm4,%xmm6 + pmovsxbd (%ecx),%xmm4 + pmovsxwq %xmm4,%xmm6 + pmovsxwq (%ecx),%xmm4 + pmovzxbd %xmm4,%xmm6 + pmovzxbd (%ecx),%xmm4 + pmovzxwq %xmm4,%xmm6 + pmovzxwq (%ecx),%xmm4 + ucomiss %xmm4,%xmm6 + ucomiss (%ecx),%xmm4 + +# Tests for op mem32, xmm + movss (%ecx),%xmm4 + +# Tests for op xmm, mem32 + movss %xmm4,(%ecx) + +# Tests for op xmm, regl/mem32 +# Tests for op regl/mem32, xmm + movd %xmm4,%ecx + movd %xmm4,(%ecx) + movd %ecx,%xmm4 + movd (%ecx),%xmm4 + +# Tests for op xmm/mem32, regl + cvtss2si %xmm4,%ecx + cvtss2si (%ecx),%ecx + cvttss2si %xmm4,%ecx + cvttss2si (%ecx),%ecx + +# Tests for op imm8, xmm, regq/mem32 + extractps $100,%xmm4,(%ecx) +# Tests for op imm8, xmm, regl/mem32 + pextrd $100,%xmm4,%ecx + pextrd $100,%xmm4,(%ecx) + extractps $100,%xmm4,%ecx + extractps $100,%xmm4,(%ecx) + +# Tests for op regl/mem32, xmm[, xmm] + cvtsi2sd %ecx,%xmm4 + cvtsi2sd (%ecx),%xmm4 + cvtsi2ss %ecx,%xmm4 + cvtsi2ss (%ecx),%xmm4 + +# Tests for op imm8, xmm/mem32, xmm[, xmm] + cmpss $100,%xmm4,%xmm6 + cmpss $100,(%ecx),%xmm6 + insertps $100,%xmm4,%xmm6 + insertps $100,(%ecx),%xmm6 + roundss $100,%xmm4,%xmm6 + roundss $100,(%ecx),%xmm6 + +# Tests for op xmm/m16, xmm + pmovsxbq %xmm4,%xmm6 + pmovsxbq (%ecx),%xmm4 + pmovzxbq %xmm4,%xmm6 + pmovzxbq (%ecx),%xmm4 + +# Tests for op imm8, xmm, regl/mem16 + pextrw $100,%xmm4,%ecx + pextrw $100,%xmm4,(%ecx) + +# Tests for op imm8, xmm, regq/mem16 + pextrw $100,%xmm4,(%ecx) + +# Tests for op imm8, regl/mem16, xmm[, xmm] + pinsrw $100,%ecx,%xmm4 + pinsrw $100,(%ecx),%xmm4 + + +# Tests for op imm8, xmm, regl/mem8 + pextrb $100,%xmm4,%ecx + pextrb $100,%xmm4,(%ecx) + +# Tests for op imm8, regl/mem8, xmm[, xmm] + pinsrb $100,%ecx,%xmm4 + pinsrb $100,(%ecx),%xmm4 + +# Tests for op imm8, xmm, regq/mem8 + pextrb $100,%xmm4,(%ecx) + +# Tests for op imm8, regl/mem8, xmm[, xmm] + pinsrb $100,%ecx,%xmm4 + pinsrb $100,(%ecx),%xmm4 + +# Tests for op xmm, xmm + maskmovdqu %xmm4,%xmm6 + movq %xmm4,%xmm6 + +# Tests for op xmm, regl + movmskpd %xmm4,%ecx + movmskps %xmm4,%ecx + pmovmskb %xmm4,%ecx +# Tests for op xmm, xmm[, xmm] + movhlps %xmm4,%xmm6 + movlhps %xmm4,%xmm6 + movsd %xmm4,%xmm6 + movss %xmm4,%xmm6 + +# Tests for op imm8, xmm[, xmm] + pslld $100,%xmm4 + pslldq $100,%xmm4 + psllq $100,%xmm4 + psllw $100,%xmm4 + psrad $100,%xmm4 + psraw $100,%xmm4 + psrld $100,%xmm4 + psrldq $100,%xmm4 + psrlq $100,%xmm4 + psrlw $100,%xmm4 + +# Tests for op imm8, xmm, regl + pextrw $100,%xmm4,%ecx + diff --git a/gas/testsuite/gas/i386/x86-64-aes-intel.d b/gas/testsuite/gas/i386/x86-64-aes-intel.d new file mode 100644 index 0000000..3f0d5c4 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-aes-intel.d @@ -0,0 +1,35 @@ +#source: x86-64-aes.s +#as: -J +#objdump: -dw -Mintel +#name: x86-64 AES (Intel mode) + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist xmm0,XMMWORD PTR \[rcx\],0x8 +[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist xmm0,xmm1,0x8 +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist xmm0,XMMWORD PTR \[rcx\],0x8 +[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist xmm0,xmm1,0x8 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-aes.d b/gas/testsuite/gas/i386/x86-64-aes.d new file mode 100644 index 0000000..3c62dcd --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-aes.d @@ -0,0 +1,34 @@ +#as: -J +#objdump: -dw +#name: x86-64 AES + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist \$0x8,\(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist \$0x8,\(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist \$0x8,%xmm1,%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-aes.s b/gas/testsuite/gas/i386/x86-64-aes.s new file mode 100644 index 0000000..955619d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-aes.s @@ -0,0 +1,30 @@ +# Check 64bit AES new instructions. + + .text +foo: + aesenc (%rcx),%xmm0 + aesenc %xmm1,%xmm0 + aesenclast (%rcx),%xmm0 + aesenclast %xmm1,%xmm0 + aesdec (%rcx),%xmm0 + aesdec %xmm1,%xmm0 + aesdeclast (%rcx),%xmm0 + aesdeclast %xmm1,%xmm0 + aesimc (%rcx),%xmm0 + aesimc %xmm1,%xmm0 + aeskeygenassist $8,(%rcx),%xmm0 + aeskeygenassist $8,%xmm1,%xmm0 + + .intel_syntax noprefix + aesenc xmm0,XMMWORD PTR [rcx] + aesenc xmm0,xmm1 + aesenclast xmm0,XMMWORD PTR [rcx] + aesenclast xmm0,xmm1 + aesdec xmm0,XMMWORD PTR [rcx] + aesdec xmm0,xmm1 + aesdeclast xmm0,XMMWORD PTR [rcx] + aesdeclast xmm0,xmm1 + aesimc xmm0,XMMWORD PTR [rcx] + aesimc xmm0,xmm1 + aeskeygenassist xmm0,XMMWORD PTR [rcx],8 + aeskeygenassist xmm0,xmm1,8 diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d index 235b627..69cd92f 100644 --- a/gas/testsuite/gas/i386/x86-64-arch-2.d +++ b/gas/testsuite/gas/i386/x86-64-arch-2.d @@ -1,4 +1,4 @@ -#as: -march=generic64+sse4+vmx+smx+xsave+sse5+3dnowa+svme+padlock +#as: -march=generic64+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock #objdump: -dw #name: x86-64 arch 2 @@ -15,9 +15,13 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3 [ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3 [ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[a-f0-9]+: c5 fc 77 vzeroall [ ]*[a-f0-9]+: 0f 01 c4 vmxoff [ ]*[a-f0-9]+: 0f 37 getsec [ ]*[a-f0-9]+: 0f 01 d0 xgetbv +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 [ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3 [ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3 [ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1 diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s index e5e799d..73625e4 100644 --- a/gas/testsuite/gas/i386/x86-64-arch-2.s +++ b/gas/testsuite/gas/i386/x86-64-arch-2.s @@ -16,12 +16,20 @@ phaddw %xmm4,%xmm3 phminposuw %xmm1,%xmm3 # SSE4.2 crc32 %ecx,%ebx +# AVX +vzeroall # VMX vmxoff # SMX getsec # Xsave xgetbv +# AES +aesenc (%rcx),%xmm0 +# CLMUL +pclmulqdq $8,%xmm1,%xmm0 +# FMA +vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 # 3DNow pmulhrw %mm4,%mm3 # 3DNow Extensions diff --git a/gas/testsuite/gas/i386/x86-64-avx-intel.d b/gas/testsuite/gas/i386/x86-64-avx-intel.d new file mode 100644 index 0000000..8a76897 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-intel.d @@ -0,0 +1,3047 @@ +#objdump: -drwMintel +#name: x86-64 AVX (Intel mode) +#source: x86-64-avx.s + +.*: +file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: c5 fc 77 vzeroall +[ ]*[a-f0-9]+: c5 f8 77 vzeroupper +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 5d 2d 31 vmaskmovpd ymm6,ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd YMMWORD PTR \[rcx\],ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps ymm6,ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[rcx\],ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 58 11 vaddps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd d0 d4 vaddsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd d0 11 vaddsubpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cf d0 d4 vaddsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf d0 11 vaddsubps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 55 d4 vandnpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 55 11 vandnpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 55 d4 vandnps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 55 11 vandnps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 54 d4 vandpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 54 11 vandpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 54 d4 vandps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 54 11 vandps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 5e d4 vdivpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5e 11 vdivpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 5e d4 vdivps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5e 11 vdivps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 7c d4 vhaddpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 7c 11 vhaddpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cf 7c d4 vhaddps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf 7c 11 vhaddps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 7d d4 vhsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 7d 11 vhsubpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cf 7d d4 vhsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf 7d 11 vhsubps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 5f d4 vmaxpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5f 11 vmaxpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 5f d4 vmaxps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5f 11 vmaxps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 5d d4 vminpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5d 11 vminpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 5d d4 vminps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5d 11 vminps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 59 d4 vmulpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 59 11 vmulpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 59 d4 vmulps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 59 11 vmulps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 56 d4 vorpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 56 11 vorpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 56 d4 vorps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 56 11 vorps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 4d 0d d4 vpermilpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 4d 0d 11 vpermilpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 4d 0c d4 vpermilps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 4d 0c 11 vpermilps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 5c d4 vsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5c 11 vsubpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 5c d4 vsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5c 11 vsubps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 15 d4 vunpckhpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 15 11 vunpckhpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 15 d4 vunpckhps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 15 11 vunpckhps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 14 d4 vunpcklpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 14 11 vunpcklpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 14 d4 vunpcklps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 14 11 vunpcklps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 57 d4 vxorpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 57 11 vxorpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 57 d4 vxorps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 57 11 vxorps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 10 vcmpeq_ospd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 11 vcmplt_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 11 vcmplt_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 12 vcmple_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 12 vcmple_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 13 vcmpunord_spd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 13 vcmpunord_spd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 14 vcmpneq_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 14 vcmpneq_uspd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 15 vcmpnlt_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 15 vcmpnlt_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 16 vcmpnle_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 16 vcmpnle_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 17 vcmpord_spd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 17 vcmpord_spd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 18 vcmpeq_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 18 vcmpeq_uspd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 19 vcmpnge_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 19 vcmpnge_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1a vcmpngt_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1a vcmpngt_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1b vcmpfalse_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1b vcmpfalse_ospd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1c vcmpneq_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1c vcmpneq_ospd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1d vcmpge_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1d vcmpge_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1e vcmpgt_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1e vcmpgt_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1f vcmptrue_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 10 vcmpeq_osps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 11 vcmplt_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 11 vcmplt_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 12 vcmple_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 12 vcmple_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 13 vcmpunord_sps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 13 vcmpunord_sps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 14 vcmpneq_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 14 vcmpneq_usps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 15 vcmpnlt_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 15 vcmpnlt_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 16 vcmpnle_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 16 vcmpnle_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 17 vcmpord_sps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 17 vcmpord_sps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 18 vcmpeq_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 18 vcmpeq_usps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 19 vcmpnge_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 19 vcmpnge_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1a vcmpngt_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1a vcmpngt_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1b vcmpfalse_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1b vcmpfalse_osps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1c vcmpneq_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1c vcmpneq_osps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1d vcmpge_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1d vcmpge_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1e vcmpgt_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4 +[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2ps xmm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq xmm4,ymm4 +[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dq xmm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[rcx\] +[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd ymm7,ymm2,ymm6,ymm4,0xa +[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps ymm7,ymm2,ymm6,ymm4,0xa +[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa +[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 ymm6,ymm4,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 xmm4,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[rcx\],ymm4,0x64 +[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dq xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2ps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dq xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 0e f4 vtestps xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0e 21 vtestps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 0f f4 vtestpd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0f 21 vtestpd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu xmm4,\[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fe e6 e4 vcvtdq2pd ymm4,xmm4 +[ ]*[a-f0-9]+: c5 fe e6 21 vcvtdq2pd ymm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 5a e4 vcvtps2pd ymm4,xmm4 +[ ]*[a-f0-9]+: c5 fc 5a 21 vcvtps2pd ymm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 58 d4 vaddpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 58 39 vaddpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 58 d4 vaddps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 58 39 vaddps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d0 d4 vaddsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d0 39 vaddsubpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb d0 d4 vaddsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb d0 39 vaddsubps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 55 d4 vandnpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 55 39 vandnpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 55 d4 vandnps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 55 39 vandnps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 54 d4 vandpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 54 39 vandpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 54 d4 vandps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 54 39 vandps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 5e d4 vdivpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5e 39 vdivpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 5e d4 vdivps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5e 39 vdivps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 7c d4 vhaddpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 7c 39 vhaddpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 7c d4 vhaddps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 7c 39 vhaddps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 7d d4 vhsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 7d 39 vhsubpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 7d d4 vhsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 7d 39 vhsubps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 5f d4 vmaxpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5f 39 vmaxpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 5f d4 vmaxps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5f 39 vmaxps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 5d d4 vminpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5d 39 vminpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 5d d4 vminps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5d 39 vminps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 59 d4 vmulpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 59 39 vmulpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 59 d4 vmulps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 59 39 vmulps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 56 d4 vorpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 56 39 vorpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 56 d4 vorps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 56 39 vorps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 63 d4 vpacksswb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 63 39 vpacksswb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 6b d4 vpackssdw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6b 39 vpackssdw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 67 d4 vpackuswb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 67 39 vpackuswb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 2b d4 vpackusdw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 2b 39 vpackusdw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fc d4 vpaddb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fc 39 vpaddb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fd d4 vpaddw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fd 39 vpaddw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fe d4 vpaddd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fe 39 vpaddd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d4 d4 vpaddq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d4 39 vpaddq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ec d4 vpaddsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ec 39 vpaddsb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ed d4 vpaddsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ed 39 vpaddsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 dc d4 vpaddusb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 dc 39 vpaddusb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 dd d4 vpaddusw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 dd 39 vpaddusw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 db d4 vpand xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 db 39 vpand xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 df d4 vpandn xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 df 39 vpandn xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e0 d4 vpavgb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e0 39 vpavgb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e3 d4 vpavgw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e3 39 vpavgw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 74 d4 vpcmpeqb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 74 39 vpcmpeqb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 75 d4 vpcmpeqw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 75 39 vpcmpeqw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 76 d4 vpcmpeqd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 76 39 vpcmpeqd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 29 d4 vpcmpeqq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 29 39 vpcmpeqq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 64 d4 vpcmpgtb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 64 39 vpcmpgtb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 65 d4 vpcmpgtw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 65 39 vpcmpgtw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 66 d4 vpcmpgtd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 66 39 vpcmpgtd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 37 d4 vpcmpgtq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 37 39 vpcmpgtq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 0d d4 vpermilpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0d 39 vpermilpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 0c d4 vpermilps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0c 39 vpermilps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 01 d4 vphaddw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 01 39 vphaddw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 02 d4 vphaddd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 02 39 vphaddd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 03 d4 vphaddsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 03 39 vphaddsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 05 d4 vphsubw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 05 39 vphsubw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 06 d4 vphsubd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 06 39 vphsubd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 07 d4 vphsubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 07 39 vphsubsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f5 d4 vpmaddwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f5 39 vpmaddwd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 04 d4 vpmaddubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 04 39 vpmaddubsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3c d4 vpmaxsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3c 39 vpmaxsb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ee d4 vpmaxsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ee 39 vpmaxsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3d d4 vpmaxsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3d 39 vpmaxsd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 de d4 vpmaxub xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 de 39 vpmaxub xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3e d4 vpmaxuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3e 39 vpmaxuw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3f d4 vpmaxud xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3f 39 vpmaxud xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 38 d4 vpminsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 38 39 vpminsb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ea d4 vpminsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ea 39 vpminsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 39 d4 vpminsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 39 39 vpminsd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 da d4 vpminub xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 da 39 vpminub xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3a d4 vpminuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3a 39 vpminuw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3b d4 vpminud xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3b 39 vpminud xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e4 d4 vpmulhuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e4 39 vpmulhuw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 0b d4 vpmulhrsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0b 39 vpmulhrsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e5 d4 vpmulhw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e5 39 vpmulhw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d5 d4 vpmullw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d5 39 vpmullw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 40 d4 vpmulld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 40 39 vpmulld xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f4 d4 vpmuludq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f4 39 vpmuludq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 28 d4 vpmuldq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 28 39 vpmuldq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 eb d4 vpor xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 eb 39 vpor xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f6 d4 vpsadbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f6 39 vpsadbw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 00 d4 vpshufb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 00 39 vpshufb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 08 d4 vpsignb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 08 39 vpsignb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 09 d4 vpsignw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 09 39 vpsignw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 0a d4 vpsignd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0a 39 vpsignd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f1 d4 vpsllw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f1 39 vpsllw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f2 d4 vpslld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f2 39 vpslld xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f3 d4 vpsllq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f3 39 vpsllq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e1 d4 vpsraw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e1 39 vpsraw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e2 d4 vpsrad xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e2 39 vpsrad xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d1 d4 vpsrlw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d1 39 vpsrlw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d2 d4 vpsrld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d2 39 vpsrld xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d3 d4 vpsrlq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d3 39 vpsrlq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f8 d4 vpsubb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f8 39 vpsubb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f9 d4 vpsubw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f9 39 vpsubw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fa d4 vpsubd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fa 39 vpsubd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fb d4 vpsubq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fb 39 vpsubq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e8 d4 vpsubsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e8 39 vpsubsb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e9 d4 vpsubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e9 39 vpsubsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d8 d4 vpsubusb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d8 39 vpsubusb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d9 d4 vpsubusw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d9 39 vpsubusw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 68 d4 vpunpckhbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 68 39 vpunpckhbw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 69 d4 vpunpckhwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 69 39 vpunpckhwd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 6a d4 vpunpckhdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6a 39 vpunpckhdq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 6d d4 vpunpckhqdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6d 39 vpunpckhqdq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 60 d4 vpunpcklbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 60 39 vpunpcklbw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 61 d4 vpunpcklwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 61 39 vpunpcklwd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 62 d4 vpunpckldq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 62 39 vpunpckldq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 6c d4 vpunpcklqdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6c 39 vpunpcklqdq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ef d4 vpxor xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ef 39 vpxor xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 5c d4 vsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5c 39 vsubpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 5c d4 vsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5c 39 vsubps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 15 d4 vunpckhpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 15 39 vunpckhpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 15 d4 vunpckhps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 15 39 vunpckhps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 14 d4 vunpcklpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 14 39 vunpcklpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 14 d4 vunpcklps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 14 39 vunpcklps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 57 d4 vxorpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 57 39 vxorpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 57 d4 vxorps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 57 39 vxorps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 00 vcmpeqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 00 vcmpeqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 01 vcmpltpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 01 vcmpltpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 02 vcmplepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 02 vcmplepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 03 vcmpunordpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 03 vcmpunordpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 04 vcmpneqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 04 vcmpneqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 05 vcmpnltpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 05 vcmpnltpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 06 vcmpnlepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 06 vcmpnlepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 07 vcmpordpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 08 vcmpeq_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 08 vcmpeq_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 09 vcmpngepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 09 vcmpngepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0a vcmpngtpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0a vcmpngtpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0b vcmpfalsepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0b vcmpfalsepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0c vcmpneq_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0c vcmpneq_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0d vcmpgepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0d vcmpgepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0e vcmpgtpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0e vcmpgtpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0f vcmptruepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0f vcmptruepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 10 vcmpeq_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 10 vcmpeq_ospd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 11 vcmplt_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 11 vcmplt_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 12 vcmple_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 12 vcmple_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 13 vcmpunord_spd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 13 vcmpunord_spd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 14 vcmpneq_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 14 vcmpneq_uspd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 15 vcmpnlt_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 15 vcmpnlt_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 16 vcmpnle_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 16 vcmpnle_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 17 vcmpord_spd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 17 vcmpord_spd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 18 vcmpeq_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 18 vcmpeq_uspd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 19 vcmpnge_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 19 vcmpnge_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1a vcmpngt_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1a vcmpngt_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1b vcmpfalse_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1b vcmpfalse_ospd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1c vcmpneq_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1c vcmpneq_ospd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1d vcmpge_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1d vcmpge_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1e vcmpgt_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1e vcmpgt_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1f vcmptrue_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1f vcmptrue_uspd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 00 vcmpeqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 00 vcmpeqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 01 vcmpltps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 01 vcmpltps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 02 vcmpleps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 02 vcmpleps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 03 vcmpunordps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 03 vcmpunordps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 04 vcmpneqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 04 vcmpneqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 05 vcmpnltps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 05 vcmpnltps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 06 vcmpnleps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 06 vcmpnleps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 07 vcmpordps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 08 vcmpeq_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 08 vcmpeq_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 09 vcmpngeps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 09 vcmpngeps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0a vcmpngtps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0a vcmpngtps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0b vcmpfalseps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0b vcmpfalseps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0c vcmpneq_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0c vcmpneq_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0d vcmpgeps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0d vcmpgeps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0e vcmpgtps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0e vcmpgtps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0f vcmptrueps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0f vcmptrueps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 10 vcmpeq_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 10 vcmpeq_osps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 11 vcmplt_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 11 vcmplt_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 12 vcmple_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 12 vcmple_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 13 vcmpunord_sps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 13 vcmpunord_sps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 14 vcmpneq_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 14 vcmpneq_usps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 15 vcmpnlt_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 15 vcmpnlt_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 16 vcmpnle_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 16 vcmpnle_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 17 vcmpord_sps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 17 vcmpord_sps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 18 vcmpeq_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 18 vcmpeq_usps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 19 vcmpnge_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 19 vcmpnge_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1a vcmpngt_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1a vcmpngt_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1b vcmpfalse_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1b vcmpfalse_osps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1c vcmpneq_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1c vcmpneq_osps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1d vcmpge_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1d vcmpge_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1e vcmpgt_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[rcx\],xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[rcx\],xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd xmm7,xmm2,xmm6,xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa +[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps xmm7,xmm2,xmm6,xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa +[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa +[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e1 f9 7e e1 vmovq rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 f9 6e e1 vmovq xmm4,rcx +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si ecx,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si ecx,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 fb 2d cc vcvtsd2si rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 fb 2d 09 vcvtsd2si rcx,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 fb 2c cc vcvttsd2si rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 fb 2c 09 vcvttsd2si rcx,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 db 2a f1 vcvtsi2sd xmm6,xmm4,rcx +[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sd xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss xmm6,xmm4,rcx +[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 d9 22 f1 64 vpinsrq xmm6,xmm4,rcx,0x64 +[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq rcx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq QWORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 e9 6b fc 60 vfmaddsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6b 39 60 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6b 39 40 vfmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6f fc 60 vfmsubsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6f 39 60 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6f 39 40 vfmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7b fc 60 vfnmaddsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7b 39 60 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7b 39 40 vfnmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7f fc 60 vfnmsubsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7f 39 60 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7f 39 40 vfnmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5a 11 vcvtsd2ss xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5e d4 vdivsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5e 11 vdivsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5f d4 vmaxsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5f 11 vmaxsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5d d4 vminsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5d 11 vminsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 59 d4 vmulsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 59 11 vmulsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 51 d4 vsqrtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 51 11 vsqrtsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5c d4 vsubsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 10 vcmpeq_ossd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 11 vcmplt_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 11 vcmplt_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 12 vcmple_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 12 vcmple_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 13 vcmpunord_ssd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 13 vcmpunord_ssd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 14 vcmpneq_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 14 vcmpneq_ussd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 15 vcmpnlt_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 15 vcmpnlt_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 16 vcmpnle_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 16 vcmpnle_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 17 vcmpord_ssd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 17 vcmpord_ssd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 18 vcmpeq_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 18 vcmpeq_ussd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 19 vcmpnge_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 19 vcmpnge_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1a vcmpngt_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1a vcmpngt_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1b vcmpfalse_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1b vcmpfalse_ossd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1c vcmpneq_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1c vcmpneq_ossd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1d vcmpge_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1d vcmpge_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1e vcmpgt_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5a 11 vcvtss2sd xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5e d4 vdivss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5e 11 vdivss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5f d4 vmaxss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5f 11 vmaxss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5d d4 vminss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5d 11 vminss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 59 d4 vmulss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 59 11 vmulss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 53 d4 vrcpss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 53 11 vrcpss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 52 d4 vrsqrtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 52 11 vrsqrtss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 51 d4 vsqrtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 51 11 vsqrtss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5c d4 vsubss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 10 vcmpeq_osss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 11 vcmplt_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 11 vcmplt_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 12 vcmple_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 12 vcmple_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 13 vcmpunord_sss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 13 vcmpunord_sss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 14 vcmpneq_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 14 vcmpneq_usss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 15 vcmpnlt_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 15 vcmpnlt_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 16 vcmpnle_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 16 vcmpnle_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 17 vcmpord_sss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 17 vcmpord_sss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 18 vcmpeq_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 18 vcmpeq_usss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 19 vcmpnge_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 19 vcmpnge_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1a vcmpngt_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1a vcmpngt_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1b vcmpfalse_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1b vcmpfalse_osss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1c vcmpneq_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1c vcmpneq_osss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1d vcmpge_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1d vcmpge_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1e vcmpgt_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1e vcmpgt_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1f vcmptrue_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1f vcmptrue_usss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 7d 18 21 vbroadcastss ymm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 18 21 vbroadcastss xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd xmm4,ecx +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si ecx,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si ecx,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 fa 2d cc vcvtss2si rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 fa 2d 09 vcvtss2si rcx,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 fa 2c cc vcvttss2si rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 fa 2c 09 vcvttss2si rcx,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb ecx,xmm4 +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd xmm6,xmm4,ecx +[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss xmm6,xmm4,ecx +[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 e9 6a fc 60 vfmaddss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6a 39 60 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6a 39 40 vfmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6e fc 60 vfmsubss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6e 39 60 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6e 39 40 vfmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7a fc 60 vfnmaddss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7a 39 60 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7a 39 40 vfnmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7e fc 60 vfnmsubss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7e 39 60 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7e 39 40 vfnmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb ecx,xmm4 +[ ]*[a-f0-9]+: c5 c8 12 d4 vmovhlps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4 +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4 +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4 +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ff e6 f4 vcvtpd2dq xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fd 5a f4 vcvtpd2ps xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fd e6 f4 vcvttpd2dq xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 78 56 34 12 vldmxcsr DWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 79 6f 04 25 78 56 34 12 vmovdqa xmm8,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 79 7f 04 25 78 56 34 12 vmovdqa XMMWORD PTR ds:0x12345678,xmm8 +[ ]*[a-f0-9]+: c5 79 7e 04 25 78 56 34 12 vmovd DWORD PTR ds:0x12345678,xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 04 25 78 56 34 12 vcvtsd2si r8d,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 7e e6 04 25 78 56 34 12 vcvtdq2pd ymm8,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 7d 5a 04 25 78 56 34 12 vcvtpd2ps xmm8,YMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 39 e0 3c 25 78 56 34 12 vpavgb xmm15,xmm8,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 64 vpextrb BYTE PTR ds:0x12345678,xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 3c 25 78 56 34 12 vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c4 63 19 4a 34 25 78 56 34 12 80 vblendvps xmm14,xmm12,XMMWORD PTR ds:0x12345678,xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 64 vpinsrb xmm15,xmm8,BYTE PTR ds:0x12345678,0x64 +[ ]*[a-f0-9]+: c5 7d 6f 04 25 78 56 34 12 vmovdqa ymm8,YMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 7d 7f 04 25 78 56 34 12 vmovdqa YMMWORD PTR ds:0x12345678,ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 78 56 34 12 vpermilpd ymm15,ymm8,YMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 64 vroundpd ymm8,YMMWORD PTR ds:0x12345678,0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 64 vextractf128 XMMWORD PTR ds:0x12345678,ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 64 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 78 56 34 12 80 vblendvpd ymm14,ymm12,YMMWORD PTR ds:0x12345678,ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr DWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 79 6f 45 00 vmovdqa xmm8,XMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 79 7f 45 00 vmovdqa XMMWORD PTR \[rbp\+0x0\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 45 00 vmovd DWORD PTR \[rbp\+0x0\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 45 00 vcvtsd2si r8d,QWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 7e e6 45 00 vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 7d 5a 45 00 vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 39 e0 7d 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c4 63 79 14 45 00 64 vpextrb BYTE PTR \[rbp\+0x0\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 7d 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c4 63 19 4a 75 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+0x0\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 7d 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x0\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 45 00 vmovdqa ymm8,YMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 7d 7f 45 00 vmovdqa YMMWORD PTR \[rbp\+0x0\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 7d 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c4 63 7d 09 45 00 64 vroundpd ymm8,YMMWORD PTR \[rbp\+0x0\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 45 00 64 vextractf128 XMMWORD PTR \[rbp\+0x0\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 75 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+0x0\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 14 24 vldmxcsr DWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c5 79 6f 04 24 vmovdqa xmm8,XMMWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c5 79 7f 04 24 vmovdqa XMMWORD PTR \[rsp\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 04 24 vmovd DWORD PTR \[rsp\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 04 24 vcvtsd2si r8d,QWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c5 7e e6 04 24 vcvtdq2pd ymm8,XMMWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c5 7d 5a 04 24 vcvtpd2ps xmm8,YMMWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c5 39 e0 3c 24 vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c4 63 79 14 04 24 64 vpextrb BYTE PTR \[rsp\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 3c 24 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c4 63 19 4a 34 24 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 3c 24 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 04 24 vmovdqa ymm8,YMMWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c5 7d 7f 04 24 vmovdqa YMMWORD PTR \[rsp\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 24 vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\] +[ ]*[a-f0-9]+: c4 63 7d 09 04 24 64 vroundpd ymm8,YMMWORD PTR \[rsp\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 04 24 64 vextractf128 XMMWORD PTR \[rsp\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 24 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 24 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr DWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 79 6f 85 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 79 7f 85 99 00 00 00 vmovdqa XMMWORD PTR \[rbp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 85 99 00 00 00 vmovd DWORD PTR \[rbp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 85 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 7e e6 85 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 85 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 39 e0 bd 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 64 vpextrb BYTE PTR \[rbp\+0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a bd 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a b5 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 85 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 85 99 00 00 00 vmovdqa YMMWORD PTR \[rbp\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d bd 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rbp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 64 vextractf128 XMMWORD PTR \[rbp\+0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b b5 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 c1 78 ae 97 99 00 00 00 vldmxcsr DWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 79 6f 87 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 79 7f 87 99 00 00 00 vmovdqa XMMWORD PTR \[r15\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 41 79 7e 87 99 00 00 00 vmovd DWORD PTR \[r15\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 41 7b 2d 87 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 7e e6 87 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 7d 5a 87 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 39 e0 bf 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 64 vpextrb BYTE PTR \[r15\+0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 41 3b 2a bf 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 43 19 4a b7 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r15\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[r15\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 41 7d 6f 87 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 7d 7f 87 99 00 00 00 vmovdqa YMMWORD PTR \[r15\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 42 3d 0d bf 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[r15\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 64 vextractf128 XMMWORD PTR \[r15\+0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r15\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 43 1d 4b b7 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r15\+0x99\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr DWORD PTR \[rip\+0x99\] # 1a27 <_start\+0x1a27> +[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rip\+0x99\] # 1a2f <_start\+0x1a2f> +[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa XMMWORD PTR \[rip\+0x99\],xmm8 # 1a37 <_start\+0x1a37> +[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd DWORD PTR \[rip\+0x99\],xmm8 # 1a3f <_start\+0x1a3f> +[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rip\+0x99\] # 1a47 <_start\+0x1a47> +[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rip\+0x99\] # 1a4f <_start\+0x1a4f> +[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rip\+0x99\] # 1a57 <_start\+0x1a57> +[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rip\+0x99\] # 1a5f <_start\+0x1a5f> +[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 64 vpextrb BYTE PTR \[rip\+0x99\],xmm8,0x64 # 1a69 <_start\+0x1a69> +[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # 1a71 <_start\+0x1a71> +[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rip\+0x99\],xmm8 # 1a7b <_start\+0x1a7b> +[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rip\+0x99\],0x64 # 1a85 <_start\+0x1a85> +[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rip\+0x99\] # 1a8d <_start\+0x1a8d> +[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa YMMWORD PTR \[rip\+0x99\],ymm8 # 1a95 <_start\+0x1a95> +[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rip\+0x99\] # 1a9e <_start\+0x1a9e> +[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rip\+0x99\],0x64 # 1aa8 <_start\+0x1aa8> +[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 64 vextractf128 XMMWORD PTR \[rip\+0x99\],ymm8,0x64 # 1ab2 <_start\+0x1ab2> +[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rip\+0x99\],0x64 # 1abc <_start\+0x1abc> +[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rip\+0x99\],ymm8 # 1ac6 <_start\+0x1ac6> +[ ]*[a-f0-9]+: c5 f8 ae 94 24 99 00 00 00 vldmxcsr DWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 79 6f 84 24 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 79 7f 84 24 99 00 00 00 vmovdqa XMMWORD PTR \[rsp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 84 24 99 00 00 00 vmovd DWORD PTR \[rsp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 84 24 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 7e e6 84 24 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 84 24 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 39 e0 bc 24 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 64 vpextrb BYTE PTR \[rsp\+0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a b4 24 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 84 24 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 84 24 99 00 00 00 vmovdqa YMMWORD PTR \[rsp\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d bc 24 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rsp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 64 vextractf128 XMMWORD PTR \[rsp\+0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 24 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 c1 78 ae 94 24 99 00 00 00 vldmxcsr DWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 79 6f 84 24 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 79 7f 84 24 99 00 00 00 vmovdqa XMMWORD PTR \[r12\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 41 79 7e 84 24 99 00 00 00 vmovd DWORD PTR \[r12\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 41 7b 2d 84 24 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 7e e6 84 24 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 7d 5a 84 24 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 39 e0 bc 24 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 64 vpextrb BYTE PTR \[r12\+0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 41 3b 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 43 19 4a b4 24 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r12\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 41 7d 6f 84 24 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 7d 7f 84 24 99 00 00 00 vmovdqa YMMWORD PTR \[r12\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 42 3d 0d bc 24 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[r12\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 64 vextractf128 XMMWORD PTR \[r12\+0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 43 1d 4b b4 24 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r12\+0x99\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 67 ff ff ff vldmxcsr DWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 79 6f 04 25 67 ff ff ff vmovdqa xmm8,XMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 79 7f 04 25 67 ff ff ff vmovdqa XMMWORD PTR ds:0xffffffffffffff67,xmm8 +[ ]*[a-f0-9]+: c5 79 7e 04 25 67 ff ff ff vmovd DWORD PTR ds:0xffffffffffffff67,xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 04 25 67 ff ff ff vcvtsd2si r8d,QWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 7e e6 04 25 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 7d 5a 04 25 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 39 e0 3c 25 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 64 vpextrb BYTE PTR ds:0xffffffffffffff67,xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 3c 25 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 63 19 4a 34 25 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR ds:0xffffffffffffff67,xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR ds:0xffffffffffffff67,0x64 +[ ]*[a-f0-9]+: c5 7d 6f 04 25 67 ff ff ff vmovdqa ymm8,YMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 7d 7f 04 25 67 ff ff ff vmovdqa YMMWORD PTR ds:0xffffffffffffff67,ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 64 vextractf128 XMMWORD PTR ds:0xffffffffffffff67,ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR ds:0xffffffffffffff67,ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 14 65 67 ff ff ff vldmxcsr DWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 79 6f 04 65 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 79 7f 04 65 67 ff ff ff vmovdqa XMMWORD PTR \[riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 04 65 67 ff ff ff vmovd DWORD PTR \[riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 04 65 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7e e6 04 65 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 04 65 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 39 e0 3c 65 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 64 vpextrb BYTE PTR \[riz\*2-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 3c 65 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a 34 65 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 04 65 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 04 65 67 ff ff ff vmovdqa YMMWORD PTR \[riz\*2-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 65 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 64 vextractf128 XMMWORD PTR \[riz\*2-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 65 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[riz\*2-0x99\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 94 23 67 ff ff ff vldmxcsr DWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 79 6f 84 23 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 79 7f 84 23 67 ff ff ff vmovdqa XMMWORD PTR \[rbx\+riz\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 84 23 67 ff ff ff vmovd DWORD PTR \[rbx\+riz\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 84 23 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 7e e6 84 23 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 84 23 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 39 e0 bc 23 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 64 vpextrb BYTE PTR \[rbx\+riz\*1-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a bc 23 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a b4 23 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbx\+riz\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 84 23 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 84 23 67 ff ff ff vmovdqa YMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d bc 23 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 23 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 94 63 67 ff ff ff vldmxcsr DWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 79 6f 84 63 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 79 7f 84 63 67 ff ff ff vmovdqa XMMWORD PTR \[rbx\+riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 84 63 67 ff ff ff vmovd DWORD PTR \[rbx\+riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 84 63 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7e e6 84 63 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 84 63 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 39 e0 bc 63 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 64 vpextrb BYTE PTR \[rbx\+riz\*2-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a bc 63 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a b4 63 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbx\+riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 84 63 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 84 63 67 ff ff ff vmovdqa YMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d bc 63 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 63 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 81 78 ae 94 bc 67 ff ff ff vldmxcsr DWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 79 6f 84 bc 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 79 7f 84 bc 67 ff ff ff vmovdqa XMMWORD PTR \[r12\+r15\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 01 79 7e 84 bc 67 ff ff ff vmovd DWORD PTR \[r12\+r15\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 01 7b 2d 84 bc 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 7e e6 84 bc 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 7d 5a 84 bc 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 39 e0 bc bc 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 64 vpextrb BYTE PTR \[r12\+r15\*4-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 01 3b 2a bc bc 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 03 19 4a b4 bc 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r12\+r15\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+r15\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 01 7d 6f 84 bc 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 7d 7f 84 bc 67 ff ff ff vmovdqa YMMWORD PTR \[r12\+r15\*4-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 02 3d 0d bc bc 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 64 vextractf128 XMMWORD PTR \[r12\+r15\*4-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 03 1d 4b b4 bc 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r12\+r15\*4-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 81 78 ae 94 f8 67 ff ff ff vldmxcsr DWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 79 6f 84 f8 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 79 7f 84 f8 67 ff ff ff vmovdqa XMMWORD PTR \[r8\+r15\*8-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 01 79 7e 84 f8 67 ff ff ff vmovd DWORD PTR \[r8\+r15\*8-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 01 7b 2d 84 f8 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 7e e6 84 f8 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 7d 5a 84 f8 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 39 e0 bc f8 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 64 vpextrb BYTE PTR \[r8\+r15\*8-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 01 3b 2a bc f8 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 03 19 4a b4 f8 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r8\+r15\*8-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[r8\+r15\*8-0x99\],0x64 +[ ]*[a-f0-9]+: c4 01 7d 6f 84 f8 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 7d 7f 84 f8 67 ff ff ff vmovdqa YMMWORD PTR \[r8\+r15\*8-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 02 3d 0d bc f8 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x64 +[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 64 vextractf128 XMMWORD PTR \[r8\+r15\*8-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x64 +[ ]*[a-f0-9]+: c4 03 1d 4b b4 f8 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r8\+r15\*8-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 a1 78 ae 94 ad 67 ff ff ff vldmxcsr DWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 79 6f 84 ad 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 79 7f 84 ad 67 ff ff ff vmovdqa XMMWORD PTR \[rbp\+r13\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 21 79 7e 84 ad 67 ff ff ff vmovd DWORD PTR \[rbp\+r13\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 21 7b 2d 84 ad 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 7e e6 84 ad 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 7d 5a 84 ad 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 39 e0 bc ad 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 23 79 14 84 ad 67 ff ff ff 64 vpextrb BYTE PTR \[rbp\+r13\*4-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 21 3b 2a bc ad 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 23 19 4a b4 ad 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+r13\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 23 39 20 bc ad 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+r13\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 21 7d 6f 84 ad 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 7d 7f 84 ad 67 ff ff ff vmovdqa YMMWORD PTR \[rbp\+r13\*4-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 22 3d 0d bc ad 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\] +[ ]*[a-f0-9]+: c4 23 7d 09 84 ad 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 23 7d 19 84 ad 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbp\+r13\*4-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 23 3d 06 bc ad 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 23 1d 4b b4 ad 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+r13\*4-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 a1 78 ae 94 24 67 ff ff ff vldmxcsr DWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 79 6f 84 24 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 79 7f 84 24 67 ff ff ff vmovdqa XMMWORD PTR \[rsp\+r12\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 21 79 7e 84 24 67 ff ff ff vmovd DWORD PTR \[rsp\+r12\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 21 7b 2d 84 24 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 7e e6 84 24 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 7d 5a 84 24 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 39 e0 bc 24 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 23 79 14 84 24 67 ff ff ff 64 vpextrb BYTE PTR \[rsp\+r12\*1-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 21 3b 2a bc 24 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 23 19 4a b4 24 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\+r12\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 23 39 20 bc 24 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+r12\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 21 7d 6f 84 24 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 7d 7f 84 24 67 ff ff ff vmovdqa YMMWORD PTR \[rsp\+r12\*1-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 22 3d 0d bc 24 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\] +[ ]*[a-f0-9]+: c4 23 7d 09 84 24 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 23 7d 19 84 24 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rsp\+r12\*1-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 23 3d 06 bc 24 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 23 1d 4b b4 24 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\+r12\*1-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 41 79 50 c0 vmovmskpd r8d,xmm8 +[ ]*[a-f0-9]+: c4 c1 01 72 f0 64 vpslld xmm15,xmm8,0x64 +[ ]*[a-f0-9]+: c4 41 7c 50 c0 vmovmskps r8d,ymm8 +[ ]*[a-f0-9]+: c4 41 79 6f f8 vmovdqa xmm15,xmm8 +[ ]*[a-f0-9]+: c4 41 79 7e c0 vmovd r8d,xmm8 +[ ]*[a-f0-9]+: c4 41 7b 2d c0 vcvtsd2si r8d,xmm8 +[ ]*[a-f0-9]+: c4 41 7e e6 c0 vcvtdq2pd ymm8,xmm8 +[ ]*[a-f0-9]+: c4 41 7d 5a c0 vcvtpd2ps xmm8,ymm8 +[ ]*[a-f0-9]+: c4 43 79 14 c0 64 vpextrb r8d,xmm8,0x64 +[ ]*[a-f0-9]+: c4 41 3b 2a f8 vcvtsi2sd xmm15,xmm8,r8d +[ ]*[a-f0-9]+: c4 43 19 4a f0 80 vblendvps xmm14,xmm12,xmm8,xmm8 +[ ]*[a-f0-9]+: c4 43 39 20 f8 64 vpinsrb xmm15,xmm8,r8d,0x64 +[ ]*[a-f0-9]+: c4 41 7d 6f f8 vmovdqa ymm15,ymm8 +[ ]*[a-f0-9]+: c4 42 05 0d e0 vpermilpd ymm12,ymm15,ymm8 +[ ]*[a-f0-9]+: c4 43 7d 09 f8 64 vroundpd ymm15,ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 7d 19 c0 64 vextractf128 xmm8,ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 05 06 e0 64 vperm2f128 ymm12,ymm15,ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 1d 4b f7 80 vblendvpd ymm14,ymm12,ymm15,ymm8 +[ ]*[a-f0-9]+: c4 43 3d 18 f8 64 vinsertf128 ymm15,ymm8,xmm8,0x64 +[ ]*[a-f0-9]+: c4 61 fb 2d 01 vcvtsd2si r8,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 43 79 17 c0 0a vextractps r8d,xmm8,0xa +[ ]*[a-f0-9]+: c4 61 fa 2d 01 vcvtss2si r8,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 41 01 c4 c0 64 vpinsrw xmm8,xmm15,r8d,0x64 +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 5d 2d 31 vmaskmovpd ymm6,ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd YMMWORD PTR \[rcx\],ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps ymm6,ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[rcx\],ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps ymm2,ymm6,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 58 11 vaddps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd d0 d4 vaddsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd d0 11 vaddsubpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cf d0 d4 vaddsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf d0 11 vaddsubps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 55 d4 vandnpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 55 11 vandnpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 55 d4 vandnps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 55 11 vandnps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 54 d4 vandpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 54 11 vandpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 54 d4 vandps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 54 11 vandps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 5e d4 vdivpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5e 11 vdivpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 5e d4 vdivps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5e 11 vdivps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 7c d4 vhaddpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 7c 11 vhaddpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cf 7c d4 vhaddps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf 7c 11 vhaddps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 7d d4 vhsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 7d 11 vhsubpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cf 7d d4 vhsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cf 7d 11 vhsubps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 5f d4 vmaxpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5f 11 vmaxpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 5f d4 vmaxps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5f 11 vmaxps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 5d d4 vminpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5d 11 vminpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 5d d4 vminps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5d 11 vminps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 59 d4 vmulpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 59 11 vmulpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 59 d4 vmulps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 59 11 vmulps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 56 d4 vorpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 56 11 vorpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 56 d4 vorps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 56 11 vorps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 4d 0d d4 vpermilpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 4d 0d 11 vpermilpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 4d 0c d4 vpermilps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e2 4d 0c 11 vpermilps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 5c d4 vsubpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 5c 11 vsubpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 5c d4 vsubps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 5c 11 vsubps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 15 d4 vunpckhpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 15 11 vunpckhpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 15 d4 vunpckhps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 15 11 vunpckhps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 14 d4 vunpcklpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 14 11 vunpcklpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 14 d4 vunpcklps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 14 11 vunpcklps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd 57 d4 vxorpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd 57 11 vxorpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc 57 d4 vxorps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc 57 11 vxorps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 10 vcmpeq_ospd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 11 vcmplt_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 11 vcmplt_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 12 vcmple_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 12 vcmple_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 13 vcmpunord_spd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 13 vcmpunord_spd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 14 vcmpneq_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 14 vcmpneq_uspd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 15 vcmpnlt_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 15 vcmpnlt_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 16 vcmpnle_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 16 vcmpnle_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 17 vcmpord_spd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 17 vcmpord_spd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 18 vcmpeq_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 18 vcmpeq_uspd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 19 vcmpnge_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 19 vcmpnge_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1a vcmpngt_uqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1a vcmpngt_uqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1b vcmpfalse_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1b vcmpfalse_ospd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1c vcmpneq_ospd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1c vcmpneq_ospd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1d vcmpge_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1d vcmpge_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1e vcmpgt_oqpd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1e vcmpgt_oqpd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cd c2 d4 1f vcmptrue_uspd ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 10 vcmpeq_osps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 11 vcmplt_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 11 vcmplt_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 12 vcmple_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 12 vcmple_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 13 vcmpunord_sps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 13 vcmpunord_sps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 14 vcmpneq_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 14 vcmpneq_usps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 15 vcmpnlt_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 15 vcmpnlt_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 16 vcmpnle_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 16 vcmpnle_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 17 vcmpord_sps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 17 vcmpord_sps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 18 vcmpeq_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 18 vcmpeq_usps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 19 vcmpnge_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 19 vcmpnge_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1a vcmpngt_uqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1a vcmpngt_uqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1b vcmpfalse_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1b vcmpfalse_osps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1c vcmpneq_osps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1c vcmpneq_osps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1d vcmpge_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1d vcmpge_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1e vcmpgt_oqps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4 +[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2ps xmm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq xmm4,ymm4 +[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dq xmm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps ymm4,ymm4 +[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps ymm4,ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[rcx\] +[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps ymm2,ymm6,ymm4,0x64 +[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps ymm7,ymm2,ymm6,ymm4 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd ymm7,ymm2,ymm6,ymm4,0xa +[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps ymm7,ymm2,ymm6,ymm4,0xa +[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa +[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 ymm6,ymm4,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 xmm4,ymm4,0x64 +[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[rcx\],ymm4,0x64 +[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dq xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2ps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dq xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 0e f4 vtestps xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0e 21 vtestps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 0f f4 vtestpd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0f 21 vtestpd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu xmm4,\[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fe e6 e4 vcvtdq2pd ymm4,xmm4 +[ ]*[a-f0-9]+: c5 fe e6 21 vcvtdq2pd ymm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fc 5a e4 vcvtps2pd ymm4,xmm4 +[ ]*[a-f0-9]+: c5 fc 5a 21 vcvtps2pd ymm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 58 d4 vaddpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 58 39 vaddpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 58 d4 vaddps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 58 39 vaddps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d0 d4 vaddsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d0 39 vaddsubpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb d0 d4 vaddsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb d0 39 vaddsubps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 55 d4 vandnpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 55 39 vandnpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 55 d4 vandnps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 55 39 vandnps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 54 d4 vandpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 54 39 vandpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 54 d4 vandps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 54 39 vandps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 5e d4 vdivpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5e 39 vdivpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 5e d4 vdivps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5e 39 vdivps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 7c d4 vhaddpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 7c 39 vhaddpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 7c d4 vhaddps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 7c 39 vhaddps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 7d d4 vhsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 7d 39 vhsubpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 7d d4 vhsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 7d 39 vhsubps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 5f d4 vmaxpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5f 39 vmaxpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 5f d4 vmaxps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5f 39 vmaxps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 5d d4 vminpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5d 39 vminpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 5d d4 vminps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5d 39 vminps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 59 d4 vmulpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 59 39 vmulpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 59 d4 vmulps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 59 39 vmulps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 56 d4 vorpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 56 39 vorpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 56 d4 vorps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 56 39 vorps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 63 d4 vpacksswb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 63 39 vpacksswb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 6b d4 vpackssdw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6b 39 vpackssdw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 67 d4 vpackuswb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 67 39 vpackuswb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 2b d4 vpackusdw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 2b 39 vpackusdw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fc d4 vpaddb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fc 39 vpaddb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fd d4 vpaddw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fd 39 vpaddw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fe d4 vpaddd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fe 39 vpaddd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d4 d4 vpaddq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d4 39 vpaddq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ec d4 vpaddsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ec 39 vpaddsb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ed d4 vpaddsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ed 39 vpaddsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 dc d4 vpaddusb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 dc 39 vpaddusb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 dd d4 vpaddusw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 dd 39 vpaddusw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 db d4 vpand xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 db 39 vpand xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 df d4 vpandn xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 df 39 vpandn xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e0 d4 vpavgb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e0 39 vpavgb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e3 d4 vpavgw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e3 39 vpavgw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 74 d4 vpcmpeqb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 74 39 vpcmpeqb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 75 d4 vpcmpeqw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 75 39 vpcmpeqw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 76 d4 vpcmpeqd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 76 39 vpcmpeqd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 29 d4 vpcmpeqq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 29 39 vpcmpeqq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 64 d4 vpcmpgtb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 64 39 vpcmpgtb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 65 d4 vpcmpgtw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 65 39 vpcmpgtw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 66 d4 vpcmpgtd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 66 39 vpcmpgtd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 37 d4 vpcmpgtq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 37 39 vpcmpgtq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 0d d4 vpermilpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0d 39 vpermilpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 0c d4 vpermilps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0c 39 vpermilps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 01 d4 vphaddw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 01 39 vphaddw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 02 d4 vphaddd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 02 39 vphaddd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 03 d4 vphaddsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 03 39 vphaddsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 05 d4 vphsubw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 05 39 vphsubw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 06 d4 vphsubd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 06 39 vphsubd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 07 d4 vphsubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 07 39 vphsubsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f5 d4 vpmaddwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f5 39 vpmaddwd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 04 d4 vpmaddubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 04 39 vpmaddubsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3c d4 vpmaxsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3c 39 vpmaxsb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ee d4 vpmaxsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ee 39 vpmaxsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3d d4 vpmaxsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3d 39 vpmaxsd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 de d4 vpmaxub xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 de 39 vpmaxub xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3e d4 vpmaxuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3e 39 vpmaxuw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3f d4 vpmaxud xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3f 39 vpmaxud xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 38 d4 vpminsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 38 39 vpminsb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ea d4 vpminsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ea 39 vpminsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 39 d4 vpminsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 39 39 vpminsd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 da d4 vpminub xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 da 39 vpminub xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3a d4 vpminuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3a 39 vpminuw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 3b d4 vpminud xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 3b 39 vpminud xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e4 d4 vpmulhuw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e4 39 vpmulhuw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 0b d4 vpmulhrsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0b 39 vpmulhrsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e5 d4 vpmulhw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e5 39 vpmulhw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d5 d4 vpmullw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d5 39 vpmullw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 40 d4 vpmulld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 40 39 vpmulld xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f4 d4 vpmuludq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f4 39 vpmuludq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 28 d4 vpmuldq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 28 39 vpmuldq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 eb d4 vpor xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 eb 39 vpor xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f6 d4 vpsadbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f6 39 vpsadbw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 00 d4 vpshufb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 00 39 vpshufb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 08 d4 vpsignb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 08 39 vpsignb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 09 d4 vpsignw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 09 39 vpsignw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 49 0a d4 vpsignd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 0a 39 vpsignd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f1 d4 vpsllw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f1 39 vpsllw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f2 d4 vpslld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f2 39 vpslld xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f3 d4 vpsllq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f3 39 vpsllq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e1 d4 vpsraw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e1 39 vpsraw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e2 d4 vpsrad xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e2 39 vpsrad xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d1 d4 vpsrlw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d1 39 vpsrlw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d2 d4 vpsrld xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d2 39 vpsrld xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d3 d4 vpsrlq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d3 39 vpsrlq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f8 d4 vpsubb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f8 39 vpsubb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 f9 d4 vpsubw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 f9 39 vpsubw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fa d4 vpsubd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fa 39 vpsubd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 fb d4 vpsubq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 fb 39 vpsubq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e8 d4 vpsubsb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e8 39 vpsubsb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 e9 d4 vpsubsw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 e9 39 vpsubsw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d8 d4 vpsubusb xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d8 39 vpsubusb xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 d9 d4 vpsubusw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 d9 39 vpsubusw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 68 d4 vpunpckhbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 68 39 vpunpckhbw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 69 d4 vpunpckhwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 69 39 vpunpckhwd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 6a d4 vpunpckhdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6a 39 vpunpckhdq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 6d d4 vpunpckhqdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6d 39 vpunpckhqdq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 60 d4 vpunpcklbw xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 60 39 vpunpcklbw xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 61 d4 vpunpcklwd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 61 39 vpunpcklwd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 62 d4 vpunpckldq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 62 39 vpunpckldq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 6c d4 vpunpcklqdq xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 6c 39 vpunpcklqdq xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 ef d4 vpxor xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 ef 39 vpxor xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 5c d4 vsubpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 5c 39 vsubpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 5c d4 vsubps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 5c 39 vsubps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 15 d4 vunpckhpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 15 39 vunpckhpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 15 d4 vunpckhps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 15 39 vunpckhps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 14 d4 vunpcklpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 14 39 vunpcklpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 14 d4 vunpcklps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 14 39 vunpcklps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 57 d4 vxorpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 57 39 vxorpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 57 d4 vxorps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 57 39 vxorps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 00 vcmpeqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 00 vcmpeqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 01 vcmpltpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 01 vcmpltpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 02 vcmplepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 02 vcmplepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 03 vcmpunordpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 03 vcmpunordpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 04 vcmpneqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 04 vcmpneqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 05 vcmpnltpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 05 vcmpnltpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 06 vcmpnlepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 06 vcmpnlepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 07 vcmpordpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 08 vcmpeq_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 08 vcmpeq_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 09 vcmpngepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 09 vcmpngepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0a vcmpngtpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0a vcmpngtpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0b vcmpfalsepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0b vcmpfalsepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0c vcmpneq_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0c vcmpneq_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0d vcmpgepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0d vcmpgepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0e vcmpgtpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0e vcmpgtpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 0f vcmptruepd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 0f vcmptruepd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 10 vcmpeq_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 10 vcmpeq_ospd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 11 vcmplt_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 11 vcmplt_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 12 vcmple_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 12 vcmple_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 13 vcmpunord_spd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 13 vcmpunord_spd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 14 vcmpneq_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 14 vcmpneq_uspd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 15 vcmpnlt_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 15 vcmpnlt_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 16 vcmpnle_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 16 vcmpnle_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 17 vcmpord_spd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 17 vcmpord_spd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 18 vcmpeq_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 18 vcmpeq_uspd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 19 vcmpnge_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 19 vcmpnge_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1a vcmpngt_uqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1a vcmpngt_uqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1b vcmpfalse_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1b vcmpfalse_ospd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1c vcmpneq_ospd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1c vcmpneq_ospd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1d vcmpge_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1d vcmpge_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1e vcmpgt_oqpd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1e vcmpgt_oqpd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c9 c2 d4 1f vcmptrue_uspd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 c2 39 1f vcmptrue_uspd xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 00 vcmpeqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 00 vcmpeqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 01 vcmpltps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 01 vcmpltps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 02 vcmpleps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 02 vcmpleps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 03 vcmpunordps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 03 vcmpunordps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 04 vcmpneqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 04 vcmpneqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 05 vcmpnltps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 05 vcmpnltps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 06 vcmpnleps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 06 vcmpnleps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 07 vcmpordps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 08 vcmpeq_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 08 vcmpeq_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 09 vcmpngeps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 09 vcmpngeps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0a vcmpngtps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0a vcmpngtps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0b vcmpfalseps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0b vcmpfalseps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0c vcmpneq_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0c vcmpneq_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0d vcmpgeps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0d vcmpgeps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0e vcmpgtps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0e vcmpgtps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 0f vcmptrueps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 0f vcmptrueps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 10 vcmpeq_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 10 vcmpeq_osps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 11 vcmplt_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 11 vcmplt_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 12 vcmple_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 12 vcmple_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 13 vcmpunord_sps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 13 vcmpunord_sps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 14 vcmpneq_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 14 vcmpneq_usps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 15 vcmpnlt_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 15 vcmpnlt_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 16 vcmpnle_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 16 vcmpnle_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 17 vcmpord_sps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 17 vcmpord_sps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 18 vcmpeq_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 18 vcmpeq_usps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 19 vcmpnge_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 19 vcmpnge_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1a vcmpngt_uqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1a vcmpngt_uqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1b vcmpfalse_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1b vcmpfalse_osps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1c vcmpneq_osps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1c vcmpneq_osps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1d vcmpge_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1d vcmpge_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1e vcmpgt_oqps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[rcx\],xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[rcx\],xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd xmm7,xmm2,xmm6,xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa +[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps xmm7,xmm2,xmm6,xmm4,0xa +[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa +[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa +[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e1 f9 7e e1 vmovq rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 f9 6e e1 vmovq xmm4,rcx +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si ecx,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si ecx,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 fb 2d cc vcvtsd2si rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 fb 2d 09 vcvtsd2si rcx,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 fb 2c cc vcvttsd2si rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 fb 2c 09 vcvttsd2si rcx,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 db 2a f1 vcvtsi2sd xmm6,xmm4,rcx +[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sd xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss xmm6,xmm4,rcx +[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 d9 22 f1 64 vpinsrq xmm6,xmm4,rcx,0x64 +[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq rcx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq QWORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 e9 6b fc 60 vfmaddsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6b 39 60 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6b 39 40 vfmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6f fc 60 vfmsubsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6f 39 60 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6f 39 40 vfmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7b fc 60 vfnmaddsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7b 39 60 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7b 39 40 vfnmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7f fc 60 vfnmsubsd xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7f 39 60 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7f 39 40 vfnmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5a 11 vcvtsd2ss xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5e d4 vdivsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5e 11 vdivsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5f d4 vmaxsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5f 11 vmaxsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5d d4 vminsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5d 11 vminsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 59 d4 vmulsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 59 11 vmulsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 51 d4 vsqrtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 51 11 vsqrtsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb 5c d4 vsubsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 10 vcmpeq_ossd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 11 vcmplt_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 11 vcmplt_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 12 vcmple_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 12 vcmple_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 13 vcmpunord_ssd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 13 vcmpunord_ssd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 14 vcmpneq_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 14 vcmpneq_ussd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 15 vcmpnlt_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 15 vcmpnlt_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 16 vcmpnle_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 16 vcmpnle_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 17 vcmpord_ssd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 17 vcmpord_ssd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 18 vcmpeq_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 18 vcmpeq_ussd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 19 vcmpnge_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 19 vcmpnge_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1a vcmpngt_uqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1a vcmpngt_uqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1b vcmpfalse_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1b vcmpfalse_ossd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1c vcmpneq_ossd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1c vcmpneq_ossd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1d vcmpge_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1d vcmpge_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1e vcmpgt_oqsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5a 11 vcvtss2sd xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5e d4 vdivss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5e 11 vdivss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5f d4 vmaxss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5f 11 vmaxss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5d d4 vminss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5d 11 vminss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 59 d4 vmulss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 59 11 vmulss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 53 d4 vrcpss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 53 11 vrcpss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 52 d4 vrsqrtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 52 11 vrsqrtss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 51 d4 vsqrtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 51 11 vsqrtss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca 5c d4 vsubss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 10 vcmpeq_osss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 11 vcmplt_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 11 vcmplt_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 12 vcmple_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 12 vcmple_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 13 vcmpunord_sss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 13 vcmpunord_sss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 14 vcmpneq_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 14 vcmpneq_usss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 15 vcmpnlt_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 15 vcmpnlt_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 16 vcmpnle_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 16 vcmpnle_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 17 vcmpord_sss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 17 vcmpord_sss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 18 vcmpeq_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 18 vcmpeq_usss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 19 vcmpnge_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 19 vcmpnge_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1a vcmpngt_uqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1a vcmpngt_uqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1b vcmpfalse_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1b vcmpfalse_osss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1c vcmpneq_osss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1c vcmpneq_osss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1d vcmpge_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1d vcmpge_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1e vcmpgt_oqss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1e vcmpgt_oqss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 1f vcmptrue_usss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca c2 11 1f vcmptrue_usss xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 7d 18 21 vbroadcastss ymm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 18 21 vbroadcastss xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd xmm4,ecx +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si ecx,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si ecx,xmm4 +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si ecx,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 fa 2d cc vcvtss2si rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 fa 2d 09 vcvtss2si rcx,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e1 fa 2c cc vcvttss2si rcx,xmm4 +[ ]*[a-f0-9]+: c4 e1 fa 2c 09 vcvttss2si rcx,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb ecx,xmm4 +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd xmm6,xmm4,ecx +[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss xmm6,xmm4,ecx +[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss xmm2,xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 e9 6a fc 60 vfmaddss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6a 39 60 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6a 39 40 vfmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6e fc 60 vfmsubss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 6e 39 60 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 6e 39 40 vfmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7a fc 60 vfnmaddss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7a 39 60 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7a 39 40 vfnmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7e fc 60 vfnmsubss xmm7,xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e3 e9 7e 39 60 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e3 69 7e 39 40 vfnmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq xmm6,xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[rcx\] +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4 +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps ecx,xmm4 +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb ecx,xmm4 +[ ]*[a-f0-9]+: c5 c8 12 d4 vmovhlps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4 +[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw xmm6,xmm4,0x64 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64 +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4 +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4 +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4 +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 ff e6 f4 vcvtpd2dq xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fd 5a f4 vcvtpd2ps xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq xmm6,xmm4 +[ ]*[a-f0-9]+: c5 fd e6 f4 vcvttpd2dq xmm6,ymm4 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 78 56 34 12 vldmxcsr DWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 79 6f 04 25 78 56 34 12 vmovdqa xmm8,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 79 7f 04 25 78 56 34 12 vmovdqa XMMWORD PTR ds:0x12345678,xmm8 +[ ]*[a-f0-9]+: c5 79 7e 04 25 78 56 34 12 vmovd DWORD PTR ds:0x12345678,xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 04 25 78 56 34 12 vcvtsd2si r8d,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 7e e6 04 25 78 56 34 12 vcvtdq2pd ymm8,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 7d 5a 04 25 78 56 34 12 vcvtpd2ps xmm8,YMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 39 e0 3c 25 78 56 34 12 vpavgb xmm15,xmm8,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 64 vpextrb BYTE PTR ds:0x12345678,xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 3c 25 78 56 34 12 vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c4 63 19 4a 34 25 78 56 34 12 80 vblendvps xmm14,xmm12,XMMWORD PTR ds:0x12345678,xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 64 vpinsrb xmm15,xmm8,BYTE PTR ds:0x12345678,0x64 +[ ]*[a-f0-9]+: c5 7d 6f 04 25 78 56 34 12 vmovdqa ymm8,YMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c5 7d 7f 04 25 78 56 34 12 vmovdqa YMMWORD PTR ds:0x12345678,ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 78 56 34 12 vpermilpd ymm15,ymm8,YMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 64 vroundpd ymm8,YMMWORD PTR ds:0x12345678,0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 64 vextractf128 XMMWORD PTR ds:0x12345678,ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 64 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 78 56 34 12 80 vblendvpd ymm14,ymm12,YMMWORD PTR ds:0x12345678,ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr DWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 79 6f 45 00 vmovdqa xmm8,XMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 79 7f 45 00 vmovdqa XMMWORD PTR \[rbp\+0x0\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 45 00 vmovd DWORD PTR \[rbp\+0x0\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 45 00 vcvtsd2si r8d,QWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 7e e6 45 00 vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 7d 5a 45 00 vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 39 e0 7d 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c4 63 79 14 45 00 64 vpextrb BYTE PTR \[rbp\+0x0\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 7d 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c4 63 19 4a 75 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+0x0\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 7d 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x0\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 45 00 vmovdqa ymm8,YMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c5 7d 7f 45 00 vmovdqa YMMWORD PTR \[rbp\+0x0\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 7d 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\] +[ ]*[a-f0-9]+: c4 63 7d 09 45 00 64 vroundpd ymm8,YMMWORD PTR \[rbp\+0x0\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 45 00 64 vextractf128 XMMWORD PTR \[rbp\+0x0\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 75 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+0x0\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr DWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 79 6f 85 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 79 7f 85 99 00 00 00 vmovdqa XMMWORD PTR \[rbp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 85 99 00 00 00 vmovd DWORD PTR \[rbp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 85 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 7e e6 85 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 85 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 39 e0 bd 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 64 vpextrb BYTE PTR \[rbp\+0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a bd 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a b5 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 85 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 85 99 00 00 00 vmovdqa YMMWORD PTR \[rbp\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d bd 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rbp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 64 vextractf128 XMMWORD PTR \[rbp\+0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b b5 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 c1 78 ae 97 99 00 00 00 vldmxcsr DWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 79 6f 87 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 79 7f 87 99 00 00 00 vmovdqa XMMWORD PTR \[r15\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 41 79 7e 87 99 00 00 00 vmovd DWORD PTR \[r15\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 41 7b 2d 87 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 7e e6 87 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 7d 5a 87 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 39 e0 bf 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 64 vpextrb BYTE PTR \[r15\+0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 41 3b 2a bf 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 43 19 4a b7 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r15\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[r15\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 41 7d 6f 87 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 41 7d 7f 87 99 00 00 00 vmovdqa YMMWORD PTR \[r15\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 42 3d 0d bf 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[r15\+0x99\] +[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[r15\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 64 vextractf128 XMMWORD PTR \[r15\+0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r15\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 43 1d 4b b7 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r15\+0x99\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr DWORD PTR \[rip\+0x99\] # 3bd9 <_start\+0x3bd9> +[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rip\+0x99\] # 3be1 <_start\+0x3be1> +[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa XMMWORD PTR \[rip\+0x99\],xmm8 # 3be9 <_start\+0x3be9> +[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd DWORD PTR \[rip\+0x99\],xmm8 # 3bf1 <_start\+0x3bf1> +[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rip\+0x99\] # 3bf9 <_start\+0x3bf9> +[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rip\+0x99\] # 3c01 <_start\+0x3c01> +[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rip\+0x99\] # 3c09 <_start\+0x3c09> +[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rip\+0x99\] # 3c11 <_start\+0x3c11> +[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 64 vpextrb BYTE PTR \[rip\+0x99\],xmm8,0x64 # 3c1b <_start\+0x3c1b> +[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # 3c23 <_start\+0x3c23> +[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rip\+0x99\],xmm8 # 3c2d <_start\+0x3c2d> +[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rip\+0x99\],0x64 # 3c37 <_start\+0x3c37> +[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rip\+0x99\] # 3c3f <_start\+0x3c3f> +[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa YMMWORD PTR \[rip\+0x99\],ymm8 # 3c47 <_start\+0x3c47> +[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rip\+0x99\] # 3c50 <_start\+0x3c50> +[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rip\+0x99\],0x64 # 3c5a <_start\+0x3c5a> +[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 64 vextractf128 XMMWORD PTR \[rip\+0x99\],ymm8,0x64 # 3c64 <_start\+0x3c64> +[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rip\+0x99\],0x64 # 3c6e <_start\+0x3c6e> +[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rip\+0x99\],ymm8 # 3c78 <_start\+0x3c78> +[ ]*[a-f0-9]+: c5 f8 ae 94 24 99 00 00 00 vldmxcsr DWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 79 6f 84 24 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 79 7f 84 24 99 00 00 00 vmovdqa XMMWORD PTR \[rsp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 84 24 99 00 00 00 vmovd DWORD PTR \[rsp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 84 24 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 7e e6 84 24 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 84 24 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 39 e0 bc 24 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 64 vpextrb BYTE PTR \[rsp\+0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a b4 24 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 84 24 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 84 24 99 00 00 00 vmovdqa YMMWORD PTR \[rsp\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d bc 24 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rsp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 64 vextractf128 XMMWORD PTR \[rsp\+0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 24 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 c1 78 ae 94 24 99 00 00 00 vldmxcsr DWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 79 6f 84 24 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 79 7f 84 24 99 00 00 00 vmovdqa XMMWORD PTR \[r12\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 41 79 7e 84 24 99 00 00 00 vmovd DWORD PTR \[r12\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 41 7b 2d 84 24 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 7e e6 84 24 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 7d 5a 84 24 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 39 e0 bc 24 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 64 vpextrb BYTE PTR \[r12\+0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 41 3b 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 43 19 4a b4 24 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r12\+0x99\],xmm8 +[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 41 7d 6f 84 24 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 41 7d 7f 84 24 99 00 00 00 vmovdqa YMMWORD PTR \[r12\+0x99\],ymm8 +[ ]*[a-f0-9]+: c4 42 3d 0d bc 24 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[r12\+0x99\] +[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[r12\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 64 vextractf128 XMMWORD PTR \[r12\+0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+0x99\],0x64 +[ ]*[a-f0-9]+: c4 43 1d 4b b4 24 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r12\+0x99\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 67 ff ff ff vldmxcsr DWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 79 6f 04 25 67 ff ff ff vmovdqa xmm8,XMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 79 7f 04 25 67 ff ff ff vmovdqa XMMWORD PTR ds:0xffffffffffffff67,xmm8 +[ ]*[a-f0-9]+: c5 79 7e 04 25 67 ff ff ff vmovd DWORD PTR ds:0xffffffffffffff67,xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 04 25 67 ff ff ff vcvtsd2si r8d,QWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 7e e6 04 25 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 7d 5a 04 25 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 39 e0 3c 25 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 64 vpextrb BYTE PTR ds:0xffffffffffffff67,xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 3c 25 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 63 19 4a 34 25 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR ds:0xffffffffffffff67,xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR ds:0xffffffffffffff67,0x64 +[ ]*[a-f0-9]+: c5 7d 6f 04 25 67 ff ff ff vmovdqa ymm8,YMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 7d 7f 04 25 67 ff ff ff vmovdqa YMMWORD PTR ds:0xffffffffffffff67,ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 64 vextractf128 XMMWORD PTR ds:0xffffffffffffff67,ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR ds:0xffffffffffffff67,ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 14 65 67 ff ff ff vldmxcsr DWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 79 6f 04 65 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 79 7f 04 65 67 ff ff ff vmovdqa XMMWORD PTR \[riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 04 65 67 ff ff ff vmovd DWORD PTR \[riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 04 65 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7e e6 04 65 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 04 65 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 39 e0 3c 65 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 64 vpextrb BYTE PTR \[riz\*2-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a 3c 65 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a 34 65 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 04 65 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 04 65 67 ff ff ff vmovdqa YMMWORD PTR \[riz\*2-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 65 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 64 vextractf128 XMMWORD PTR \[riz\*2-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 65 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[riz\*2-0x99\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 94 23 67 ff ff ff vldmxcsr DWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 79 6f 84 23 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 79 7f 84 23 67 ff ff ff vmovdqa XMMWORD PTR \[rbx\+riz\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 84 23 67 ff ff ff vmovd DWORD PTR \[rbx\+riz\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 84 23 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 7e e6 84 23 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 84 23 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 39 e0 bc 23 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 64 vpextrb BYTE PTR \[rbx\+riz\*1-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a bc 23 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a b4 23 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbx\+riz\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 84 23 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 84 23 67 ff ff ff vmovdqa YMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d bc 23 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 23 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8 +[ ]*[a-f0-9]+: c5 f8 ae 94 63 67 ff ff ff vldmxcsr DWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 79 6f 84 63 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 79 7f 84 63 67 ff ff ff vmovdqa XMMWORD PTR \[rbx\+riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 79 7e 84 63 67 ff ff ff vmovd DWORD PTR \[rbx\+riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c5 7b 2d 84 63 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7e e6 84 63 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7d 5a 84 63 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 39 e0 bc 63 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 64 vpextrb BYTE PTR \[rbx\+riz\*2-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c5 3b 2a bc 63 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 19 4a b4 63 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbx\+riz\*2-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c5 7d 6f 84 63 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c5 7d 7f 84 63 67 ff ff ff vmovdqa YMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 62 3d 0d bc 63 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\] +[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x64 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 63 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 81 78 ae 94 bc 67 ff ff ff vldmxcsr DWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 79 6f 84 bc 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 79 7f 84 bc 67 ff ff ff vmovdqa XMMWORD PTR \[r12\+r15\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 01 79 7e 84 bc 67 ff ff ff vmovd DWORD PTR \[r12\+r15\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 01 7b 2d 84 bc 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 7e e6 84 bc 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 7d 5a 84 bc 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 39 e0 bc bc 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 64 vpextrb BYTE PTR \[r12\+r15\*4-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 01 3b 2a bc bc 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 03 19 4a b4 bc 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r12\+r15\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+r15\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 01 7d 6f 84 bc 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 01 7d 7f 84 bc 67 ff ff ff vmovdqa YMMWORD PTR \[r12\+r15\*4-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 02 3d 0d bc bc 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\] +[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 64 vextractf128 XMMWORD PTR \[r12\+r15\*4-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 03 1d 4b b4 bc 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r12\+r15\*4-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 81 78 ae 94 f8 67 ff ff ff vldmxcsr DWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 79 6f 84 f8 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 79 7f 84 f8 67 ff ff ff vmovdqa XMMWORD PTR \[r8\+r15\*8-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 01 79 7e 84 f8 67 ff ff ff vmovd DWORD PTR \[r8\+r15\*8-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 01 7b 2d 84 f8 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 7e e6 84 f8 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 7d 5a 84 f8 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 39 e0 bc f8 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 64 vpextrb BYTE PTR \[r8\+r15\*8-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 01 3b 2a bc f8 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 03 19 4a b4 f8 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r8\+r15\*8-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[r8\+r15\*8-0x99\],0x64 +[ ]*[a-f0-9]+: c4 01 7d 6f 84 f8 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 01 7d 7f 84 f8 67 ff ff ff vmovdqa YMMWORD PTR \[r8\+r15\*8-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 02 3d 0d bc f8 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\] +[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x64 +[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 64 vextractf128 XMMWORD PTR \[r8\+r15\*8-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x64 +[ ]*[a-f0-9]+: c4 03 1d 4b b4 f8 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r8\+r15\*8-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 a1 78 ae 94 a5 67 ff ff ff vldmxcsr DWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 79 6f 84 a5 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 79 7f 84 a5 67 ff ff ff vmovdqa XMMWORD PTR \[rbp\+r12\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 21 79 7e 84 a5 67 ff ff ff vmovd DWORD PTR \[rbp\+r12\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 21 7b 2d 84 a5 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 7e e6 84 a5 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 7d 5a 84 a5 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 39 e0 bc a5 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 23 79 14 84 a5 67 ff ff ff 64 vpextrb BYTE PTR \[rbp\+r12\*4-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 21 3b 2a bc a5 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 23 19 4a b4 a5 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+r12\*4-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 23 39 20 bc a5 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+r12\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 21 7d 6f 84 a5 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 21 7d 7f 84 a5 67 ff ff ff vmovdqa YMMWORD PTR \[rbp\+r12\*4-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 22 3d 0d bc a5 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\] +[ ]*[a-f0-9]+: c4 23 7d 09 84 a5 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 23 7d 19 84 a5 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbp\+r12\*4-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 23 3d 06 bc a5 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\],0x64 +[ ]*[a-f0-9]+: c4 23 1d 4b b4 a5 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+r12\*4-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 a1 78 ae 94 2c 67 ff ff ff vldmxcsr DWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 79 6f 84 2c 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 79 7f 84 2c 67 ff ff ff vmovdqa XMMWORD PTR \[rsp\+r13\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 21 79 7e 84 2c 67 ff ff ff vmovd DWORD PTR \[rsp\+r13\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 21 7b 2d 84 2c 67 ff ff ff vcvtsd2si r8d,QWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 7e e6 84 2c 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 7d 5a 84 2c 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 39 e0 bc 2c 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 23 79 14 84 2c 67 ff ff ff 64 vpextrb BYTE PTR \[rsp\+r13\*1-0x99\],xmm8,0x64 +[ ]*[a-f0-9]+: c4 21 3b 2a bc 2c 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 23 19 4a b4 2c 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\+r13\*1-0x99\],xmm8 +[ ]*[a-f0-9]+: c4 23 39 20 bc 2c 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+r13\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 21 7d 6f 84 2c 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 21 7d 7f 84 2c 67 ff ff ff vmovdqa YMMWORD PTR \[rsp\+r13\*1-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 22 3d 0d bc 2c 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\] +[ ]*[a-f0-9]+: c4 23 7d 09 84 2c 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 23 7d 19 84 2c 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rsp\+r13\*1-0x99\],ymm8,0x64 +[ ]*[a-f0-9]+: c4 23 3d 06 bc 2c 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\],0x64 +[ ]*[a-f0-9]+: c4 23 1d 4b b4 2c 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\+r13\*1-0x99\],ymm8 +[ ]*[a-f0-9]+: c4 41 79 50 c0 vmovmskpd r8d,xmm8 +[ ]*[a-f0-9]+: c4 c1 01 72 f0 64 vpslld xmm15,xmm8,0x64 +[ ]*[a-f0-9]+: c4 41 7c 50 c0 vmovmskps r8d,ymm8 +[ ]*[a-f0-9]+: c4 41 79 6f f8 vmovdqa xmm15,xmm8 +[ ]*[a-f0-9]+: c4 41 79 7e c0 vmovd r8d,xmm8 +[ ]*[a-f0-9]+: c4 41 7b 2d c0 vcvtsd2si r8d,xmm8 +[ ]*[a-f0-9]+: c4 41 7e e6 c0 vcvtdq2pd ymm8,xmm8 +[ ]*[a-f0-9]+: c4 41 7d 5a c0 vcvtpd2ps xmm8,ymm8 +[ ]*[a-f0-9]+: c4 43 79 14 c0 64 vpextrb r8d,xmm8,0x64 +[ ]*[a-f0-9]+: c4 41 3b 2a f8 vcvtsi2sd xmm15,xmm8,r8d +[ ]*[a-f0-9]+: c4 43 19 4a f0 80 vblendvps xmm14,xmm12,xmm8,xmm8 +[ ]*[a-f0-9]+: c4 43 39 20 f8 64 vpinsrb xmm15,xmm8,r8d,0x64 +[ ]*[a-f0-9]+: c4 41 7d 6f f8 vmovdqa ymm15,ymm8 +[ ]*[a-f0-9]+: c4 42 05 0d e0 vpermilpd ymm12,ymm15,ymm8 +[ ]*[a-f0-9]+: c4 43 7d 09 f8 64 vroundpd ymm15,ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 7d 19 c0 64 vextractf128 xmm8,ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 05 06 e0 64 vperm2f128 ymm12,ymm15,ymm8,0x64 +[ ]*[a-f0-9]+: c4 43 1d 4b f7 80 vblendvpd ymm14,ymm12,ymm15,ymm8 +[ ]*[a-f0-9]+: c4 43 3d 18 f8 64 vinsertf128 ymm15,ymm8,xmm8,0x64 +[ ]*[a-f0-9]+: c4 61 fb 2d 01 vcvtsd2si r8,QWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 43 79 17 c0 0a vextractps r8d,xmm8,0xa +[ ]*[a-f0-9]+: c4 61 fa 2d 01 vcvtss2si r8,DWORD PTR \[rcx\] +[ ]*[a-f0-9]+: c4 41 01 c4 c0 64 vpinsrw xmm8,xmm15,r8d,0x64 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx.d b/gas/testsuite/gas/i386/x86-64-avx.d new file mode 100644 index 0000000..a3e551a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx.d @@ -0,0 +1,3046 @@ +#objdump: -dw +#name: x86-64 AVX + +.*: file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: c5 fc 77 vzeroall +[ ]*[a-f0-9]+: c5 f8 77 vzeroupper +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\) +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%rcx\) +[ ]*[a-f0-9]+: c4 e2 5d 2d 31 vmaskmovpd \(%rcx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd %ymm4,%ymm6,\(%rcx\) +[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps \(%rcx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%rcx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%rcx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%rcx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%rcx\),%ymm6 +[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 58 11 vaddps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd d0 d4 vaddsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd d0 11 vaddsubpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf d0 d4 vaddsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf d0 11 vaddsubps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 55 d4 vandnpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 55 11 vandnpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 55 d4 vandnps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 55 11 vandnps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 54 d4 vandpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 54 11 vandpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 54 d4 vandps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 54 11 vandps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5e d4 vdivpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5e 11 vdivpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5e d4 vdivps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5e 11 vdivps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7c d4 vhaddpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7c 11 vhaddpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7c d4 vhaddps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7c 11 vhaddps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7d d4 vhsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7d 11 vhsubpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7d d4 vhsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7d 11 vhsubps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5f d4 vmaxpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5f 11 vmaxpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5f d4 vmaxps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5f 11 vmaxps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5d d4 vminpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5d 11 vminpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5d d4 vminps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5d 11 vminps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 59 d4 vmulpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 59 11 vmulpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 59 d4 vmulps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 59 11 vmulps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 56 d4 vorpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 56 11 vorpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 56 d4 vorps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 56 11 vorps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0d d4 vpermilpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0d 11 vpermilpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0c d4 vpermilps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0c 11 vpermilps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5c d4 vsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5c 11 vsubpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5c d4 vsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5c 11 vsubps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 15 d4 vunpckhpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 15 11 vunpckhpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 15 d4 vunpckhps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 15 11 vunpckhps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 14 d4 vunpcklpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 14 11 vunpcklpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 14 d4 vunpcklps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 14 11 vunpcklps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 57 d4 vxorpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 57 11 vxorpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 57 d4 vxorps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 57 11 vxorps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 10 vcmpeq_ospd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 11 vcmplt_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 11 vcmplt_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 12 vcmple_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 12 vcmple_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 13 vcmpunord_spd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 13 vcmpunord_spd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 14 vcmpneq_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 14 vcmpneq_uspd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 15 vcmpnlt_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 15 vcmpnlt_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 16 vcmpnle_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 16 vcmpnle_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 17 vcmpord_spd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 17 vcmpord_spd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 18 vcmpeq_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 18 vcmpeq_uspd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 19 vcmpnge_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 19 vcmpnge_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1a vcmpngt_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1a vcmpngt_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1b vcmpfalse_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1b vcmpfalse_ospd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1c vcmpneq_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1c vcmpneq_ospd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1d vcmpge_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1d vcmpge_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1e vcmpgt_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1e vcmpgt_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1f vcmptrue_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 10 vcmpeq_osps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 11 vcmplt_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 11 vcmplt_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 12 vcmple_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 12 vcmple_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 13 vcmpunord_sps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 13 vcmpunord_sps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 14 vcmpneq_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 14 vcmpneq_usps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 15 vcmpnlt_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 15 vcmpnlt_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 16 vcmpnle_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 16 vcmpnle_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 17 vcmpord_sps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 17 vcmpord_sps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 18 vcmpeq_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 18 vcmpeq_usps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 19 vcmpnge_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 19 vcmpnge_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1a vcmpngt_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1a vcmpngt_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1b vcmpfalse_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1b vcmpfalse_osps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1c vcmpneq_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1c vcmpneq_osps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1d vcmpge_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1d vcmpge_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1e vcmpgt_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2psy \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dqy \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%rcx\),%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd \$0xa,%ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps \$0xa,%ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 \$0x64,%xmm4,%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%rcx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 \$0x64,%ymm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dqx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2psx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dqx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0e f4 vtestps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 0e 21 vtestps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0f f4 vtestpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 0f 21 vtestpd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fe e6 e4 vcvtdq2pd %xmm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe e6 21 vcvtdq2pd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 5a e4 vcvtps2pd %xmm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 5a 21 vcvtps2pd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 c9 58 d4 vaddpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 58 39 vaddpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 58 d4 vaddps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 58 39 vaddps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d0 d4 vaddsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d0 39 vaddsubpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb d0 d4 vaddsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb d0 39 vaddsubps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 55 d4 vandnpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 55 39 vandnpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 55 d4 vandnps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 55 39 vandnps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 54 d4 vandpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 54 39 vandpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 54 d4 vandps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 54 39 vandps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5e d4 vdivpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5e 39 vdivpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5e d4 vdivps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5e 39 vdivps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 7c d4 vhaddpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 7c 39 vhaddpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb 7c d4 vhaddps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 7c 39 vhaddps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 7d d4 vhsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 7d 39 vhsubpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb 7d d4 vhsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 7d 39 vhsubps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5f d4 vmaxpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5f 39 vmaxpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5f d4 vmaxps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5f 39 vmaxps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5d d4 vminpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5d 39 vminpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5d d4 vminps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5d 39 vminps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 59 d4 vmulpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 59 39 vmulpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 59 d4 vmulps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 59 39 vmulps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 56 d4 vorpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 56 39 vorpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 56 d4 vorps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 56 39 vorps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 63 d4 vpacksswb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 63 39 vpacksswb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6b d4 vpackssdw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6b 39 vpackssdw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 67 d4 vpackuswb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 67 39 vpackuswb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 2b d4 vpackusdw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 2b 39 vpackusdw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fc d4 vpaddb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fc 39 vpaddb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fd d4 vpaddw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fd 39 vpaddw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fe d4 vpaddd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fe 39 vpaddd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d4 d4 vpaddq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d4 39 vpaddq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ec d4 vpaddsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ec 39 vpaddsb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ed d4 vpaddsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ed 39 vpaddsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 dc d4 vpaddusb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 dc 39 vpaddusb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 dd d4 vpaddusw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 dd 39 vpaddusw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 db d4 vpand %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 db 39 vpand \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 df d4 vpandn %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 df 39 vpandn \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e0 d4 vpavgb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e0 39 vpavgb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e3 d4 vpavgw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e3 39 vpavgw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 74 d4 vpcmpeqb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 74 39 vpcmpeqb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 75 d4 vpcmpeqw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 75 39 vpcmpeqw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 76 d4 vpcmpeqd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 76 39 vpcmpeqd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 29 d4 vpcmpeqq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 29 39 vpcmpeqq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 64 d4 vpcmpgtb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 64 39 vpcmpgtb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 65 39 vpcmpgtw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 66 d4 vpcmpgtd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 66 39 vpcmpgtd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 37 d4 vpcmpgtq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 37 39 vpcmpgtq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0d d4 vpermilpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0d 39 vpermilpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0c d4 vpermilps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0c 39 vpermilps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 01 d4 vphaddw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 01 39 vphaddw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 02 d4 vphaddd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 02 39 vphaddd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 03 d4 vphaddsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 03 39 vphaddsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 05 d4 vphsubw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 05 39 vphsubw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 06 d4 vphsubd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 06 39 vphsubd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 07 d4 vphsubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 07 39 vphsubsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f5 39 vpmaddwd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 04 39 vpmaddubsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3c d4 vpmaxsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3c 39 vpmaxsb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ee d4 vpmaxsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ee 39 vpmaxsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3d d4 vpmaxsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3d 39 vpmaxsd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 de d4 vpmaxub %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 de 39 vpmaxub \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3e d4 vpmaxuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3e 39 vpmaxuw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3f d4 vpmaxud %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3f 39 vpmaxud \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 38 d4 vpminsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 38 39 vpminsb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ea d4 vpminsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ea 39 vpminsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 39 d4 vpminsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 39 39 vpminsd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 da d4 vpminub %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 da 39 vpminub \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3a d4 vpminuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3a 39 vpminuw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3b d4 vpminud %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3b 39 vpminud \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e4 d4 vpmulhuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e4 39 vpmulhuw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0b d4 vpmulhrsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0b 39 vpmulhrsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e5 d4 vpmulhw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e5 39 vpmulhw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d5 d4 vpmullw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d5 39 vpmullw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 40 d4 vpmulld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 40 39 vpmulld \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f4 d4 vpmuludq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f4 39 vpmuludq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 28 d4 vpmuldq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 28 39 vpmuldq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 eb d4 vpor %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 eb 39 vpor \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f6 d4 vpsadbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f6 39 vpsadbw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 00 d4 vpshufb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 00 39 vpshufb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 08 d4 vpsignb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 08 39 vpsignb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 09 d4 vpsignw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 09 39 vpsignw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0a d4 vpsignd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0a 39 vpsignd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f1 d4 vpsllw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f1 39 vpsllw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f2 d4 vpslld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f2 39 vpslld \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f3 d4 vpsllq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f3 39 vpsllq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e1 d4 vpsraw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e1 39 vpsraw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e2 d4 vpsrad %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e2 39 vpsrad \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d1 d4 vpsrlw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d1 39 vpsrlw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d2 d4 vpsrld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d2 39 vpsrld \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d3 d4 vpsrlq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d3 39 vpsrlq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f8 d4 vpsubb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f8 39 vpsubb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f9 d4 vpsubw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f9 39 vpsubw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fa d4 vpsubd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fa 39 vpsubd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fb d4 vpsubq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fb 39 vpsubq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e8 d4 vpsubsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e8 39 vpsubsb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e9 d4 vpsubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e9 39 vpsubsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d8 d4 vpsubusb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d8 39 vpsubusb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d9 d4 vpsubusw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d9 39 vpsubusw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 68 d4 vpunpckhbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 68 39 vpunpckhbw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 69 d4 vpunpckhwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 69 39 vpunpckhwd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6a d4 vpunpckhdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6a 39 vpunpckhdq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6d d4 vpunpckhqdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6d 39 vpunpckhqdq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 60 d4 vpunpcklbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 60 39 vpunpcklbw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 61 d4 vpunpcklwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 61 39 vpunpcklwd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 62 d4 vpunpckldq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 62 39 vpunpckldq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6c d4 vpunpcklqdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6c 39 vpunpcklqdq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ef d4 vpxor %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ef 39 vpxor \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5c d4 vsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5c 39 vsubpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5c d4 vsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5c 39 vsubps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 15 d4 vunpckhpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 15 39 vunpckhpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 15 d4 vunpckhps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 15 39 vunpckhps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 14 d4 vunpcklpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 14 39 vunpcklpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 14 d4 vunpcklps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 14 39 vunpcklps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 57 d4 vxorpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 57 39 vxorpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 57 d4 vxorps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 57 39 vxorps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 00 vcmpeqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 00 vcmpeqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 01 vcmpltpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 01 vcmpltpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 02 vcmplepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 02 vcmplepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 03 vcmpunordpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 03 vcmpunordpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 04 vcmpneqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 04 vcmpneqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 05 vcmpnltpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 05 vcmpnltpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 06 vcmpnlepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 06 vcmpnlepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 07 vcmpordpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 08 vcmpeq_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 08 vcmpeq_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 09 vcmpngepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 09 vcmpngepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0a vcmpngtpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0a vcmpngtpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0b vcmpfalsepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0b vcmpfalsepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0c vcmpneq_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0c vcmpneq_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0d vcmpgepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0d vcmpgepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0e vcmpgtpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0e vcmpgtpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0f vcmptruepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0f vcmptruepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 10 vcmpeq_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 10 vcmpeq_ospd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 11 vcmplt_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 11 vcmplt_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 12 vcmple_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 12 vcmple_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 13 vcmpunord_spd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 13 vcmpunord_spd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 14 vcmpneq_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 14 vcmpneq_uspd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 15 vcmpnlt_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 15 vcmpnlt_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 16 vcmpnle_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 16 vcmpnle_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 17 vcmpord_spd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 17 vcmpord_spd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 18 vcmpeq_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 18 vcmpeq_uspd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 19 vcmpnge_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 19 vcmpnge_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1a vcmpngt_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1a vcmpngt_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1b vcmpfalse_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1b vcmpfalse_ospd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1c vcmpneq_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1c vcmpneq_ospd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1d vcmpge_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1d vcmpge_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1e vcmpgt_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1e vcmpgt_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1f vcmptrue_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1f vcmptrue_uspd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 00 vcmpeqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 00 vcmpeqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 01 vcmpltps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 01 vcmpltps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 02 vcmpleps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 02 vcmpleps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 03 vcmpunordps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 03 vcmpunordps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 04 vcmpneqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 04 vcmpneqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 05 vcmpnltps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 05 vcmpnltps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 06 vcmpnleps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 06 vcmpnleps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 07 vcmpordps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 08 vcmpeq_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 08 vcmpeq_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 09 vcmpngeps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 09 vcmpngeps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0a vcmpngtps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0a vcmpngtps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0b vcmpfalseps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0b vcmpfalseps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0c vcmpneq_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0c vcmpneq_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0d vcmpgeps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0d vcmpgeps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0e vcmpgtps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0e vcmpgtps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0f vcmptrueps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0f vcmptrueps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 10 vcmpeq_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 10 vcmpeq_osps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 11 vcmplt_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 11 vcmplt_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 12 vcmple_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 12 vcmple_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 13 vcmpunord_sps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 13 vcmpunord_sps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 14 vcmpneq_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 14 vcmpneq_usps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 15 vcmpnlt_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 15 vcmpnlt_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 16 vcmpnle_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 16 vcmpnle_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 17 vcmpord_sps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 17 vcmpord_sps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 18 vcmpeq_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 18 vcmpeq_usps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 19 vcmpnge_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 19 vcmpnge_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1a vcmpngt_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1a vcmpngt_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1b vcmpfalse_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1b vcmpfalse_osps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1c vcmpneq_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1c vcmpneq_osps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1d vcmpge_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1d vcmpge_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1e vcmpgt_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%rcx\) +[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd \$0xa,%xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps \$0xa,%xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c4 e1 fb 2d cc vcvtsd2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2d 09 vcvtsd2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2c cc vcvttsd2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2c 09 vcvttsd2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 db 2a f1 vcvtsi2sd %rcx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sdq \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss %rcx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 d9 22 f1 64 vpinsrq \$0x64,%rcx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq \$0x64,%xmm4,%rcx +[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 e9 6b fc 60 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6b 39 60 vfmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6b 39 40 vfmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6f fc 60 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6f 39 60 vfmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6f 39 40 vfmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7b fc 60 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7b 39 60 vfnmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7b 39 40 vfnmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7f fc 60 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7f 39 60 vfnmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7f 39 40 vfnmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5a 11 vcvtsd2ss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5e d4 vdivsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5e 11 vdivsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5f d4 vmaxsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5f 11 vmaxsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5d d4 vminsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5d 11 vminsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 59 d4 vmulsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 59 11 vmulsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 51 d4 vsqrtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 51 11 vsqrtsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5c d4 vsubsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 10 vcmpeq_ossd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 11 vcmplt_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 11 vcmplt_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 12 vcmple_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 12 vcmple_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 13 vcmpunord_ssd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 13 vcmpunord_ssd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 14 vcmpneq_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 14 vcmpneq_ussd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 15 vcmpnlt_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 15 vcmpnlt_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 16 vcmpnle_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 16 vcmpnle_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 17 vcmpord_ssd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 17 vcmpord_ssd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 18 vcmpeq_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 18 vcmpeq_ussd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 19 vcmpnge_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 19 vcmpnge_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1a vcmpngt_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1a vcmpngt_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1b vcmpfalse_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1b vcmpfalse_ossd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1c vcmpneq_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1c vcmpneq_ossd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1d vcmpge_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1d vcmpge_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1e vcmpgt_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5a 11 vcvtss2sd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5e d4 vdivss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5e 11 vdivss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5f d4 vmaxss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5f 11 vmaxss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5d d4 vminss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5d 11 vminss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 59 d4 vmulss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 59 11 vmulss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 53 d4 vrcpss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 53 11 vrcpss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 52 d4 vrsqrtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 52 11 vrsqrtss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 51 d4 vsqrtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 51 11 vsqrtss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5c d4 vsubss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 10 vcmpeq_osss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 11 vcmplt_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 11 vcmplt_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 12 vcmple_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 12 vcmple_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 13 vcmpunord_sss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 13 vcmpunord_sss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 14 vcmpneq_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 14 vcmpneq_usss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 15 vcmpnlt_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 15 vcmpnlt_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 16 vcmpnle_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 16 vcmpnle_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 17 vcmpord_sss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 17 vcmpord_sss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 18 vcmpeq_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 18 vcmpeq_usss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 19 vcmpnge_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 19 vcmpnge_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1a vcmpngt_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1a vcmpngt_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1b vcmpfalse_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1b vcmpfalse_osss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1c vcmpneq_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1c vcmpneq_osss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1d vcmpge_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1d vcmpge_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1e vcmpgt_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1e vcmpgt_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1f vcmptrue_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1f vcmptrue_usss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 7d 18 21 vbroadcastss \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 18 21 vbroadcastss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c4 e1 fa 2d cc vcvtss2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2d 09 vcvtss2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2c cc vcvttss2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2c 09 vcvttss2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd %ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss %ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 e9 6a fc 60 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6a 39 60 vfmaddss \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6a 39 40 vfmaddss %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6e fc 60 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6e 39 60 vfmsubss \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6e 39 40 vfmsubss %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7a fc 60 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7a 39 60 vfnmaddss \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7a 39 40 vfnmaddss %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7e fc 60 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7e 39 60 vfnmsubss \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7e 39 40 vfnmsubss %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c5 c8 12 d4 vmovhlps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 ff e6 f4 vcvtpd2dq %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fd 5a f4 vcvtpd2ps %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fd e6 f4 vcvttpd2dq %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 78 56 34 12 vldmxcsr 0x12345678 +[ ]*[a-f0-9]+: c5 79 6f 04 25 78 56 34 12 vmovdqa 0x12345678,%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 04 25 78 56 34 12 vmovdqa %xmm8,0x12345678 +[ ]*[a-f0-9]+: c5 79 7e 04 25 78 56 34 12 vmovd %xmm8,0x12345678 +[ ]*[a-f0-9]+: c5 7b 2d 04 25 78 56 34 12 vcvtsd2si 0x12345678,%r8d +[ ]*[a-f0-9]+: c5 7e e6 04 25 78 56 34 12 vcvtdq2pd 0x12345678,%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 04 25 78 56 34 12 vcvtpd2psy 0x12345678,%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 3c 25 78 56 34 12 vpavgb 0x12345678,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 64 vpextrb \$0x64,%xmm8,0x12345678 +[ ]*[a-f0-9]+: c5 3b 2a 3c 25 78 56 34 12 vcvtsi2sdl 0x12345678,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 34 25 78 56 34 12 80 vblendvps %xmm8,0x12345678,%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 64 vpinsrb \$0x64,0x12345678,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 04 25 78 56 34 12 vmovdqa 0x12345678,%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 04 25 78 56 34 12 vmovdqa %ymm8,0x12345678 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 78 56 34 12 vpermilpd 0x12345678,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 64 vroundpd \$0x64,0x12345678,%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 64 vextractf128 \$0x64,%ymm8,0x12345678 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 64 vperm2f128 \$0x64,0x12345678,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 78 56 34 12 80 vblendvpd %ymm8,0x12345678,%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%rbp\) +[ ]*[a-f0-9]+: c5 79 6f 45 00 vmovdqa 0x0\(%rbp\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 45 00 vmovdqa %xmm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c5 79 7e 45 00 vmovd %xmm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c5 7b 2d 45 00 vcvtsd2si 0x0\(%rbp\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 45 00 vcvtdq2pd 0x0\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 45 00 vcvtpd2psy 0x0\(%rbp\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 7d 00 vpavgb 0x0\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 45 00 64 vpextrb \$0x64,%xmm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c5 3b 2a 7d 00 vcvtsi2sdl 0x0\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 75 00 80 vblendvps %xmm8,0x0\(%rbp\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 7d 00 64 vpinsrb \$0x64,0x0\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 45 00 vmovdqa 0x0\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 45 00 vmovdqa %ymm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c4 62 3d 0d 7d 00 vpermilpd 0x0\(%rbp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 45 00 64 vroundpd \$0x64,0x0\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 45 00 64 vextractf128 \$0x64,%ymm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 64 vperm2f128 \$0x64,0x0\(%rbp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 75 00 80 vblendvpd %ymm8,0x0\(%rbp\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 14 24 vldmxcsr \(%rsp\) +[ ]*[a-f0-9]+: c5 79 6f 04 24 vmovdqa \(%rsp\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 04 24 vmovdqa %xmm8,\(%rsp\) +[ ]*[a-f0-9]+: c5 79 7e 04 24 vmovd %xmm8,\(%rsp\) +[ ]*[a-f0-9]+: c5 7b 2d 04 24 vcvtsd2si \(%rsp\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 04 24 vcvtdq2pd \(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 04 24 vcvtpd2psy \(%rsp\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 3c 24 vpavgb \(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 04 24 64 vpextrb \$0x64,%xmm8,\(%rsp\) +[ ]*[a-f0-9]+: c5 3b 2a 3c 24 vcvtsi2sdl \(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 34 24 80 vblendvps %xmm8,\(%rsp\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 3c 24 64 vpinsrb \$0x64,\(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 04 24 vmovdqa \(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 04 24 vmovdqa %ymm8,\(%rsp\) +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 24 vpermilpd \(%rsp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 04 24 64 vroundpd \$0x64,\(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 04 24 64 vextractf128 \$0x64,%ymm8,\(%rsp\) +[ ]*[a-f0-9]+: c4 63 3d 06 3c 24 64 vperm2f128 \$0x64,\(%rsp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 24 80 vblendvpd %ymm8,\(%rsp\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr 0x99\(%rbp\) +[ ]*[a-f0-9]+: c5 79 6f 85 99 00 00 00 vmovdqa 0x99\(%rbp\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 85 99 00 00 00 vmovdqa %xmm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c5 79 7e 85 99 00 00 00 vmovd %xmm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c5 7b 2d 85 99 00 00 00 vcvtsd2si 0x99\(%rbp\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 85 99 00 00 00 vcvtdq2pd 0x99\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 85 99 00 00 00 vcvtpd2psy 0x99\(%rbp\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 bd 99 00 00 00 vpavgb 0x99\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c5 3b 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a b5 99 00 00 00 80 vblendvps %xmm8,0x99\(%rbp\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 85 99 00 00 00 vmovdqa 0x99\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 85 99 00 00 00 vmovdqa %ymm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c4 62 3d 0d bd 99 00 00 00 vpermilpd 0x99\(%rbp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 64 vroundpd \$0x64,0x99\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rbp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b b5 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rbp\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 c1 78 ae 97 99 00 00 00 vldmxcsr 0x99\(%r15\) +[ ]*[a-f0-9]+: c4 41 79 6f 87 99 00 00 00 vmovdqa 0x99\(%r15\),%xmm8 +[ ]*[a-f0-9]+: c4 41 79 7f 87 99 00 00 00 vmovdqa %xmm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 41 79 7e 87 99 00 00 00 vmovd %xmm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 41 7b 2d 87 99 00 00 00 vcvtsd2si 0x99\(%r15\),%r8d +[ ]*[a-f0-9]+: c4 41 7e e6 87 99 00 00 00 vcvtdq2pd 0x99\(%r15\),%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 5a 87 99 00 00 00 vcvtpd2psy 0x99\(%r15\),%xmm8 +[ ]*[a-f0-9]+: c4 41 39 e0 bf 99 00 00 00 vpavgb 0x99\(%r15\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 41 3b 2a bf 99 00 00 00 vcvtsi2sdl 0x99\(%r15\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 19 4a b7 99 00 00 00 80 vblendvps %xmm8,0x99\(%r15\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 64 vpinsrb \$0x64,0x99\(%r15\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 7d 6f 87 99 00 00 00 vmovdqa 0x99\(%r15\),%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 7f 87 99 00 00 00 vmovdqa %ymm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 42 3d 0d bf 99 00 00 00 vpermilpd 0x99\(%r15\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 64 vroundpd \$0x64,0x99\(%r15\),%ymm8 +[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%r15\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 1d 4b b7 99 00 00 00 80 vblendvpd %ymm8,0x99\(%r15\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr 0x99\(%rip\) # 1a27 <_start\+0x1a27> +[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%xmm8 # 1a2f <_start\+0x1a2f> +[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa %xmm8,0x99\(%rip\) # 1a37 <_start\+0x1a37> +[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd %xmm8,0x99\(%rip\) # 1a3f <_start\+0x1a3f> +[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si 0x99\(%rip\),%r8d # 1a47 <_start\+0x1a47> +[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd 0x99\(%rip\),%ymm8 # 1a4f <_start\+0x1a4f> +[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2psy 0x99\(%rip\),%xmm8 # 1a57 <_start\+0x1a57> +[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb 0x99\(%rip\),%xmm8,%xmm15 # 1a5f <_start\+0x1a5f> +[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rip\) # 1a69 <_start\+0x1a69> +[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # 1a71 <_start\+0x1a71> +[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps %xmm8,0x99\(%rip\),%xmm12,%xmm14 # 1a7b <_start\+0x1a7b> +[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rip\),%xmm8,%xmm15 # 1a85 <_start\+0x1a85> +[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%ymm8 # 1a8d <_start\+0x1a8d> +[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa %ymm8,0x99\(%rip\) # 1a95 <_start\+0x1a95> +[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd 0x99\(%rip\),%ymm8,%ymm15 # 1a9e <_start\+0x1a9e> +[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 64 vroundpd \$0x64,0x99\(%rip\),%ymm8 # 1aa8 <_start\+0x1aa8> +[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rip\) # 1ab2 <_start\+0x1ab2> +[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rip\),%ymm8,%ymm15 # 1abc <_start\+0x1abc> +[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rip\),%ymm12,%ymm14 # 1ac6 <_start\+0x1ac6> +[ ]*[a-f0-9]+: c5 f8 ae 94 24 99 00 00 00 vldmxcsr 0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 79 6f 84 24 99 00 00 00 vmovdqa 0x99\(%rsp\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 84 24 99 00 00 00 vmovdqa %xmm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 79 7e 84 24 99 00 00 00 vmovd %xmm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 7b 2d 84 24 99 00 00 00 vcvtsd2si 0x99\(%rsp\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 84 24 99 00 00 00 vcvtdq2pd 0x99\(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 84 24 99 00 00 00 vcvtpd2psy 0x99\(%rsp\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 bc 24 99 00 00 00 vpavgb 0x99\(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 3b 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a b4 24 99 00 00 00 80 vblendvps %xmm8,0x99\(%rsp\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 84 24 99 00 00 00 vmovdqa 0x99\(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 84 24 99 00 00 00 vmovdqa %ymm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c4 62 3d 0d bc 24 99 00 00 00 vpermilpd 0x99\(%rsp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 64 vroundpd \$0x64,0x99\(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rsp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 24 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rsp\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 c1 78 ae 94 24 99 00 00 00 vldmxcsr 0x99\(%r12\) +[ ]*[a-f0-9]+: c4 41 79 6f 84 24 99 00 00 00 vmovdqa 0x99\(%r12\),%xmm8 +[ ]*[a-f0-9]+: c4 41 79 7f 84 24 99 00 00 00 vmovdqa %xmm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 41 79 7e 84 24 99 00 00 00 vmovd %xmm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 41 7b 2d 84 24 99 00 00 00 vcvtsd2si 0x99\(%r12\),%r8d +[ ]*[a-f0-9]+: c4 41 7e e6 84 24 99 00 00 00 vcvtdq2pd 0x99\(%r12\),%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 5a 84 24 99 00 00 00 vcvtpd2psy 0x99\(%r12\),%xmm8 +[ ]*[a-f0-9]+: c4 41 39 e0 bc 24 99 00 00 00 vpavgb 0x99\(%r12\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 41 3b 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%r12\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 19 4a b4 24 99 00 00 00 80 vblendvps %xmm8,0x99\(%r12\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 64 vpinsrb \$0x64,0x99\(%r12\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 7d 6f 84 24 99 00 00 00 vmovdqa 0x99\(%r12\),%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 7f 84 24 99 00 00 00 vmovdqa %ymm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 42 3d 0d bc 24 99 00 00 00 vpermilpd 0x99\(%r12\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 64 vroundpd \$0x64,0x99\(%r12\),%ymm8 +[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%r12\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 1d 4b b4 24 99 00 00 00 80 vblendvpd %ymm8,0x99\(%r12\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 67 ff ff ff vldmxcsr 0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 79 6f 04 25 67 ff ff ff vmovdqa 0xffffffffffffff67,%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 04 25 67 ff ff ff vmovdqa %xmm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 79 7e 04 25 67 ff ff ff vmovd %xmm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 7b 2d 04 25 67 ff ff ff vcvtsd2si 0xffffffffffffff67,%r8d +[ ]*[a-f0-9]+: c5 7e e6 04 25 67 ff ff ff vcvtdq2pd 0xffffffffffffff67,%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 04 25 67 ff ff ff vcvtpd2psy 0xffffffffffffff67,%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 3c 25 67 ff ff ff vpavgb 0xffffffffffffff67,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 64 vpextrb \$0x64,%xmm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 3b 2a 3c 25 67 ff ff ff vcvtsi2sdl 0xffffffffffffff67,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 34 25 67 ff ff ff 80 vblendvps %xmm8,0xffffffffffffff67,%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 64 vpinsrb \$0x64,0xffffffffffffff67,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 04 25 67 ff ff ff vmovdqa 0xffffffffffffff67,%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 04 25 67 ff ff ff vmovdqa %ymm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 67 ff ff ff vpermilpd 0xffffffffffffff67,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 64 vroundpd \$0x64,0xffffffffffffff67,%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 64 vperm2f128 \$0x64,0xffffffffffffff67,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 67 ff ff ff 80 vblendvpd %ymm8,0xffffffffffffff67,%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 14 65 67 ff ff ff vldmxcsr -0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c5 79 6f 04 65 67 ff ff ff vmovdqa -0x99\(,%riz,2\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 04 65 67 ff ff ff vmovdqa %xmm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c5 79 7e 04 65 67 ff ff ff vmovd %xmm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c5 7b 2d 04 65 67 ff ff ff vcvtsd2si -0x99\(,%riz,2\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 04 65 67 ff ff ff vcvtdq2pd -0x99\(,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 04 65 67 ff ff ff vcvtpd2psy -0x99\(,%riz,2\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 3c 65 67 ff ff ff vpavgb -0x99\(,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c5 3b 2a 3c 65 67 ff ff ff vcvtsi2sdl -0x99\(,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 34 65 67 ff ff ff 80 vblendvps %xmm8,-0x99\(,%riz,2\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 04 65 67 ff ff ff vmovdqa -0x99\(,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 04 65 67 ff ff ff vmovdqa %ymm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 65 67 ff ff ff vpermilpd -0x99\(,%riz,2\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 64 vroundpd \$0x64,-0x99\(,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(,%riz,2\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 65 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(,%riz,2\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 94 23 67 ff ff ff vldmxcsr -0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c5 79 6f 84 23 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,1\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 84 23 67 ff ff ff vmovdqa %xmm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c5 79 7e 84 23 67 ff ff ff vmovd %xmm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c5 7b 2d 84 23 67 ff ff ff vcvtsd2si -0x99\(%rbx,%riz,1\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 84 23 67 ff ff ff vcvtdq2pd -0x99\(%rbx,%riz,1\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 84 23 67 ff ff ff vcvtpd2psy -0x99\(%rbx,%riz,1\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 bc 23 67 ff ff ff vpavgb -0x99\(%rbx,%riz,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c5 3b 2a bc 23 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a b4 23 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbx,%riz,1\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbx,%riz,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 84 23 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,1\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 84 23 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c4 62 3d 0d bc 23 67 ff ff ff vpermilpd -0x99\(%rbx,%riz,1\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbx,%riz,1\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbx,%riz,1\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 23 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbx,%riz,1\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 94 63 67 ff ff ff vldmxcsr -0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c5 79 6f 84 63 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,2\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 84 63 67 ff ff ff vmovdqa %xmm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c5 79 7e 84 63 67 ff ff ff vmovd %xmm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c5 7b 2d 84 63 67 ff ff ff vcvtsd2si -0x99\(%rbx,%riz,2\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 84 63 67 ff ff ff vcvtdq2pd -0x99\(%rbx,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 84 63 67 ff ff ff vcvtpd2psy -0x99\(%rbx,%riz,2\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 bc 63 67 ff ff ff vpavgb -0x99\(%rbx,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c5 3b 2a bc 63 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a b4 63 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbx,%riz,2\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbx,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 84 63 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 84 63 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c4 62 3d 0d bc 63 67 ff ff ff vpermilpd -0x99\(%rbx,%riz,2\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbx,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbx,%riz,2\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 63 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbx,%riz,2\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 81 78 ae 94 bc 67 ff ff ff vldmxcsr -0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 01 79 6f 84 bc 67 ff ff ff vmovdqa -0x99\(%r12,%r15,4\),%xmm8 +[ ]*[a-f0-9]+: c4 01 79 7f 84 bc 67 ff ff ff vmovdqa %xmm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 01 79 7e 84 bc 67 ff ff ff vmovd %xmm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 01 7b 2d 84 bc 67 ff ff ff vcvtsd2si -0x99\(%r12,%r15,4\),%r8d +[ ]*[a-f0-9]+: c4 01 7e e6 84 bc 67 ff ff ff vcvtdq2pd -0x99\(%r12,%r15,4\),%ymm8 +[ ]*[a-f0-9]+: c4 01 7d 5a 84 bc 67 ff ff ff vcvtpd2psy -0x99\(%r12,%r15,4\),%xmm8 +[ ]*[a-f0-9]+: c4 01 39 e0 bc bc 67 ff ff ff vpavgb -0x99\(%r12,%r15,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 01 3b 2a bc bc 67 ff ff ff vcvtsi2sdl -0x99\(%r12,%r15,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 03 19 4a b4 bc 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%r12,%r15,4\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%r12,%r15,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 01 7d 6f 84 bc 67 ff ff ff vmovdqa -0x99\(%r12,%r15,4\),%ymm8 +[ ]*[a-f0-9]+: c4 01 7d 7f 84 bc 67 ff ff ff vmovdqa %ymm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 02 3d 0d bc bc 67 ff ff ff vpermilpd -0x99\(%r12,%r15,4\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%r12,%r15,4\),%ymm8 +[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%r12,%r15,4\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 03 1d 4b b4 bc 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%r12,%r15,4\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 81 78 ae 94 f8 67 ff ff ff vldmxcsr -0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 01 79 6f 84 f8 67 ff ff ff vmovdqa -0x99\(%r8,%r15,8\),%xmm8 +[ ]*[a-f0-9]+: c4 01 79 7f 84 f8 67 ff ff ff vmovdqa %xmm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 01 79 7e 84 f8 67 ff ff ff vmovd %xmm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 01 7b 2d 84 f8 67 ff ff ff vcvtsd2si -0x99\(%r8,%r15,8\),%r8d +[ ]*[a-f0-9]+: c4 01 7e e6 84 f8 67 ff ff ff vcvtdq2pd -0x99\(%r8,%r15,8\),%ymm8 +[ ]*[a-f0-9]+: c4 01 7d 5a 84 f8 67 ff ff ff vcvtpd2psy -0x99\(%r8,%r15,8\),%xmm8 +[ ]*[a-f0-9]+: c4 01 39 e0 bc f8 67 ff ff ff vpavgb -0x99\(%r8,%r15,8\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 01 3b 2a bc f8 67 ff ff ff vcvtsi2sdl -0x99\(%r8,%r15,8\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 03 19 4a b4 f8 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%r8,%r15,8\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%r8,%r15,8\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 01 7d 6f 84 f8 67 ff ff ff vmovdqa -0x99\(%r8,%r15,8\),%ymm8 +[ ]*[a-f0-9]+: c4 01 7d 7f 84 f8 67 ff ff ff vmovdqa %ymm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 02 3d 0d bc f8 67 ff ff ff vpermilpd -0x99\(%r8,%r15,8\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%r8,%r15,8\),%ymm8 +[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%r8,%r15,8\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 03 1d 4b b4 f8 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%r8,%r15,8\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 a1 78 ae 94 ad 67 ff ff ff vldmxcsr -0x99\(%rbp,%r13,4\) +[ ]*[a-f0-9]+: c4 21 79 6f 84 ad 67 ff ff ff vmovdqa -0x99\(%rbp,%r13,4\),%xmm8 +[ ]*[a-f0-9]+: c4 21 79 7f 84 ad 67 ff ff ff vmovdqa %xmm8,-0x99\(%rbp,%r13,4\) +[ ]*[a-f0-9]+: c4 21 79 7e 84 ad 67 ff ff ff vmovd %xmm8,-0x99\(%rbp,%r13,4\) +[ ]*[a-f0-9]+: c4 21 7b 2d 84 ad 67 ff ff ff vcvtsd2si -0x99\(%rbp,%r13,4\),%r8d +[ ]*[a-f0-9]+: c4 21 7e e6 84 ad 67 ff ff ff vcvtdq2pd -0x99\(%rbp,%r13,4\),%ymm8 +[ ]*[a-f0-9]+: c4 21 7d 5a 84 ad 67 ff ff ff vcvtpd2psy -0x99\(%rbp,%r13,4\),%xmm8 +[ ]*[a-f0-9]+: c4 21 39 e0 bc ad 67 ff ff ff vpavgb -0x99\(%rbp,%r13,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 23 79 14 84 ad 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbp,%r13,4\) +[ ]*[a-f0-9]+: c4 21 3b 2a bc ad 67 ff ff ff vcvtsi2sdl -0x99\(%rbp,%r13,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 23 19 4a b4 ad 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbp,%r13,4\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 23 39 20 bc ad 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbp,%r13,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 21 7d 6f 84 ad 67 ff ff ff vmovdqa -0x99\(%rbp,%r13,4\),%ymm8 +[ ]*[a-f0-9]+: c4 21 7d 7f 84 ad 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbp,%r13,4\) +[ ]*[a-f0-9]+: c4 22 3d 0d bc ad 67 ff ff ff vpermilpd -0x99\(%rbp,%r13,4\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 23 7d 09 84 ad 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbp,%r13,4\),%ymm8 +[ ]*[a-f0-9]+: c4 23 7d 19 84 ad 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbp,%r13,4\) +[ ]*[a-f0-9]+: c4 23 3d 06 bc ad 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbp,%r13,4\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 23 1d 4b b4 ad 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbp,%r13,4\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 a1 78 ae 94 24 67 ff ff ff vldmxcsr -0x99\(%rsp,%r12,1\) +[ ]*[a-f0-9]+: c4 21 79 6f 84 24 67 ff ff ff vmovdqa -0x99\(%rsp,%r12,1\),%xmm8 +[ ]*[a-f0-9]+: c4 21 79 7f 84 24 67 ff ff ff vmovdqa %xmm8,-0x99\(%rsp,%r12,1\) +[ ]*[a-f0-9]+: c4 21 79 7e 84 24 67 ff ff ff vmovd %xmm8,-0x99\(%rsp,%r12,1\) +[ ]*[a-f0-9]+: c4 21 7b 2d 84 24 67 ff ff ff vcvtsd2si -0x99\(%rsp,%r12,1\),%r8d +[ ]*[a-f0-9]+: c4 21 7e e6 84 24 67 ff ff ff vcvtdq2pd -0x99\(%rsp,%r12,1\),%ymm8 +[ ]*[a-f0-9]+: c4 21 7d 5a 84 24 67 ff ff ff vcvtpd2psy -0x99\(%rsp,%r12,1\),%xmm8 +[ ]*[a-f0-9]+: c4 21 39 e0 bc 24 67 ff ff ff vpavgb -0x99\(%rsp,%r12,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 23 79 14 84 24 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rsp,%r12,1\) +[ ]*[a-f0-9]+: c4 21 3b 2a bc 24 67 ff ff ff vcvtsi2sdl -0x99\(%rsp,%r12,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 23 19 4a b4 24 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rsp,%r12,1\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 23 39 20 bc 24 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rsp,%r12,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 21 7d 6f 84 24 67 ff ff ff vmovdqa -0x99\(%rsp,%r12,1\),%ymm8 +[ ]*[a-f0-9]+: c4 21 7d 7f 84 24 67 ff ff ff vmovdqa %ymm8,-0x99\(%rsp,%r12,1\) +[ ]*[a-f0-9]+: c4 22 3d 0d bc 24 67 ff ff ff vpermilpd -0x99\(%rsp,%r12,1\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 23 7d 09 84 24 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rsp,%r12,1\),%ymm8 +[ ]*[a-f0-9]+: c4 23 7d 19 84 24 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rsp,%r12,1\) +[ ]*[a-f0-9]+: c4 23 3d 06 bc 24 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rsp,%r12,1\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 23 1d 4b b4 24 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rsp,%r12,1\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 41 79 50 c0 vmovmskpd %xmm8,%r8d +[ ]*[a-f0-9]+: c4 c1 01 72 f0 64 vpslld \$0x64,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 7c 50 c0 vmovmskps %ymm8,%r8d +[ ]*[a-f0-9]+: c4 41 79 6f f8 vmovdqa %xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 79 7e c0 vmovd %xmm8,%r8d +[ ]*[a-f0-9]+: c4 41 7b 2d c0 vcvtsd2si %xmm8,%r8d +[ ]*[a-f0-9]+: c4 41 7e e6 c0 vcvtdq2pd %xmm8,%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 5a c0 vcvtpd2ps %ymm8,%xmm8 +[ ]*[a-f0-9]+: c4 43 79 14 c0 64 vpextrb \$0x64,%xmm8,%r8d +[ ]*[a-f0-9]+: c4 41 3b 2a f8 vcvtsi2sd %r8d,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 19 4a f0 80 vblendvps %xmm8,%xmm8,%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 43 39 20 f8 64 vpinsrb \$0x64,%r8d,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 7d 6f f8 vmovdqa %ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 42 05 0d e0 vpermilpd %ymm8,%ymm15,%ymm12 +[ ]*[a-f0-9]+: c4 43 7d 09 f8 64 vroundpd \$0x64,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 7d 19 c0 64 vextractf128 \$0x64,%ymm8,%xmm8 +[ ]*[a-f0-9]+: c4 43 05 06 e0 64 vperm2f128 \$0x64,%ymm8,%ymm15,%ymm12 +[ ]*[a-f0-9]+: c4 43 1d 4b f7 80 vblendvpd %ymm8,%ymm15,%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 43 3d 18 f8 64 vinsertf128 \$0x64,%xmm8,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 61 fb 2d 01 vcvtsd2si \(%rcx\),%r8 +[ ]*[a-f0-9]+: c4 43 79 17 c0 0a vextractps \$0xa,%xmm8,%r8d +[ ]*[a-f0-9]+: c4 61 fa 2d 01 vcvtss2si \(%rcx\),%r8 +[ ]*[a-f0-9]+: c4 41 01 c4 c0 64 vpinsrw \$0x64,%r8d,%xmm15,%xmm8 +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\) +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%rcx\) +[ ]*[a-f0-9]+: c4 e2 5d 2d 31 vmaskmovpd \(%rcx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd %ymm4,%ymm6,\(%rcx\) +[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps \(%rcx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%rcx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%rcx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%rcx\),%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps \$0x64,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%rcx\),%ymm6 +[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 58 11 vaddps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd d0 d4 vaddsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd d0 11 vaddsubpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf d0 d4 vaddsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf d0 11 vaddsubps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 55 d4 vandnpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 55 11 vandnpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 55 d4 vandnps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 55 11 vandnps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 54 d4 vandpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 54 11 vandpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 54 d4 vandps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 54 11 vandps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5e d4 vdivpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5e 11 vdivpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5e d4 vdivps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5e 11 vdivps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7c d4 vhaddpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7c 11 vhaddpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7c d4 vhaddps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7c 11 vhaddps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7d d4 vhsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 7d 11 vhsubpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7d d4 vhsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cf 7d 11 vhsubps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5f d4 vmaxpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5f 11 vmaxpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5f d4 vmaxps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5f 11 vmaxps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5d d4 vminpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5d 11 vminpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5d d4 vminps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5d 11 vminps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 59 d4 vmulpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 59 11 vmulpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 59 d4 vmulps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 59 11 vmulps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 56 d4 vorpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 56 11 vorpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 56 d4 vorps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 56 11 vorps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0d d4 vpermilpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0d 11 vpermilpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0c d4 vpermilps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d 0c 11 vpermilps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5c d4 vsubpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 5c 11 vsubpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5c d4 vsubps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 5c 11 vsubps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 15 d4 vunpckhpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 15 11 vunpckhpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 15 d4 vunpckhps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 15 11 vunpckhps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 14 d4 vunpcklpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 14 11 vunpcklpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 14 d4 vunpcklps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 14 11 vunpcklps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 57 d4 vxorpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd 57 11 vxorpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 57 d4 vxorps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc 57 11 vxorps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 10 vcmpeq_ospd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 11 vcmplt_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 11 vcmplt_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 12 vcmple_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 12 vcmple_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 13 vcmpunord_spd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 13 vcmpunord_spd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 14 vcmpneq_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 14 vcmpneq_uspd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 15 vcmpnlt_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 15 vcmpnlt_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 16 vcmpnle_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 16 vcmpnle_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 17 vcmpord_spd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 17 vcmpord_spd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 18 vcmpeq_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 18 vcmpeq_uspd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 19 vcmpnge_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 19 vcmpnge_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1a vcmpngt_uqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1a vcmpngt_uqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1b vcmpfalse_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1b vcmpfalse_ospd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1c vcmpneq_ospd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1c vcmpneq_ospd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1d vcmpge_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1d vcmpge_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1e vcmpgt_oqpd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1e vcmpgt_oqpd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 1f vcmptrue_uspd %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 10 vcmpeq_osps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 11 vcmplt_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 11 vcmplt_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 12 vcmple_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 12 vcmple_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 13 vcmpunord_sps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 13 vcmpunord_sps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 14 vcmpneq_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 14 vcmpneq_usps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 15 vcmpnlt_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 15 vcmpnlt_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 16 vcmpnle_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 16 vcmpnle_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 17 vcmpord_sps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 17 vcmpord_sps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 18 vcmpeq_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 18 vcmpeq_usps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 19 vcmpnge_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 19 vcmpnge_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1a vcmpngt_uqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1a vcmpngt_uqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1b vcmpfalse_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1b vcmpfalse_osps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1c vcmpneq_osps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1c vcmpneq_osps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1d vcmpge_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1d vcmpge_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1e vcmpgt_oqps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2psy \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq %ymm4,%xmm4 +[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dqy \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps %ymm4,%ymm4 +[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps \$0x64,%ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%rcx\),%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%rcx\),%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 69 39 60 vfmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 68 fc 60 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 68 39 60 vfmaddps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5d fc 60 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5d 39 60 vfmaddsubpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5c fc 60 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5c 39 60 vfmaddsubps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5f fc 60 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5f 39 60 vfmsubaddpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5e fc 60 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 5e 39 60 vfmsubaddps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6d fc 60 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6d 39 60 vfmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6c fc 60 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 6c 39 60 vfmsubps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 79 fc 60 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 79 39 60 vfnmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 78 fc 60 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 78 39 60 vfnmaddps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7d fc 60 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7d 39 60 vfnmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7c fc 60 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 7c 39 60 vfnmsubps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd \$0xa,%ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps \$0xa,%ymm4,%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7 +[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 \$0x64,%xmm4,%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%rcx\),%ymm4,%ymm6 +[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 \$0x64,%ymm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dqx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2psx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dqx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0e f4 vtestps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 0e 21 vtestps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 0f f4 vtestpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 0f 21 vtestpd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fe e6 e4 vcvtdq2pd %xmm4,%ymm4 +[ ]*[a-f0-9]+: c5 fe e6 21 vcvtdq2pd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 fc 5a e4 vcvtps2pd %xmm4,%ymm4 +[ ]*[a-f0-9]+: c5 fc 5a 21 vcvtps2pd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 c9 58 d4 vaddpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 58 39 vaddpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 58 d4 vaddps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 58 39 vaddps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d0 d4 vaddsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d0 39 vaddsubpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb d0 d4 vaddsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb d0 39 vaddsubps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 55 d4 vandnpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 55 39 vandnpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 55 d4 vandnps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 55 39 vandnps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 54 d4 vandpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 54 39 vandpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 54 d4 vandps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 54 39 vandps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5e d4 vdivpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5e 39 vdivpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5e d4 vdivps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5e 39 vdivps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 7c d4 vhaddpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 7c 39 vhaddpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb 7c d4 vhaddps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 7c 39 vhaddps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 7d d4 vhsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 7d 39 vhsubpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 cb 7d d4 vhsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 7d 39 vhsubps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5f d4 vmaxpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5f 39 vmaxpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5f d4 vmaxps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5f 39 vmaxps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5d d4 vminpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5d 39 vminpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5d d4 vminps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5d 39 vminps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 59 d4 vmulpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 59 39 vmulpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 59 d4 vmulps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 59 39 vmulps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 56 d4 vorpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 56 39 vorpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 56 d4 vorps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 56 39 vorps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 63 d4 vpacksswb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 63 39 vpacksswb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6b d4 vpackssdw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6b 39 vpackssdw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 67 d4 vpackuswb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 67 39 vpackuswb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 2b d4 vpackusdw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 2b 39 vpackusdw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fc d4 vpaddb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fc 39 vpaddb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fd d4 vpaddw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fd 39 vpaddw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fe d4 vpaddd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fe 39 vpaddd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d4 d4 vpaddq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d4 39 vpaddq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ec d4 vpaddsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ec 39 vpaddsb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ed d4 vpaddsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ed 39 vpaddsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 dc d4 vpaddusb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 dc 39 vpaddusb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 dd d4 vpaddusw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 dd 39 vpaddusw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 db d4 vpand %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 db 39 vpand \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 df d4 vpandn %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 df 39 vpandn \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e0 d4 vpavgb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e0 39 vpavgb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e3 d4 vpavgw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e3 39 vpavgw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 74 d4 vpcmpeqb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 74 39 vpcmpeqb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 75 d4 vpcmpeqw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 75 39 vpcmpeqw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 76 d4 vpcmpeqd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 76 39 vpcmpeqd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 29 d4 vpcmpeqq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 29 39 vpcmpeqq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 64 d4 vpcmpgtb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 64 39 vpcmpgtb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 65 39 vpcmpgtw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 66 d4 vpcmpgtd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 66 39 vpcmpgtd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 37 d4 vpcmpgtq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 37 39 vpcmpgtq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0d d4 vpermilpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0d 39 vpermilpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0c d4 vpermilps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0c 39 vpermilps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 01 d4 vphaddw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 01 39 vphaddw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 02 d4 vphaddd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 02 39 vphaddd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 03 d4 vphaddsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 03 39 vphaddsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 05 d4 vphsubw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 05 39 vphsubw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 06 d4 vphsubd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 06 39 vphsubd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 07 d4 vphsubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 07 39 vphsubsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f5 39 vpmaddwd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 04 39 vpmaddubsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3c d4 vpmaxsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3c 39 vpmaxsb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ee d4 vpmaxsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ee 39 vpmaxsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3d d4 vpmaxsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3d 39 vpmaxsd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 de d4 vpmaxub %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 de 39 vpmaxub \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3e d4 vpmaxuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3e 39 vpmaxuw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3f d4 vpmaxud %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3f 39 vpmaxud \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 38 d4 vpminsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 38 39 vpminsb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ea d4 vpminsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ea 39 vpminsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 39 d4 vpminsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 39 39 vpminsd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 da d4 vpminub %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 da 39 vpminub \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3a d4 vpminuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3a 39 vpminuw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 3b d4 vpminud %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 3b 39 vpminud \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e4 d4 vpmulhuw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e4 39 vpmulhuw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0b d4 vpmulhrsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0b 39 vpmulhrsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e5 d4 vpmulhw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e5 39 vpmulhw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d5 d4 vpmullw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d5 39 vpmullw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 40 d4 vpmulld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 40 39 vpmulld \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f4 d4 vpmuludq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f4 39 vpmuludq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 28 d4 vpmuldq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 28 39 vpmuldq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 eb d4 vpor %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 eb 39 vpor \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f6 d4 vpsadbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f6 39 vpsadbw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 00 d4 vpshufb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 00 39 vpshufb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 08 d4 vpsignb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 08 39 vpsignb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 09 d4 vpsignw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 09 39 vpsignw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 49 0a d4 vpsignd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 49 0a 39 vpsignd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f1 d4 vpsllw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f1 39 vpsllw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f2 d4 vpslld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f2 39 vpslld \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f3 d4 vpsllq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f3 39 vpsllq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e1 d4 vpsraw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e1 39 vpsraw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e2 d4 vpsrad %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e2 39 vpsrad \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d1 d4 vpsrlw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d1 39 vpsrlw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d2 d4 vpsrld %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d2 39 vpsrld \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d3 d4 vpsrlq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d3 39 vpsrlq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f8 d4 vpsubb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f8 39 vpsubb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 f9 d4 vpsubw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 f9 39 vpsubw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fa d4 vpsubd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fa 39 vpsubd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 fb d4 vpsubq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 fb 39 vpsubq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e8 d4 vpsubsb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e8 39 vpsubsb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 e9 d4 vpsubsw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 e9 39 vpsubsw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d8 d4 vpsubusb %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d8 39 vpsubusb \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 d9 d4 vpsubusw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 d9 39 vpsubusw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 68 d4 vpunpckhbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 68 39 vpunpckhbw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 69 d4 vpunpckhwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 69 39 vpunpckhwd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6a d4 vpunpckhdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6a 39 vpunpckhdq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6d d4 vpunpckhqdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6d 39 vpunpckhqdq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 60 d4 vpunpcklbw %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 60 39 vpunpcklbw \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 61 d4 vpunpcklwd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 61 39 vpunpcklwd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 62 d4 vpunpckldq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 62 39 vpunpckldq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 6c d4 vpunpcklqdq %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 6c 39 vpunpcklqdq \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 ef d4 vpxor %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 ef 39 vpxor \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 5c d4 vsubpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 5c 39 vsubpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 5c d4 vsubps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 5c 39 vsubps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 15 d4 vunpckhpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 15 39 vunpckhpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 15 d4 vunpckhps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 15 39 vunpckhps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 14 d4 vunpcklpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 14 39 vunpcklpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 14 d4 vunpcklps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 14 39 vunpcklps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 57 d4 vxorpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 57 39 vxorpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 57 d4 vxorps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 57 39 vxorps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 00 vcmpeqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 00 vcmpeqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 01 vcmpltpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 01 vcmpltpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 02 vcmplepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 02 vcmplepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 03 vcmpunordpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 03 vcmpunordpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 04 vcmpneqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 04 vcmpneqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 05 vcmpnltpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 05 vcmpnltpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 06 vcmpnlepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 06 vcmpnlepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 07 vcmpordpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 08 vcmpeq_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 08 vcmpeq_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 09 vcmpngepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 09 vcmpngepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0a vcmpngtpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0a vcmpngtpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0b vcmpfalsepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0b vcmpfalsepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0c vcmpneq_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0c vcmpneq_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0d vcmpgepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0d vcmpgepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0e vcmpgtpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0e vcmpgtpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 0f vcmptruepd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 0f vcmptruepd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 10 vcmpeq_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 10 vcmpeq_ospd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 11 vcmplt_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 11 vcmplt_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 12 vcmple_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 12 vcmple_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 13 vcmpunord_spd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 13 vcmpunord_spd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 14 vcmpneq_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 14 vcmpneq_uspd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 15 vcmpnlt_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 15 vcmpnlt_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 16 vcmpnle_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 16 vcmpnle_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 17 vcmpord_spd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 17 vcmpord_spd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 18 vcmpeq_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 18 vcmpeq_uspd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 19 vcmpnge_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 19 vcmpnge_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1a vcmpngt_uqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1a vcmpngt_uqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1b vcmpfalse_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1b vcmpfalse_ospd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1c vcmpneq_ospd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1c vcmpneq_ospd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1d vcmpge_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1d vcmpge_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1e vcmpgt_oqpd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1e vcmpgt_oqpd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c9 c2 d4 1f vcmptrue_uspd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 39 1f vcmptrue_uspd \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 00 vcmpeqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 00 vcmpeqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 01 vcmpltps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 01 vcmpltps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 02 vcmpleps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 02 vcmpleps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 03 vcmpunordps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 03 vcmpunordps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 04 vcmpneqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 04 vcmpneqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 05 vcmpnltps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 05 vcmpnltps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 06 vcmpnleps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 06 vcmpnleps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 07 vcmpordps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 08 vcmpeq_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 08 vcmpeq_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 09 vcmpngeps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 09 vcmpngeps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0a vcmpngtps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0a vcmpngtps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0b vcmpfalseps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0b vcmpfalseps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0c vcmpneq_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0c vcmpneq_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0d vcmpgeps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0d vcmpgeps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0e vcmpgtps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0e vcmpgtps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 0f vcmptrueps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 0f vcmptrueps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 10 vcmpeq_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 10 vcmpeq_osps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 11 vcmplt_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 11 vcmplt_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 12 vcmple_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 12 vcmple_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 13 vcmpunord_sps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 13 vcmpunord_sps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 14 vcmpneq_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 14 vcmpneq_usps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 15 vcmpnlt_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 15 vcmpnlt_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 16 vcmpnle_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 16 vcmpnle_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 17 vcmpord_sps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 17 vcmpord_sps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 18 vcmpeq_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 18 vcmpeq_usps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 19 vcmpnge_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 19 vcmpnge_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1a vcmpngt_uqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1a vcmpngt_uqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1b vcmpfalse_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1b vcmpfalse_osps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1c vcmpneq_osps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1c vcmpneq_osps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1d vcmpge_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1d vcmpge_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1e vcmpgt_oqps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7 +[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%rcx\) +[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 69 fc 60 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 69 39 60 vfmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 69 39 40 vfmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 68 fc 60 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 68 39 60 vfmaddps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 68 39 40 vfmaddps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5d fc 60 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5d 39 60 vfmaddsubpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5d 39 40 vfmaddsubpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5c fc 60 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5c 39 60 vfmaddsubps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5c 39 40 vfmaddsubps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5f fc 60 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5f 39 60 vfmsubaddpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5f 39 40 vfmsubaddpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5e fc 60 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 5e 39 60 vfmsubaddps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 5e 39 40 vfmsubaddps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6d fc 60 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6d 39 60 vfmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6d 39 40 vfmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6c fc 60 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6c 39 60 vfmsubps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6c 39 40 vfmsubps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 79 fc 60 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 79 39 60 vfnmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 79 39 40 vfnmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 78 fc 60 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 78 39 60 vfnmaddps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 78 39 40 vfnmaddps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7d fc 60 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7d 39 60 vfnmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7d 39 40 vfnmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7c fc 60 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7c 39 60 vfnmsubps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7c 39 40 vfnmsubps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd \$0xa,%xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps \$0xa,%xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c4 e1 fb 2d cc vcvtsd2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2d 09 vcvtsd2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2c cc vcvttsd2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2c 09 vcvttsd2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 db 2a f1 vcvtsi2sd %rcx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sdq \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss %rcx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 d9 22 f1 64 vpinsrq \$0x64,%rcx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq \$0x64,%xmm4,%rcx +[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 e9 6b fc 60 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6b 39 60 vfmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6b 39 40 vfmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6f fc 60 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6f 39 60 vfmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6f 39 40 vfmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7b fc 60 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7b 39 60 vfnmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7b 39 40 vfnmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7f fc 60 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7f 39 60 vfnmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7f 39 40 vfnmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5a 11 vcvtsd2ss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5e d4 vdivsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5e 11 vdivsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5f d4 vmaxsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5f 11 vmaxsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5d d4 vminsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5d 11 vminsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 59 d4 vmulsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 59 11 vmulsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 51 d4 vsqrtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 51 11 vsqrtsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5c d4 vsubsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 10 vcmpeq_ossd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 11 vcmplt_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 11 vcmplt_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 12 vcmple_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 12 vcmple_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 13 vcmpunord_ssd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 13 vcmpunord_ssd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 14 vcmpneq_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 14 vcmpneq_ussd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 15 vcmpnlt_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 15 vcmpnlt_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 16 vcmpnle_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 16 vcmpnle_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 17 vcmpord_ssd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 17 vcmpord_ssd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 18 vcmpeq_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 18 vcmpeq_ussd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 19 vcmpnge_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 19 vcmpnge_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1a vcmpngt_uqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1a vcmpngt_uqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1b vcmpfalse_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1b vcmpfalse_ossd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1c vcmpneq_ossd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1c vcmpneq_ossd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1d vcmpge_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1d vcmpge_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1e vcmpgt_oqsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5a 11 vcvtss2sd \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5e d4 vdivss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5e 11 vdivss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5f d4 vmaxss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5f 11 vmaxss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5d d4 vminss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5d 11 vminss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 59 d4 vmulss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 59 11 vmulss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 53 d4 vrcpss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 53 11 vrcpss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 52 d4 vrsqrtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 52 11 vrsqrtss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 51 d4 vsqrtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 51 11 vsqrtss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5c d4 vsubss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 10 vcmpeq_osss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 11 vcmplt_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 11 vcmplt_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 12 vcmple_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 12 vcmple_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 13 vcmpunord_sss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 13 vcmpunord_sss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 14 vcmpneq_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 14 vcmpneq_usss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 15 vcmpnlt_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 15 vcmpnlt_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 16 vcmpnle_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 16 vcmpnle_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 17 vcmpord_sss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 17 vcmpord_sss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 18 vcmpeq_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 18 vcmpeq_usss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 19 vcmpnge_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 19 vcmpnge_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1a vcmpngt_uqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1a vcmpngt_uqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1b vcmpfalse_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1b vcmpfalse_osss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1c vcmpneq_osss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1c vcmpneq_osss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1d vcmpge_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1d vcmpge_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1e vcmpgt_oqss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1e vcmpgt_oqss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 d4 1f vcmptrue_usss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 1f vcmptrue_usss \(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 7d 18 21 vbroadcastss \(%rcx\),%ymm4 +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 18 21 vbroadcastss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c4 e1 fa 2d cc vcvtss2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2d 09 vcvtss2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2c cc vcvttss2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2c 09 vcvttss2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd %ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss %ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%rcx\),%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e3 e9 6a fc 60 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6a 39 60 vfmaddss \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6a 39 40 vfmaddss %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6e fc 60 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 6e 39 60 vfmsubss \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 6e 39 40 vfmsubss %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7a fc 60 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7a 39 60 vfnmaddss \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7a 39 40 vfnmaddss %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7e fc 60 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 e9 7e 39 60 vfnmsubss \(%rcx\),%xmm6,%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e3 69 7e 39 40 vfnmsubss %xmm4,\(%rcx\),%xmm2,%xmm7 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c5 c8 12 d4 vmovhlps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 ff e6 f4 vcvtpd2dq %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fd 5a f4 vcvtpd2ps %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fd e6 f4 vcvttpd2dq %ymm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 78 56 34 12 vldmxcsr 0x12345678 +[ ]*[a-f0-9]+: c5 79 6f 04 25 78 56 34 12 vmovdqa 0x12345678,%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 04 25 78 56 34 12 vmovdqa %xmm8,0x12345678 +[ ]*[a-f0-9]+: c5 79 7e 04 25 78 56 34 12 vmovd %xmm8,0x12345678 +[ ]*[a-f0-9]+: c5 7b 2d 04 25 78 56 34 12 vcvtsd2si 0x12345678,%r8d +[ ]*[a-f0-9]+: c5 7e e6 04 25 78 56 34 12 vcvtdq2pd 0x12345678,%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 04 25 78 56 34 12 vcvtpd2psy 0x12345678,%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 3c 25 78 56 34 12 vpavgb 0x12345678,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 64 vpextrb \$0x64,%xmm8,0x12345678 +[ ]*[a-f0-9]+: c5 3b 2a 3c 25 78 56 34 12 vcvtsi2sdl 0x12345678,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 34 25 78 56 34 12 80 vblendvps %xmm8,0x12345678,%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 64 vpinsrb \$0x64,0x12345678,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 04 25 78 56 34 12 vmovdqa 0x12345678,%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 04 25 78 56 34 12 vmovdqa %ymm8,0x12345678 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 78 56 34 12 vpermilpd 0x12345678,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 64 vroundpd \$0x64,0x12345678,%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 64 vextractf128 \$0x64,%ymm8,0x12345678 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 64 vperm2f128 \$0x64,0x12345678,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 78 56 34 12 80 vblendvpd %ymm8,0x12345678,%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%rbp\) +[ ]*[a-f0-9]+: c5 79 6f 45 00 vmovdqa 0x0\(%rbp\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 45 00 vmovdqa %xmm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c5 79 7e 45 00 vmovd %xmm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c5 7b 2d 45 00 vcvtsd2si 0x0\(%rbp\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 45 00 vcvtdq2pd 0x0\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 45 00 vcvtpd2psy 0x0\(%rbp\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 7d 00 vpavgb 0x0\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 45 00 64 vpextrb \$0x64,%xmm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c5 3b 2a 7d 00 vcvtsi2sdl 0x0\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 75 00 80 vblendvps %xmm8,0x0\(%rbp\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 7d 00 64 vpinsrb \$0x64,0x0\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 45 00 vmovdqa 0x0\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 45 00 vmovdqa %ymm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c4 62 3d 0d 7d 00 vpermilpd 0x0\(%rbp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 45 00 64 vroundpd \$0x64,0x0\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 45 00 64 vextractf128 \$0x64,%ymm8,0x0\(%rbp\) +[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 64 vperm2f128 \$0x64,0x0\(%rbp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 75 00 80 vblendvpd %ymm8,0x0\(%rbp\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr 0x99\(%rbp\) +[ ]*[a-f0-9]+: c5 79 6f 85 99 00 00 00 vmovdqa 0x99\(%rbp\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 85 99 00 00 00 vmovdqa %xmm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c5 79 7e 85 99 00 00 00 vmovd %xmm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c5 7b 2d 85 99 00 00 00 vcvtsd2si 0x99\(%rbp\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 85 99 00 00 00 vcvtdq2pd 0x99\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 85 99 00 00 00 vcvtpd2psy 0x99\(%rbp\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 bd 99 00 00 00 vpavgb 0x99\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c5 3b 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a b5 99 00 00 00 80 vblendvps %xmm8,0x99\(%rbp\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rbp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 85 99 00 00 00 vmovdqa 0x99\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 85 99 00 00 00 vmovdqa %ymm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c4 62 3d 0d bd 99 00 00 00 vpermilpd 0x99\(%rbp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 64 vroundpd \$0x64,0x99\(%rbp\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rbp\) +[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rbp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b b5 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rbp\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 c1 78 ae 97 99 00 00 00 vldmxcsr 0x99\(%r15\) +[ ]*[a-f0-9]+: c4 41 79 6f 87 99 00 00 00 vmovdqa 0x99\(%r15\),%xmm8 +[ ]*[a-f0-9]+: c4 41 79 7f 87 99 00 00 00 vmovdqa %xmm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 41 79 7e 87 99 00 00 00 vmovd %xmm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 41 7b 2d 87 99 00 00 00 vcvtsd2si 0x99\(%r15\),%r8d +[ ]*[a-f0-9]+: c4 41 7e e6 87 99 00 00 00 vcvtdq2pd 0x99\(%r15\),%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 5a 87 99 00 00 00 vcvtpd2psy 0x99\(%r15\),%xmm8 +[ ]*[a-f0-9]+: c4 41 39 e0 bf 99 00 00 00 vpavgb 0x99\(%r15\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 41 3b 2a bf 99 00 00 00 vcvtsi2sdl 0x99\(%r15\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 19 4a b7 99 00 00 00 80 vblendvps %xmm8,0x99\(%r15\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 64 vpinsrb \$0x64,0x99\(%r15\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 7d 6f 87 99 00 00 00 vmovdqa 0x99\(%r15\),%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 7f 87 99 00 00 00 vmovdqa %ymm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 42 3d 0d bf 99 00 00 00 vpermilpd 0x99\(%r15\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 64 vroundpd \$0x64,0x99\(%r15\),%ymm8 +[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%r15\) +[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%r15\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 1d 4b b7 99 00 00 00 80 vblendvpd %ymm8,0x99\(%r15\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr 0x99\(%rip\) # 3bd9 <_start\+0x3bd9> +[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%xmm8 # 3be1 <_start\+0x3be1> +[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa %xmm8,0x99\(%rip\) # 3be9 <_start\+0x3be9> +[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd %xmm8,0x99\(%rip\) # 3bf1 <_start\+0x3bf1> +[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si 0x99\(%rip\),%r8d # 3bf9 <_start\+0x3bf9> +[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd 0x99\(%rip\),%ymm8 # 3c01 <_start\+0x3c01> +[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2psy 0x99\(%rip\),%xmm8 # 3c09 <_start\+0x3c09> +[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb 0x99\(%rip\),%xmm8,%xmm15 # 3c11 <_start\+0x3c11> +[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rip\) # 3c1b <_start\+0x3c1b> +[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # 3c23 <_start\+0x3c23> +[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps %xmm8,0x99\(%rip\),%xmm12,%xmm14 # 3c2d <_start\+0x3c2d> +[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rip\),%xmm8,%xmm15 # 3c37 <_start\+0x3c37> +[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%ymm8 # 3c3f <_start\+0x3c3f> +[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa %ymm8,0x99\(%rip\) # 3c47 <_start\+0x3c47> +[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd 0x99\(%rip\),%ymm8,%ymm15 # 3c50 <_start\+0x3c50> +[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 64 vroundpd \$0x64,0x99\(%rip\),%ymm8 # 3c5a <_start\+0x3c5a> +[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rip\) # 3c64 <_start\+0x3c64> +[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rip\),%ymm8,%ymm15 # 3c6e <_start\+0x3c6e> +[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rip\),%ymm12,%ymm14 # 3c78 <_start\+0x3c78> +[ ]*[a-f0-9]+: c5 f8 ae 94 24 99 00 00 00 vldmxcsr 0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 79 6f 84 24 99 00 00 00 vmovdqa 0x99\(%rsp\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 84 24 99 00 00 00 vmovdqa %xmm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 79 7e 84 24 99 00 00 00 vmovd %xmm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 7b 2d 84 24 99 00 00 00 vcvtsd2si 0x99\(%rsp\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 84 24 99 00 00 00 vcvtdq2pd 0x99\(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 84 24 99 00 00 00 vcvtpd2psy 0x99\(%rsp\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 bc 24 99 00 00 00 vpavgb 0x99\(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 3b 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a b4 24 99 00 00 00 80 vblendvps %xmm8,0x99\(%rsp\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rsp\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 84 24 99 00 00 00 vmovdqa 0x99\(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 84 24 99 00 00 00 vmovdqa %ymm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c4 62 3d 0d bc 24 99 00 00 00 vpermilpd 0x99\(%rsp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 64 vroundpd \$0x64,0x99\(%rsp\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rsp\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 24 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rsp\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 c1 78 ae 94 24 99 00 00 00 vldmxcsr 0x99\(%r12\) +[ ]*[a-f0-9]+: c4 41 79 6f 84 24 99 00 00 00 vmovdqa 0x99\(%r12\),%xmm8 +[ ]*[a-f0-9]+: c4 41 79 7f 84 24 99 00 00 00 vmovdqa %xmm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 41 79 7e 84 24 99 00 00 00 vmovd %xmm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 41 7b 2d 84 24 99 00 00 00 vcvtsd2si 0x99\(%r12\),%r8d +[ ]*[a-f0-9]+: c4 41 7e e6 84 24 99 00 00 00 vcvtdq2pd 0x99\(%r12\),%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 5a 84 24 99 00 00 00 vcvtpd2psy 0x99\(%r12\),%xmm8 +[ ]*[a-f0-9]+: c4 41 39 e0 bc 24 99 00 00 00 vpavgb 0x99\(%r12\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 41 3b 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%r12\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 19 4a b4 24 99 00 00 00 80 vblendvps %xmm8,0x99\(%r12\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 64 vpinsrb \$0x64,0x99\(%r12\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 7d 6f 84 24 99 00 00 00 vmovdqa 0x99\(%r12\),%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 7f 84 24 99 00 00 00 vmovdqa %ymm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 42 3d 0d bc 24 99 00 00 00 vpermilpd 0x99\(%r12\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 64 vroundpd \$0x64,0x99\(%r12\),%ymm8 +[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%r12\) +[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%r12\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 1d 4b b4 24 99 00 00 00 80 vblendvpd %ymm8,0x99\(%r12\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 14 25 67 ff ff ff vldmxcsr 0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 79 6f 04 25 67 ff ff ff vmovdqa 0xffffffffffffff67,%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 04 25 67 ff ff ff vmovdqa %xmm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 79 7e 04 25 67 ff ff ff vmovd %xmm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 7b 2d 04 25 67 ff ff ff vcvtsd2si 0xffffffffffffff67,%r8d +[ ]*[a-f0-9]+: c5 7e e6 04 25 67 ff ff ff vcvtdq2pd 0xffffffffffffff67,%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 04 25 67 ff ff ff vcvtpd2psy 0xffffffffffffff67,%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 3c 25 67 ff ff ff vpavgb 0xffffffffffffff67,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 64 vpextrb \$0x64,%xmm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c5 3b 2a 3c 25 67 ff ff ff vcvtsi2sdl 0xffffffffffffff67,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 34 25 67 ff ff ff 80 vblendvps %xmm8,0xffffffffffffff67,%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 64 vpinsrb \$0x64,0xffffffffffffff67,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 04 25 67 ff ff ff vmovdqa 0xffffffffffffff67,%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 04 25 67 ff ff ff vmovdqa %ymm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 67 ff ff ff vpermilpd 0xffffffffffffff67,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 64 vroundpd \$0x64,0xffffffffffffff67,%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,0xffffffffffffff67 +[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 64 vperm2f128 \$0x64,0xffffffffffffff67,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 67 ff ff ff 80 vblendvpd %ymm8,0xffffffffffffff67,%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 14 65 67 ff ff ff vldmxcsr -0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c5 79 6f 04 65 67 ff ff ff vmovdqa -0x99\(,%riz,2\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 04 65 67 ff ff ff vmovdqa %xmm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c5 79 7e 04 65 67 ff ff ff vmovd %xmm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c5 7b 2d 04 65 67 ff ff ff vcvtsd2si -0x99\(,%riz,2\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 04 65 67 ff ff ff vcvtdq2pd -0x99\(,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 04 65 67 ff ff ff vcvtpd2psy -0x99\(,%riz,2\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 3c 65 67 ff ff ff vpavgb -0x99\(,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c5 3b 2a 3c 65 67 ff ff ff vcvtsi2sdl -0x99\(,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a 34 65 67 ff ff ff 80 vblendvps %xmm8,-0x99\(,%riz,2\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 04 65 67 ff ff ff vmovdqa -0x99\(,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 04 65 67 ff ff ff vmovdqa %ymm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c4 62 3d 0d 3c 65 67 ff ff ff vpermilpd -0x99\(,%riz,2\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 64 vroundpd \$0x64,-0x99\(,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(,%riz,2\) +[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(,%riz,2\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b 34 65 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(,%riz,2\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 94 23 67 ff ff ff vldmxcsr -0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c5 79 6f 84 23 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,1\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 84 23 67 ff ff ff vmovdqa %xmm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c5 79 7e 84 23 67 ff ff ff vmovd %xmm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c5 7b 2d 84 23 67 ff ff ff vcvtsd2si -0x99\(%rbx,%riz,1\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 84 23 67 ff ff ff vcvtdq2pd -0x99\(%rbx,%riz,1\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 84 23 67 ff ff ff vcvtpd2psy -0x99\(%rbx,%riz,1\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 bc 23 67 ff ff ff vpavgb -0x99\(%rbx,%riz,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c5 3b 2a bc 23 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a b4 23 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbx,%riz,1\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbx,%riz,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 84 23 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,1\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 84 23 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c4 62 3d 0d bc 23 67 ff ff ff vpermilpd -0x99\(%rbx,%riz,1\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbx,%riz,1\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbx,%riz,1\) +[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbx,%riz,1\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 23 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbx,%riz,1\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c5 f8 ae 94 63 67 ff ff ff vldmxcsr -0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c5 79 6f 84 63 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,2\),%xmm8 +[ ]*[a-f0-9]+: c5 79 7f 84 63 67 ff ff ff vmovdqa %xmm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c5 79 7e 84 63 67 ff ff ff vmovd %xmm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c5 7b 2d 84 63 67 ff ff ff vcvtsd2si -0x99\(%rbx,%riz,2\),%r8d +[ ]*[a-f0-9]+: c5 7e e6 84 63 67 ff ff ff vcvtdq2pd -0x99\(%rbx,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 5a 84 63 67 ff ff ff vcvtpd2psy -0x99\(%rbx,%riz,2\),%xmm8 +[ ]*[a-f0-9]+: c5 39 e0 bc 63 67 ff ff ff vpavgb -0x99\(%rbx,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c5 3b 2a bc 63 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 63 19 4a b4 63 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbx,%riz,2\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbx,%riz,2\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c5 7d 6f 84 63 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c5 7d 7f 84 63 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c4 62 3d 0d bc 63 67 ff ff ff vpermilpd -0x99\(%rbx,%riz,2\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbx,%riz,2\),%ymm8 +[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbx,%riz,2\) +[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbx,%riz,2\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 63 1d 4b b4 63 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbx,%riz,2\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 81 78 ae 94 bc 67 ff ff ff vldmxcsr -0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 01 79 6f 84 bc 67 ff ff ff vmovdqa -0x99\(%r12,%r15,4\),%xmm8 +[ ]*[a-f0-9]+: c4 01 79 7f 84 bc 67 ff ff ff vmovdqa %xmm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 01 79 7e 84 bc 67 ff ff ff vmovd %xmm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 01 7b 2d 84 bc 67 ff ff ff vcvtsd2si -0x99\(%r12,%r15,4\),%r8d +[ ]*[a-f0-9]+: c4 01 7e e6 84 bc 67 ff ff ff vcvtdq2pd -0x99\(%r12,%r15,4\),%ymm8 +[ ]*[a-f0-9]+: c4 01 7d 5a 84 bc 67 ff ff ff vcvtpd2psy -0x99\(%r12,%r15,4\),%xmm8 +[ ]*[a-f0-9]+: c4 01 39 e0 bc bc 67 ff ff ff vpavgb -0x99\(%r12,%r15,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 01 3b 2a bc bc 67 ff ff ff vcvtsi2sdl -0x99\(%r12,%r15,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 03 19 4a b4 bc 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%r12,%r15,4\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%r12,%r15,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 01 7d 6f 84 bc 67 ff ff ff vmovdqa -0x99\(%r12,%r15,4\),%ymm8 +[ ]*[a-f0-9]+: c4 01 7d 7f 84 bc 67 ff ff ff vmovdqa %ymm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 02 3d 0d bc bc 67 ff ff ff vpermilpd -0x99\(%r12,%r15,4\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%r12,%r15,4\),%ymm8 +[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%r12,%r15,4\) +[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%r12,%r15,4\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 03 1d 4b b4 bc 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%r12,%r15,4\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 81 78 ae 94 f8 67 ff ff ff vldmxcsr -0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 01 79 6f 84 f8 67 ff ff ff vmovdqa -0x99\(%r8,%r15,8\),%xmm8 +[ ]*[a-f0-9]+: c4 01 79 7f 84 f8 67 ff ff ff vmovdqa %xmm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 01 79 7e 84 f8 67 ff ff ff vmovd %xmm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 01 7b 2d 84 f8 67 ff ff ff vcvtsd2si -0x99\(%r8,%r15,8\),%r8d +[ ]*[a-f0-9]+: c4 01 7e e6 84 f8 67 ff ff ff vcvtdq2pd -0x99\(%r8,%r15,8\),%ymm8 +[ ]*[a-f0-9]+: c4 01 7d 5a 84 f8 67 ff ff ff vcvtpd2psy -0x99\(%r8,%r15,8\),%xmm8 +[ ]*[a-f0-9]+: c4 01 39 e0 bc f8 67 ff ff ff vpavgb -0x99\(%r8,%r15,8\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 01 3b 2a bc f8 67 ff ff ff vcvtsi2sdl -0x99\(%r8,%r15,8\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 03 19 4a b4 f8 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%r8,%r15,8\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%r8,%r15,8\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 01 7d 6f 84 f8 67 ff ff ff vmovdqa -0x99\(%r8,%r15,8\),%ymm8 +[ ]*[a-f0-9]+: c4 01 7d 7f 84 f8 67 ff ff ff vmovdqa %ymm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 02 3d 0d bc f8 67 ff ff ff vpermilpd -0x99\(%r8,%r15,8\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%r8,%r15,8\),%ymm8 +[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%r8,%r15,8\) +[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%r8,%r15,8\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 03 1d 4b b4 f8 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%r8,%r15,8\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 a1 78 ae 94 a5 67 ff ff ff vldmxcsr -0x99\(%rbp,%r12,4\) +[ ]*[a-f0-9]+: c4 21 79 6f 84 a5 67 ff ff ff vmovdqa -0x99\(%rbp,%r12,4\),%xmm8 +[ ]*[a-f0-9]+: c4 21 79 7f 84 a5 67 ff ff ff vmovdqa %xmm8,-0x99\(%rbp,%r12,4\) +[ ]*[a-f0-9]+: c4 21 79 7e 84 a5 67 ff ff ff vmovd %xmm8,-0x99\(%rbp,%r12,4\) +[ ]*[a-f0-9]+: c4 21 7b 2d 84 a5 67 ff ff ff vcvtsd2si -0x99\(%rbp,%r12,4\),%r8d +[ ]*[a-f0-9]+: c4 21 7e e6 84 a5 67 ff ff ff vcvtdq2pd -0x99\(%rbp,%r12,4\),%ymm8 +[ ]*[a-f0-9]+: c4 21 7d 5a 84 a5 67 ff ff ff vcvtpd2psy -0x99\(%rbp,%r12,4\),%xmm8 +[ ]*[a-f0-9]+: c4 21 39 e0 bc a5 67 ff ff ff vpavgb -0x99\(%rbp,%r12,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 23 79 14 84 a5 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbp,%r12,4\) +[ ]*[a-f0-9]+: c4 21 3b 2a bc a5 67 ff ff ff vcvtsi2sdl -0x99\(%rbp,%r12,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 23 19 4a b4 a5 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbp,%r12,4\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 23 39 20 bc a5 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbp,%r12,4\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 21 7d 6f 84 a5 67 ff ff ff vmovdqa -0x99\(%rbp,%r12,4\),%ymm8 +[ ]*[a-f0-9]+: c4 21 7d 7f 84 a5 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbp,%r12,4\) +[ ]*[a-f0-9]+: c4 22 3d 0d bc a5 67 ff ff ff vpermilpd -0x99\(%rbp,%r12,4\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 23 7d 09 84 a5 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbp,%r12,4\),%ymm8 +[ ]*[a-f0-9]+: c4 23 7d 19 84 a5 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbp,%r12,4\) +[ ]*[a-f0-9]+: c4 23 3d 06 bc a5 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbp,%r12,4\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 23 1d 4b b4 a5 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbp,%r12,4\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 a1 78 ae 94 2c 67 ff ff ff vldmxcsr -0x99\(%rsp,%r13,1\) +[ ]*[a-f0-9]+: c4 21 79 6f 84 2c 67 ff ff ff vmovdqa -0x99\(%rsp,%r13,1\),%xmm8 +[ ]*[a-f0-9]+: c4 21 79 7f 84 2c 67 ff ff ff vmovdqa %xmm8,-0x99\(%rsp,%r13,1\) +[ ]*[a-f0-9]+: c4 21 79 7e 84 2c 67 ff ff ff vmovd %xmm8,-0x99\(%rsp,%r13,1\) +[ ]*[a-f0-9]+: c4 21 7b 2d 84 2c 67 ff ff ff vcvtsd2si -0x99\(%rsp,%r13,1\),%r8d +[ ]*[a-f0-9]+: c4 21 7e e6 84 2c 67 ff ff ff vcvtdq2pd -0x99\(%rsp,%r13,1\),%ymm8 +[ ]*[a-f0-9]+: c4 21 7d 5a 84 2c 67 ff ff ff vcvtpd2psy -0x99\(%rsp,%r13,1\),%xmm8 +[ ]*[a-f0-9]+: c4 21 39 e0 bc 2c 67 ff ff ff vpavgb -0x99\(%rsp,%r13,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 23 79 14 84 2c 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rsp,%r13,1\) +[ ]*[a-f0-9]+: c4 21 3b 2a bc 2c 67 ff ff ff vcvtsi2sdl -0x99\(%rsp,%r13,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 23 19 4a b4 2c 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rsp,%r13,1\),%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 23 39 20 bc 2c 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rsp,%r13,1\),%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 21 7d 6f 84 2c 67 ff ff ff vmovdqa -0x99\(%rsp,%r13,1\),%ymm8 +[ ]*[a-f0-9]+: c4 21 7d 7f 84 2c 67 ff ff ff vmovdqa %ymm8,-0x99\(%rsp,%r13,1\) +[ ]*[a-f0-9]+: c4 22 3d 0d bc 2c 67 ff ff ff vpermilpd -0x99\(%rsp,%r13,1\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 23 7d 09 84 2c 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rsp,%r13,1\),%ymm8 +[ ]*[a-f0-9]+: c4 23 7d 19 84 2c 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rsp,%r13,1\) +[ ]*[a-f0-9]+: c4 23 3d 06 bc 2c 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rsp,%r13,1\),%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 23 1d 4b b4 2c 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rsp,%r13,1\),%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 41 79 50 c0 vmovmskpd %xmm8,%r8d +[ ]*[a-f0-9]+: c4 c1 01 72 f0 64 vpslld \$0x64,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 7c 50 c0 vmovmskps %ymm8,%r8d +[ ]*[a-f0-9]+: c4 41 79 6f f8 vmovdqa %xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 79 7e c0 vmovd %xmm8,%r8d +[ ]*[a-f0-9]+: c4 41 7b 2d c0 vcvtsd2si %xmm8,%r8d +[ ]*[a-f0-9]+: c4 41 7e e6 c0 vcvtdq2pd %xmm8,%ymm8 +[ ]*[a-f0-9]+: c4 41 7d 5a c0 vcvtpd2ps %ymm8,%xmm8 +[ ]*[a-f0-9]+: c4 43 79 14 c0 64 vpextrb \$0x64,%xmm8,%r8d +[ ]*[a-f0-9]+: c4 41 3b 2a f8 vcvtsi2sd %r8d,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 43 19 4a f0 80 vblendvps %xmm8,%xmm8,%xmm12,%xmm14 +[ ]*[a-f0-9]+: c4 43 39 20 f8 64 vpinsrb \$0x64,%r8d,%xmm8,%xmm15 +[ ]*[a-f0-9]+: c4 41 7d 6f f8 vmovdqa %ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 42 05 0d e0 vpermilpd %ymm8,%ymm15,%ymm12 +[ ]*[a-f0-9]+: c4 43 7d 09 f8 64 vroundpd \$0x64,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 43 7d 19 c0 64 vextractf128 \$0x64,%ymm8,%xmm8 +[ ]*[a-f0-9]+: c4 43 05 06 e0 64 vperm2f128 \$0x64,%ymm8,%ymm15,%ymm12 +[ ]*[a-f0-9]+: c4 43 1d 4b f7 80 vblendvpd %ymm8,%ymm15,%ymm12,%ymm14 +[ ]*[a-f0-9]+: c4 43 3d 18 f8 64 vinsertf128 \$0x64,%xmm8,%ymm8,%ymm15 +[ ]*[a-f0-9]+: c4 61 fb 2d 01 vcvtsd2si \(%rcx\),%r8 +[ ]*[a-f0-9]+: c4 43 79 17 c0 0a vextractps \$0xa,%xmm8,%r8d +[ ]*[a-f0-9]+: c4 61 fa 2d 01 vcvtss2si \(%rcx\),%r8 +[ ]*[a-f0-9]+: c4 41 01 c4 c0 64 vpinsrw \$0x64,%r8d,%xmm15,%xmm8 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx.s b/gas/testsuite/gas/i386/x86-64-avx.s new file mode 100644 index 0000000..2008ef3 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx.s @@ -0,0 +1,3360 @@ +# Check 64bit AVX instructions + + .allow_index_reg + .text +_start: +# Tests for op + vzeroall + vzeroupper + +# Tests for op mem64 + vldmxcsr (%rcx) + vstmxcsr (%rcx) + +# Tests for op mem256, mask, ymm +# Tests for op ymm, mask, mem256 + vmaskmovpd (%rcx),%ymm4,%ymm6 + vmaskmovpd %ymm4,%ymm6,(%rcx) + vmaskmovps (%rcx),%ymm4,%ymm6 + vmaskmovps %ymm4,%ymm6,(%rcx) + +# Tests for op imm8, ymm/mem256, ymm + vpermilpd $100,%ymm6,%ymm2 + vpermilpd $100,(%rcx),%ymm6 + vpermilps $100,%ymm6,%ymm2 + vpermilps $100,(%rcx),%ymm6 + vroundpd $100,%ymm6,%ymm2 + vroundpd $100,(%rcx),%ymm6 + vroundps $100,%ymm6,%ymm2 + vroundps $100,(%rcx),%ymm6 + +# Tests for op ymm/mem256, ymm, ymm + vaddpd %ymm4,%ymm6,%ymm2 + vaddpd (%rcx),%ymm6,%ymm2 + vaddps %ymm4,%ymm6,%ymm2 + vaddps (%rcx),%ymm6,%ymm2 + vaddsubpd %ymm4,%ymm6,%ymm2 + vaddsubpd (%rcx),%ymm6,%ymm2 + vaddsubps %ymm4,%ymm6,%ymm2 + vaddsubps (%rcx),%ymm6,%ymm2 + vandnpd %ymm4,%ymm6,%ymm2 + vandnpd (%rcx),%ymm6,%ymm2 + vandnps %ymm4,%ymm6,%ymm2 + vandnps (%rcx),%ymm6,%ymm2 + vandpd %ymm4,%ymm6,%ymm2 + vandpd (%rcx),%ymm6,%ymm2 + vandps %ymm4,%ymm6,%ymm2 + vandps (%rcx),%ymm6,%ymm2 + vdivpd %ymm4,%ymm6,%ymm2 + vdivpd (%rcx),%ymm6,%ymm2 + vdivps %ymm4,%ymm6,%ymm2 + vdivps (%rcx),%ymm6,%ymm2 + vhaddpd %ymm4,%ymm6,%ymm2 + vhaddpd (%rcx),%ymm6,%ymm2 + vhaddps %ymm4,%ymm6,%ymm2 + vhaddps (%rcx),%ymm6,%ymm2 + vhsubpd %ymm4,%ymm6,%ymm2 + vhsubpd (%rcx),%ymm6,%ymm2 + vhsubps %ymm4,%ymm6,%ymm2 + vhsubps (%rcx),%ymm6,%ymm2 + vmaxpd %ymm4,%ymm6,%ymm2 + vmaxpd (%rcx),%ymm6,%ymm2 + vmaxps %ymm4,%ymm6,%ymm2 + vmaxps (%rcx),%ymm6,%ymm2 + vminpd %ymm4,%ymm6,%ymm2 + vminpd (%rcx),%ymm6,%ymm2 + vminps %ymm4,%ymm6,%ymm2 + vminps (%rcx),%ymm6,%ymm2 + vmulpd %ymm4,%ymm6,%ymm2 + vmulpd (%rcx),%ymm6,%ymm2 + vmulps %ymm4,%ymm6,%ymm2 + vmulps (%rcx),%ymm6,%ymm2 + vorpd %ymm4,%ymm6,%ymm2 + vorpd (%rcx),%ymm6,%ymm2 + vorps %ymm4,%ymm6,%ymm2 + vorps (%rcx),%ymm6,%ymm2 + vpermilpd %ymm4,%ymm6,%ymm2 + vpermilpd (%rcx),%ymm6,%ymm2 + vpermilps %ymm4,%ymm6,%ymm2 + vpermilps (%rcx),%ymm6,%ymm2 + vsubpd %ymm4,%ymm6,%ymm2 + vsubpd (%rcx),%ymm6,%ymm2 + vsubps %ymm4,%ymm6,%ymm2 + vsubps (%rcx),%ymm6,%ymm2 + vunpckhpd %ymm4,%ymm6,%ymm2 + vunpckhpd (%rcx),%ymm6,%ymm2 + vunpckhps %ymm4,%ymm6,%ymm2 + vunpckhps (%rcx),%ymm6,%ymm2 + vunpcklpd %ymm4,%ymm6,%ymm2 + vunpcklpd (%rcx),%ymm6,%ymm2 + vunpcklps %ymm4,%ymm6,%ymm2 + vunpcklps (%rcx),%ymm6,%ymm2 + vxorpd %ymm4,%ymm6,%ymm2 + vxorpd (%rcx),%ymm6,%ymm2 + vxorps %ymm4,%ymm6,%ymm2 + vxorps (%rcx),%ymm6,%ymm2 + vcmpeqpd %ymm4,%ymm6,%ymm2 + vcmpeqpd (%rcx),%ymm6,%ymm2 + vcmpltpd %ymm4,%ymm6,%ymm2 + vcmpltpd (%rcx),%ymm6,%ymm2 + vcmplepd %ymm4,%ymm6,%ymm2 + vcmplepd (%rcx),%ymm6,%ymm2 + vcmpunordpd %ymm4,%ymm6,%ymm2 + vcmpunordpd (%rcx),%ymm6,%ymm2 + vcmpneqpd %ymm4,%ymm6,%ymm2 + vcmpneqpd (%rcx),%ymm6,%ymm2 + vcmpnltpd %ymm4,%ymm6,%ymm2 + vcmpnltpd (%rcx),%ymm6,%ymm2 + vcmpnlepd %ymm4,%ymm6,%ymm2 + vcmpnlepd (%rcx),%ymm6,%ymm2 + vcmpordpd %ymm4,%ymm6,%ymm2 + vcmpordpd (%rcx),%ymm6,%ymm2 + vcmpeq_uqpd %ymm4,%ymm6,%ymm2 + vcmpeq_uqpd (%rcx),%ymm6,%ymm2 + vcmpngepd %ymm4,%ymm6,%ymm2 + vcmpngepd (%rcx),%ymm6,%ymm2 + vcmpngtpd %ymm4,%ymm6,%ymm2 + vcmpngtpd (%rcx),%ymm6,%ymm2 + vcmpfalsepd %ymm4,%ymm6,%ymm2 + vcmpfalsepd (%rcx),%ymm6,%ymm2 + vcmpneq_oqpd %ymm4,%ymm6,%ymm2 + vcmpneq_oqpd (%rcx),%ymm6,%ymm2 + vcmpgepd %ymm4,%ymm6,%ymm2 + vcmpgepd (%rcx),%ymm6,%ymm2 + vcmpgtpd %ymm4,%ymm6,%ymm2 + vcmpgtpd (%rcx),%ymm6,%ymm2 + vcmptruepd %ymm4,%ymm6,%ymm2 + vcmptruepd (%rcx),%ymm6,%ymm2 + vcmpeq_ospd %ymm4,%ymm6,%ymm2 + vcmpeq_ospd (%rcx),%ymm6,%ymm2 + vcmplt_oqpd %ymm4,%ymm6,%ymm2 + vcmplt_oqpd (%rcx),%ymm6,%ymm2 + vcmple_oqpd %ymm4,%ymm6,%ymm2 + vcmple_oqpd (%rcx),%ymm6,%ymm2 + vcmpunord_spd %ymm4,%ymm6,%ymm2 + vcmpunord_spd (%rcx),%ymm6,%ymm2 + vcmpneq_uspd %ymm4,%ymm6,%ymm2 + vcmpneq_uspd (%rcx),%ymm6,%ymm2 + vcmpnlt_uqpd %ymm4,%ymm6,%ymm2 + vcmpnlt_uqpd (%rcx),%ymm6,%ymm2 + vcmpnle_uqpd %ymm4,%ymm6,%ymm2 + vcmpnle_uqpd (%rcx),%ymm6,%ymm2 + vcmpord_spd %ymm4,%ymm6,%ymm2 + vcmpord_spd (%rcx),%ymm6,%ymm2 + vcmpeq_uspd %ymm4,%ymm6,%ymm2 + vcmpeq_uspd (%rcx),%ymm6,%ymm2 + vcmpnge_uqpd %ymm4,%ymm6,%ymm2 + vcmpnge_uqpd (%rcx),%ymm6,%ymm2 + vcmpngt_uqpd %ymm4,%ymm6,%ymm2 + vcmpngt_uqpd (%rcx),%ymm6,%ymm2 + vcmpfalse_ospd %ymm4,%ymm6,%ymm2 + vcmpfalse_ospd (%rcx),%ymm6,%ymm2 + vcmpneq_ospd %ymm4,%ymm6,%ymm2 + vcmpneq_ospd (%rcx),%ymm6,%ymm2 + vcmpge_oqpd %ymm4,%ymm6,%ymm2 + vcmpge_oqpd (%rcx),%ymm6,%ymm2 + vcmpgt_oqpd %ymm4,%ymm6,%ymm2 + vcmpgt_oqpd (%rcx),%ymm6,%ymm2 + vcmptrue_uspd %ymm4,%ymm6,%ymm2 + vcmptrue_uspd (%rcx),%ymm6,%ymm2 + vcmpeqps %ymm4,%ymm6,%ymm2 + vcmpeqps (%rcx),%ymm6,%ymm2 + vcmpltps %ymm4,%ymm6,%ymm2 + vcmpltps (%rcx),%ymm6,%ymm2 + vcmpleps %ymm4,%ymm6,%ymm2 + vcmpleps (%rcx),%ymm6,%ymm2 + vcmpunordps %ymm4,%ymm6,%ymm2 + vcmpunordps (%rcx),%ymm6,%ymm2 + vcmpneqps %ymm4,%ymm6,%ymm2 + vcmpneqps (%rcx),%ymm6,%ymm2 + vcmpnltps %ymm4,%ymm6,%ymm2 + vcmpnltps (%rcx),%ymm6,%ymm2 + vcmpnleps %ymm4,%ymm6,%ymm2 + vcmpnleps (%rcx),%ymm6,%ymm2 + vcmpordps %ymm4,%ymm6,%ymm2 + vcmpordps (%rcx),%ymm6,%ymm2 + vcmpeq_uqps %ymm4,%ymm6,%ymm2 + vcmpeq_uqps (%rcx),%ymm6,%ymm2 + vcmpngeps %ymm4,%ymm6,%ymm2 + vcmpngeps (%rcx),%ymm6,%ymm2 + vcmpngtps %ymm4,%ymm6,%ymm2 + vcmpngtps (%rcx),%ymm6,%ymm2 + vcmpfalseps %ymm4,%ymm6,%ymm2 + vcmpfalseps (%rcx),%ymm6,%ymm2 + vcmpneq_oqps %ymm4,%ymm6,%ymm2 + vcmpneq_oqps (%rcx),%ymm6,%ymm2 + vcmpgeps %ymm4,%ymm6,%ymm2 + vcmpgeps (%rcx),%ymm6,%ymm2 + vcmpgtps %ymm4,%ymm6,%ymm2 + vcmpgtps (%rcx),%ymm6,%ymm2 + vcmptrueps %ymm4,%ymm6,%ymm2 + vcmptrueps (%rcx),%ymm6,%ymm2 + vcmpeq_osps %ymm4,%ymm6,%ymm2 + vcmpeq_osps (%rcx),%ymm6,%ymm2 + vcmplt_oqps %ymm4,%ymm6,%ymm2 + vcmplt_oqps (%rcx),%ymm6,%ymm2 + vcmple_oqps %ymm4,%ymm6,%ymm2 + vcmple_oqps (%rcx),%ymm6,%ymm2 + vcmpunord_sps %ymm4,%ymm6,%ymm2 + vcmpunord_sps (%rcx),%ymm6,%ymm2 + vcmpneq_usps %ymm4,%ymm6,%ymm2 + vcmpneq_usps (%rcx),%ymm6,%ymm2 + vcmpnlt_uqps %ymm4,%ymm6,%ymm2 + vcmpnlt_uqps (%rcx),%ymm6,%ymm2 + vcmpnle_uqps %ymm4,%ymm6,%ymm2 + vcmpnle_uqps (%rcx),%ymm6,%ymm2 + vcmpord_sps %ymm4,%ymm6,%ymm2 + vcmpord_sps (%rcx),%ymm6,%ymm2 + vcmpeq_usps %ymm4,%ymm6,%ymm2 + vcmpeq_usps (%rcx),%ymm6,%ymm2 + vcmpnge_uqps %ymm4,%ymm6,%ymm2 + vcmpnge_uqps (%rcx),%ymm6,%ymm2 + vcmpngt_uqps %ymm4,%ymm6,%ymm2 + vcmpngt_uqps (%rcx),%ymm6,%ymm2 + vcmpfalse_osps %ymm4,%ymm6,%ymm2 + vcmpfalse_osps (%rcx),%ymm6,%ymm2 + vcmpneq_osps %ymm4,%ymm6,%ymm2 + vcmpneq_osps (%rcx),%ymm6,%ymm2 + vcmpge_oqps %ymm4,%ymm6,%ymm2 + vcmpge_oqps (%rcx),%ymm6,%ymm2 + vcmpgt_oqps %ymm4,%ymm6,%ymm2 + vcmpgt_oqps (%rcx),%ymm6,%ymm2 + vcmptrue_usps %ymm4,%ymm6,%ymm2 + vcmptrue_usps (%rcx),%ymm6,%ymm2 + +# Tests for op ymm/mem256, xmm + vcvtpd2dqy %ymm4,%xmm4 + vcvtpd2dqy (%rcx),%xmm4 + vcvtpd2psy %ymm4,%xmm4 + vcvtpd2psy (%rcx),%xmm4 + vcvttpd2dqy %ymm4,%xmm4 + vcvttpd2dqy (%rcx),%xmm4 + +# Tests for op ymm/mem256, ymm + vcvtdq2ps %ymm4,%ymm4 + vcvtdq2ps (%rcx),%ymm4 + vcvtps2dq %ymm4,%ymm4 + vcvtps2dq (%rcx),%ymm4 + vcvttps2dq %ymm4,%ymm4 + vcvttps2dq (%rcx),%ymm4 + vmovapd %ymm4,%ymm4 + vmovapd (%rcx),%ymm4 + vmovaps %ymm4,%ymm4 + vmovaps (%rcx),%ymm4 + vmovdqa %ymm4,%ymm4 + vmovdqa (%rcx),%ymm4 + vmovdqu %ymm4,%ymm4 + vmovdqu (%rcx),%ymm4 + vmovddup %ymm4,%ymm4 + vmovddup (%rcx),%ymm4 + vmovshdup %ymm4,%ymm4 + vmovshdup (%rcx),%ymm4 + vmovsldup %ymm4,%ymm4 + vmovsldup (%rcx),%ymm4 + vmovupd %ymm4,%ymm4 + vmovupd (%rcx),%ymm4 + vmovups %ymm4,%ymm4 + vmovups (%rcx),%ymm4 + vptest %ymm4,%ymm4 + vptest (%rcx),%ymm4 + vrcpps %ymm4,%ymm4 + vrcpps (%rcx),%ymm4 + vrsqrtps %ymm4,%ymm4 + vrsqrtps (%rcx),%ymm4 + vsqrtpd %ymm4,%ymm4 + vsqrtpd (%rcx),%ymm4 + vsqrtps %ymm4,%ymm4 + vsqrtps (%rcx),%ymm4 + vtestpd %ymm4,%ymm4 + vtestpd (%rcx),%ymm4 + vtestps %ymm4,%ymm4 + vtestps (%rcx),%ymm4 + +# Tests for op mem256, ymm + vlddqu (%rcx),%ymm4 + +# Tests for op imm8, ymm/mem256, ymm, ymm + vblendpd $100,%ymm4,%ymm6,%ymm2 + vblendpd $100,(%rcx),%ymm6,%ymm2 + vblendps $100,%ymm4,%ymm6,%ymm2 + vblendps $100,(%rcx),%ymm6,%ymm2 + vcmppd $100,%ymm4,%ymm6,%ymm2 + vcmppd $100,(%rcx),%ymm6,%ymm2 + vcmpps $100,%ymm4,%ymm6,%ymm2 + vcmpps $100,(%rcx),%ymm6,%ymm2 + vdpps $100,%ymm4,%ymm6,%ymm2 + vdpps $100,(%rcx),%ymm6,%ymm2 + vperm2f128 $100,%ymm4,%ymm6,%ymm2 + vperm2f128 $100,(%rcx),%ymm6,%ymm2 + vshufpd $100,%ymm4,%ymm6,%ymm2 + vshufpd $100,(%rcx),%ymm6,%ymm2 + vshufps $100,%ymm4,%ymm6,%ymm2 + vshufps $100,(%rcx),%ymm6,%ymm2 + +# Tests for op ymm, ymm/mem256, ymm, ymm + vblendvpd %ymm4,%ymm6,%ymm2,%ymm7 + vblendvpd %ymm4,(%rcx),%ymm2,%ymm7 + vblendvps %ymm4,%ymm6,%ymm2,%ymm7 + vblendvps %ymm4,(%rcx),%ymm2,%ymm7 + +# Tests for op ymm/mem256, ymm, ymm, ymm +# Tests for op ymm, ymm/mem256, ymm, ymm + vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7 + vfmaddpd (%rcx),%ymm6,%ymm2,%ymm7 + vfmaddps %ymm4,%ymm6,%ymm2,%ymm7 + vfmaddps (%rcx),%ymm6,%ymm2,%ymm7 + vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7 + vfmaddsubpd (%rcx),%ymm6,%ymm2,%ymm7 + vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7 + vfmaddsubps (%rcx),%ymm6,%ymm2,%ymm7 + vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7 + vfmsubaddpd (%rcx),%ymm6,%ymm2,%ymm7 + vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7 + vfmsubaddps (%rcx),%ymm6,%ymm2,%ymm7 + vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7 + vfmsubpd (%rcx),%ymm6,%ymm2,%ymm7 + vfmsubps %ymm4,%ymm6,%ymm2,%ymm7 + vfmsubps (%rcx),%ymm6,%ymm2,%ymm7 + vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7 + vfnmaddpd (%rcx),%ymm6,%ymm2,%ymm7 + vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7 + vfnmaddps (%rcx),%ymm6,%ymm2,%ymm7 + vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7 + vfnmsubpd (%rcx),%ymm6,%ymm2,%ymm7 + vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7 + vfnmsubps (%rcx),%ymm6,%ymm2,%ymm7 + vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7 + vpermilmo2pd (%rcx),%ymm6,%ymm2,%ymm7 + vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7 + vpermilmz2pd (%rcx),%ymm6,%ymm2,%ymm7 + vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7 + vpermiltd2pd (%rcx),%ymm6,%ymm2,%ymm7 + vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7 + vpermilmo2ps (%rcx),%ymm6,%ymm2,%ymm7 + vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7 + vpermilmz2ps (%rcx),%ymm6,%ymm2,%ymm7 + vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7 + vpermiltd2ps (%rcx),%ymm6,%ymm2,%ymm7 + +# Tests for op imm4, ymm/mem256, ymm, ymm, ymm +# Tests for op imm4, ymm, ymm/mem256, ymm, ymm + vpermil2pd $10,%ymm4,%ymm6,%ymm2,%ymm7 + vpermil2pd $10,(%rcx),%ymm6,%ymm2,%ymm7 + vpermil2ps $10,%ymm4,%ymm6,%ymm2,%ymm7 + vpermil2ps $10,(%rcx),%ymm6,%ymm2,%ymm7 + +# Tests for op imm8, xmm/mem128, ymm, ymm + vinsertf128 $100,%xmm4,%ymm4,%ymm6 + vinsertf128 $100,(%rcx),%ymm4,%ymm6 + +# Tests for op imm8, ymm, xmm/mem128 + vextractf128 $100,%ymm4,%xmm4 + vextractf128 $100,%ymm4,(%rcx) + +# Tests for op xmm/mem128, xmm +# Tests for op mem128, ymm + vbroadcastf128 (%rcx),%ymm4 + +# Tests for op xmm/mem128, xmm + vcvtdq2ps %xmm4,%xmm6 + vcvtdq2ps (%rcx),%xmm4 + vcvtpd2dqx %xmm4,%xmm6 + vcvtpd2dqx (%rcx),%xmm4 + vcvtpd2psx %xmm4,%xmm6 + vcvtpd2psx (%rcx),%xmm4 + vcvtps2dq %xmm4,%xmm6 + vcvtps2dq (%rcx),%xmm4 + vcvttpd2dqx %xmm4,%xmm6 + vcvttpd2dqx (%rcx),%xmm4 + vcvttps2dq %xmm4,%xmm6 + vcvttps2dq (%rcx),%xmm4 + vmovapd %xmm4,%xmm6 + vmovapd (%rcx),%xmm4 + vmovaps %xmm4,%xmm6 + vmovaps (%rcx),%xmm4 + vmovdqa %xmm4,%xmm6 + vmovdqa (%rcx),%xmm4 + vmovdqu %xmm4,%xmm6 + vmovdqu (%rcx),%xmm4 + vmovshdup %xmm4,%xmm6 + vmovshdup (%rcx),%xmm4 + vmovsldup %xmm4,%xmm6 + vmovsldup (%rcx),%xmm4 + vmovupd %xmm4,%xmm6 + vmovupd (%rcx),%xmm4 + vmovups %xmm4,%xmm6 + vmovups (%rcx),%xmm4 + vpabsb %xmm4,%xmm6 + vpabsb (%rcx),%xmm4 + vpabsw %xmm4,%xmm6 + vpabsw (%rcx),%xmm4 + vpabsd %xmm4,%xmm6 + vpabsd (%rcx),%xmm4 + vphminposuw %xmm4,%xmm6 + vphminposuw (%rcx),%xmm4 + vptest %xmm4,%xmm6 + vptest (%rcx),%xmm4 + vtestps %xmm4,%xmm6 + vtestps (%rcx),%xmm4 + vtestpd %xmm4,%xmm6 + vtestpd (%rcx),%xmm4 + vrcpps %xmm4,%xmm6 + vrcpps (%rcx),%xmm4 + vrsqrtps %xmm4,%xmm6 + vrsqrtps (%rcx),%xmm4 + vsqrtpd %xmm4,%xmm6 + vsqrtpd (%rcx),%xmm4 + vsqrtps %xmm4,%xmm6 + vsqrtps (%rcx),%xmm4 + +# Tests for op xmm, xmm/mem128 + vmovapd %xmm4,%xmm6 + vmovapd %xmm4,(%rcx) + vmovaps %xmm4,%xmm6 + vmovaps %xmm4,(%rcx) + vmovdqa %xmm4,%xmm6 + vmovdqa %xmm4,(%rcx) + vmovdqu %xmm4,%xmm6 + vmovdqu %xmm4,(%rcx) + vmovupd %xmm4,%xmm6 + vmovupd %xmm4,(%rcx) + vmovups %xmm4,%xmm6 + vmovups %xmm4,(%rcx) + +# Tests for op mem128, xmm + vlddqu (%rcx),%xmm4 + vmovntdqa (%rcx),%xmm4 + +# Tests for op xmm, mem128 + vmovntdq %xmm4,(%rcx) + vmovntpd %xmm4,(%rcx) + vmovntps %xmm4,(%rcx) + +# Tests for op xmm/mem128, ymm + vcvtdq2pd %xmm4,%ymm4 + vcvtdq2pd (%rcx),%ymm4 + vcvtps2pd %xmm4,%ymm4 + vcvtps2pd (%rcx),%ymm4 + +# Tests for op xmm/mem128, xmm, xmm + vaddpd %xmm4,%xmm6,%xmm2 + vaddpd (%rcx),%xmm6,%xmm7 + vaddps %xmm4,%xmm6,%xmm2 + vaddps (%rcx),%xmm6,%xmm7 + vaddsubpd %xmm4,%xmm6,%xmm2 + vaddsubpd (%rcx),%xmm6,%xmm7 + vaddsubps %xmm4,%xmm6,%xmm2 + vaddsubps (%rcx),%xmm6,%xmm7 + vandnpd %xmm4,%xmm6,%xmm2 + vandnpd (%rcx),%xmm6,%xmm7 + vandnps %xmm4,%xmm6,%xmm2 + vandnps (%rcx),%xmm6,%xmm7 + vandpd %xmm4,%xmm6,%xmm2 + vandpd (%rcx),%xmm6,%xmm7 + vandps %xmm4,%xmm6,%xmm2 + vandps (%rcx),%xmm6,%xmm7 + vdivpd %xmm4,%xmm6,%xmm2 + vdivpd (%rcx),%xmm6,%xmm7 + vdivps %xmm4,%xmm6,%xmm2 + vdivps (%rcx),%xmm6,%xmm7 + vhaddpd %xmm4,%xmm6,%xmm2 + vhaddpd (%rcx),%xmm6,%xmm7 + vhaddps %xmm4,%xmm6,%xmm2 + vhaddps (%rcx),%xmm6,%xmm7 + vhsubpd %xmm4,%xmm6,%xmm2 + vhsubpd (%rcx),%xmm6,%xmm7 + vhsubps %xmm4,%xmm6,%xmm2 + vhsubps (%rcx),%xmm6,%xmm7 + vmaxpd %xmm4,%xmm6,%xmm2 + vmaxpd (%rcx),%xmm6,%xmm7 + vmaxps %xmm4,%xmm6,%xmm2 + vmaxps (%rcx),%xmm6,%xmm7 + vminpd %xmm4,%xmm6,%xmm2 + vminpd (%rcx),%xmm6,%xmm7 + vminps %xmm4,%xmm6,%xmm2 + vminps (%rcx),%xmm6,%xmm7 + vmulpd %xmm4,%xmm6,%xmm2 + vmulpd (%rcx),%xmm6,%xmm7 + vmulps %xmm4,%xmm6,%xmm2 + vmulps (%rcx),%xmm6,%xmm7 + vorpd %xmm4,%xmm6,%xmm2 + vorpd (%rcx),%xmm6,%xmm7 + vorps %xmm4,%xmm6,%xmm2 + vorps (%rcx),%xmm6,%xmm7 + vpacksswb %xmm4,%xmm6,%xmm2 + vpacksswb (%rcx),%xmm6,%xmm7 + vpackssdw %xmm4,%xmm6,%xmm2 + vpackssdw (%rcx),%xmm6,%xmm7 + vpackuswb %xmm4,%xmm6,%xmm2 + vpackuswb (%rcx),%xmm6,%xmm7 + vpackusdw %xmm4,%xmm6,%xmm2 + vpackusdw (%rcx),%xmm6,%xmm7 + vpaddb %xmm4,%xmm6,%xmm2 + vpaddb (%rcx),%xmm6,%xmm7 + vpaddw %xmm4,%xmm6,%xmm2 + vpaddw (%rcx),%xmm6,%xmm7 + vpaddd %xmm4,%xmm6,%xmm2 + vpaddd (%rcx),%xmm6,%xmm7 + vpaddq %xmm4,%xmm6,%xmm2 + vpaddq (%rcx),%xmm6,%xmm7 + vpaddsb %xmm4,%xmm6,%xmm2 + vpaddsb (%rcx),%xmm6,%xmm7 + vpaddsw %xmm4,%xmm6,%xmm2 + vpaddsw (%rcx),%xmm6,%xmm7 + vpaddusb %xmm4,%xmm6,%xmm2 + vpaddusb (%rcx),%xmm6,%xmm7 + vpaddusw %xmm4,%xmm6,%xmm2 + vpaddusw (%rcx),%xmm6,%xmm7 + vpand %xmm4,%xmm6,%xmm2 + vpand (%rcx),%xmm6,%xmm7 + vpandn %xmm4,%xmm6,%xmm2 + vpandn (%rcx),%xmm6,%xmm7 + vpavgb %xmm4,%xmm6,%xmm2 + vpavgb (%rcx),%xmm6,%xmm7 + vpavgw %xmm4,%xmm6,%xmm2 + vpavgw (%rcx),%xmm6,%xmm7 + vpcmpeqb %xmm4,%xmm6,%xmm2 + vpcmpeqb (%rcx),%xmm6,%xmm7 + vpcmpeqw %xmm4,%xmm6,%xmm2 + vpcmpeqw (%rcx),%xmm6,%xmm7 + vpcmpeqd %xmm4,%xmm6,%xmm2 + vpcmpeqd (%rcx),%xmm6,%xmm7 + vpcmpeqq %xmm4,%xmm6,%xmm2 + vpcmpeqq (%rcx),%xmm6,%xmm7 + vpcmpgtb %xmm4,%xmm6,%xmm2 + vpcmpgtb (%rcx),%xmm6,%xmm7 + vpcmpgtw %xmm4,%xmm6,%xmm2 + vpcmpgtw (%rcx),%xmm6,%xmm7 + vpcmpgtd %xmm4,%xmm6,%xmm2 + vpcmpgtd (%rcx),%xmm6,%xmm7 + vpcmpgtq %xmm4,%xmm6,%xmm2 + vpcmpgtq (%rcx),%xmm6,%xmm7 + vpermilpd %xmm4,%xmm6,%xmm2 + vpermilpd (%rcx),%xmm6,%xmm7 + vpermilps %xmm4,%xmm6,%xmm2 + vpermilps (%rcx),%xmm6,%xmm7 + vphaddw %xmm4,%xmm6,%xmm2 + vphaddw (%rcx),%xmm6,%xmm7 + vphaddd %xmm4,%xmm6,%xmm2 + vphaddd (%rcx),%xmm6,%xmm7 + vphaddsw %xmm4,%xmm6,%xmm2 + vphaddsw (%rcx),%xmm6,%xmm7 + vphsubw %xmm4,%xmm6,%xmm2 + vphsubw (%rcx),%xmm6,%xmm7 + vphsubd %xmm4,%xmm6,%xmm2 + vphsubd (%rcx),%xmm6,%xmm7 + vphsubsw %xmm4,%xmm6,%xmm2 + vphsubsw (%rcx),%xmm6,%xmm7 + vpmaddwd %xmm4,%xmm6,%xmm2 + vpmaddwd (%rcx),%xmm6,%xmm7 + vpmaddubsw %xmm4,%xmm6,%xmm2 + vpmaddubsw (%rcx),%xmm6,%xmm7 + vpmaxsb %xmm4,%xmm6,%xmm2 + vpmaxsb (%rcx),%xmm6,%xmm7 + vpmaxsw %xmm4,%xmm6,%xmm2 + vpmaxsw (%rcx),%xmm6,%xmm7 + vpmaxsd %xmm4,%xmm6,%xmm2 + vpmaxsd (%rcx),%xmm6,%xmm7 + vpmaxub %xmm4,%xmm6,%xmm2 + vpmaxub (%rcx),%xmm6,%xmm7 + vpmaxuw %xmm4,%xmm6,%xmm2 + vpmaxuw (%rcx),%xmm6,%xmm7 + vpmaxud %xmm4,%xmm6,%xmm2 + vpmaxud (%rcx),%xmm6,%xmm7 + vpminsb %xmm4,%xmm6,%xmm2 + vpminsb (%rcx),%xmm6,%xmm7 + vpminsw %xmm4,%xmm6,%xmm2 + vpminsw (%rcx),%xmm6,%xmm7 + vpminsd %xmm4,%xmm6,%xmm2 + vpminsd (%rcx),%xmm6,%xmm7 + vpminub %xmm4,%xmm6,%xmm2 + vpminub (%rcx),%xmm6,%xmm7 + vpminuw %xmm4,%xmm6,%xmm2 + vpminuw (%rcx),%xmm6,%xmm7 + vpminud %xmm4,%xmm6,%xmm2 + vpminud (%rcx),%xmm6,%xmm7 + vpmulhuw %xmm4,%xmm6,%xmm2 + vpmulhuw (%rcx),%xmm6,%xmm7 + vpmulhrsw %xmm4,%xmm6,%xmm2 + vpmulhrsw (%rcx),%xmm6,%xmm7 + vpmulhw %xmm4,%xmm6,%xmm2 + vpmulhw (%rcx),%xmm6,%xmm7 + vpmullw %xmm4,%xmm6,%xmm2 + vpmullw (%rcx),%xmm6,%xmm7 + vpmulld %xmm4,%xmm6,%xmm2 + vpmulld (%rcx),%xmm6,%xmm7 + vpmuludq %xmm4,%xmm6,%xmm2 + vpmuludq (%rcx),%xmm6,%xmm7 + vpmuldq %xmm4,%xmm6,%xmm2 + vpmuldq (%rcx),%xmm6,%xmm7 + vpor %xmm4,%xmm6,%xmm2 + vpor (%rcx),%xmm6,%xmm7 + vpsadbw %xmm4,%xmm6,%xmm2 + vpsadbw (%rcx),%xmm6,%xmm7 + vpshufb %xmm4,%xmm6,%xmm2 + vpshufb (%rcx),%xmm6,%xmm7 + vpsignb %xmm4,%xmm6,%xmm2 + vpsignb (%rcx),%xmm6,%xmm7 + vpsignw %xmm4,%xmm6,%xmm2 + vpsignw (%rcx),%xmm6,%xmm7 + vpsignd %xmm4,%xmm6,%xmm2 + vpsignd (%rcx),%xmm6,%xmm7 + vpsllw %xmm4,%xmm6,%xmm2 + vpsllw (%rcx),%xmm6,%xmm7 + vpslld %xmm4,%xmm6,%xmm2 + vpslld (%rcx),%xmm6,%xmm7 + vpsllq %xmm4,%xmm6,%xmm2 + vpsllq (%rcx),%xmm6,%xmm7 + vpsraw %xmm4,%xmm6,%xmm2 + vpsraw (%rcx),%xmm6,%xmm7 + vpsrad %xmm4,%xmm6,%xmm2 + vpsrad (%rcx),%xmm6,%xmm7 + vpsrlw %xmm4,%xmm6,%xmm2 + vpsrlw (%rcx),%xmm6,%xmm7 + vpsrld %xmm4,%xmm6,%xmm2 + vpsrld (%rcx),%xmm6,%xmm7 + vpsrlq %xmm4,%xmm6,%xmm2 + vpsrlq (%rcx),%xmm6,%xmm7 + vpsubb %xmm4,%xmm6,%xmm2 + vpsubb (%rcx),%xmm6,%xmm7 + vpsubw %xmm4,%xmm6,%xmm2 + vpsubw (%rcx),%xmm6,%xmm7 + vpsubd %xmm4,%xmm6,%xmm2 + vpsubd (%rcx),%xmm6,%xmm7 + vpsubq %xmm4,%xmm6,%xmm2 + vpsubq (%rcx),%xmm6,%xmm7 + vpsubsb %xmm4,%xmm6,%xmm2 + vpsubsb (%rcx),%xmm6,%xmm7 + vpsubsw %xmm4,%xmm6,%xmm2 + vpsubsw (%rcx),%xmm6,%xmm7 + vpsubusb %xmm4,%xmm6,%xmm2 + vpsubusb (%rcx),%xmm6,%xmm7 + vpsubusw %xmm4,%xmm6,%xmm2 + vpsubusw (%rcx),%xmm6,%xmm7 + vpunpckhbw %xmm4,%xmm6,%xmm2 + vpunpckhbw (%rcx),%xmm6,%xmm7 + vpunpckhwd %xmm4,%xmm6,%xmm2 + vpunpckhwd (%rcx),%xmm6,%xmm7 + vpunpckhdq %xmm4,%xmm6,%xmm2 + vpunpckhdq (%rcx),%xmm6,%xmm7 + vpunpckhqdq %xmm4,%xmm6,%xmm2 + vpunpckhqdq (%rcx),%xmm6,%xmm7 + vpunpcklbw %xmm4,%xmm6,%xmm2 + vpunpcklbw (%rcx),%xmm6,%xmm7 + vpunpcklwd %xmm4,%xmm6,%xmm2 + vpunpcklwd (%rcx),%xmm6,%xmm7 + vpunpckldq %xmm4,%xmm6,%xmm2 + vpunpckldq (%rcx),%xmm6,%xmm7 + vpunpcklqdq %xmm4,%xmm6,%xmm2 + vpunpcklqdq (%rcx),%xmm6,%xmm7 + vpxor %xmm4,%xmm6,%xmm2 + vpxor (%rcx),%xmm6,%xmm7 + vsubpd %xmm4,%xmm6,%xmm2 + vsubpd (%rcx),%xmm6,%xmm7 + vsubps %xmm4,%xmm6,%xmm2 + vsubps (%rcx),%xmm6,%xmm7 + vunpckhpd %xmm4,%xmm6,%xmm2 + vunpckhpd (%rcx),%xmm6,%xmm7 + vunpckhps %xmm4,%xmm6,%xmm2 + vunpckhps (%rcx),%xmm6,%xmm7 + vunpcklpd %xmm4,%xmm6,%xmm2 + vunpcklpd (%rcx),%xmm6,%xmm7 + vunpcklps %xmm4,%xmm6,%xmm2 + vunpcklps (%rcx),%xmm6,%xmm7 + vxorpd %xmm4,%xmm6,%xmm2 + vxorpd (%rcx),%xmm6,%xmm7 + vxorps %xmm4,%xmm6,%xmm2 + vxorps (%rcx),%xmm6,%xmm7 + vcmpeqpd %xmm4,%xmm6,%xmm2 + vcmpeqpd (%rcx),%xmm6,%xmm7 + vcmpltpd %xmm4,%xmm6,%xmm2 + vcmpltpd (%rcx),%xmm6,%xmm7 + vcmplepd %xmm4,%xmm6,%xmm2 + vcmplepd (%rcx),%xmm6,%xmm7 + vcmpunordpd %xmm4,%xmm6,%xmm2 + vcmpunordpd (%rcx),%xmm6,%xmm7 + vcmpneqpd %xmm4,%xmm6,%xmm2 + vcmpneqpd (%rcx),%xmm6,%xmm7 + vcmpnltpd %xmm4,%xmm6,%xmm2 + vcmpnltpd (%rcx),%xmm6,%xmm7 + vcmpnlepd %xmm4,%xmm6,%xmm2 + vcmpnlepd (%rcx),%xmm6,%xmm7 + vcmpordpd %xmm4,%xmm6,%xmm2 + vcmpordpd (%rcx),%xmm6,%xmm7 + vcmpeq_uqpd %xmm4,%xmm6,%xmm2 + vcmpeq_uqpd (%rcx),%xmm6,%xmm7 + vcmpngepd %xmm4,%xmm6,%xmm2 + vcmpngepd (%rcx),%xmm6,%xmm7 + vcmpngtpd %xmm4,%xmm6,%xmm2 + vcmpngtpd (%rcx),%xmm6,%xmm7 + vcmpfalsepd %xmm4,%xmm6,%xmm2 + vcmpfalsepd (%rcx),%xmm6,%xmm7 + vcmpneq_oqpd %xmm4,%xmm6,%xmm2 + vcmpneq_oqpd (%rcx),%xmm6,%xmm7 + vcmpgepd %xmm4,%xmm6,%xmm2 + vcmpgepd (%rcx),%xmm6,%xmm7 + vcmpgtpd %xmm4,%xmm6,%xmm2 + vcmpgtpd (%rcx),%xmm6,%xmm7 + vcmptruepd %xmm4,%xmm6,%xmm2 + vcmptruepd (%rcx),%xmm6,%xmm7 + vcmpeq_ospd %xmm4,%xmm6,%xmm2 + vcmpeq_ospd (%rcx),%xmm6,%xmm7 + vcmplt_oqpd %xmm4,%xmm6,%xmm2 + vcmplt_oqpd (%rcx),%xmm6,%xmm7 + vcmple_oqpd %xmm4,%xmm6,%xmm2 + vcmple_oqpd (%rcx),%xmm6,%xmm7 + vcmpunord_spd %xmm4,%xmm6,%xmm2 + vcmpunord_spd (%rcx),%xmm6,%xmm7 + vcmpneq_uspd %xmm4,%xmm6,%xmm2 + vcmpneq_uspd (%rcx),%xmm6,%xmm7 + vcmpnlt_uqpd %xmm4,%xmm6,%xmm2 + vcmpnlt_uqpd (%rcx),%xmm6,%xmm7 + vcmpnle_uqpd %xmm4,%xmm6,%xmm2 + vcmpnle_uqpd (%rcx),%xmm6,%xmm7 + vcmpord_spd %xmm4,%xmm6,%xmm2 + vcmpord_spd (%rcx),%xmm6,%xmm7 + vcmpeq_uspd %xmm4,%xmm6,%xmm2 + vcmpeq_uspd (%rcx),%xmm6,%xmm7 + vcmpnge_uqpd %xmm4,%xmm6,%xmm2 + vcmpnge_uqpd (%rcx),%xmm6,%xmm7 + vcmpngt_uqpd %xmm4,%xmm6,%xmm2 + vcmpngt_uqpd (%rcx),%xmm6,%xmm7 + vcmpfalse_ospd %xmm4,%xmm6,%xmm2 + vcmpfalse_ospd (%rcx),%xmm6,%xmm7 + vcmpneq_ospd %xmm4,%xmm6,%xmm2 + vcmpneq_ospd (%rcx),%xmm6,%xmm7 + vcmpge_oqpd %xmm4,%xmm6,%xmm2 + vcmpge_oqpd (%rcx),%xmm6,%xmm7 + vcmpgt_oqpd %xmm4,%xmm6,%xmm2 + vcmpgt_oqpd (%rcx),%xmm6,%xmm7 + vcmptrue_uspd %xmm4,%xmm6,%xmm2 + vcmptrue_uspd (%rcx),%xmm6,%xmm7 + vcmpeqps %xmm4,%xmm6,%xmm2 + vcmpeqps (%rcx),%xmm6,%xmm7 + vcmpltps %xmm4,%xmm6,%xmm2 + vcmpltps (%rcx),%xmm6,%xmm7 + vcmpleps %xmm4,%xmm6,%xmm2 + vcmpleps (%rcx),%xmm6,%xmm7 + vcmpunordps %xmm4,%xmm6,%xmm2 + vcmpunordps (%rcx),%xmm6,%xmm7 + vcmpneqps %xmm4,%xmm6,%xmm2 + vcmpneqps (%rcx),%xmm6,%xmm7 + vcmpnltps %xmm4,%xmm6,%xmm2 + vcmpnltps (%rcx),%xmm6,%xmm7 + vcmpnleps %xmm4,%xmm6,%xmm2 + vcmpnleps (%rcx),%xmm6,%xmm7 + vcmpordps %xmm4,%xmm6,%xmm2 + vcmpordps (%rcx),%xmm6,%xmm7 + vcmpeq_uqps %xmm4,%xmm6,%xmm2 + vcmpeq_uqps (%rcx),%xmm6,%xmm7 + vcmpngeps %xmm4,%xmm6,%xmm2 + vcmpngeps (%rcx),%xmm6,%xmm7 + vcmpngtps %xmm4,%xmm6,%xmm2 + vcmpngtps (%rcx),%xmm6,%xmm7 + vcmpfalseps %xmm4,%xmm6,%xmm2 + vcmpfalseps (%rcx),%xmm6,%xmm7 + vcmpneq_oqps %xmm4,%xmm6,%xmm2 + vcmpneq_oqps (%rcx),%xmm6,%xmm7 + vcmpgeps %xmm4,%xmm6,%xmm2 + vcmpgeps (%rcx),%xmm6,%xmm7 + vcmpgtps %xmm4,%xmm6,%xmm2 + vcmpgtps (%rcx),%xmm6,%xmm7 + vcmptrueps %xmm4,%xmm6,%xmm2 + vcmptrueps (%rcx),%xmm6,%xmm7 + vcmpeq_osps %xmm4,%xmm6,%xmm2 + vcmpeq_osps (%rcx),%xmm6,%xmm7 + vcmplt_oqps %xmm4,%xmm6,%xmm2 + vcmplt_oqps (%rcx),%xmm6,%xmm7 + vcmple_oqps %xmm4,%xmm6,%xmm2 + vcmple_oqps (%rcx),%xmm6,%xmm7 + vcmpunord_sps %xmm4,%xmm6,%xmm2 + vcmpunord_sps (%rcx),%xmm6,%xmm7 + vcmpneq_usps %xmm4,%xmm6,%xmm2 + vcmpneq_usps (%rcx),%xmm6,%xmm7 + vcmpnlt_uqps %xmm4,%xmm6,%xmm2 + vcmpnlt_uqps (%rcx),%xmm6,%xmm7 + vcmpnle_uqps %xmm4,%xmm6,%xmm2 + vcmpnle_uqps (%rcx),%xmm6,%xmm7 + vcmpord_sps %xmm4,%xmm6,%xmm2 + vcmpord_sps (%rcx),%xmm6,%xmm7 + vcmpeq_usps %xmm4,%xmm6,%xmm2 + vcmpeq_usps (%rcx),%xmm6,%xmm7 + vcmpnge_uqps %xmm4,%xmm6,%xmm2 + vcmpnge_uqps (%rcx),%xmm6,%xmm7 + vcmpngt_uqps %xmm4,%xmm6,%xmm2 + vcmpngt_uqps (%rcx),%xmm6,%xmm7 + vcmpfalse_osps %xmm4,%xmm6,%xmm2 + vcmpfalse_osps (%rcx),%xmm6,%xmm7 + vcmpneq_osps %xmm4,%xmm6,%xmm2 + vcmpneq_osps (%rcx),%xmm6,%xmm7 + vcmpge_oqps %xmm4,%xmm6,%xmm2 + vcmpge_oqps (%rcx),%xmm6,%xmm7 + vcmpgt_oqps %xmm4,%xmm6,%xmm2 + vcmpgt_oqps (%rcx),%xmm6,%xmm7 + vcmptrue_usps %xmm4,%xmm6,%xmm2 + vcmptrue_usps (%rcx),%xmm6,%xmm7 + +# Tests for op mem128, xmm, xmm + vmaskmovps (%rcx),%xmm4,%xmm6 + vmaskmovpd (%rcx),%xmm4,%xmm6 + +# Tests for op imm8, xmm/mem128, xmm + vpcmpestri $100,%xmm4,%xmm6 + vpcmpestri $100,(%rcx),%xmm6 + vpcmpestrm $100,%xmm4,%xmm6 + vpcmpestrm $100,(%rcx),%xmm6 + vpcmpistri $100,%xmm4,%xmm6 + vpcmpistri $100,(%rcx),%xmm6 + vpcmpistrm $100,%xmm4,%xmm6 + vpcmpistrm $100,(%rcx),%xmm6 + vpermilpd $100,%xmm4,%xmm6 + vpermilpd $100,(%rcx),%xmm6 + vpermilps $100,%xmm4,%xmm6 + vpermilps $100,(%rcx),%xmm6 + vpshufd $100,%xmm4,%xmm6 + vpshufd $100,(%rcx),%xmm6 + vpshufhw $100,%xmm4,%xmm6 + vpshufhw $100,(%rcx),%xmm6 + vpshuflw $100,%xmm4,%xmm6 + vpshuflw $100,(%rcx),%xmm6 + vroundpd $100,%xmm4,%xmm6 + vroundpd $100,(%rcx),%xmm6 + vroundps $100,%xmm4,%xmm6 + vroundps $100,(%rcx),%xmm6 + +# Tests for op xmm, xmm, mem128 + vmaskmovps %xmm4,%xmm6,(%rcx) + vmaskmovpd %xmm4,%xmm6,(%rcx) + +# Tests for op imm8, xmm/mem128, xmm, xmm + vblendpd $100,%xmm4,%xmm6,%xmm2 + vblendpd $100,(%rcx),%xmm6,%xmm2 + vblendps $100,%xmm4,%xmm6,%xmm2 + vblendps $100,(%rcx),%xmm6,%xmm2 + vcmppd $100,%xmm4,%xmm6,%xmm2 + vcmppd $100,(%rcx),%xmm6,%xmm2 + vcmpps $100,%xmm4,%xmm6,%xmm2 + vcmpps $100,(%rcx),%xmm6,%xmm2 + vdppd $100,%xmm4,%xmm6,%xmm2 + vdppd $100,(%rcx),%xmm6,%xmm2 + vdpps $100,%xmm4,%xmm6,%xmm2 + vdpps $100,(%rcx),%xmm6,%xmm2 + vmpsadbw $100,%xmm4,%xmm6,%xmm2 + vmpsadbw $100,(%rcx),%xmm6,%xmm2 + vpalignr $100,%xmm4,%xmm6,%xmm2 + vpalignr $100,(%rcx),%xmm6,%xmm2 + vpblendw $100,%xmm4,%xmm6,%xmm2 + vpblendw $100,(%rcx),%xmm6,%xmm2 + vshufpd $100,%xmm4,%xmm6,%xmm2 + vshufpd $100,(%rcx),%xmm6,%xmm2 + vshufps $100,%xmm4,%xmm6,%xmm2 + vshufps $100,(%rcx),%xmm6,%xmm2 + +# Tests for op xmm, xmm/mem128, xmm, xmm + vblendvpd %xmm4,%xmm6,%xmm2,%xmm7 + vblendvpd %xmm4,(%rcx),%xmm2,%xmm7 + vblendvps %xmm4,%xmm6,%xmm2,%xmm7 + vblendvps %xmm4,(%rcx),%xmm2,%xmm7 + vpblendvb %xmm4,%xmm6,%xmm2,%xmm7 + vpblendvb %xmm4,(%rcx),%xmm2,%xmm7 + +# Tests for op xmm/mem128, xmm, xmm, xmm +# Tests for op xmm, xmm/mem128, xmm, xmm + vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddpd (%rcx),%xmm6,%xmm2,%xmm7 + vfmaddpd %xmm4,(%rcx),%xmm2,%xmm7 + vfmaddps %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddps (%rcx),%xmm6,%xmm2,%xmm7 + vfmaddps %xmm4,(%rcx),%xmm2,%xmm7 + vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddsubpd (%rcx),%xmm6,%xmm2,%xmm7 + vfmaddsubpd %xmm4,(%rcx),%xmm2,%xmm7 + vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddsubps (%rcx),%xmm6,%xmm2,%xmm7 + vfmaddsubps %xmm4,(%rcx),%xmm2,%xmm7 + vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubaddpd (%rcx),%xmm6,%xmm2,%xmm7 + vfmsubaddpd %xmm4,(%rcx),%xmm2,%xmm7 + vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubaddps (%rcx),%xmm6,%xmm2,%xmm7 + vfmsubaddps %xmm4,(%rcx),%xmm2,%xmm7 + vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubpd (%rcx),%xmm6,%xmm2,%xmm7 + vfmsubpd %xmm4,(%rcx),%xmm2,%xmm7 + vfmsubps %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubps (%rcx),%xmm6,%xmm2,%xmm7 + vfmsubps %xmm4,(%rcx),%xmm2,%xmm7 + vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7 + vfnmaddpd (%rcx),%xmm6,%xmm2,%xmm7 + vfnmaddpd %xmm4,(%rcx),%xmm2,%xmm7 + vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7 + vfnmaddps (%rcx),%xmm6,%xmm2,%xmm7 + vfnmaddps %xmm4,(%rcx),%xmm2,%xmm7 + vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7 + vfnmsubpd (%rcx),%xmm6,%xmm2,%xmm7 + vfnmsubpd %xmm4,(%rcx),%xmm2,%xmm7 + vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7 + vfnmsubps (%rcx),%xmm6,%xmm2,%xmm7 + vfnmsubps %xmm4,(%rcx),%xmm2,%xmm7 + vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7 + vpermilmo2pd (%rcx),%xmm6,%xmm2,%xmm7 + vpermilmo2pd %xmm4,(%rcx),%xmm2,%xmm7 + vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7 + vpermilmz2pd (%rcx),%xmm6,%xmm2,%xmm7 + vpermilmz2pd %xmm4,(%rcx),%xmm2,%xmm7 + vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7 + vpermiltd2pd (%rcx),%xmm6,%xmm2,%xmm7 + vpermiltd2pd %xmm4,(%rcx),%xmm2,%xmm7 + vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7 + vpermilmo2ps (%rcx),%xmm6,%xmm2,%xmm7 + vpermilmo2ps %xmm4,(%rcx),%xmm2,%xmm7 + vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7 + vpermilmz2ps (%rcx),%xmm6,%xmm2,%xmm7 + vpermilmz2ps %xmm4,(%rcx),%xmm2,%xmm7 + vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7 + vpermiltd2ps (%rcx),%xmm6,%xmm2,%xmm7 + vpermiltd2ps %xmm4,(%rcx),%xmm2,%xmm7 + +# Tests for op imm4, xmm/mem128, xmm, xmm, xmm +# Tests for op imm4, xmm, xmm/mem128, xmm, xmm + vpermil2pd $10,%xmm4,%xmm6,%xmm2,%xmm7 + vpermil2pd $10,(%rcx),%xmm6,%xmm2,%xmm7 + vpermil2pd $10,%xmm4,(%rcx),%xmm2,%xmm7 + vpermil2ps $10,%xmm4,%xmm6,%xmm2,%xmm7 + vpermil2ps $10,(%rcx),%xmm6,%xmm2,%xmm7 + vpermil2ps $10,%xmm4,(%rcx),%xmm2,%xmm7 + +# Tests for op mem64, ymm + vbroadcastsd (%rcx),%ymm4 + +# Tests for op xmm/mem64, xmm + vcomisd %xmm4,%xmm6 + vcomisd (%rcx),%xmm4 + vcvtdq2pd %xmm4,%xmm6 + vcvtdq2pd (%rcx),%xmm4 + vcvtps2pd %xmm4,%xmm6 + vcvtps2pd (%rcx),%xmm4 + vmovddup %xmm4,%xmm6 + vmovddup (%rcx),%xmm4 + vpmovsxbw %xmm4,%xmm6 + vpmovsxbw (%rcx),%xmm4 + vpmovsxwd %xmm4,%xmm6 + vpmovsxwd (%rcx),%xmm4 + vpmovsxdq %xmm4,%xmm6 + vpmovsxdq (%rcx),%xmm4 + vpmovzxbw %xmm4,%xmm6 + vpmovzxbw (%rcx),%xmm4 + vpmovzxwd %xmm4,%xmm6 + vpmovzxwd (%rcx),%xmm4 + vpmovzxdq %xmm4,%xmm6 + vpmovzxdq (%rcx),%xmm4 + vucomisd %xmm4,%xmm6 + vucomisd (%rcx),%xmm4 + +# Tests for op mem64, xmm + vmovsd (%rcx),%xmm4 + +# Tests for op xmm, mem64 + vmovlpd %xmm4,(%rcx) + vmovlps %xmm4,(%rcx) + vmovhpd %xmm4,(%rcx) + vmovhps %xmm4,(%rcx) + vmovsd %xmm4,(%rcx) + +# Tests for op xmm, regq/mem64 +# Tests for op regq/mem64, xmm + vmovq %xmm4,%rcx + vmovq %rcx,%xmm4 + vmovq %xmm4,(%rcx) + vmovq (%rcx),%xmm4 + +# Tests for op xmm/mem64, regl + vcvtsd2si %xmm4,%ecx + vcvtsd2si (%rcx),%ecx + vcvttsd2si %xmm4,%ecx + vcvttsd2si (%rcx),%ecx + +# Tests for op xmm/mem64, regq + vcvtsd2si %xmm4,%rcx + vcvtsd2si (%rcx),%rcx + vcvttsd2si %xmm4,%rcx + vcvttsd2si (%rcx),%rcx + +# Tests for op regq/mem64, xmm, xmm + vcvtsi2sdq %rcx,%xmm4,%xmm6 + vcvtsi2sdq (%rcx),%xmm4,%xmm6 + vcvtsi2ssq %rcx,%xmm4,%xmm6 + vcvtsi2ssq (%rcx),%xmm4,%xmm6 + +# Tests for op imm8, regq/mem64, xmm, xmm + vpinsrq $100,%rcx,%xmm4,%xmm6 + vpinsrq $100,(%rcx),%xmm4,%xmm6 + +# Testsf for op imm8, xmm, regq/mem64 + vpextrq $100,%xmm4,%rcx + vpextrq $100,%xmm4,(%rcx) + +# Tests for op mem64, xmm, xmm + vmovlpd (%rcx),%xmm4,%xmm6 + vmovlps (%rcx),%xmm4,%xmm6 + vmovhpd (%rcx),%xmm4,%xmm6 + vmovhps (%rcx),%xmm4,%xmm6 + +# Tests for op imm8, xmm/mem64, xmm, xmm + vcmpsd $100,%xmm4,%xmm6,%xmm2 + vcmpsd $100,(%rcx),%xmm6,%xmm2 + vroundsd $100,%xmm4,%xmm6,%xmm2 + vroundsd $100,(%rcx),%xmm6,%xmm2 + +# Tests for op xmm/mem64, xmm, xmm, xmm +# Tests for op xmm, xmm/mem64, xmm, xmm + vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddsd (%rcx),%xmm6,%xmm2,%xmm7 + vfmaddsd %xmm4,(%rcx),%xmm2,%xmm7 + vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubsd (%rcx),%xmm6,%xmm2,%xmm7 + vfmsubsd %xmm4,(%rcx),%xmm2,%xmm7 + vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7 + vfnmaddsd (%rcx),%xmm6,%xmm2,%xmm7 + vfnmaddsd %xmm4,(%rcx),%xmm2,%xmm7 + vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7 + vfnmsubsd (%rcx),%xmm6,%xmm2,%xmm7 + vfnmsubsd %xmm4,(%rcx),%xmm2,%xmm7 + +# Tests for op xmm/mem64, xmm, xmm + vaddsd %xmm4,%xmm6,%xmm2 + vaddsd (%rcx),%xmm6,%xmm2 + vcvtsd2ss %xmm4,%xmm6,%xmm2 + vcvtsd2ss (%rcx),%xmm6,%xmm2 + vdivsd %xmm4,%xmm6,%xmm2 + vdivsd (%rcx),%xmm6,%xmm2 + vmaxsd %xmm4,%xmm6,%xmm2 + vmaxsd (%rcx),%xmm6,%xmm2 + vminsd %xmm4,%xmm6,%xmm2 + vminsd (%rcx),%xmm6,%xmm2 + vmulsd %xmm4,%xmm6,%xmm2 + vmulsd (%rcx),%xmm6,%xmm2 + vsqrtsd %xmm4,%xmm6,%xmm2 + vsqrtsd (%rcx),%xmm6,%xmm2 + vsubsd %xmm4,%xmm6,%xmm2 + vsubsd (%rcx),%xmm6,%xmm2 + vcmpeqsd %xmm4,%xmm6,%xmm2 + vcmpeqsd (%rcx),%xmm6,%xmm2 + vcmpltsd %xmm4,%xmm6,%xmm2 + vcmpltsd (%rcx),%xmm6,%xmm2 + vcmplesd %xmm4,%xmm6,%xmm2 + vcmplesd (%rcx),%xmm6,%xmm2 + vcmpunordsd %xmm4,%xmm6,%xmm2 + vcmpunordsd (%rcx),%xmm6,%xmm2 + vcmpneqsd %xmm4,%xmm6,%xmm2 + vcmpneqsd (%rcx),%xmm6,%xmm2 + vcmpnltsd %xmm4,%xmm6,%xmm2 + vcmpnltsd (%rcx),%xmm6,%xmm2 + vcmpnlesd %xmm4,%xmm6,%xmm2 + vcmpnlesd (%rcx),%xmm6,%xmm2 + vcmpordsd %xmm4,%xmm6,%xmm2 + vcmpordsd (%rcx),%xmm6,%xmm2 + vcmpeq_uqsd %xmm4,%xmm6,%xmm2 + vcmpeq_uqsd (%rcx),%xmm6,%xmm2 + vcmpngesd %xmm4,%xmm6,%xmm2 + vcmpngesd (%rcx),%xmm6,%xmm2 + vcmpngtsd %xmm4,%xmm6,%xmm2 + vcmpngtsd (%rcx),%xmm6,%xmm2 + vcmpfalsesd %xmm4,%xmm6,%xmm2 + vcmpfalsesd (%rcx),%xmm6,%xmm2 + vcmpneq_oqsd %xmm4,%xmm6,%xmm2 + vcmpneq_oqsd (%rcx),%xmm6,%xmm2 + vcmpgesd %xmm4,%xmm6,%xmm2 + vcmpgesd (%rcx),%xmm6,%xmm2 + vcmpgtsd %xmm4,%xmm6,%xmm2 + vcmpgtsd (%rcx),%xmm6,%xmm2 + vcmptruesd %xmm4,%xmm6,%xmm2 + vcmptruesd (%rcx),%xmm6,%xmm2 + vcmpeq_ossd %xmm4,%xmm6,%xmm2 + vcmpeq_ossd (%rcx),%xmm6,%xmm2 + vcmplt_oqsd %xmm4,%xmm6,%xmm2 + vcmplt_oqsd (%rcx),%xmm6,%xmm2 + vcmple_oqsd %xmm4,%xmm6,%xmm2 + vcmple_oqsd (%rcx),%xmm6,%xmm2 + vcmpunord_ssd %xmm4,%xmm6,%xmm2 + vcmpunord_ssd (%rcx),%xmm6,%xmm2 + vcmpneq_ussd %xmm4,%xmm6,%xmm2 + vcmpneq_ussd (%rcx),%xmm6,%xmm2 + vcmpnlt_uqsd %xmm4,%xmm6,%xmm2 + vcmpnlt_uqsd (%rcx),%xmm6,%xmm2 + vcmpnle_uqsd %xmm4,%xmm6,%xmm2 + vcmpnle_uqsd (%rcx),%xmm6,%xmm2 + vcmpord_ssd %xmm4,%xmm6,%xmm2 + vcmpord_ssd (%rcx),%xmm6,%xmm2 + vcmpeq_ussd %xmm4,%xmm6,%xmm2 + vcmpeq_ussd (%rcx),%xmm6,%xmm2 + vcmpnge_uqsd %xmm4,%xmm6,%xmm2 + vcmpnge_uqsd (%rcx),%xmm6,%xmm2 + vcmpngt_uqsd %xmm4,%xmm6,%xmm2 + vcmpngt_uqsd (%rcx),%xmm6,%xmm2 + vcmpfalse_ossd %xmm4,%xmm6,%xmm2 + vcmpfalse_ossd (%rcx),%xmm6,%xmm2 + vcmpneq_ossd %xmm4,%xmm6,%xmm2 + vcmpneq_ossd (%rcx),%xmm6,%xmm2 + vcmpge_oqsd %xmm4,%xmm6,%xmm2 + vcmpge_oqsd (%rcx),%xmm6,%xmm2 + vcmpgt_oqsd %xmm4,%xmm6,%xmm2 + vcmpgt_oqsd (%rcx),%xmm6,%xmm2 + vcmptrue_ussd %xmm4,%xmm6,%xmm2 + vcmptrue_ussd (%rcx),%xmm6,%xmm2 + +# Tests for op xmm/mem32, xmm, xmm + vaddss %xmm4,%xmm6,%xmm2 + vaddss (%rcx),%xmm6,%xmm2 + vcvtss2sd %xmm4,%xmm6,%xmm2 + vcvtss2sd (%rcx),%xmm6,%xmm2 + vdivss %xmm4,%xmm6,%xmm2 + vdivss (%rcx),%xmm6,%xmm2 + vmaxss %xmm4,%xmm6,%xmm2 + vmaxss (%rcx),%xmm6,%xmm2 + vminss %xmm4,%xmm6,%xmm2 + vminss (%rcx),%xmm6,%xmm2 + vmulss %xmm4,%xmm6,%xmm2 + vmulss (%rcx),%xmm6,%xmm2 + vrcpss %xmm4,%xmm6,%xmm2 + vrcpss (%rcx),%xmm6,%xmm2 + vrsqrtss %xmm4,%xmm6,%xmm2 + vrsqrtss (%rcx),%xmm6,%xmm2 + vsqrtss %xmm4,%xmm6,%xmm2 + vsqrtss (%rcx),%xmm6,%xmm2 + vsubss %xmm4,%xmm6,%xmm2 + vsubss (%rcx),%xmm6,%xmm2 + vcmpeqss %xmm4,%xmm6,%xmm2 + vcmpeqss (%rcx),%xmm6,%xmm2 + vcmpltss %xmm4,%xmm6,%xmm2 + vcmpltss (%rcx),%xmm6,%xmm2 + vcmpless %xmm4,%xmm6,%xmm2 + vcmpless (%rcx),%xmm6,%xmm2 + vcmpunordss %xmm4,%xmm6,%xmm2 + vcmpunordss (%rcx),%xmm6,%xmm2 + vcmpneqss %xmm4,%xmm6,%xmm2 + vcmpneqss (%rcx),%xmm6,%xmm2 + vcmpnltss %xmm4,%xmm6,%xmm2 + vcmpnltss (%rcx),%xmm6,%xmm2 + vcmpnless %xmm4,%xmm6,%xmm2 + vcmpnless (%rcx),%xmm6,%xmm2 + vcmpordss %xmm4,%xmm6,%xmm2 + vcmpordss (%rcx),%xmm6,%xmm2 + vcmpeq_uqss %xmm4,%xmm6,%xmm2 + vcmpeq_uqss (%rcx),%xmm6,%xmm2 + vcmpngess %xmm4,%xmm6,%xmm2 + vcmpngess (%rcx),%xmm6,%xmm2 + vcmpngtss %xmm4,%xmm6,%xmm2 + vcmpngtss (%rcx),%xmm6,%xmm2 + vcmpfalsess %xmm4,%xmm6,%xmm2 + vcmpfalsess (%rcx),%xmm6,%xmm2 + vcmpneq_oqss %xmm4,%xmm6,%xmm2 + vcmpneq_oqss (%rcx),%xmm6,%xmm2 + vcmpgess %xmm4,%xmm6,%xmm2 + vcmpgess (%rcx),%xmm6,%xmm2 + vcmpgtss %xmm4,%xmm6,%xmm2 + vcmpgtss (%rcx),%xmm6,%xmm2 + vcmptruess %xmm4,%xmm6,%xmm2 + vcmptruess (%rcx),%xmm6,%xmm2 + vcmpeq_osss %xmm4,%xmm6,%xmm2 + vcmpeq_osss (%rcx),%xmm6,%xmm2 + vcmplt_oqss %xmm4,%xmm6,%xmm2 + vcmplt_oqss (%rcx),%xmm6,%xmm2 + vcmple_oqss %xmm4,%xmm6,%xmm2 + vcmple_oqss (%rcx),%xmm6,%xmm2 + vcmpunord_sss %xmm4,%xmm6,%xmm2 + vcmpunord_sss (%rcx),%xmm6,%xmm2 + vcmpneq_usss %xmm4,%xmm6,%xmm2 + vcmpneq_usss (%rcx),%xmm6,%xmm2 + vcmpnlt_uqss %xmm4,%xmm6,%xmm2 + vcmpnlt_uqss (%rcx),%xmm6,%xmm2 + vcmpnle_uqss %xmm4,%xmm6,%xmm2 + vcmpnle_uqss (%rcx),%xmm6,%xmm2 + vcmpord_sss %xmm4,%xmm6,%xmm2 + vcmpord_sss (%rcx),%xmm6,%xmm2 + vcmpeq_usss %xmm4,%xmm6,%xmm2 + vcmpeq_usss (%rcx),%xmm6,%xmm2 + vcmpnge_uqss %xmm4,%xmm6,%xmm2 + vcmpnge_uqss (%rcx),%xmm6,%xmm2 + vcmpngt_uqss %xmm4,%xmm6,%xmm2 + vcmpngt_uqss (%rcx),%xmm6,%xmm2 + vcmpfalse_osss %xmm4,%xmm6,%xmm2 + vcmpfalse_osss (%rcx),%xmm6,%xmm2 + vcmpneq_osss %xmm4,%xmm6,%xmm2 + vcmpneq_osss (%rcx),%xmm6,%xmm2 + vcmpge_oqss %xmm4,%xmm6,%xmm2 + vcmpge_oqss (%rcx),%xmm6,%xmm2 + vcmpgt_oqss %xmm4,%xmm6,%xmm2 + vcmpgt_oqss (%rcx),%xmm6,%xmm2 + vcmptrue_usss %xmm4,%xmm6,%xmm2 + vcmptrue_usss (%rcx),%xmm6,%xmm2 + +# Tests for op mem32, ymm + vbroadcastss (%rcx),%ymm4 + +# Tests for op xmm/mem32, xmm + vcomiss %xmm4,%xmm6 + vcomiss (%rcx),%xmm4 + vpmovsxbd %xmm4,%xmm6 + vpmovsxbd (%rcx),%xmm4 + vpmovsxwq %xmm4,%xmm6 + vpmovsxwq (%rcx),%xmm4 + vpmovzxbd %xmm4,%xmm6 + vpmovzxbd (%rcx),%xmm4 + vpmovzxwq %xmm4,%xmm6 + vpmovzxwq (%rcx),%xmm4 + vucomiss %xmm4,%xmm6 + vucomiss (%rcx),%xmm4 + +# Tests for op mem32, xmm + vbroadcastss (%rcx),%xmm4 + vmovss (%rcx),%xmm4 + +# Tests for op xmm, mem32 + vmovss %xmm4,(%rcx) + +# Tests for op xmm, regl/mem32 +# Tests for op regl/mem32, xmm + vmovd %xmm4,%ecx + vmovd %xmm4,(%rcx) + vmovd %ecx,%xmm4 + vmovd (%rcx),%xmm4 + +# Tests for op xmm/mem32, regl + vcvtss2si %xmm4,%ecx + vcvtss2si (%rcx),%ecx + vcvttss2si %xmm4,%ecx + vcvttss2si (%rcx),%ecx + +# Tests for op xmm/mem32, regq + vcvtss2si %xmm4,%rcx + vcvtss2si (%rcx),%rcx + vcvttss2si %xmm4,%rcx + vcvttss2si (%rcx),%rcx + +# Tests for op xmm, regq + vmovmskpd %xmm4,%rcx + vmovmskps %xmm4,%rcx + vpmovmskb %xmm4,%rcx + +# Tests for op imm8, xmm, regq/mem32 + vextractps $100,%xmm4,%rcx + vextractps $100,%xmm4,(%rcx) +# Tests for op imm8, xmm, regl/mem32 + vpextrd $100,%xmm4,%ecx + vpextrd $100,%xmm4,(%rcx) + vextractps $100,%xmm4,%ecx + vextractps $100,%xmm4,(%rcx) + +# Tests for op regl/mem32, xmm, xmm + vcvtsi2sd %ecx,%xmm4,%xmm6 + vcvtsi2sd (%rcx),%xmm4,%xmm6 + vcvtsi2ss %ecx,%xmm4,%xmm6 + vcvtsi2ss (%rcx),%xmm4,%xmm6 + +# Tests for op imm8, xmm/mem32, xmm, xmm + vcmpss $100,%xmm4,%xmm6,%xmm2 + vcmpss $100,(%rcx),%xmm6,%xmm2 + vinsertps $100,%xmm4,%xmm6,%xmm2 + vinsertps $100,(%rcx),%xmm6,%xmm2 + vroundss $100,%xmm4,%xmm6,%xmm2 + vroundss $100,(%rcx),%xmm6,%xmm2 + +# Tests for op xmm/mem32, xmm, xmm, xmm +# Tests for op xmm, xmm/mem32, xmm, xmm + vfmaddss %xmm4,%xmm6,%xmm2,%xmm7 + vfmaddss (%rcx),%xmm6,%xmm2,%xmm7 + vfmaddss %xmm4,(%rcx),%xmm2,%xmm7 + vfmsubss %xmm4,%xmm6,%xmm2,%xmm7 + vfmsubss (%rcx),%xmm6,%xmm2,%xmm7 + vfmsubss %xmm4,(%rcx),%xmm2,%xmm7 + vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7 + vfnmaddss (%rcx),%xmm6,%xmm2,%xmm7 + vfnmaddss %xmm4,(%rcx),%xmm2,%xmm7 + vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7 + vfnmsubss (%rcx),%xmm6,%xmm2,%xmm7 + vfnmsubss %xmm4,(%rcx),%xmm2,%xmm7 + +# Tests for op xmm/m16, xmm + vpmovsxbq %xmm4,%xmm6 + vpmovsxbq (%rcx),%xmm4 + vpmovzxbq %xmm4,%xmm6 + vpmovzxbq (%rcx),%xmm4 + +# Tests for op imm8, xmm, regl/mem16 + vpextrw $100,%xmm4,%ecx + vpextrw $100,%xmm4,(%rcx) + +# Tests for op imm8, xmm, regq/mem16 + vpextrw $100,%xmm4,%rcx + vpextrw $100,%xmm4,(%rcx) + +# Tests for op imm8, regl/mem16, xmm, xmm + vpinsrw $100,%ecx,%xmm4,%xmm6 + vpinsrw $100,(%rcx),%xmm4,%xmm6 + + + vpinsrw $100,%rcx,%xmm4,%xmm6 + vpinsrw $100,(%rcx),%xmm4,%xmm6 + +# Tests for op imm8, xmm, regl/mem8 + vpextrb $100,%xmm4,%ecx + vpextrb $100,%xmm4,(%rcx) + +# Tests for op imm8, regl/mem8, xmm, xmm + vpinsrb $100,%ecx,%xmm4,%xmm6 + vpinsrb $100,(%rcx),%xmm4,%xmm6 + +# Tests for op imm8, xmm, regq + vpextrw $100,%xmm4,%rcx +# Tests for op imm8, xmm, regq/mem8 + vpextrb $100,%xmm4,%rcx + vpextrb $100,%xmm4,(%rcx) + +# Tests for op imm8, regl/mem8, xmm, xmm + vpinsrb $100,%ecx,%xmm4,%xmm6 + vpinsrb $100,(%rcx),%xmm4,%xmm6 + +# Tests for op xmm, xmm + vmaskmovdqu %xmm4,%xmm6 + vmovq %xmm4,%xmm6 + +# Tests for op xmm, regl + vmovmskpd %xmm4,%ecx + vmovmskps %xmm4,%ecx + vpmovmskb %xmm4,%ecx +# Tests for op xmm, xmm, xmm + vmovhlps %xmm4,%xmm6,%xmm2 + vmovlhps %xmm4,%xmm6,%xmm2 + vmovsd %xmm4,%xmm6,%xmm2 + vmovss %xmm4,%xmm6,%xmm2 + +# Tests for op imm8, xmm, xmm + vpslld $100,%xmm4,%xmm6 + vpslldq $100,%xmm4,%xmm6 + vpsllq $100,%xmm4,%xmm6 + vpsllw $100,%xmm4,%xmm6 + vpsrad $100,%xmm4,%xmm6 + vpsraw $100,%xmm4,%xmm6 + vpsrld $100,%xmm4,%xmm6 + vpsrldq $100,%xmm4,%xmm6 + vpsrlq $100,%xmm4,%xmm6 + vpsrlw $100,%xmm4,%xmm6 + +# Tests for op imm8, xmm, regl + vpextrw $100,%xmm4,%ecx + +# Tests for op ymm, regl + vmovmskpd %ymm4,%ecx + vmovmskps %ymm4,%ecx + +# Tests for op ymm, regq + vmovmskpd %ymm4,%rcx + vmovmskps %ymm4,%rcx + + +# Default instructions without suffixes. + vcvtpd2dq %xmm4,%xmm6 + vcvtpd2dq %ymm4,%xmm6 + vcvtpd2ps %xmm4,%xmm6 + vcvtpd2ps %ymm4,%xmm6 + vcvttpd2dq %xmm4,%xmm6 + vcvttpd2dq %ymm4,%xmm6 + +#Tests with different memory and register operands. + vldmxcsr 0x12345678 + vmovdqa 0x12345678,%xmm8 + vmovdqa %xmm8,0x12345678 + vmovd %xmm8,0x12345678 + vcvtsd2si 0x12345678,%r8d + vcvtdq2pd 0x12345678,%ymm8 + vcvtpd2psy 0x12345678,%xmm8 + vpavgb 0x12345678,%xmm8,%xmm15 + vpextrb $100,%xmm8,0x12345678 + vcvtsi2sdl 0x12345678,%xmm8,%xmm15 + vblendvps %xmm8,0x12345678,%xmm12,%xmm14 + vpinsrb $100,0x12345678,%xmm8,%xmm15 + vmovdqa 0x12345678,%ymm8 + vmovdqa %ymm8,0x12345678 + vpermilpd 0x12345678,%ymm8,%ymm15 + vroundpd $100,0x12345678,%ymm8 + vextractf128 $100,%ymm8,0x12345678 + vperm2f128 $100,0x12345678,%ymm8,%ymm15 + vblendvpd %ymm8,0x12345678,%ymm12,%ymm14 + vldmxcsr (%rbp) + vmovdqa (%rbp),%xmm8 + vmovdqa %xmm8,(%rbp) + vmovd %xmm8,(%rbp) + vcvtsd2si (%rbp),%r8d + vcvtdq2pd (%rbp),%ymm8 + vcvtpd2psy (%rbp),%xmm8 + vpavgb (%rbp),%xmm8,%xmm15 + vpextrb $100,%xmm8,(%rbp) + vcvtsi2sdl (%rbp),%xmm8,%xmm15 + vblendvps %xmm8,(%rbp),%xmm12,%xmm14 + vpinsrb $100,(%rbp),%xmm8,%xmm15 + vmovdqa (%rbp),%ymm8 + vmovdqa %ymm8,(%rbp) + vpermilpd (%rbp),%ymm8,%ymm15 + vroundpd $100,(%rbp),%ymm8 + vextractf128 $100,%ymm8,(%rbp) + vperm2f128 $100,(%rbp),%ymm8,%ymm15 + vblendvpd %ymm8,(%rbp),%ymm12,%ymm14 + vldmxcsr (%rsp) + vmovdqa (%rsp),%xmm8 + vmovdqa %xmm8,(%rsp) + vmovd %xmm8,(%rsp) + vcvtsd2si (%rsp),%r8d + vcvtdq2pd (%rsp),%ymm8 + vcvtpd2psy (%rsp),%xmm8 + vpavgb (%rsp),%xmm8,%xmm15 + vpextrb $100,%xmm8,(%rsp) + vcvtsi2sdl (%rsp),%xmm8,%xmm15 + vblendvps %xmm8,(%rsp),%xmm12,%xmm14 + vpinsrb $100,(%rsp),%xmm8,%xmm15 + vmovdqa (%rsp),%ymm8 + vmovdqa %ymm8,(%rsp) + vpermilpd (%rsp),%ymm8,%ymm15 + vroundpd $100,(%rsp),%ymm8 + vextractf128 $100,%ymm8,(%rsp) + vperm2f128 $100,(%rsp),%ymm8,%ymm15 + vblendvpd %ymm8,(%rsp),%ymm12,%ymm14 + vldmxcsr 0x99(%rbp) + vmovdqa 0x99(%rbp),%xmm8 + vmovdqa %xmm8,0x99(%rbp) + vmovd %xmm8,0x99(%rbp) + vcvtsd2si 0x99(%rbp),%r8d + vcvtdq2pd 0x99(%rbp),%ymm8 + vcvtpd2psy 0x99(%rbp),%xmm8 + vpavgb 0x99(%rbp),%xmm8,%xmm15 + vpextrb $100,%xmm8,0x99(%rbp) + vcvtsi2sdl 0x99(%rbp),%xmm8,%xmm15 + vblendvps %xmm8,0x99(%rbp),%xmm12,%xmm14 + vpinsrb $100,0x99(%rbp),%xmm8,%xmm15 + vmovdqa 0x99(%rbp),%ymm8 + vmovdqa %ymm8,0x99(%rbp) + vpermilpd 0x99(%rbp),%ymm8,%ymm15 + vroundpd $100,0x99(%rbp),%ymm8 + vextractf128 $100,%ymm8,0x99(%rbp) + vperm2f128 $100,0x99(%rbp),%ymm8,%ymm15 + vblendvpd %ymm8,0x99(%rbp),%ymm12,%ymm14 + vldmxcsr 0x99(%r15) + vmovdqa 0x99(%r15),%xmm8 + vmovdqa %xmm8,0x99(%r15) + vmovd %xmm8,0x99(%r15) + vcvtsd2si 0x99(%r15),%r8d + vcvtdq2pd 0x99(%r15),%ymm8 + vcvtpd2psy 0x99(%r15),%xmm8 + vpavgb 0x99(%r15),%xmm8,%xmm15 + vpextrb $100,%xmm8,0x99(%r15) + vcvtsi2sdl 0x99(%r15),%xmm8,%xmm15 + vblendvps %xmm8,0x99(%r15),%xmm12,%xmm14 + vpinsrb $100,0x99(%r15),%xmm8,%xmm15 + vmovdqa 0x99(%r15),%ymm8 + vmovdqa %ymm8,0x99(%r15) + vpermilpd 0x99(%r15),%ymm8,%ymm15 + vroundpd $100,0x99(%r15),%ymm8 + vextractf128 $100,%ymm8,0x99(%r15) + vperm2f128 $100,0x99(%r15),%ymm8,%ymm15 + vblendvpd %ymm8,0x99(%r15),%ymm12,%ymm14 + vldmxcsr 0x99(%rip) + vmovdqa 0x99(%rip),%xmm8 + vmovdqa %xmm8,0x99(%rip) + vmovd %xmm8,0x99(%rip) + vcvtsd2si 0x99(%rip),%r8d + vcvtdq2pd 0x99(%rip),%ymm8 + vcvtpd2psy 0x99(%rip),%xmm8 + vpavgb 0x99(%rip),%xmm8,%xmm15 + vpextrb $100,%xmm8,0x99(%rip) + vcvtsi2sdl 0x99(%rip),%xmm8,%xmm15 + vblendvps %xmm8,0x99(%rip),%xmm12,%xmm14 + vpinsrb $100,0x99(%rip),%xmm8,%xmm15 + vmovdqa 0x99(%rip),%ymm8 + vmovdqa %ymm8,0x99(%rip) + vpermilpd 0x99(%rip),%ymm8,%ymm15 + vroundpd $100,0x99(%rip),%ymm8 + vextractf128 $100,%ymm8,0x99(%rip) + vperm2f128 $100,0x99(%rip),%ymm8,%ymm15 + vblendvpd %ymm8,0x99(%rip),%ymm12,%ymm14 + vldmxcsr 0x99(%rsp) + vmovdqa 0x99(%rsp),%xmm8 + vmovdqa %xmm8,0x99(%rsp) + vmovd %xmm8,0x99(%rsp) + vcvtsd2si 0x99(%rsp),%r8d + vcvtdq2pd 0x99(%rsp),%ymm8 + vcvtpd2psy 0x99(%rsp),%xmm8 + vpavgb 0x99(%rsp),%xmm8,%xmm15 + vpextrb $100,%xmm8,0x99(%rsp) + vcvtsi2sdl 0x99(%rsp),%xmm8,%xmm15 + vblendvps %xmm8,0x99(%rsp),%xmm12,%xmm14 + vpinsrb $100,0x99(%rsp),%xmm8,%xmm15 + vmovdqa 0x99(%rsp),%ymm8 + vmovdqa %ymm8,0x99(%rsp) + vpermilpd 0x99(%rsp),%ymm8,%ymm15 + vroundpd $100,0x99(%rsp),%ymm8 + vextractf128 $100,%ymm8,0x99(%rsp) + vperm2f128 $100,0x99(%rsp),%ymm8,%ymm15 + vblendvpd %ymm8,0x99(%rsp),%ymm12,%ymm14 + vldmxcsr 0x99(%r12) + vmovdqa 0x99(%r12),%xmm8 + vmovdqa %xmm8,0x99(%r12) + vmovd %xmm8,0x99(%r12) + vcvtsd2si 0x99(%r12),%r8d + vcvtdq2pd 0x99(%r12),%ymm8 + vcvtpd2psy 0x99(%r12),%xmm8 + vpavgb 0x99(%r12),%xmm8,%xmm15 + vpextrb $100,%xmm8,0x99(%r12) + vcvtsi2sdl 0x99(%r12),%xmm8,%xmm15 + vblendvps %xmm8,0x99(%r12),%xmm12,%xmm14 + vpinsrb $100,0x99(%r12),%xmm8,%xmm15 + vmovdqa 0x99(%r12),%ymm8 + vmovdqa %ymm8,0x99(%r12) + vpermilpd 0x99(%r12),%ymm8,%ymm15 + vroundpd $100,0x99(%r12),%ymm8 + vextractf128 $100,%ymm8,0x99(%r12) + vperm2f128 $100,0x99(%r12),%ymm8,%ymm15 + vblendvpd %ymm8,0x99(%r12),%ymm12,%ymm14 + vldmxcsr -0x99(,%riz) + vmovdqa -0x99(,%riz),%xmm8 + vmovdqa %xmm8,-0x99(,%riz) + vmovd %xmm8,-0x99(,%riz) + vcvtsd2si -0x99(,%riz),%r8d + vcvtdq2pd -0x99(,%riz),%ymm8 + vcvtpd2psy -0x99(,%riz),%xmm8 + vpavgb -0x99(,%riz),%xmm8,%xmm15 + vpextrb $100,%xmm8,-0x99(,%riz) + vcvtsi2sdl -0x99(,%riz),%xmm8,%xmm15 + vblendvps %xmm8,-0x99(,%riz),%xmm12,%xmm14 + vpinsrb $100,-0x99(,%riz),%xmm8,%xmm15 + vmovdqa -0x99(,%riz),%ymm8 + vmovdqa %ymm8,-0x99(,%riz) + vpermilpd -0x99(,%riz),%ymm8,%ymm15 + vroundpd $100,-0x99(,%riz),%ymm8 + vextractf128 $100,%ymm8,-0x99(,%riz) + vperm2f128 $100,-0x99(,%riz),%ymm8,%ymm15 + vblendvpd %ymm8,-0x99(,%riz),%ymm12,%ymm14 + vldmxcsr -0x99(,%riz,2) + vmovdqa -0x99(,%riz,2),%xmm8 + vmovdqa %xmm8,-0x99(,%riz,2) + vmovd %xmm8,-0x99(,%riz,2) + vcvtsd2si -0x99(,%riz,2),%r8d + vcvtdq2pd -0x99(,%riz,2),%ymm8 + vcvtpd2psy -0x99(,%riz,2),%xmm8 + vpavgb -0x99(,%riz,2),%xmm8,%xmm15 + vpextrb $100,%xmm8,-0x99(,%riz,2) + vcvtsi2sdl -0x99(,%riz,2),%xmm8,%xmm15 + vblendvps %xmm8,-0x99(,%riz,2),%xmm12,%xmm14 + vpinsrb $100,-0x99(,%riz,2),%xmm8,%xmm15 + vmovdqa -0x99(,%riz,2),%ymm8 + vmovdqa %ymm8,-0x99(,%riz,2) + vpermilpd -0x99(,%riz,2),%ymm8,%ymm15 + vroundpd $100,-0x99(,%riz,2),%ymm8 + vextractf128 $100,%ymm8,-0x99(,%riz,2) + vperm2f128 $100,-0x99(,%riz,2),%ymm8,%ymm15 + vblendvpd %ymm8,-0x99(,%riz,2),%ymm12,%ymm14 + vldmxcsr -0x99(%rbx,%riz) + vmovdqa -0x99(%rbx,%riz),%xmm8 + vmovdqa %xmm8,-0x99(%rbx,%riz) + vmovd %xmm8,-0x99(%rbx,%riz) + vcvtsd2si -0x99(%rbx,%riz),%r8d + vcvtdq2pd -0x99(%rbx,%riz),%ymm8 + vcvtpd2psy -0x99(%rbx,%riz),%xmm8 + vpavgb -0x99(%rbx,%riz),%xmm8,%xmm15 + vpextrb $100,%xmm8,-0x99(%rbx,%riz) + vcvtsi2sdl -0x99(%rbx,%riz),%xmm8,%xmm15 + vblendvps %xmm8,-0x99(%rbx,%riz),%xmm12,%xmm14 + vpinsrb $100,-0x99(%rbx,%riz),%xmm8,%xmm15 + vmovdqa -0x99(%rbx,%riz),%ymm8 + vmovdqa %ymm8,-0x99(%rbx,%riz) + vpermilpd -0x99(%rbx,%riz),%ymm8,%ymm15 + vroundpd $100,-0x99(%rbx,%riz),%ymm8 + vextractf128 $100,%ymm8,-0x99(%rbx,%riz) + vperm2f128 $100,-0x99(%rbx,%riz),%ymm8,%ymm15 + vblendvpd %ymm8,-0x99(%rbx,%riz),%ymm12,%ymm14 + vldmxcsr -0x99(%rbx,%riz,2) + vmovdqa -0x99(%rbx,%riz,2),%xmm8 + vmovdqa %xmm8,-0x99(%rbx,%riz,2) + vmovd %xmm8,-0x99(%rbx,%riz,2) + vcvtsd2si -0x99(%rbx,%riz,2),%r8d + vcvtdq2pd -0x99(%rbx,%riz,2),%ymm8 + vcvtpd2psy -0x99(%rbx,%riz,2),%xmm8 + vpavgb -0x99(%rbx,%riz,2),%xmm8,%xmm15 + vpextrb $100,%xmm8,-0x99(%rbx,%riz,2) + vcvtsi2sdl -0x99(%rbx,%riz,2),%xmm8,%xmm15 + vblendvps %xmm8,-0x99(%rbx,%riz,2),%xmm12,%xmm14 + vpinsrb $100,-0x99(%rbx,%riz,2),%xmm8,%xmm15 + vmovdqa -0x99(%rbx,%riz,2),%ymm8 + vmovdqa %ymm8,-0x99(%rbx,%riz,2) + vpermilpd -0x99(%rbx,%riz,2),%ymm8,%ymm15 + vroundpd $100,-0x99(%rbx,%riz,2),%ymm8 + vextractf128 $100,%ymm8,-0x99(%rbx,%riz,2) + vperm2f128 $100,-0x99(%rbx,%riz,2),%ymm8,%ymm15 + vblendvpd %ymm8,-0x99(%rbx,%riz,2),%ymm12,%ymm14 + vldmxcsr -0x99(%r12,%r15,4) + vmovdqa -0x99(%r12,%r15,4),%xmm8 + vmovdqa %xmm8,-0x99(%r12,%r15,4) + vmovd %xmm8,-0x99(%r12,%r15,4) + vcvtsd2si -0x99(%r12,%r15,4),%r8d + vcvtdq2pd -0x99(%r12,%r15,4),%ymm8 + vcvtpd2psy -0x99(%r12,%r15,4),%xmm8 + vpavgb -0x99(%r12,%r15,4),%xmm8,%xmm15 + vpextrb $100,%xmm8,-0x99(%r12,%r15,4) + vcvtsi2sdl -0x99(%r12,%r15,4),%xmm8,%xmm15 + vblendvps %xmm8,-0x99(%r12,%r15,4),%xmm12,%xmm14 + vpinsrb $100,-0x99(%r12,%r15,4),%xmm8,%xmm15 + vmovdqa -0x99(%r12,%r15,4),%ymm8 + vmovdqa %ymm8,-0x99(%r12,%r15,4) + vpermilpd -0x99(%r12,%r15,4),%ymm8,%ymm15 + vroundpd $100,-0x99(%r12,%r15,4),%ymm8 + vextractf128 $100,%ymm8,-0x99(%r12,%r15,4) + vperm2f128 $100,-0x99(%r12,%r15,4),%ymm8,%ymm15 + vblendvpd %ymm8,-0x99(%r12,%r15,4),%ymm12,%ymm14 + vldmxcsr -0x99(%r8,%r15,8) + vmovdqa -0x99(%r8,%r15,8),%xmm8 + vmovdqa %xmm8,-0x99(%r8,%r15,8) + vmovd %xmm8,-0x99(%r8,%r15,8) + vcvtsd2si -0x99(%r8,%r15,8),%r8d + vcvtdq2pd -0x99(%r8,%r15,8),%ymm8 + vcvtpd2psy -0x99(%r8,%r15,8),%xmm8 + vpavgb -0x99(%r8,%r15,8),%xmm8,%xmm15 + vpextrb $100,%xmm8,-0x99(%r8,%r15,8) + vcvtsi2sdl -0x99(%r8,%r15,8),%xmm8,%xmm15 + vblendvps %xmm8,-0x99(%r8,%r15,8),%xmm12,%xmm14 + vpinsrb $100,-0x99(%r8,%r15,8),%xmm8,%xmm15 + vmovdqa -0x99(%r8,%r15,8),%ymm8 + vmovdqa %ymm8,-0x99(%r8,%r15,8) + vpermilpd -0x99(%r8,%r15,8),%ymm8,%ymm15 + vroundpd $100,-0x99(%r8,%r15,8),%ymm8 + vextractf128 $100,%ymm8,-0x99(%r8,%r15,8) + vperm2f128 $100,-0x99(%r8,%r15,8),%ymm8,%ymm15 + vblendvpd %ymm8,-0x99(%r8,%r15,8),%ymm12,%ymm14 + vldmxcsr -0x99(%rbp,%r13,4) + vmovdqa -0x99(%rbp,%r13,4),%xmm8 + vmovdqa %xmm8,-0x99(%rbp,%r13,4) + vmovd %xmm8,-0x99(%rbp,%r13,4) + vcvtsd2si -0x99(%rbp,%r13,4),%r8d + vcvtdq2pd -0x99(%rbp,%r13,4),%ymm8 + vcvtpd2psy -0x99(%rbp,%r13,4),%xmm8 + vpavgb -0x99(%rbp,%r13,4),%xmm8,%xmm15 + vpextrb $100,%xmm8,-0x99(%rbp,%r13,4) + vcvtsi2sdl -0x99(%rbp,%r13,4),%xmm8,%xmm15 + vblendvps %xmm8,-0x99(%rbp,%r13,4),%xmm12,%xmm14 + vpinsrb $100,-0x99(%rbp,%r13,4),%xmm8,%xmm15 + vmovdqa -0x99(%rbp,%r13,4),%ymm8 + vmovdqa %ymm8,-0x99(%rbp,%r13,4) + vpermilpd -0x99(%rbp,%r13,4),%ymm8,%ymm15 + vroundpd $100,-0x99(%rbp,%r13,4),%ymm8 + vextractf128 $100,%ymm8,-0x99(%rbp,%r13,4) + vperm2f128 $100,-0x99(%rbp,%r13,4),%ymm8,%ymm15 + vblendvpd %ymm8,-0x99(%rbp,%r13,4),%ymm12,%ymm14 + vldmxcsr -0x99(%rsp,%r12,1) + vmovdqa -0x99(%rsp,%r12,1),%xmm8 + vmovdqa %xmm8,-0x99(%rsp,%r12,1) + vmovd %xmm8,-0x99(%rsp,%r12,1) + vcvtsd2si -0x99(%rsp,%r12,1),%r8d + vcvtdq2pd -0x99(%rsp,%r12,1),%ymm8 + vcvtpd2psy -0x99(%rsp,%r12,1),%xmm8 + vpavgb -0x99(%rsp,%r12,1),%xmm8,%xmm15 + vpextrb $100,%xmm8,-0x99(%rsp,%r12,1) + vcvtsi2sdl -0x99(%rsp,%r12,1),%xmm8,%xmm15 + vblendvps %xmm8,-0x99(%rsp,%r12,1),%xmm12,%xmm14 + vpinsrb $100,-0x99(%rsp,%r12,1),%xmm8,%xmm15 + vmovdqa -0x99(%rsp,%r12,1),%ymm8 + vmovdqa %ymm8,-0x99(%rsp,%r12,1) + vpermilpd -0x99(%rsp,%r12,1),%ymm8,%ymm15 + vroundpd $100,-0x99(%rsp,%r12,1),%ymm8 + vextractf128 $100,%ymm8,-0x99(%rsp,%r12,1) + vperm2f128 $100,-0x99(%rsp,%r12,1),%ymm8,%ymm15 + vblendvpd %ymm8,-0x99(%rsp,%r12,1),%ymm12,%ymm14 +# Tests for all register operands. + vmovmskpd %xmm8,%r8d + vpslld $100,%xmm8,%xmm15 + vmovmskps %ymm8,%r8d + vmovdqa %xmm8,%xmm15 + vmovd %xmm8,%r8d + vcvtsd2si %xmm8,%r8d + vcvtdq2pd %xmm8,%ymm8 + vcvtpd2psy %ymm8,%xmm8 + vpextrb $100,%xmm8,%r8d + vcvtsi2sdl %r8d,%xmm8,%xmm15 + vblendvps %xmm8,%xmm8,%xmm12,%xmm14 + vpinsrb $100,%r8d,%xmm8,%xmm15 + vmovdqa %ymm8,%ymm15 + vpermilpd %ymm8,%ymm15,%ymm12 + vroundpd $100,%ymm8,%ymm15 + vextractf128 $100,%ymm8,%xmm8 + vperm2f128 $100,%ymm8,%ymm15,%ymm12 + vblendvpd %ymm8,%ymm15,%ymm12,%ymm14 + vinsertf128 $100,%xmm8,%ymm8,%ymm15 +# Tests for different memory/register operand + vcvtsd2si (%rcx),%r8 + vextractps $10,%xmm8,%r8 + vcvtss2si (%rcx),%r8 + vpinsrw $100,%r8,%xmm15,%xmm8 + + .intel_syntax noprefix +# Tests for op mem64 + vldmxcsr DWORD PTR [rcx] + vstmxcsr DWORD PTR [rcx] + +# Tests for op mem256, mask, ymm +# Tests for op ymm, mask, mem256 + vmaskmovpd ymm6,ymm4,YMMWORD PTR [rcx] + vmaskmovpd YMMWORD PTR [rcx],ymm6,ymm4 + vmaskmovps ymm6,ymm4,YMMWORD PTR [rcx] + vmaskmovps YMMWORD PTR [rcx],ymm6,ymm4 + +# Tests for op imm8, ymm/mem256, ymm + vpermilpd ymm2,ymm6,100 + vpermilpd ymm6,YMMWORD PTR [rcx],100 + vpermilps ymm2,ymm6,100 + vpermilps ymm6,YMMWORD PTR [rcx],100 + vroundpd ymm2,ymm6,100 + vroundpd ymm6,YMMWORD PTR [rcx],100 + vroundps ymm2,ymm6,100 + vroundps ymm6,YMMWORD PTR [rcx],100 + +# Tests for op ymm/mem256, ymm, ymm + vaddpd ymm2,ymm6,ymm4 + vaddpd ymm2,ymm6,YMMWORD PTR [rcx] + vaddps ymm2,ymm6,ymm4 + vaddps ymm2,ymm6,YMMWORD PTR [rcx] + vaddsubpd ymm2,ymm6,ymm4 + vaddsubpd ymm2,ymm6,YMMWORD PTR [rcx] + vaddsubps ymm2,ymm6,ymm4 + vaddsubps ymm2,ymm6,YMMWORD PTR [rcx] + vandnpd ymm2,ymm6,ymm4 + vandnpd ymm2,ymm6,YMMWORD PTR [rcx] + vandnps ymm2,ymm6,ymm4 + vandnps ymm2,ymm6,YMMWORD PTR [rcx] + vandpd ymm2,ymm6,ymm4 + vandpd ymm2,ymm6,YMMWORD PTR [rcx] + vandps ymm2,ymm6,ymm4 + vandps ymm2,ymm6,YMMWORD PTR [rcx] + vdivpd ymm2,ymm6,ymm4 + vdivpd ymm2,ymm6,YMMWORD PTR [rcx] + vdivps ymm2,ymm6,ymm4 + vdivps ymm2,ymm6,YMMWORD PTR [rcx] + vhaddpd ymm2,ymm6,ymm4 + vhaddpd ymm2,ymm6,YMMWORD PTR [rcx] + vhaddps ymm2,ymm6,ymm4 + vhaddps ymm2,ymm6,YMMWORD PTR [rcx] + vhsubpd ymm2,ymm6,ymm4 + vhsubpd ymm2,ymm6,YMMWORD PTR [rcx] + vhsubps ymm2,ymm6,ymm4 + vhsubps ymm2,ymm6,YMMWORD PTR [rcx] + vmaxpd ymm2,ymm6,ymm4 + vmaxpd ymm2,ymm6,YMMWORD PTR [rcx] + vmaxps ymm2,ymm6,ymm4 + vmaxps ymm2,ymm6,YMMWORD PTR [rcx] + vminpd ymm2,ymm6,ymm4 + vminpd ymm2,ymm6,YMMWORD PTR [rcx] + vminps ymm2,ymm6,ymm4 + vminps ymm2,ymm6,YMMWORD PTR [rcx] + vmulpd ymm2,ymm6,ymm4 + vmulpd ymm2,ymm6,YMMWORD PTR [rcx] + vmulps ymm2,ymm6,ymm4 + vmulps ymm2,ymm6,YMMWORD PTR [rcx] + vorpd ymm2,ymm6,ymm4 + vorpd ymm2,ymm6,YMMWORD PTR [rcx] + vorps ymm2,ymm6,ymm4 + vorps ymm2,ymm6,YMMWORD PTR [rcx] + vpermilpd ymm2,ymm6,ymm4 + vpermilpd ymm2,ymm6,YMMWORD PTR [rcx] + vpermilps ymm2,ymm6,ymm4 + vpermilps ymm2,ymm6,YMMWORD PTR [rcx] + vsubpd ymm2,ymm6,ymm4 + vsubpd ymm2,ymm6,YMMWORD PTR [rcx] + vsubps ymm2,ymm6,ymm4 + vsubps ymm2,ymm6,YMMWORD PTR [rcx] + vunpckhpd ymm2,ymm6,ymm4 + vunpckhpd ymm2,ymm6,YMMWORD PTR [rcx] + vunpckhps ymm2,ymm6,ymm4 + vunpckhps ymm2,ymm6,YMMWORD PTR [rcx] + vunpcklpd ymm2,ymm6,ymm4 + vunpcklpd ymm2,ymm6,YMMWORD PTR [rcx] + vunpcklps ymm2,ymm6,ymm4 + vunpcklps ymm2,ymm6,YMMWORD PTR [rcx] + vxorpd ymm2,ymm6,ymm4 + vxorpd ymm2,ymm6,YMMWORD PTR [rcx] + vxorps ymm2,ymm6,ymm4 + vxorps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpeqpd ymm2,ymm6,ymm4 + vcmpeqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpltpd ymm2,ymm6,ymm4 + vcmpltpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmplepd ymm2,ymm6,ymm4 + vcmplepd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpunordpd ymm2,ymm6,ymm4 + vcmpunordpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpneqpd ymm2,ymm6,ymm4 + vcmpneqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnltpd ymm2,ymm6,ymm4 + vcmpnltpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnlepd ymm2,ymm6,ymm4 + vcmpnlepd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpordpd ymm2,ymm6,ymm4 + vcmpordpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpeq_uqpd ymm2,ymm6,ymm4 + vcmpeq_uqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpngepd ymm2,ymm6,ymm4 + vcmpngepd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpngtpd ymm2,ymm6,ymm4 + vcmpngtpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpfalsepd ymm2,ymm6,ymm4 + vcmpfalsepd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpneq_oqpd ymm2,ymm6,ymm4 + vcmpneq_oqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpgepd ymm2,ymm6,ymm4 + vcmpgepd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpgtpd ymm2,ymm6,ymm4 + vcmpgtpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmptruepd ymm2,ymm6,ymm4 + vcmptruepd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpeq_ospd ymm2,ymm6,ymm4 + vcmpeq_ospd ymm2,ymm6,YMMWORD PTR [rcx] + vcmplt_oqpd ymm2,ymm6,ymm4 + vcmplt_oqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmple_oqpd ymm2,ymm6,ymm4 + vcmple_oqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpunord_spd ymm2,ymm6,ymm4 + vcmpunord_spd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpneq_uspd ymm2,ymm6,ymm4 + vcmpneq_uspd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnlt_uqpd ymm2,ymm6,ymm4 + vcmpnlt_uqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnle_uqpd ymm2,ymm6,ymm4 + vcmpnle_uqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpord_spd ymm2,ymm6,ymm4 + vcmpord_spd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpeq_uspd ymm2,ymm6,ymm4 + vcmpeq_uspd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnge_uqpd ymm2,ymm6,ymm4 + vcmpnge_uqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpngt_uqpd ymm2,ymm6,ymm4 + vcmpngt_uqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpfalse_ospd ymm2,ymm6,ymm4 + vcmpfalse_ospd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpneq_ospd ymm2,ymm6,ymm4 + vcmpneq_ospd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpge_oqpd ymm2,ymm6,ymm4 + vcmpge_oqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpgt_oqpd ymm2,ymm6,ymm4 + vcmpgt_oqpd ymm2,ymm6,YMMWORD PTR [rcx] + vcmptrue_uspd ymm2,ymm6,ymm4 + vcmptrue_uspd ymm2,ymm6,YMMWORD PTR [rcx] + vcmpeqps ymm2,ymm6,ymm4 + vcmpeqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpltps ymm2,ymm6,ymm4 + vcmpltps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpleps ymm2,ymm6,ymm4 + vcmpleps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpunordps ymm2,ymm6,ymm4 + vcmpunordps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpneqps ymm2,ymm6,ymm4 + vcmpneqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnltps ymm2,ymm6,ymm4 + vcmpnltps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnleps ymm2,ymm6,ymm4 + vcmpnleps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpordps ymm2,ymm6,ymm4 + vcmpordps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpeq_uqps ymm2,ymm6,ymm4 + vcmpeq_uqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpngeps ymm2,ymm6,ymm4 + vcmpngeps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpngtps ymm2,ymm6,ymm4 + vcmpngtps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpfalseps ymm2,ymm6,ymm4 + vcmpfalseps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpneq_oqps ymm2,ymm6,ymm4 + vcmpneq_oqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpgeps ymm2,ymm6,ymm4 + vcmpgeps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpgtps ymm2,ymm6,ymm4 + vcmpgtps ymm2,ymm6,YMMWORD PTR [rcx] + vcmptrueps ymm2,ymm6,ymm4 + vcmptrueps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpeq_osps ymm2,ymm6,ymm4 + vcmpeq_osps ymm2,ymm6,YMMWORD PTR [rcx] + vcmplt_oqps ymm2,ymm6,ymm4 + vcmplt_oqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmple_oqps ymm2,ymm6,ymm4 + vcmple_oqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpunord_sps ymm2,ymm6,ymm4 + vcmpunord_sps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpneq_usps ymm2,ymm6,ymm4 + vcmpneq_usps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnlt_uqps ymm2,ymm6,ymm4 + vcmpnlt_uqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnle_uqps ymm2,ymm6,ymm4 + vcmpnle_uqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpord_sps ymm2,ymm6,ymm4 + vcmpord_sps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpeq_usps ymm2,ymm6,ymm4 + vcmpeq_usps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpnge_uqps ymm2,ymm6,ymm4 + vcmpnge_uqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpngt_uqps ymm2,ymm6,ymm4 + vcmpngt_uqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpfalse_osps ymm2,ymm6,ymm4 + vcmpfalse_osps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpneq_osps ymm2,ymm6,ymm4 + vcmpneq_osps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpge_oqps ymm2,ymm6,ymm4 + vcmpge_oqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmpgt_oqps ymm2,ymm6,ymm4 + vcmpgt_oqps ymm2,ymm6,YMMWORD PTR [rcx] + vcmptrue_usps ymm2,ymm6,ymm4 + vcmptrue_usps ymm2,ymm6,YMMWORD PTR [rcx] + +# Tests for op ymm/mem256, xmm + vcvtpd2dq xmm4,ymm4 + vcvtpd2dq xmm4,YMMWORD PTR [rcx] + vcvtpd2ps xmm4,ymm4 + vcvtpd2ps xmm4,YMMWORD PTR [rcx] + vcvttpd2dq xmm4,ymm4 + vcvttpd2dq xmm4,YMMWORD PTR [rcx] + +# Tests for op ymm/mem256, ymm + vcvtdq2ps ymm4,ymm4 + vcvtdq2ps ymm4,YMMWORD PTR [rcx] + vcvtps2dq ymm4,ymm4 + vcvtps2dq ymm4,YMMWORD PTR [rcx] + vcvttps2dq ymm4,ymm4 + vcvttps2dq ymm4,YMMWORD PTR [rcx] + vmovapd ymm4,ymm4 + vmovapd ymm4,YMMWORD PTR [rcx] + vmovaps ymm4,ymm4 + vmovaps ymm4,YMMWORD PTR [rcx] + vmovdqa ymm4,ymm4 + vmovdqa ymm4,YMMWORD PTR [rcx] + vmovdqu ymm4,ymm4 + vmovdqu ymm4,YMMWORD PTR [rcx] + vmovddup ymm4,ymm4 + vmovddup ymm4,YMMWORD PTR [rcx] + vmovshdup ymm4,ymm4 + vmovshdup ymm4,YMMWORD PTR [rcx] + vmovsldup ymm4,ymm4 + vmovsldup ymm4,YMMWORD PTR [rcx] + vmovupd ymm4,ymm4 + vmovupd ymm4,YMMWORD PTR [rcx] + vmovups ymm4,ymm4 + vmovups ymm4,YMMWORD PTR [rcx] + vptest ymm4,ymm4 + vptest ymm4,YMMWORD PTR [rcx] + vrcpps ymm4,ymm4 + vrcpps ymm4,YMMWORD PTR [rcx] + vrsqrtps ymm4,ymm4 + vrsqrtps ymm4,YMMWORD PTR [rcx] + vsqrtpd ymm4,ymm4 + vsqrtpd ymm4,YMMWORD PTR [rcx] + vsqrtps ymm4,ymm4 + vsqrtps ymm4,YMMWORD PTR [rcx] + vtestpd ymm4,ymm4 + vtestpd ymm4,YMMWORD PTR [rcx] + vtestps ymm4,ymm4 + vtestps ymm4,YMMWORD PTR [rcx] + +# Tests for op mem256, ymm + vlddqu ymm4,YMMWORD PTR [rcx] + +# Tests for op imm8, ymm/mem256, ymm, ymm + vblendpd ymm2,ymm6,ymm4,100 + vblendpd ymm2,ymm6,YMMWORD PTR [rcx],100 + vblendps ymm2,ymm6,ymm4,100 + vblendps ymm2,ymm6,YMMWORD PTR [rcx],100 + vcmppd ymm2,ymm6,ymm4,100 + vcmppd ymm2,ymm6,YMMWORD PTR [rcx],100 + vcmpps ymm2,ymm6,ymm4,100 + vcmpps ymm2,ymm6,YMMWORD PTR [rcx],100 + vdpps ymm2,ymm6,ymm4,100 + vdpps ymm2,ymm6,YMMWORD PTR [rcx],100 + vperm2f128 ymm2,ymm6,ymm4,100 + vperm2f128 ymm2,ymm6,YMMWORD PTR [rcx],100 + vshufpd ymm2,ymm6,ymm4,100 + vshufpd ymm2,ymm6,YMMWORD PTR [rcx],100 + vshufps ymm2,ymm6,ymm4,100 + vshufps ymm2,ymm6,YMMWORD PTR [rcx],100 + +# Tests for op ymm, ymm/mem256, ymm, ymm + vblendvpd ymm7,ymm2,ymm6,ymm4 + vblendvpd ymm7,ymm2,YMMWORD PTR [rcx],ymm4 + vblendvps ymm7,ymm2,ymm6,ymm4 + vblendvps ymm7,ymm2,YMMWORD PTR [rcx],ymm4 + +# Tests for op ymm/mem256, ymm, ymm, ymm +# Tests for op ymm, ymm/mem256, ymm, ymm + vfmaddpd ymm7,ymm2,ymm6,ymm4 + vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfmaddps ymm7,ymm2,ymm6,ymm4 + vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfmaddsubpd ymm7,ymm2,ymm6,ymm4 + vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfmaddsubps ymm7,ymm2,ymm6,ymm4 + vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfmsubaddpd ymm7,ymm2,ymm6,ymm4 + vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfmsubaddps ymm7,ymm2,ymm6,ymm4 + vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfmsubpd ymm7,ymm2,ymm6,ymm4 + vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfmsubps ymm7,ymm2,ymm6,ymm4 + vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfnmaddpd ymm7,ymm2,ymm6,ymm4 + vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfnmaddps ymm7,ymm2,ymm6,ymm4 + vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfnmsubpd ymm7,ymm2,ymm6,ymm4 + vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vfnmsubps ymm7,ymm2,ymm6,ymm4 + vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vpermilmo2pd ymm7,ymm2,ymm6,ymm4 + vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vpermilmz2pd ymm7,ymm2,ymm6,ymm4 + vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vpermiltd2pd ymm7,ymm2,ymm6,ymm4 + vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vpermilmo2ps ymm7,ymm2,ymm6,ymm4 + vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vpermilmz2ps ymm7,ymm2,ymm6,ymm4 + vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + vpermiltd2ps ymm7,ymm2,ymm6,ymm4 + vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR [rcx] + +# Tests for op imm4, ymm/mem256, ymm, ymm, ymm +# Tests for op imm4, ymm, ymm/mem256, ymm, ymm + vpermil2pd ymm7,ymm2,ymm6,ymm4,10 + vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR [rcx],10 + vpermil2ps ymm7,ymm2,ymm6,ymm4,10 + vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR [rcx],10 + +# Tests for op imm8, xmm/mem128, ymm, ymm + vinsertf128 ymm6,ymm4,xmm4,100 + vinsertf128 ymm6,ymm4,XMMWORD PTR [rcx],100 + +# Tests for op imm8, ymm, xmm/mem128 + vextractf128 xmm4,ymm4,100 + vextractf128 XMMWORD PTR [rcx],ymm4,100 + +# Tests for op xmm/mem128, xmm +# Tests for op mem128, ymm + vbroadcastf128 ymm4,XMMWORD PTR [rcx] + +# Tests for op xmm/mem128, xmm + vcvtdq2ps xmm6,xmm4 + vcvtdq2ps xmm4,XMMWORD PTR [rcx] + vcvtpd2dq xmm6,xmm4 + vcvtpd2dq xmm4,XMMWORD PTR [rcx] + vcvtpd2ps xmm6,xmm4 + vcvtpd2ps xmm4,XMMWORD PTR [rcx] + vcvtps2dq xmm6,xmm4 + vcvtps2dq xmm4,XMMWORD PTR [rcx] + vcvttpd2dq xmm6,xmm4 + vcvttpd2dq xmm4,XMMWORD PTR [rcx] + vcvttps2dq xmm6,xmm4 + vcvttps2dq xmm4,XMMWORD PTR [rcx] + vmovapd xmm6,xmm4 + vmovapd xmm4,XMMWORD PTR [rcx] + vmovaps xmm6,xmm4 + vmovaps xmm4,XMMWORD PTR [rcx] + vmovdqa xmm6,xmm4 + vmovdqa xmm4,XMMWORD PTR [rcx] + vmovdqu xmm6,xmm4 + vmovdqu xmm4,XMMWORD PTR [rcx] + vmovshdup xmm6,xmm4 + vmovshdup xmm4,XMMWORD PTR [rcx] + vmovsldup xmm6,xmm4 + vmovsldup xmm4,XMMWORD PTR [rcx] + vmovupd xmm6,xmm4 + vmovupd xmm4,XMMWORD PTR [rcx] + vmovups xmm6,xmm4 + vmovups xmm4,XMMWORD PTR [rcx] + vpabsb xmm6,xmm4 + vpabsb xmm4,XMMWORD PTR [rcx] + vpabsw xmm6,xmm4 + vpabsw xmm4,XMMWORD PTR [rcx] + vpabsd xmm6,xmm4 + vpabsd xmm4,XMMWORD PTR [rcx] + vphminposuw xmm6,xmm4 + vphminposuw xmm4,XMMWORD PTR [rcx] + vptest xmm6,xmm4 + vptest xmm4,XMMWORD PTR [rcx] + vtestps xmm6,xmm4 + vtestps xmm4,XMMWORD PTR [rcx] + vtestpd xmm6,xmm4 + vtestpd xmm4,XMMWORD PTR [rcx] + vrcpps xmm6,xmm4 + vrcpps xmm4,XMMWORD PTR [rcx] + vrsqrtps xmm6,xmm4 + vrsqrtps xmm4,XMMWORD PTR [rcx] + vsqrtpd xmm6,xmm4 + vsqrtpd xmm4,XMMWORD PTR [rcx] + vsqrtps xmm6,xmm4 + vsqrtps xmm4,XMMWORD PTR [rcx] + +# Tests for op xmm, xmm/mem128 + vmovapd xmm6,xmm4 + vmovapd XMMWORD PTR [rcx],xmm4 + vmovaps xmm6,xmm4 + vmovaps XMMWORD PTR [rcx],xmm4 + vmovdqa xmm6,xmm4 + vmovdqa XMMWORD PTR [rcx],xmm4 + vmovdqu xmm6,xmm4 + vmovdqu XMMWORD PTR [rcx],xmm4 + vmovupd xmm6,xmm4 + vmovupd XMMWORD PTR [rcx],xmm4 + vmovups xmm6,xmm4 + vmovups XMMWORD PTR [rcx],xmm4 + +# Tests for op mem128, xmm + vlddqu xmm4,XMMWORD PTR [rcx] + vmovntdqa xmm4,XMMWORD PTR [rcx] + +# Tests for op xmm, mem128 + vmovntdq XMMWORD PTR [rcx],xmm4 + vmovntpd XMMWORD PTR [rcx],xmm4 + vmovntps XMMWORD PTR [rcx],xmm4 + +# Tests for op xmm/mem128, ymm + vcvtdq2pd ymm4,xmm4 + vcvtdq2pd ymm4,XMMWORD PTR [rcx] + vcvtps2pd ymm4,xmm4 + vcvtps2pd ymm4,XMMWORD PTR [rcx] + +# Tests for op xmm/mem128, xmm, xmm + vaddpd xmm2,xmm6,xmm4 + vaddpd xmm7,xmm6,XMMWORD PTR [rcx] + vaddps xmm2,xmm6,xmm4 + vaddps xmm7,xmm6,XMMWORD PTR [rcx] + vaddsubpd xmm2,xmm6,xmm4 + vaddsubpd xmm7,xmm6,XMMWORD PTR [rcx] + vaddsubps xmm2,xmm6,xmm4 + vaddsubps xmm7,xmm6,XMMWORD PTR [rcx] + vandnpd xmm2,xmm6,xmm4 + vandnpd xmm7,xmm6,XMMWORD PTR [rcx] + vandnps xmm2,xmm6,xmm4 + vandnps xmm7,xmm6,XMMWORD PTR [rcx] + vandpd xmm2,xmm6,xmm4 + vandpd xmm7,xmm6,XMMWORD PTR [rcx] + vandps xmm2,xmm6,xmm4 + vandps xmm7,xmm6,XMMWORD PTR [rcx] + vdivpd xmm2,xmm6,xmm4 + vdivpd xmm7,xmm6,XMMWORD PTR [rcx] + vdivps xmm2,xmm6,xmm4 + vdivps xmm7,xmm6,XMMWORD PTR [rcx] + vhaddpd xmm2,xmm6,xmm4 + vhaddpd xmm7,xmm6,XMMWORD PTR [rcx] + vhaddps xmm2,xmm6,xmm4 + vhaddps xmm7,xmm6,XMMWORD PTR [rcx] + vhsubpd xmm2,xmm6,xmm4 + vhsubpd xmm7,xmm6,XMMWORD PTR [rcx] + vhsubps xmm2,xmm6,xmm4 + vhsubps xmm7,xmm6,XMMWORD PTR [rcx] + vmaxpd xmm2,xmm6,xmm4 + vmaxpd xmm7,xmm6,XMMWORD PTR [rcx] + vmaxps xmm2,xmm6,xmm4 + vmaxps xmm7,xmm6,XMMWORD PTR [rcx] + vminpd xmm2,xmm6,xmm4 + vminpd xmm7,xmm6,XMMWORD PTR [rcx] + vminps xmm2,xmm6,xmm4 + vminps xmm7,xmm6,XMMWORD PTR [rcx] + vmulpd xmm2,xmm6,xmm4 + vmulpd xmm7,xmm6,XMMWORD PTR [rcx] + vmulps xmm2,xmm6,xmm4 + vmulps xmm7,xmm6,XMMWORD PTR [rcx] + vorpd xmm2,xmm6,xmm4 + vorpd xmm7,xmm6,XMMWORD PTR [rcx] + vorps xmm2,xmm6,xmm4 + vorps xmm7,xmm6,XMMWORD PTR [rcx] + vpacksswb xmm2,xmm6,xmm4 + vpacksswb xmm7,xmm6,XMMWORD PTR [rcx] + vpackssdw xmm2,xmm6,xmm4 + vpackssdw xmm7,xmm6,XMMWORD PTR [rcx] + vpackuswb xmm2,xmm6,xmm4 + vpackuswb xmm7,xmm6,XMMWORD PTR [rcx] + vpackusdw xmm2,xmm6,xmm4 + vpackusdw xmm7,xmm6,XMMWORD PTR [rcx] + vpaddb xmm2,xmm6,xmm4 + vpaddb xmm7,xmm6,XMMWORD PTR [rcx] + vpaddw xmm2,xmm6,xmm4 + vpaddw xmm7,xmm6,XMMWORD PTR [rcx] + vpaddd xmm2,xmm6,xmm4 + vpaddd xmm7,xmm6,XMMWORD PTR [rcx] + vpaddq xmm2,xmm6,xmm4 + vpaddq xmm7,xmm6,XMMWORD PTR [rcx] + vpaddsb xmm2,xmm6,xmm4 + vpaddsb xmm7,xmm6,XMMWORD PTR [rcx] + vpaddsw xmm2,xmm6,xmm4 + vpaddsw xmm7,xmm6,XMMWORD PTR [rcx] + vpaddusb xmm2,xmm6,xmm4 + vpaddusb xmm7,xmm6,XMMWORD PTR [rcx] + vpaddusw xmm2,xmm6,xmm4 + vpaddusw xmm7,xmm6,XMMWORD PTR [rcx] + vpand xmm2,xmm6,xmm4 + vpand xmm7,xmm6,XMMWORD PTR [rcx] + vpandn xmm2,xmm6,xmm4 + vpandn xmm7,xmm6,XMMWORD PTR [rcx] + vpavgb xmm2,xmm6,xmm4 + vpavgb xmm7,xmm6,XMMWORD PTR [rcx] + vpavgw xmm2,xmm6,xmm4 + vpavgw xmm7,xmm6,XMMWORD PTR [rcx] + vpcmpeqb xmm2,xmm6,xmm4 + vpcmpeqb xmm7,xmm6,XMMWORD PTR [rcx] + vpcmpeqw xmm2,xmm6,xmm4 + vpcmpeqw xmm7,xmm6,XMMWORD PTR [rcx] + vpcmpeqd xmm2,xmm6,xmm4 + vpcmpeqd xmm7,xmm6,XMMWORD PTR [rcx] + vpcmpeqq xmm2,xmm6,xmm4 + vpcmpeqq xmm7,xmm6,XMMWORD PTR [rcx] + vpcmpgtb xmm2,xmm6,xmm4 + vpcmpgtb xmm7,xmm6,XMMWORD PTR [rcx] + vpcmpgtw xmm2,xmm6,xmm4 + vpcmpgtw xmm7,xmm6,XMMWORD PTR [rcx] + vpcmpgtd xmm2,xmm6,xmm4 + vpcmpgtd xmm7,xmm6,XMMWORD PTR [rcx] + vpcmpgtq xmm2,xmm6,xmm4 + vpcmpgtq xmm7,xmm6,XMMWORD PTR [rcx] + vpermilpd xmm2,xmm6,xmm4 + vpermilpd xmm7,xmm6,XMMWORD PTR [rcx] + vpermilps xmm2,xmm6,xmm4 + vpermilps xmm7,xmm6,XMMWORD PTR [rcx] + vphaddw xmm2,xmm6,xmm4 + vphaddw xmm7,xmm6,XMMWORD PTR [rcx] + vphaddd xmm2,xmm6,xmm4 + vphaddd xmm7,xmm6,XMMWORD PTR [rcx] + vphaddsw xmm2,xmm6,xmm4 + vphaddsw xmm7,xmm6,XMMWORD PTR [rcx] + vphsubw xmm2,xmm6,xmm4 + vphsubw xmm7,xmm6,XMMWORD PTR [rcx] + vphsubd xmm2,xmm6,xmm4 + vphsubd xmm7,xmm6,XMMWORD PTR [rcx] + vphsubsw xmm2,xmm6,xmm4 + vphsubsw xmm7,xmm6,XMMWORD PTR [rcx] + vpmaddwd xmm2,xmm6,xmm4 + vpmaddwd xmm7,xmm6,XMMWORD PTR [rcx] + vpmaddubsw xmm2,xmm6,xmm4 + vpmaddubsw xmm7,xmm6,XMMWORD PTR [rcx] + vpmaxsb xmm2,xmm6,xmm4 + vpmaxsb xmm7,xmm6,XMMWORD PTR [rcx] + vpmaxsw xmm2,xmm6,xmm4 + vpmaxsw xmm7,xmm6,XMMWORD PTR [rcx] + vpmaxsd xmm2,xmm6,xmm4 + vpmaxsd xmm7,xmm6,XMMWORD PTR [rcx] + vpmaxub xmm2,xmm6,xmm4 + vpmaxub xmm7,xmm6,XMMWORD PTR [rcx] + vpmaxuw xmm2,xmm6,xmm4 + vpmaxuw xmm7,xmm6,XMMWORD PTR [rcx] + vpmaxud xmm2,xmm6,xmm4 + vpmaxud xmm7,xmm6,XMMWORD PTR [rcx] + vpminsb xmm2,xmm6,xmm4 + vpminsb xmm7,xmm6,XMMWORD PTR [rcx] + vpminsw xmm2,xmm6,xmm4 + vpminsw xmm7,xmm6,XMMWORD PTR [rcx] + vpminsd xmm2,xmm6,xmm4 + vpminsd xmm7,xmm6,XMMWORD PTR [rcx] + vpminub xmm2,xmm6,xmm4 + vpminub xmm7,xmm6,XMMWORD PTR [rcx] + vpminuw xmm2,xmm6,xmm4 + vpminuw xmm7,xmm6,XMMWORD PTR [rcx] + vpminud xmm2,xmm6,xmm4 + vpminud xmm7,xmm6,XMMWORD PTR [rcx] + vpmulhuw xmm2,xmm6,xmm4 + vpmulhuw xmm7,xmm6,XMMWORD PTR [rcx] + vpmulhrsw xmm2,xmm6,xmm4 + vpmulhrsw xmm7,xmm6,XMMWORD PTR [rcx] + vpmulhw xmm2,xmm6,xmm4 + vpmulhw xmm7,xmm6,XMMWORD PTR [rcx] + vpmullw xmm2,xmm6,xmm4 + vpmullw xmm7,xmm6,XMMWORD PTR [rcx] + vpmulld xmm2,xmm6,xmm4 + vpmulld xmm7,xmm6,XMMWORD PTR [rcx] + vpmuludq xmm2,xmm6,xmm4 + vpmuludq xmm7,xmm6,XMMWORD PTR [rcx] + vpmuldq xmm2,xmm6,xmm4 + vpmuldq xmm7,xmm6,XMMWORD PTR [rcx] + vpor xmm2,xmm6,xmm4 + vpor xmm7,xmm6,XMMWORD PTR [rcx] + vpsadbw xmm2,xmm6,xmm4 + vpsadbw xmm7,xmm6,XMMWORD PTR [rcx] + vpshufb xmm2,xmm6,xmm4 + vpshufb xmm7,xmm6,XMMWORD PTR [rcx] + vpsignb xmm2,xmm6,xmm4 + vpsignb xmm7,xmm6,XMMWORD PTR [rcx] + vpsignw xmm2,xmm6,xmm4 + vpsignw xmm7,xmm6,XMMWORD PTR [rcx] + vpsignd xmm2,xmm6,xmm4 + vpsignd xmm7,xmm6,XMMWORD PTR [rcx] + vpsllw xmm2,xmm6,xmm4 + vpsllw xmm7,xmm6,XMMWORD PTR [rcx] + vpslld xmm2,xmm6,xmm4 + vpslld xmm7,xmm6,XMMWORD PTR [rcx] + vpsllq xmm2,xmm6,xmm4 + vpsllq xmm7,xmm6,XMMWORD PTR [rcx] + vpsraw xmm2,xmm6,xmm4 + vpsraw xmm7,xmm6,XMMWORD PTR [rcx] + vpsrad xmm2,xmm6,xmm4 + vpsrad xmm7,xmm6,XMMWORD PTR [rcx] + vpsrlw xmm2,xmm6,xmm4 + vpsrlw xmm7,xmm6,XMMWORD PTR [rcx] + vpsrld xmm2,xmm6,xmm4 + vpsrld xmm7,xmm6,XMMWORD PTR [rcx] + vpsrlq xmm2,xmm6,xmm4 + vpsrlq xmm7,xmm6,XMMWORD PTR [rcx] + vpsubb xmm2,xmm6,xmm4 + vpsubb xmm7,xmm6,XMMWORD PTR [rcx] + vpsubw xmm2,xmm6,xmm4 + vpsubw xmm7,xmm6,XMMWORD PTR [rcx] + vpsubd xmm2,xmm6,xmm4 + vpsubd xmm7,xmm6,XMMWORD PTR [rcx] + vpsubq xmm2,xmm6,xmm4 + vpsubq xmm7,xmm6,XMMWORD PTR [rcx] + vpsubsb xmm2,xmm6,xmm4 + vpsubsb xmm7,xmm6,XMMWORD PTR [rcx] + vpsubsw xmm2,xmm6,xmm4 + vpsubsw xmm7,xmm6,XMMWORD PTR [rcx] + vpsubusb xmm2,xmm6,xmm4 + vpsubusb xmm7,xmm6,XMMWORD PTR [rcx] + vpsubusw xmm2,xmm6,xmm4 + vpsubusw xmm7,xmm6,XMMWORD PTR [rcx] + vpunpckhbw xmm2,xmm6,xmm4 + vpunpckhbw xmm7,xmm6,XMMWORD PTR [rcx] + vpunpckhwd xmm2,xmm6,xmm4 + vpunpckhwd xmm7,xmm6,XMMWORD PTR [rcx] + vpunpckhdq xmm2,xmm6,xmm4 + vpunpckhdq xmm7,xmm6,XMMWORD PTR [rcx] + vpunpckhqdq xmm2,xmm6,xmm4 + vpunpckhqdq xmm7,xmm6,XMMWORD PTR [rcx] + vpunpcklbw xmm2,xmm6,xmm4 + vpunpcklbw xmm7,xmm6,XMMWORD PTR [rcx] + vpunpcklwd xmm2,xmm6,xmm4 + vpunpcklwd xmm7,xmm6,XMMWORD PTR [rcx] + vpunpckldq xmm2,xmm6,xmm4 + vpunpckldq xmm7,xmm6,XMMWORD PTR [rcx] + vpunpcklqdq xmm2,xmm6,xmm4 + vpunpcklqdq xmm7,xmm6,XMMWORD PTR [rcx] + vpxor xmm2,xmm6,xmm4 + vpxor xmm7,xmm6,XMMWORD PTR [rcx] + vsubpd xmm2,xmm6,xmm4 + vsubpd xmm7,xmm6,XMMWORD PTR [rcx] + vsubps xmm2,xmm6,xmm4 + vsubps xmm7,xmm6,XMMWORD PTR [rcx] + vunpckhpd xmm2,xmm6,xmm4 + vunpckhpd xmm7,xmm6,XMMWORD PTR [rcx] + vunpckhps xmm2,xmm6,xmm4 + vunpckhps xmm7,xmm6,XMMWORD PTR [rcx] + vunpcklpd xmm2,xmm6,xmm4 + vunpcklpd xmm7,xmm6,XMMWORD PTR [rcx] + vunpcklps xmm2,xmm6,xmm4 + vunpcklps xmm7,xmm6,XMMWORD PTR [rcx] + vxorpd xmm2,xmm6,xmm4 + vxorpd xmm7,xmm6,XMMWORD PTR [rcx] + vxorps xmm2,xmm6,xmm4 + vxorps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpeqpd xmm2,xmm6,xmm4 + vcmpeqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpltpd xmm2,xmm6,xmm4 + vcmpltpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmplepd xmm2,xmm6,xmm4 + vcmplepd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpunordpd xmm2,xmm6,xmm4 + vcmpunordpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpneqpd xmm2,xmm6,xmm4 + vcmpneqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnltpd xmm2,xmm6,xmm4 + vcmpnltpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnlepd xmm2,xmm6,xmm4 + vcmpnlepd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpordpd xmm2,xmm6,xmm4 + vcmpordpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpeq_uqpd xmm2,xmm6,xmm4 + vcmpeq_uqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpngepd xmm2,xmm6,xmm4 + vcmpngepd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpngtpd xmm2,xmm6,xmm4 + vcmpngtpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpfalsepd xmm2,xmm6,xmm4 + vcmpfalsepd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpneq_oqpd xmm2,xmm6,xmm4 + vcmpneq_oqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpgepd xmm2,xmm6,xmm4 + vcmpgepd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpgtpd xmm2,xmm6,xmm4 + vcmpgtpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmptruepd xmm2,xmm6,xmm4 + vcmptruepd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpeq_ospd xmm2,xmm6,xmm4 + vcmpeq_ospd xmm7,xmm6,XMMWORD PTR [rcx] + vcmplt_oqpd xmm2,xmm6,xmm4 + vcmplt_oqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmple_oqpd xmm2,xmm6,xmm4 + vcmple_oqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpunord_spd xmm2,xmm6,xmm4 + vcmpunord_spd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpneq_uspd xmm2,xmm6,xmm4 + vcmpneq_uspd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnlt_uqpd xmm2,xmm6,xmm4 + vcmpnlt_uqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnle_uqpd xmm2,xmm6,xmm4 + vcmpnle_uqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpord_spd xmm2,xmm6,xmm4 + vcmpord_spd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpeq_uspd xmm2,xmm6,xmm4 + vcmpeq_uspd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnge_uqpd xmm2,xmm6,xmm4 + vcmpnge_uqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpngt_uqpd xmm2,xmm6,xmm4 + vcmpngt_uqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpfalse_ospd xmm2,xmm6,xmm4 + vcmpfalse_ospd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpneq_ospd xmm2,xmm6,xmm4 + vcmpneq_ospd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpge_oqpd xmm2,xmm6,xmm4 + vcmpge_oqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpgt_oqpd xmm2,xmm6,xmm4 + vcmpgt_oqpd xmm7,xmm6,XMMWORD PTR [rcx] + vcmptrue_uspd xmm2,xmm6,xmm4 + vcmptrue_uspd xmm7,xmm6,XMMWORD PTR [rcx] + vcmpeqps xmm2,xmm6,xmm4 + vcmpeqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpltps xmm2,xmm6,xmm4 + vcmpltps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpleps xmm2,xmm6,xmm4 + vcmpleps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpunordps xmm2,xmm6,xmm4 + vcmpunordps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpneqps xmm2,xmm6,xmm4 + vcmpneqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnltps xmm2,xmm6,xmm4 + vcmpnltps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnleps xmm2,xmm6,xmm4 + vcmpnleps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpordps xmm2,xmm6,xmm4 + vcmpordps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpeq_uqps xmm2,xmm6,xmm4 + vcmpeq_uqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpngeps xmm2,xmm6,xmm4 + vcmpngeps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpngtps xmm2,xmm6,xmm4 + vcmpngtps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpfalseps xmm2,xmm6,xmm4 + vcmpfalseps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpneq_oqps xmm2,xmm6,xmm4 + vcmpneq_oqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpgeps xmm2,xmm6,xmm4 + vcmpgeps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpgtps xmm2,xmm6,xmm4 + vcmpgtps xmm7,xmm6,XMMWORD PTR [rcx] + vcmptrueps xmm2,xmm6,xmm4 + vcmptrueps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpeq_osps xmm2,xmm6,xmm4 + vcmpeq_osps xmm7,xmm6,XMMWORD PTR [rcx] + vcmplt_oqps xmm2,xmm6,xmm4 + vcmplt_oqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmple_oqps xmm2,xmm6,xmm4 + vcmple_oqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpunord_sps xmm2,xmm6,xmm4 + vcmpunord_sps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpneq_usps xmm2,xmm6,xmm4 + vcmpneq_usps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnlt_uqps xmm2,xmm6,xmm4 + vcmpnlt_uqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnle_uqps xmm2,xmm6,xmm4 + vcmpnle_uqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpord_sps xmm2,xmm6,xmm4 + vcmpord_sps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpeq_usps xmm2,xmm6,xmm4 + vcmpeq_usps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpnge_uqps xmm2,xmm6,xmm4 + vcmpnge_uqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpngt_uqps xmm2,xmm6,xmm4 + vcmpngt_uqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpfalse_osps xmm2,xmm6,xmm4 + vcmpfalse_osps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpneq_osps xmm2,xmm6,xmm4 + vcmpneq_osps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpge_oqps xmm2,xmm6,xmm4 + vcmpge_oqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmpgt_oqps xmm2,xmm6,xmm4 + vcmpgt_oqps xmm7,xmm6,XMMWORD PTR [rcx] + vcmptrue_usps xmm2,xmm6,xmm4 + vcmptrue_usps xmm7,xmm6,XMMWORD PTR [rcx] + +# Tests for op mem128, xmm, xmm + vmaskmovps xmm6,xmm4,XMMWORD PTR [rcx] + vmaskmovpd xmm6,xmm4,XMMWORD PTR [rcx] + +# Tests for op imm8, xmm/mem128, xmm + vpcmpestri xmm6,xmm4,100 + vpcmpestri xmm6,XMMWORD PTR [rcx],100 + vpcmpestrm xmm6,xmm4,100 + vpcmpestrm xmm6,XMMWORD PTR [rcx],100 + vpcmpistri xmm6,xmm4,100 + vpcmpistri xmm6,XMMWORD PTR [rcx],100 + vpcmpistrm xmm6,xmm4,100 + vpcmpistrm xmm6,XMMWORD PTR [rcx],100 + vpermilpd xmm6,xmm4,100 + vpermilpd xmm6,XMMWORD PTR [rcx],100 + vpermilps xmm6,xmm4,100 + vpermilps xmm6,XMMWORD PTR [rcx],100 + vpshufd xmm6,xmm4,100 + vpshufd xmm6,XMMWORD PTR [rcx],100 + vpshufhw xmm6,xmm4,100 + vpshufhw xmm6,XMMWORD PTR [rcx],100 + vpshuflw xmm6,xmm4,100 + vpshuflw xmm6,XMMWORD PTR [rcx],100 + vroundpd xmm6,xmm4,100 + vroundpd xmm6,XMMWORD PTR [rcx],100 + vroundps xmm6,xmm4,100 + vroundps xmm6,XMMWORD PTR [rcx],100 + +# Tests for op xmm, xmm, mem128 + vmaskmovps XMMWORD PTR [rcx],xmm6,xmm4 + vmaskmovpd XMMWORD PTR [rcx],xmm6,xmm4 + +# Tests for op imm8, xmm/mem128, xmm, xmm + vblendpd xmm2,xmm6,xmm4,100 + vblendpd xmm2,xmm6,XMMWORD PTR [rcx],100 + vblendps xmm2,xmm6,xmm4,100 + vblendps xmm2,xmm6,XMMWORD PTR [rcx],100 + vcmppd xmm2,xmm6,xmm4,100 + vcmppd xmm2,xmm6,XMMWORD PTR [rcx],100 + vcmpps xmm2,xmm6,xmm4,100 + vcmpps xmm2,xmm6,XMMWORD PTR [rcx],100 + vdppd xmm2,xmm6,xmm4,100 + vdppd xmm2,xmm6,XMMWORD PTR [rcx],100 + vdpps xmm2,xmm6,xmm4,100 + vdpps xmm2,xmm6,XMMWORD PTR [rcx],100 + vmpsadbw xmm2,xmm6,xmm4,100 + vmpsadbw xmm2,xmm6,XMMWORD PTR [rcx],100 + vpalignr xmm2,xmm6,xmm4,100 + vpalignr xmm2,xmm6,XMMWORD PTR [rcx],100 + vpblendw xmm2,xmm6,xmm4,100 + vpblendw xmm2,xmm6,XMMWORD PTR [rcx],100 + vshufpd xmm2,xmm6,xmm4,100 + vshufpd xmm2,xmm6,XMMWORD PTR [rcx],100 + vshufps xmm2,xmm6,xmm4,100 + vshufps xmm2,xmm6,XMMWORD PTR [rcx],100 + +# Tests for op xmm, xmm/mem128, xmm, xmm + vblendvpd xmm7,xmm2,xmm6,xmm4 + vblendvpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vblendvps xmm7,xmm2,xmm6,xmm4 + vblendvps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vpblendvb xmm7,xmm2,xmm6,xmm4 + vpblendvb xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + +# Tests for op xmm/mem128, xmm, xmm, xmm +# Tests for op xmm, xmm/mem128, xmm, xmm + vfmaddpd xmm7,xmm2,xmm6,xmm4 + vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfmaddpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfmaddps xmm7,xmm2,xmm6,xmm4 + vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfmaddps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfmaddsubpd xmm7,xmm2,xmm6,xmm4 + vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfmaddsubpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfmaddsubps xmm7,xmm2,xmm6,xmm4 + vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfmaddsubps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfmsubaddpd xmm7,xmm2,xmm6,xmm4 + vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfmsubaddpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfmsubaddps xmm7,xmm2,xmm6,xmm4 + vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfmsubaddps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfmsubpd xmm7,xmm2,xmm6,xmm4 + vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfmsubpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfmsubps xmm7,xmm2,xmm6,xmm4 + vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfmsubps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfnmaddpd xmm7,xmm2,xmm6,xmm4 + vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfnmaddpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfnmaddps xmm7,xmm2,xmm6,xmm4 + vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfnmaddps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfnmsubpd xmm7,xmm2,xmm6,xmm4 + vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfnmsubpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vfnmsubps xmm7,xmm2,xmm6,xmm4 + vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vfnmsubps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vpermilmo2pd xmm7,xmm2,xmm6,xmm4 + vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vpermilmo2pd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vpermilmz2pd xmm7,xmm2,xmm6,xmm4 + vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vpermilmz2pd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vpermiltd2pd xmm7,xmm2,xmm6,xmm4 + vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vpermiltd2pd xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vpermilmo2ps xmm7,xmm2,xmm6,xmm4 + vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vpermilmo2ps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vpermilmz2ps xmm7,xmm2,xmm6,xmm4 + vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vpermilmz2ps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + vpermiltd2ps xmm7,xmm2,xmm6,xmm4 + vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR [rcx] + vpermiltd2ps xmm7,xmm2,XMMWORD PTR [rcx],xmm4 + +# Tests for op imm4, xmm/mem128, xmm, xmm, xmm +# Tests for op imm4, xmm, xmm/mem128, xmm, xmm + vpermil2pd xmm7,xmm2,xmm6,xmm4,10 + vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR [rcx],10 + vpermil2pd xmm7,xmm2,XMMWORD PTR [rcx],xmm4,10 + vpermil2ps xmm7,xmm2,xmm6,xmm4,10 + vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR [rcx],10 + vpermil2ps xmm7,xmm2,XMMWORD PTR [rcx],xmm4,10 + +# Tests for op mem64, ymm + vbroadcastsd ymm4,QWORD PTR [rcx] + +# Tests for op xmm/mem64, xmm + vcomisd xmm6,xmm4 + vcomisd xmm4,QWORD PTR [rcx] + vcvtdq2pd xmm6,xmm4 + vcvtdq2pd xmm4,QWORD PTR [rcx] + vcvtps2pd xmm6,xmm4 + vcvtps2pd xmm4,QWORD PTR [rcx] + vmovddup xmm6,xmm4 + vmovddup xmm4,QWORD PTR [rcx] + vpmovsxbw xmm6,xmm4 + vpmovsxbw xmm4,QWORD PTR [rcx] + vpmovsxwd xmm6,xmm4 + vpmovsxwd xmm4,QWORD PTR [rcx] + vpmovsxdq xmm6,xmm4 + vpmovsxdq xmm4,QWORD PTR [rcx] + vpmovzxbw xmm6,xmm4 + vpmovzxbw xmm4,QWORD PTR [rcx] + vpmovzxwd xmm6,xmm4 + vpmovzxwd xmm4,QWORD PTR [rcx] + vpmovzxdq xmm6,xmm4 + vpmovzxdq xmm4,QWORD PTR [rcx] + vucomisd xmm6,xmm4 + vucomisd xmm4,QWORD PTR [rcx] + +# Tests for op mem64, xmm + vmovsd xmm4,QWORD PTR [rcx] + +# Tests for op xmm, mem64 + vmovlpd QWORD PTR [rcx],xmm4 + vmovlps QWORD PTR [rcx],xmm4 + vmovhpd QWORD PTR [rcx],xmm4 + vmovhps QWORD PTR [rcx],xmm4 + vmovsd QWORD PTR [rcx],xmm4 + +# Tests for op xmm, regq/mem64 +# Tests for op regq/mem64, xmm + vmovq rcx,xmm4 + vmovq xmm4,rcx + vmovq QWORD PTR [rcx],xmm4 + vmovq xmm4,QWORD PTR [rcx] + +# Tests for op xmm/mem64, regl + vcvtsd2si ecx,xmm4 + vcvtsd2si ecx,QWORD PTR [rcx] + vcvttsd2si ecx,xmm4 + vcvttsd2si ecx,QWORD PTR [rcx] + +# Tests for op xmm/mem64, regq + vcvtsd2si rcx,xmm4 + vcvtsd2si rcx,QWORD PTR [rcx] + vcvttsd2si rcx,xmm4 + vcvttsd2si rcx,QWORD PTR [rcx] + +# Tests for op regq/mem64, xmm, xmm + vcvtsi2sdq xmm6,xmm4,rcx + vcvtsi2sdq xmm6,xmm4,QWORD PTR [rcx] + vcvtsi2ssq xmm6,xmm4,rcx + vcvtsi2ssq xmm6,xmm4,QWORD PTR [rcx] + +# Tests for op imm8, regq/mem64, xmm, xmm + vpinsrq xmm6,xmm4,rcx,100 + vpinsrq xmm6,xmm4,QWORD PTR [rcx],100 + +# Testsf for op imm8, xmm, regq/mem64 + vpextrq rcx,xmm4,100 + vpextrq QWORD PTR [rcx],xmm4,100 + +# Tests for op mem64, xmm, xmm + vmovlpd xmm6,xmm4,QWORD PTR [rcx] + vmovlps xmm6,xmm4,QWORD PTR [rcx] + vmovhpd xmm6,xmm4,QWORD PTR [rcx] + vmovhps xmm6,xmm4,QWORD PTR [rcx] + +# Tests for op imm8, xmm/mem64, xmm, xmm + vcmpsd xmm2,xmm6,xmm4,100 + vcmpsd xmm2,xmm6,QWORD PTR [rcx],100 + vroundsd xmm2,xmm6,xmm4,100 + vroundsd xmm2,xmm6,QWORD PTR [rcx],100 + +# Tests for op xmm/mem64, xmm, xmm, xmm +# Tests for op xmm, xmm/mem64, xmm, xmm + vfmaddsd xmm7,xmm2,xmm6,xmm4 + vfmaddsd xmm7,xmm2,xmm6,QWORD PTR [rcx] + vfmaddsd xmm7,xmm2,QWORD PTR [rcx],xmm4 + vfmsubsd xmm7,xmm2,xmm6,xmm4 + vfmsubsd xmm7,xmm2,xmm6,QWORD PTR [rcx] + vfmsubsd xmm7,xmm2,QWORD PTR [rcx],xmm4 + vfnmaddsd xmm7,xmm2,xmm6,xmm4 + vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR [rcx] + vfnmaddsd xmm7,xmm2,QWORD PTR [rcx],xmm4 + vfnmsubsd xmm7,xmm2,xmm6,xmm4 + vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR [rcx] + vfnmsubsd xmm7,xmm2,QWORD PTR [rcx],xmm4 + +# Tests for op xmm/mem64, xmm, xmm + vaddsd xmm2,xmm6,xmm4 + vaddsd xmm2,xmm6,QWORD PTR [rcx] + vcvtsd2ss xmm2,xmm6,xmm4 + vcvtsd2ss xmm2,xmm6,QWORD PTR [rcx] + vdivsd xmm2,xmm6,xmm4 + vdivsd xmm2,xmm6,QWORD PTR [rcx] + vmaxsd xmm2,xmm6,xmm4 + vmaxsd xmm2,xmm6,QWORD PTR [rcx] + vminsd xmm2,xmm6,xmm4 + vminsd xmm2,xmm6,QWORD PTR [rcx] + vmulsd xmm2,xmm6,xmm4 + vmulsd xmm2,xmm6,QWORD PTR [rcx] + vsqrtsd xmm2,xmm6,xmm4 + vsqrtsd xmm2,xmm6,QWORD PTR [rcx] + vsubsd xmm2,xmm6,xmm4 + vsubsd xmm2,xmm6,QWORD PTR [rcx] + vcmpeqsd xmm2,xmm6,xmm4 + vcmpeqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpltsd xmm2,xmm6,xmm4 + vcmpltsd xmm2,xmm6,QWORD PTR [rcx] + vcmplesd xmm2,xmm6,xmm4 + vcmplesd xmm2,xmm6,QWORD PTR [rcx] + vcmpunordsd xmm2,xmm6,xmm4 + vcmpunordsd xmm2,xmm6,QWORD PTR [rcx] + vcmpneqsd xmm2,xmm6,xmm4 + vcmpneqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpnltsd xmm2,xmm6,xmm4 + vcmpnltsd xmm2,xmm6,QWORD PTR [rcx] + vcmpnlesd xmm2,xmm6,xmm4 + vcmpnlesd xmm2,xmm6,QWORD PTR [rcx] + vcmpordsd xmm2,xmm6,xmm4 + vcmpordsd xmm2,xmm6,QWORD PTR [rcx] + vcmpeq_uqsd xmm2,xmm6,xmm4 + vcmpeq_uqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpngesd xmm2,xmm6,xmm4 + vcmpngesd xmm2,xmm6,QWORD PTR [rcx] + vcmpngtsd xmm2,xmm6,xmm4 + vcmpngtsd xmm2,xmm6,QWORD PTR [rcx] + vcmpfalsesd xmm2,xmm6,xmm4 + vcmpfalsesd xmm2,xmm6,QWORD PTR [rcx] + vcmpneq_oqsd xmm2,xmm6,xmm4 + vcmpneq_oqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpgesd xmm2,xmm6,xmm4 + vcmpgesd xmm2,xmm6,QWORD PTR [rcx] + vcmpgtsd xmm2,xmm6,xmm4 + vcmpgtsd xmm2,xmm6,QWORD PTR [rcx] + vcmptruesd xmm2,xmm6,xmm4 + vcmptruesd xmm2,xmm6,QWORD PTR [rcx] + vcmpeq_ossd xmm2,xmm6,xmm4 + vcmpeq_ossd xmm2,xmm6,QWORD PTR [rcx] + vcmplt_oqsd xmm2,xmm6,xmm4 + vcmplt_oqsd xmm2,xmm6,QWORD PTR [rcx] + vcmple_oqsd xmm2,xmm6,xmm4 + vcmple_oqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpunord_ssd xmm2,xmm6,xmm4 + vcmpunord_ssd xmm2,xmm6,QWORD PTR [rcx] + vcmpneq_ussd xmm2,xmm6,xmm4 + vcmpneq_ussd xmm2,xmm6,QWORD PTR [rcx] + vcmpnlt_uqsd xmm2,xmm6,xmm4 + vcmpnlt_uqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpnle_uqsd xmm2,xmm6,xmm4 + vcmpnle_uqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpord_ssd xmm2,xmm6,xmm4 + vcmpord_ssd xmm2,xmm6,QWORD PTR [rcx] + vcmpeq_ussd xmm2,xmm6,xmm4 + vcmpeq_ussd xmm2,xmm6,QWORD PTR [rcx] + vcmpnge_uqsd xmm2,xmm6,xmm4 + vcmpnge_uqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpngt_uqsd xmm2,xmm6,xmm4 + vcmpngt_uqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpfalse_ossd xmm2,xmm6,xmm4 + vcmpfalse_ossd xmm2,xmm6,QWORD PTR [rcx] + vcmpneq_ossd xmm2,xmm6,xmm4 + vcmpneq_ossd xmm2,xmm6,QWORD PTR [rcx] + vcmpge_oqsd xmm2,xmm6,xmm4 + vcmpge_oqsd xmm2,xmm6,QWORD PTR [rcx] + vcmpgt_oqsd xmm2,xmm6,xmm4 + vcmpgt_oqsd xmm2,xmm6,QWORD PTR [rcx] + vcmptrue_ussd xmm2,xmm6,xmm4 + vcmptrue_ussd xmm2,xmm6,QWORD PTR [rcx] + +# Tests for op xmm/mem32, xmm, xmm + vaddss xmm2,xmm6,xmm4 + vaddss xmm2,xmm6,DWORD PTR [rcx] + vcvtss2sd xmm2,xmm6,xmm4 + vcvtss2sd xmm2,xmm6,DWORD PTR [rcx] + vdivss xmm2,xmm6,xmm4 + vdivss xmm2,xmm6,DWORD PTR [rcx] + vmaxss xmm2,xmm6,xmm4 + vmaxss xmm2,xmm6,DWORD PTR [rcx] + vminss xmm2,xmm6,xmm4 + vminss xmm2,xmm6,DWORD PTR [rcx] + vmulss xmm2,xmm6,xmm4 + vmulss xmm2,xmm6,DWORD PTR [rcx] + vrcpss xmm2,xmm6,xmm4 + vrcpss xmm2,xmm6,DWORD PTR [rcx] + vrsqrtss xmm2,xmm6,xmm4 + vrsqrtss xmm2,xmm6,DWORD PTR [rcx] + vsqrtss xmm2,xmm6,xmm4 + vsqrtss xmm2,xmm6,DWORD PTR [rcx] + vsubss xmm2,xmm6,xmm4 + vsubss xmm2,xmm6,DWORD PTR [rcx] + vcmpeqss xmm2,xmm6,xmm4 + vcmpeqss xmm2,xmm6,DWORD PTR [rcx] + vcmpltss xmm2,xmm6,xmm4 + vcmpltss xmm2,xmm6,DWORD PTR [rcx] + vcmpless xmm2,xmm6,xmm4 + vcmpless xmm2,xmm6,DWORD PTR [rcx] + vcmpunordss xmm2,xmm6,xmm4 + vcmpunordss xmm2,xmm6,DWORD PTR [rcx] + vcmpneqss xmm2,xmm6,xmm4 + vcmpneqss xmm2,xmm6,DWORD PTR [rcx] + vcmpnltss xmm2,xmm6,xmm4 + vcmpnltss xmm2,xmm6,DWORD PTR [rcx] + vcmpnless xmm2,xmm6,xmm4 + vcmpnless xmm2,xmm6,DWORD PTR [rcx] + vcmpordss xmm2,xmm6,xmm4 + vcmpordss xmm2,xmm6,DWORD PTR [rcx] + vcmpeq_uqss xmm2,xmm6,xmm4 + vcmpeq_uqss xmm2,xmm6,DWORD PTR [rcx] + vcmpngess xmm2,xmm6,xmm4 + vcmpngess xmm2,xmm6,DWORD PTR [rcx] + vcmpngtss xmm2,xmm6,xmm4 + vcmpngtss xmm2,xmm6,DWORD PTR [rcx] + vcmpfalsess xmm2,xmm6,xmm4 + vcmpfalsess xmm2,xmm6,DWORD PTR [rcx] + vcmpneq_oqss xmm2,xmm6,xmm4 + vcmpneq_oqss xmm2,xmm6,DWORD PTR [rcx] + vcmpgess xmm2,xmm6,xmm4 + vcmpgess xmm2,xmm6,DWORD PTR [rcx] + vcmpgtss xmm2,xmm6,xmm4 + vcmpgtss xmm2,xmm6,DWORD PTR [rcx] + vcmptruess xmm2,xmm6,xmm4 + vcmptruess xmm2,xmm6,DWORD PTR [rcx] + vcmpeq_osss xmm2,xmm6,xmm4 + vcmpeq_osss xmm2,xmm6,DWORD PTR [rcx] + vcmplt_oqss xmm2,xmm6,xmm4 + vcmplt_oqss xmm2,xmm6,DWORD PTR [rcx] + vcmple_oqss xmm2,xmm6,xmm4 + vcmple_oqss xmm2,xmm6,DWORD PTR [rcx] + vcmpunord_sss xmm2,xmm6,xmm4 + vcmpunord_sss xmm2,xmm6,DWORD PTR [rcx] + vcmpneq_usss xmm2,xmm6,xmm4 + vcmpneq_usss xmm2,xmm6,DWORD PTR [rcx] + vcmpnlt_uqss xmm2,xmm6,xmm4 + vcmpnlt_uqss xmm2,xmm6,DWORD PTR [rcx] + vcmpnle_uqss xmm2,xmm6,xmm4 + vcmpnle_uqss xmm2,xmm6,DWORD PTR [rcx] + vcmpord_sss xmm2,xmm6,xmm4 + vcmpord_sss xmm2,xmm6,DWORD PTR [rcx] + vcmpeq_usss xmm2,xmm6,xmm4 + vcmpeq_usss xmm2,xmm6,DWORD PTR [rcx] + vcmpnge_uqss xmm2,xmm6,xmm4 + vcmpnge_uqss xmm2,xmm6,DWORD PTR [rcx] + vcmpngt_uqss xmm2,xmm6,xmm4 + vcmpngt_uqss xmm2,xmm6,DWORD PTR [rcx] + vcmpfalse_osss xmm2,xmm6,xmm4 + vcmpfalse_osss xmm2,xmm6,DWORD PTR [rcx] + vcmpneq_osss xmm2,xmm6,xmm4 + vcmpneq_osss xmm2,xmm6,DWORD PTR [rcx] + vcmpge_oqss xmm2,xmm6,xmm4 + vcmpge_oqss xmm2,xmm6,DWORD PTR [rcx] + vcmpgt_oqss xmm2,xmm6,xmm4 + vcmpgt_oqss xmm2,xmm6,DWORD PTR [rcx] + vcmptrue_usss xmm2,xmm6,xmm4 + vcmptrue_usss xmm2,xmm6,DWORD PTR [rcx] + +# Tests for op mem32, ymm + vbroadcastss ymm4,DWORD PTR [rcx] + +# Tests for op xmm/mem32, xmm + vcomiss xmm6,xmm4 + vcomiss xmm4,DWORD PTR [rcx] + vpmovsxbd xmm6,xmm4 + vpmovsxbd xmm4,DWORD PTR [rcx] + vpmovsxwq xmm6,xmm4 + vpmovsxwq xmm4,DWORD PTR [rcx] + vpmovzxbd xmm6,xmm4 + vpmovzxbd xmm4,DWORD PTR [rcx] + vpmovzxwq xmm6,xmm4 + vpmovzxwq xmm4,DWORD PTR [rcx] + vucomiss xmm6,xmm4 + vucomiss xmm4,DWORD PTR [rcx] + +# Tests for op mem32, xmm + vbroadcastss xmm4,DWORD PTR [rcx] + vmovss xmm4,DWORD PTR [rcx] + +# Tests for op xmm, mem32 + vmovss DWORD PTR [rcx],xmm4 + +# Tests for op xmm, regl/mem32 +# Tests for op regl/mem32, xmm + vmovd ecx,xmm4 + vmovd DWORD PTR [rcx],xmm4 + vmovd xmm4,ecx + vmovd xmm4,DWORD PTR [rcx] + +# Tests for op xmm/mem32, regl + vcvtss2si ecx,xmm4 + vcvtss2si ecx,DWORD PTR [rcx] + vcvttss2si ecx,xmm4 + vcvttss2si ecx,DWORD PTR [rcx] + +# Tests for op xmm/mem32, regq + vcvtss2si rcx,xmm4 + vcvtss2si rcx,DWORD PTR [rcx] + vcvttss2si rcx,xmm4 + vcvttss2si rcx,DWORD PTR [rcx] + +# Tests for op xmm, regq + vmovmskpd rcx,xmm4 + vmovmskps rcx,xmm4 + vpmovmskb rcx,xmm4 + +# Tests for op imm8, xmm, regq/mem32 + vextractps rcx,xmm4,100 + vextractps DWORD PTR [rcx],xmm4,100 +# Tests for op imm8, xmm, regl/mem32 + vpextrd ecx,xmm4,100 + vpextrd DWORD PTR [rcx],xmm4,100 + vextractps ecx,xmm4,100 + vextractps DWORD PTR [rcx],xmm4,100 + +# Tests for op regl/mem32, xmm, xmm + vcvtsi2sd xmm6,xmm4,ecx + vcvtsi2sd xmm6,xmm4,DWORD PTR [rcx] + vcvtsi2ss xmm6,xmm4,ecx + vcvtsi2ss xmm6,xmm4,DWORD PTR [rcx] + +# Tests for op imm8, xmm/mem32, xmm, xmm + vcmpss xmm2,xmm6,xmm4,100 + vcmpss xmm2,xmm6,DWORD PTR [rcx],100 + vinsertps xmm2,xmm6,xmm4,100 + vinsertps xmm2,xmm6,DWORD PTR [rcx],100 + vroundss xmm2,xmm6,xmm4,100 + vroundss xmm2,xmm6,DWORD PTR [rcx],100 + +# Tests for op xmm/mem32, xmm, xmm, xmm +# Tests for op xmm, xmm/mem32, xmm, xmm + vfmaddss xmm7,xmm2,xmm6,xmm4 + vfmaddss xmm7,xmm2,xmm6,DWORD PTR [rcx] + vfmaddss xmm7,xmm2,DWORD PTR [rcx],xmm4 + vfmsubss xmm7,xmm2,xmm6,xmm4 + vfmsubss xmm7,xmm2,xmm6,DWORD PTR [rcx] + vfmsubss xmm7,xmm2,DWORD PTR [rcx],xmm4 + vfnmaddss xmm7,xmm2,xmm6,xmm4 + vfnmaddss xmm7,xmm2,xmm6,DWORD PTR [rcx] + vfnmaddss xmm7,xmm2,DWORD PTR [rcx],xmm4 + vfnmsubss xmm7,xmm2,xmm6,xmm4 + vfnmsubss xmm7,xmm2,xmm6,DWORD PTR [rcx] + vfnmsubss xmm7,xmm2,DWORD PTR [rcx],xmm4 + +# Tests for op xmm/m16, xmm + vpmovsxbq xmm6,xmm4 + vpmovsxbq xmm4,WORD PTR [rcx] + vpmovzxbq xmm6,xmm4 + vpmovzxbq xmm4,WORD PTR [rcx] + +# Tests for op imm8, xmm, regl/mem16 + vpextrw ecx,xmm4,100 + vpextrw WORD PTR [rcx],xmm4,100 + +# Tests for op imm8, xmm, regq/mem16 + vpextrw rcx,xmm4,100 + vpextrw WORD PTR [rcx],xmm4,100 + +# Tests for op imm8, regl/mem16, xmm, xmm + vpinsrw xmm6,xmm4,ecx,100 + vpinsrw xmm6,xmm4,WORD PTR [rcx],100 + + + vpinsrw xmm6,xmm4,rcx,100 + vpinsrw xmm6,xmm4,WORD PTR [rcx],100 + +# Tests for op imm8, xmm, regl/mem8 + vpextrb ecx,xmm4,100 + vpextrb BYTE PTR [rcx],xmm4,100 + +# Tests for op imm8, regl/mem8, xmm, xmm + vpinsrb xmm6,xmm4,ecx,100 + vpinsrb xmm6,xmm4,BYTE PTR [rcx],100 + +# Tests for op imm8, xmm, regq + vpextrw rcx,xmm4,100 +# Tests for op imm8, xmm, regq/mem8 + vpextrb rcx,xmm4,100 + vpextrb BYTE PTR [rcx],xmm4,100 + +# Tests for op imm8, regl/mem8, xmm, xmm + vpinsrb xmm6,xmm4,ecx,100 + vpinsrb xmm6,xmm4,BYTE PTR [rcx],100 + +# Tests for op xmm, xmm + vmaskmovdqu xmm6,xmm4 + vmovq xmm6,xmm4 + +# Tests for op xmm, regl + vmovmskpd ecx,xmm4 + vmovmskps ecx,xmm4 + vpmovmskb ecx,xmm4 +# Tests for op xmm, xmm, xmm + vmovhlps xmm2,xmm6,xmm4 + vmovlhps xmm2,xmm6,xmm4 + vmovsd xmm2,xmm6,xmm4 + vmovss xmm2,xmm6,xmm4 + +# Tests for op imm8, xmm, xmm + vpslld xmm6,xmm4,100 + vpslldq xmm6,xmm4,100 + vpsllq xmm6,xmm4,100 + vpsllw xmm6,xmm4,100 + vpsrad xmm6,xmm4,100 + vpsraw xmm6,xmm4,100 + vpsrld xmm6,xmm4,100 + vpsrldq xmm6,xmm4,100 + vpsrlq xmm6,xmm4,100 + vpsrlw xmm6,xmm4,100 + +# Tests for op imm8, xmm, regl + vpextrw ecx,xmm4,100 + +# Tests for op ymm, regl + vmovmskpd ecx,ymm4 + vmovmskps ecx,ymm4 + +# Tests for op ymm, regq + vmovmskpd rcx,ymm4 + vmovmskps rcx,ymm4 + + +# Default instructions without suffixes. + vcvtpd2dq xmm6,xmm4 + vcvtpd2dq xmm6,ymm4 + vcvtpd2ps xmm6,xmm4 + vcvtpd2ps xmm6,ymm4 + vcvttpd2dq xmm6,xmm4 + vcvttpd2dq xmm6,ymm4 + +#Tests with different memory and register operands. + vldmxcsr DWORD PTR ds:0x12345678 + vmovdqa xmm8,XMMWORD PTR ds:0x12345678 + vmovdqa XMMWORD PTR ds:0x12345678,xmm8 + vmovd DWORD PTR ds:0x12345678,xmm8 + vcvtsd2si r8d,QWORD PTR ds:0x12345678 + vcvtdq2pd ymm8,XMMWORD PTR ds:0x12345678 + vcvtpd2ps xmm8,YMMWORD PTR ds:0x12345678 + vpavgb xmm15,xmm8,XMMWORD PTR ds:0x12345678 + vpextrb ds:0x12345678,xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678 + vblendvps xmm14,xmm12,XMMWORD PTR ds:0x12345678,xmm8 + vpinsrb xmm15,xmm8,ds:0x12345678,100 + vmovdqa ymm8,YMMWORD PTR ds:0x12345678 + vmovdqa YMMWORD PTR ds:0x12345678,ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR ds:0x12345678 + vroundpd ymm8,YMMWORD PTR ds:0x12345678,100 + vextractf128 XMMWORD PTR ds:0x12345678,ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,100 + vblendvpd ymm14,ymm12,YMMWORD PTR ds:0x12345678,ymm8 + vldmxcsr DWORD PTR [rbp] + vmovdqa xmm8,XMMWORD PTR [rbp] + vmovdqa XMMWORD PTR [rbp],xmm8 + vmovd DWORD PTR [rbp],xmm8 + vcvtsd2si r8d,QWORD PTR [rbp] + vcvtdq2pd ymm8,XMMWORD PTR [rbp] + vcvtpd2ps xmm8,YMMWORD PTR [rbp] + vpavgb xmm15,xmm8,XMMWORD PTR [rbp] + vpextrb [rbp],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp] + vblendvps xmm14,xmm12,XMMWORD PTR [rbp],xmm8 + vpinsrb xmm15,xmm8,[rbp],100 + vmovdqa ymm8,YMMWORD PTR [rbp] + vmovdqa YMMWORD PTR [rbp],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [rbp] + vroundpd ymm8,YMMWORD PTR [rbp],100 + vextractf128 XMMWORD PTR [rbp],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [rbp],ymm8 + vldmxcsr DWORD PTR [rbp+0x99] + vmovdqa xmm8,XMMWORD PTR [rbp+0x99] + vmovdqa XMMWORD PTR [rbp+0x99],xmm8 + vmovd DWORD PTR [rbp+0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [rbp+0x99] + vcvtdq2pd ymm8,XMMWORD PTR [rbp+0x99] + vcvtpd2ps xmm8,YMMWORD PTR [rbp+0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [rbp+0x99] + vpextrb [rbp+0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp+0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [rbp+0x99],xmm8 + vpinsrb xmm15,xmm8,[rbp+0x99],100 + vmovdqa ymm8,YMMWORD PTR [rbp+0x99] + vmovdqa YMMWORD PTR [rbp+0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [rbp+0x99] + vroundpd ymm8,YMMWORD PTR [rbp+0x99],100 + vextractf128 XMMWORD PTR [rbp+0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp+0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [rbp+0x99],ymm8 + vldmxcsr DWORD PTR [r15+0x99] + vmovdqa xmm8,XMMWORD PTR [r15+0x99] + vmovdqa XMMWORD PTR [r15+0x99],xmm8 + vmovd DWORD PTR [r15+0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [r15+0x99] + vcvtdq2pd ymm8,XMMWORD PTR [r15+0x99] + vcvtpd2ps xmm8,YMMWORD PTR [r15+0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [r15+0x99] + vpextrb [r15+0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [r15+0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [r15+0x99],xmm8 + vpinsrb xmm15,xmm8,[r15+0x99],100 + vmovdqa ymm8,YMMWORD PTR [r15+0x99] + vmovdqa YMMWORD PTR [r15+0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [r15+0x99] + vroundpd ymm8,YMMWORD PTR [r15+0x99],100 + vextractf128 XMMWORD PTR [r15+0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [r15+0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [r15+0x99],ymm8 + vldmxcsr DWORD PTR [rip+0x99] + vmovdqa xmm8,XMMWORD PTR [rip+0x99] + vmovdqa XMMWORD PTR [rip+0x99],xmm8 + vmovd DWORD PTR [rip+0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [rip+0x99] + vcvtdq2pd ymm8,XMMWORD PTR [rip+0x99] + vcvtpd2ps xmm8,YMMWORD PTR [rip+0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [rip+0x99] + vpextrb [rip+0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [rip+0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [rip+0x99],xmm8 + vpinsrb xmm15,xmm8,[rip+0x99],100 + vmovdqa ymm8,YMMWORD PTR [rip+0x99] + vmovdqa YMMWORD PTR [rip+0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [rip+0x99] + vroundpd ymm8,YMMWORD PTR [rip+0x99],100 + vextractf128 XMMWORD PTR [rip+0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [rip+0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [rip+0x99],ymm8 + vldmxcsr DWORD PTR [rsp+0x99] + vmovdqa xmm8,XMMWORD PTR [rsp+0x99] + vmovdqa XMMWORD PTR [rsp+0x99],xmm8 + vmovd DWORD PTR [rsp+0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [rsp+0x99] + vcvtdq2pd ymm8,XMMWORD PTR [rsp+0x99] + vcvtpd2ps xmm8,YMMWORD PTR [rsp+0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [rsp+0x99] + vpextrb [rsp+0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [rsp+0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [rsp+0x99],xmm8 + vpinsrb xmm15,xmm8,[rsp+0x99],100 + vmovdqa ymm8,YMMWORD PTR [rsp+0x99] + vmovdqa YMMWORD PTR [rsp+0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [rsp+0x99] + vroundpd ymm8,YMMWORD PTR [rsp+0x99],100 + vextractf128 XMMWORD PTR [rsp+0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [rsp+0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [rsp+0x99],ymm8 + vldmxcsr DWORD PTR [r12+0x99] + vmovdqa xmm8,XMMWORD PTR [r12+0x99] + vmovdqa XMMWORD PTR [r12+0x99],xmm8 + vmovd DWORD PTR [r12+0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [r12+0x99] + vcvtdq2pd ymm8,XMMWORD PTR [r12+0x99] + vcvtpd2ps xmm8,YMMWORD PTR [r12+0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [r12+0x99] + vpextrb [r12+0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [r12+0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [r12+0x99],xmm8 + vpinsrb xmm15,xmm8,[r12+0x99],100 + vmovdqa ymm8,YMMWORD PTR [r12+0x99] + vmovdqa YMMWORD PTR [r12+0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [r12+0x99] + vroundpd ymm8,YMMWORD PTR [r12+0x99],100 + vextractf128 XMMWORD PTR [r12+0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [r12+0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [r12+0x99],ymm8 + vldmxcsr DWORD PTR [riz*1-0x99] + vmovdqa xmm8,XMMWORD PTR [riz*1-0x99] + vmovdqa XMMWORD PTR [riz*1-0x99],xmm8 + vmovd DWORD PTR [riz*1-0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [riz*1-0x99] + vcvtdq2pd ymm8,XMMWORD PTR [riz*1-0x99] + vcvtpd2ps xmm8,YMMWORD PTR [riz*1-0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [riz*1-0x99] + vpextrb [riz*1-0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [riz*1-0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [riz*1-0x99],xmm8 + vpinsrb xmm15,xmm8,[riz*1-0x99],100 + vmovdqa ymm8,YMMWORD PTR [riz*1-0x99] + vmovdqa YMMWORD PTR [riz*1-0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [riz*1-0x99] + vroundpd ymm8,YMMWORD PTR [riz*1-0x99],100 + vextractf128 XMMWORD PTR [riz*1-0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [riz*1-0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [riz*1-0x99],ymm8 + vldmxcsr DWORD PTR [riz*2-0x99] + vmovdqa xmm8,XMMWORD PTR [riz*2-0x99] + vmovdqa XMMWORD PTR [riz*2-0x99],xmm8 + vmovd DWORD PTR [riz*2-0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [riz*2-0x99] + vcvtdq2pd ymm8,XMMWORD PTR [riz*2-0x99] + vcvtpd2ps xmm8,YMMWORD PTR [riz*2-0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [riz*2-0x99] + vpextrb [riz*2-0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [riz*2-0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [riz*2-0x99],xmm8 + vpinsrb xmm15,xmm8,[riz*2-0x99],100 + vmovdqa ymm8,YMMWORD PTR [riz*2-0x99] + vmovdqa YMMWORD PTR [riz*2-0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [riz*2-0x99] + vroundpd ymm8,YMMWORD PTR [riz*2-0x99],100 + vextractf128 XMMWORD PTR [riz*2-0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [riz*2-0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [riz*2-0x99],ymm8 + vldmxcsr DWORD PTR [rbx+riz*1-0x99] + vmovdqa xmm8,XMMWORD PTR [rbx+riz*1-0x99] + vmovdqa XMMWORD PTR [rbx+riz*1-0x99],xmm8 + vmovd DWORD PTR [rbx+riz*1-0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [rbx+riz*1-0x99] + vcvtdq2pd ymm8,XMMWORD PTR [rbx+riz*1-0x99] + vcvtpd2ps xmm8,YMMWORD PTR [rbx+riz*1-0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [rbx+riz*1-0x99] + vpextrb [rbx+riz*1-0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [rbx+riz*1-0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [rbx+riz*1-0x99],xmm8 + vpinsrb xmm15,xmm8,[rbx+riz*1-0x99],100 + vmovdqa ymm8,YMMWORD PTR [rbx+riz*1-0x99] + vmovdqa YMMWORD PTR [rbx+riz*1-0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [rbx+riz*1-0x99] + vroundpd ymm8,YMMWORD PTR [rbx+riz*1-0x99],100 + vextractf128 XMMWORD PTR [rbx+riz*1-0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [rbx+riz*1-0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [rbx+riz*1-0x99],ymm8 + vldmxcsr DWORD PTR [rbx+riz*2-0x99] + vmovdqa xmm8,XMMWORD PTR [rbx+riz*2-0x99] + vmovdqa XMMWORD PTR [rbx+riz*2-0x99],xmm8 + vmovd DWORD PTR [rbx+riz*2-0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [rbx+riz*2-0x99] + vcvtdq2pd ymm8,XMMWORD PTR [rbx+riz*2-0x99] + vcvtpd2ps xmm8,YMMWORD PTR [rbx+riz*2-0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [rbx+riz*2-0x99] + vpextrb [rbx+riz*2-0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [rbx+riz*2-0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [rbx+riz*2-0x99],xmm8 + vpinsrb xmm15,xmm8,[rbx+riz*2-0x99],100 + vmovdqa ymm8,YMMWORD PTR [rbx+riz*2-0x99] + vmovdqa YMMWORD PTR [rbx+riz*2-0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [rbx+riz*2-0x99] + vroundpd ymm8,YMMWORD PTR [rbx+riz*2-0x99],100 + vextractf128 XMMWORD PTR [rbx+riz*2-0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [rbx+riz*2-0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [rbx+riz*2-0x99],ymm8 + vldmxcsr DWORD PTR [r12+r15*4-0x99] + vmovdqa xmm8,XMMWORD PTR [r12+r15*4-0x99] + vmovdqa XMMWORD PTR [r12+r15*4-0x99],xmm8 + vmovd DWORD PTR [r12+r15*4-0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [r12+r15*4-0x99] + vcvtdq2pd ymm8,XMMWORD PTR [r12+r15*4-0x99] + vcvtpd2ps xmm8,YMMWORD PTR [r12+r15*4-0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [r12+r15*4-0x99] + vpextrb [r12+r15*4-0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [r12+r15*4-0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [r12+r15*4-0x99],xmm8 + vpinsrb xmm15,xmm8,[r12+r15*4-0x99],100 + vmovdqa ymm8,YMMWORD PTR [r12+r15*4-0x99] + vmovdqa YMMWORD PTR [r12+r15*4-0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [r12+r15*4-0x99] + vroundpd ymm8,YMMWORD PTR [r12+r15*4-0x99],100 + vextractf128 XMMWORD PTR [r12+r15*4-0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [r12+r15*4-0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [r12+r15*4-0x99],ymm8 + vldmxcsr DWORD PTR [r8+r15*8-0x99] + vmovdqa xmm8,XMMWORD PTR [r8+r15*8-0x99] + vmovdqa XMMWORD PTR [r8+r15*8-0x99],xmm8 + vmovd DWORD PTR [r8+r15*8-0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [r8+r15*8-0x99] + vcvtdq2pd ymm8,XMMWORD PTR [r8+r15*8-0x99] + vcvtpd2ps xmm8,YMMWORD PTR [r8+r15*8-0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [r8+r15*8-0x99] + vpextrb [r8+r15*8-0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [r8+r15*8-0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [r8+r15*8-0x99],xmm8 + vpinsrb xmm15,xmm8,[r8+r15*8-0x99],100 + vmovdqa ymm8,YMMWORD PTR [r8+r15*8-0x99] + vmovdqa YMMWORD PTR [r8+r15*8-0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [r8+r15*8-0x99] + vroundpd ymm8,YMMWORD PTR [r8+r15*8-0x99],100 + vextractf128 XMMWORD PTR [r8+r15*8-0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [r8+r15*8-0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [r8+r15*8-0x99],ymm8 + vldmxcsr DWORD PTR [rbp+r12*4-0x99] + vmovdqa xmm8,XMMWORD PTR [rbp+r12*4-0x99] + vmovdqa XMMWORD PTR [rbp+r12*4-0x99],xmm8 + vmovd DWORD PTR [rbp+r12*4-0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [rbp+r12*4-0x99] + vcvtdq2pd ymm8,XMMWORD PTR [rbp+r12*4-0x99] + vcvtpd2ps xmm8,YMMWORD PTR [rbp+r12*4-0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [rbp+r12*4-0x99] + vpextrb [rbp+r12*4-0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp+r12*4-0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [rbp+r12*4-0x99],xmm8 + vpinsrb xmm15,xmm8,[rbp+r12*4-0x99],100 + vmovdqa ymm8,YMMWORD PTR [rbp+r12*4-0x99] + vmovdqa YMMWORD PTR [rbp+r12*4-0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [rbp+r12*4-0x99] + vroundpd ymm8,YMMWORD PTR [rbp+r12*4-0x99],100 + vextractf128 XMMWORD PTR [rbp+r12*4-0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp+r12*4-0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [rbp+r12*4-0x99],ymm8 + vldmxcsr DWORD PTR [rsp+r13*1-0x99] + vmovdqa xmm8,XMMWORD PTR [rsp+r13*1-0x99] + vmovdqa XMMWORD PTR [rsp+r13*1-0x99],xmm8 + vmovd DWORD PTR [rsp+r13*1-0x99],xmm8 + vcvtsd2si r8d,QWORD PTR [rsp+r13*1-0x99] + vcvtdq2pd ymm8,XMMWORD PTR [rsp+r13*1-0x99] + vcvtpd2ps xmm8,YMMWORD PTR [rsp+r13*1-0x99] + vpavgb xmm15,xmm8,XMMWORD PTR [rsp+r13*1-0x99] + vpextrb [rsp+r13*1-0x99],xmm8,100 + vcvtsi2sd xmm15,xmm8,DWORD PTR [rsp+r13*1-0x99] + vblendvps xmm14,xmm12,XMMWORD PTR [rsp+r13*1-0x99],xmm8 + vpinsrb xmm15,xmm8,[rsp+r13*1-0x99],100 + vmovdqa ymm8,YMMWORD PTR [rsp+r13*1-0x99] + vmovdqa YMMWORD PTR [rsp+r13*1-0x99],ymm8 + vpermilpd ymm15,ymm8,YMMWORD PTR [rsp+r13*1-0x99] + vroundpd ymm8,YMMWORD PTR [rsp+r13*1-0x99],100 + vextractf128 XMMWORD PTR [rsp+r13*1-0x99],ymm8,100 + vperm2f128 ymm15,ymm8,YMMWORD PTR [rsp+r13*1-0x99],100 + vblendvpd ymm14,ymm12,YMMWORD PTR [rsp+r13*1-0x99],ymm8 +# Tests for all register operands. + vmovmskpd r8d,xmm8 + vpslld xmm15,xmm8,100 + vmovmskps r8d,ymm8 + vmovdqa xmm15,xmm8 + vmovd r8d,xmm8 + vcvtsd2si r8d,xmm8 + vcvtdq2pd ymm8,xmm8 + vcvtpd2ps xmm8,ymm8 + vpextrb r8d,xmm8,100 + vcvtsi2sd xmm15,xmm8,r8d + vblendvps xmm14,xmm12,xmm8,xmm8 + vpinsrb xmm15,xmm8,r8d,100 + vmovdqa ymm15,ymm8 + vpermilpd ymm12,ymm15,ymm8 + vroundpd ymm15,ymm8,100 + vextractf128 xmm8,ymm8,100 + vperm2f128 ymm12,ymm15,ymm8,100 + vblendvpd ymm14,ymm12,ymm15,ymm8 + vinsertf128 ymm15,ymm8,xmm8,100 +# Tests for different memory/register operand + vcvtsd2si r8,QWORD PTR [rcx] + vextractps r8,xmm8,10 + vcvtss2si r8,DWORD PTR [rcx] + vpinsrw xmm8,xmm15,r8,100 diff --git a/gas/testsuite/gas/i386/x86-64-clmul-intel.d b/gas/testsuite/gas/i386/x86-64-clmul-intel.d new file mode 100644 index 0000000..79a720c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clmul-intel.d @@ -0,0 +1,31 @@ +#source: x86-64-clmul.s +#as: -J +#objdump: -dw -Mintel +#name: x86-64 CLMUL (Intel mode) + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq xmm0,XMMWORD PTR \[rcx\],0x8 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq xmm0,xmm1,0x8 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq xmm0,XMMWORD PTR \[rcx\],0x8 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq xmm0,xmm1,0x8 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq xmm0,xmm1 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq xmm0,XMMWORD PTR \[rcx\] +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq xmm0,xmm1 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-clmul.d b/gas/testsuite/gas/i386/x86-64-clmul.d new file mode 100644 index 0000000..5efd606 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clmul.d @@ -0,0 +1,30 @@ +#as: -J +#objdump: -dw +#name: x86-64 CLMUL + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq \$0x8,\(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq \$0x8,\(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq %xmm1,%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq %xmm1,%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-clmul.s b/gas/testsuite/gas/i386/x86-64-clmul.s new file mode 100644 index 0000000..a62107c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clmul.s @@ -0,0 +1,26 @@ +# Check 64bit CLMUL new instructions. + + .text +foo: + pclmulqdq $8,(%rcx),%xmm0 + pclmulqdq $8,%xmm1,%xmm0 + pclmullqlqdq (%rcx),%xmm0 + pclmullqlqdq %xmm1,%xmm0 + pclmulhqlqdq (%rcx),%xmm0 + pclmulhqlqdq %xmm1,%xmm0 + pclmullqhqdq (%rcx),%xmm0 + pclmullqhqdq %xmm1,%xmm0 + pclmulhqhqdq (%rcx),%xmm0 + pclmulhqhqdq %xmm1,%xmm0 + + .intel_syntax noprefix + pclmulqdq xmm0,XMMWORD PTR [rcx],8 + pclmulqdq xmm0,xmm1,8 + pclmullqlqdq xmm0,XMMWORD PTR [rcx] + pclmullqlqdq xmm0,xmm1 + pclmulhqlqdq xmm0,XMMWORD PTR [rcx] + pclmulhqlqdq xmm0,xmm1 + pclmullqhqdq xmm0,XMMWORD PTR [rcx] + pclmullqhqdq xmm0,xmm1 + pclmulhqhqdq xmm0,XMMWORD PTR [rcx] + pclmulhqhqdq xmm0,xmm1 diff --git a/gas/testsuite/gas/i386/x86-64-inval-avx.l b/gas/testsuite/gas/i386/x86-64-inval-avx.l new file mode 100644 index 0000000..58820ba --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-inval-avx.l @@ -0,0 +1,109 @@ +.*: Assembler messages: +.*:4: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* +.*:10: Error: .* +.*:11: Error: .* +.*:12: Error: .* +.*:13: Error: .* +.*:14: Error: .* +.*:15: Error: .* +.*:16: Error: .* +.*:17: Error: .* +.*:18: Error: .* +.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* +.*:22: Error: .* +.*:23: Error: .* +.*:24: Error: .* +.*:25: Error: .* +.*:26: Error: .* +.*:27: Error: .* +.*:28: Error: .* +.*:31: Error: .* +.*:32: Error: .* +.*:33: Error: .* +.*:34: Error: .* +.*:35: Error: .* +.*:36: Error: .* +.*:37: Error: .* +.*:38: Error: .* +.*:39: Error: .* +.*:40: Error: .* +.*:41: Error: .* +.*:42: Error: .* +.*:43: Error: .* +.*:44: Error: .* +.*:45: Error: .* +.*:46: Error: .* +.*:47: Error: .* +.*:48: Error: .* +.*:49: Error: .* +.*:50: Error: .* +.*:51: Error: .* +.*:52: Error: .* +.*:53: Error: .* +.*:54: Error: .* +.*:55: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\# Check illegal 64bit AVX instructions +[ ]*2[ ]+\.text +[ ]*3[ ]+_start: +[ ]*4[ ]+vcvtpd2dq \(%rcx\),%xmm2 +[ ]*5[ ]+vcvtpd2ps \(%rcx\),%xmm2 +[ ]*6[ ]+vcvttpd2dq \(%rcx\),%xmm2 +[ ]*7[ ]+vfmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*8[ ]+vfmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*9[ ]+vfmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*10[ ]+vfmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*11[ ]+vfmaddsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*12[ ]+vfmaddsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*13[ ]+vfmsubaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*14[ ]+vfmsubaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*15[ ]+vfmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*16[ ]+vfmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*17[ ]+vfmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*18[ ]+vfmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*19[ ]+vfnmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*20[ ]+vfnmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*21[ ]+vfnmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*22[ ]+vfnmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*23[ ]+vfnmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*24[ ]+vfnmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*25[ ]+vfnmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*26[ ]+vfnmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*27[ ]+vpermil2pd \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*28[ ]+vpermil2ps \$17,%xmm4,%xmm2,%xmm1,%xmm3 +[ ]*29[ ]+ +[ ]*30[ ]+\.intel_syntax noprefix +[ ]*31[ ]+vcvtpd2dq xmm2,\[rcx\] +[ ]*32[ ]+vcvtpd2ps xmm2,\[rcx\] +[ ]*33[ ]+vcvttpd2dq xmm2,\[rcx\] +[ ]*34[ ]+vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*35[ ]+vfmaddps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*36[ ]+vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*37[ ]+vfmaddss xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*38[ ]+vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*39[ ]+vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*40[ ]+vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*41[ ]+vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*42[ ]+vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*43[ ]+vfmsubps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*44[ ]+vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*45[ ]+vfmsubss xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*46[ ]+vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*47[ ]+vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*48[ ]+vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*49[ ]+vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*50[ ]+vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*51[ ]+vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*52[ ]+vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*53[ ]+vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*54[ ]+vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10 +[ ]*55[ ]+vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10 diff --git a/gas/testsuite/gas/i386/x86-64-inval-avx.s b/gas/testsuite/gas/i386/x86-64-inval-avx.s new file mode 100644 index 0000000..3836ce4 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-inval-avx.s @@ -0,0 +1,55 @@ +# Check illegal 64bit AVX instructions + .text +_start: + vcvtpd2dq (%rcx),%xmm2 + vcvtpd2ps (%rcx),%xmm2 + vcvttpd2dq (%rcx),%xmm2 + vfmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmaddsubps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubaddps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vfnmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3 + vpermil2pd $17,%xmm4,%xmm2,%xmm1,%xmm3 + vpermil2ps $17,%xmm4,%xmm2,%xmm1,%xmm3 + + .intel_syntax noprefix + vcvtpd2dq xmm2,[rcx] + vcvtpd2ps xmm2,[rcx] + vcvttpd2dq xmm2,[rcx] + vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddps xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddss xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10 + vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubps xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10 + vfmsubss xmm3,xmm1,xmm2,xmm4,0x10 + vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10 + vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10 + vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10 + vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10 + vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10 + vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10 + vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10 + vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10 + vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10 + vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10 diff --git a/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d b/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d index cb0fdbf..7cf0c27 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d +++ b/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d @@ -42,17 +42,9 @@ Disassembly of section .text: 0+e <into>: [ ]*[a-f0-9]+: ce \(bad\) -0+f <lds>: -[ ]*[a-f0-9]+: c5 \(bad\) -[ ]*[a-f0-9]+: 10 c4 adc ah,al - -0+11 <les>: -[ ]*[a-f0-9]+: c4 \(bad\) -[ ]*[a-f0-9]+: 10 60 61 adc BYTE PTR \[rax\+0x61\],ah - -0+13 <pusha>: +0+f <pusha>: [ ]*[a-f0-9]+: 60 \(bad\) -0+14 <popa>: +0+10 <popa>: [ ]*[a-f0-9]+: 61 \(bad\) #pass diff --git a/gas/testsuite/gas/i386/x86-64-opcode-inval.d b/gas/testsuite/gas/i386/x86-64-opcode-inval.d index fab3192..ccb19ac 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode-inval.d +++ b/gas/testsuite/gas/i386/x86-64-opcode-inval.d @@ -41,17 +41,9 @@ Disassembly of section .text: 0+e <into>: [ ]*[a-f0-9]+: ce \(bad\) -0+f <lds>: -[ ]*[a-f0-9]+: c5 \(bad\) -[ ]*[a-f0-9]+: 10 c4 adc %al,%ah - -0+11 <les>: -[ ]*[a-f0-9]+: c4 \(bad\) -[ ]*[a-f0-9]+: 10 60 61 adc %ah,0x61\(%rax\) - -0+13 <pusha>: +0+f <pusha>: [ ]*[a-f0-9]+: 60 \(bad\) -0+14 <popa>: +0+10 <popa>: [ ]*[a-f0-9]+: 61 \(bad\) #pass diff --git a/gas/testsuite/gas/i386/x86-64-opcode-inval.s b/gas/testsuite/gas/i386/x86-64-opcode-inval.s index 6eb4879..6cbfe77 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode-inval.s +++ b/gas/testsuite/gas/i386/x86-64-opcode-inval.s @@ -20,10 +20,6 @@ das: das into: into -lds: - lds (%eax),%edx -les: - les (%eax),%edx pusha: pusha popa: diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx.d b/gas/testsuite/gas/i386/x86-64-sse2avx.d new file mode 100644 index 0000000..fef5b52 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sse2avx.d @@ -0,0 +1,593 @@ +#as: -msse2avx +#objdump: -dw +#name: x86-64 SSE with AVX encoding + +.*: file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\) +[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%rcx\) +[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dqx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2psx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dqx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 10 21 vmovups \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 11 21 vmovups %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 c9 58 f4 vaddpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 58 31 vaddpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 58 f4 vaddps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 58 31 vaddps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d0 f4 vaddsubpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d0 31 vaddsubpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb d0 f4 vaddsubps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb d0 31 vaddsubps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 55 f4 vandnpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 55 31 vandnpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 55 f4 vandnps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 55 31 vandnps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 54 f4 vandpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 54 31 vandpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 54 f4 vandps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 54 31 vandps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5e f4 vdivpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5e 31 vdivpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5e f4 vdivps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5e 31 vdivps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 7c f4 vhaddpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 7c 31 vhaddpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 7c f4 vhaddps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 7c 31 vhaddps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 7d f4 vhsubpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 7d 31 vhsubpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 7d f4 vhsubps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 7d 31 vhsubps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5f f4 vmaxpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5f 31 vmaxpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5f f4 vmaxps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5f 31 vmaxps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5d f4 vminpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5d 31 vminpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5d f4 vminps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5d 31 vminps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 59 f4 vmulpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 59 31 vmulpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 59 f4 vmulps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 59 31 vmulps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 56 f4 vorpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 56 31 vorpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 56 f4 vorps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 56 31 vorps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 63 f4 vpacksswb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 63 31 vpacksswb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6b f4 vpackssdw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6b 31 vpackssdw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 67 f4 vpackuswb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 67 31 vpackuswb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 2b f4 vpackusdw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 2b 31 vpackusdw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fc f4 vpaddb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fc 31 vpaddb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fd f4 vpaddw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fd 31 vpaddw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fe f4 vpaddd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fe 31 vpaddd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d4 f4 vpaddq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d4 31 vpaddq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ec f4 vpaddsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ec 31 vpaddsb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ed f4 vpaddsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ed 31 vpaddsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 dc f4 vpaddusb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 dc 31 vpaddusb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 dd f4 vpaddusw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 dd 31 vpaddusw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 db f4 vpand %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 db 31 vpand \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 df f4 vpandn %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 df 31 vpandn \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e0 f4 vpavgb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e0 31 vpavgb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e3 f4 vpavgw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e3 31 vpavgw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 74 f4 vpcmpeqb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 74 31 vpcmpeqb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 75 f4 vpcmpeqw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 75 31 vpcmpeqw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 76 f4 vpcmpeqd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 76 31 vpcmpeqd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 29 f4 vpcmpeqq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 29 31 vpcmpeqq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 64 f4 vpcmpgtb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 64 31 vpcmpgtb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 65 f4 vpcmpgtw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 65 31 vpcmpgtw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 66 f4 vpcmpgtd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 66 31 vpcmpgtd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 37 f4 vpcmpgtq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 37 31 vpcmpgtq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 01 f4 vphaddw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 01 31 vphaddw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 02 f4 vphaddd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 02 31 vphaddd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 03 f4 vphaddsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 03 31 vphaddsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 05 f4 vphsubw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 05 31 vphsubw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 06 f4 vphsubd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 06 31 vphsubd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 07 f4 vphsubsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 07 31 vphsubsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f5 f4 vpmaddwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f5 31 vpmaddwd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 04 f4 vpmaddubsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 04 31 vpmaddubsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3c f4 vpmaxsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3c 31 vpmaxsb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ee f4 vpmaxsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ee 31 vpmaxsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3d f4 vpmaxsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3d 31 vpmaxsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 de f4 vpmaxub %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 de 31 vpmaxub \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3e f4 vpmaxuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3e 31 vpmaxuw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3f f4 vpmaxud %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3f 31 vpmaxud \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 38 f4 vpminsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 38 31 vpminsb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ea f4 vpminsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ea 31 vpminsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 39 f4 vpminsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 39 31 vpminsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 da f4 vpminub %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 da 31 vpminub \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3a f4 vpminuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3a 31 vpminuw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3b f4 vpminud %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 3b 31 vpminud \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e4 f4 vpmulhuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e4 31 vpmulhuw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 0b f4 vpmulhrsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 0b 31 vpmulhrsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e5 f4 vpmulhw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e5 31 vpmulhw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d5 f4 vpmullw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d5 31 vpmullw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 40 f4 vpmulld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 40 31 vpmulld \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f4 f4 vpmuludq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f4 31 vpmuludq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 28 f4 vpmuldq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 28 31 vpmuldq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 eb f4 vpor %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 eb 31 vpor \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f6 f4 vpsadbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f6 31 vpsadbw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 00 f4 vpshufb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 00 31 vpshufb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 08 f4 vpsignb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 08 31 vpsignb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 09 f4 vpsignw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 09 31 vpsignw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 0a f4 vpsignd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 49 0a 31 vpsignd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f1 f4 vpsllw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f1 31 vpsllw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f2 f4 vpslld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f2 31 vpslld \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f3 f4 vpsllq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f3 31 vpsllq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e1 f4 vpsraw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e1 31 vpsraw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e2 f4 vpsrad %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e2 31 vpsrad \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d1 f4 vpsrlw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d1 31 vpsrlw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d2 f4 vpsrld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d2 31 vpsrld \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d3 f4 vpsrlq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d3 31 vpsrlq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f8 f4 vpsubb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f8 31 vpsubb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f9 f4 vpsubw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 f9 31 vpsubw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fa f4 vpsubd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fa 31 vpsubd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fb f4 vpsubq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 fb 31 vpsubq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e8 f4 vpsubsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e8 31 vpsubsb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e9 f4 vpsubsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 e9 31 vpsubsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d8 f4 vpsubusb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d8 31 vpsubusb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d9 f4 vpsubusw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 d9 31 vpsubusw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 68 f4 vpunpckhbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 68 31 vpunpckhbw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 69 f4 vpunpckhwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 69 31 vpunpckhwd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6a f4 vpunpckhdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6a 31 vpunpckhdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6d f4 vpunpckhqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6d 31 vpunpckhqdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 60 f4 vpunpcklbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 60 31 vpunpcklbw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 61 f4 vpunpcklwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 61 31 vpunpcklwd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 62 f4 vpunpckldq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 62 31 vpunpckldq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6c f4 vpunpcklqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 6c 31 vpunpcklqdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ef f4 vpxor %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 ef 31 vpxor \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5c f4 vsubpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 5c 31 vsubpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5c f4 vsubps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 5c 31 vsubps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 15 f4 vunpckhpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 15 31 vunpckhpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 15 f4 vunpckhps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 15 31 vunpckhps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 14 f4 vunpcklpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 14 31 vunpcklpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 14 f4 vunpcklps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 14 31 vunpcklps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 57 f4 vxorpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 57 31 vxorpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 57 f4 vxorps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 57 31 vxorps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 00 vcmpeqpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 00 vcmpeqpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 00 vcmpeqps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 00 vcmpeqps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 01 vcmpltpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 01 vcmpltpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 01 vcmpltps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 01 vcmpltps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 02 vcmplepd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 02 vcmplepd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 02 vcmpleps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 02 vcmpleps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 03 vcmpunordpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 03 vcmpunordpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 03 vcmpunordps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 03 vcmpunordps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 04 vcmpneqpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 04 vcmpneqpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 04 vcmpneqps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 04 vcmpneqps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 05 vcmpnltpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 05 vcmpnltpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 05 vcmpnltps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 05 vcmpnltps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 06 vcmpnlepd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 06 vcmpnlepd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 06 vcmpnleps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 06 vcmpnleps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 07 vcmpordpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 07 vcmpordpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 07 vcmpordps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 07 vcmpordps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0d f4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0d 31 64 vblendpd \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0c f4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0c 31 64 vblendps \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 f4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c2 31 64 vcmppd \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 f4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c2 31 64 vcmpps \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 41 f4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 41 31 64 vdppd \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 40 f4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 40 31 64 vdpps \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 42 f4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 42 31 64 vmpsadbw \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0f f4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0f 31 64 vpalignr \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0e f4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0e 31 64 vpblendw \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c6 f4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c9 c6 31 64 vshufpd \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c6 f4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 c6 31 64 vshufps \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4b f4 00 vblendvpd %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4b 31 00 vblendvpd %xmm0,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4b f4 00 vblendvpd %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4b 31 00 vblendvpd %xmm0,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4a f4 00 vblendvps %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4a 31 00 vblendvps %xmm0,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4a f4 00 vblendvps %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4a 31 00 vblendvps %xmm0,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c4 e1 fb 2d cc vcvtsd2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2d 09 vcvtsd2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2c cc vcvttsd2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fb 2c 09 vcvttsd2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 db 2a e1 vcvtsi2sd %rcx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e1 db 2a 21 vcvtsi2sdq \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e1 da 2a e1 vcvtsi2ss %rcx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e1 da 2a 21 vcvtsi2ssq \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 d9 22 e1 64 vpinsrq \$0x64,%rcx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 d9 22 21 64 vpinsrq \$0x64,\(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq \$0x64,%xmm4,%rcx +[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 d9 12 21 vmovlpd \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d8 12 21 vmovlps \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 16 21 vmovhpd \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d8 16 21 vmovhps \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 cb c2 f4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 64 vcmpsd \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0b f4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0b 31 64 vroundsd \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 58 f4 vaddsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 58 31 vaddsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5a f4 vcvtsd2ss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5a 31 vcvtsd2ss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5e f4 vdivsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5e 31 vdivsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5f f4 vmaxsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5f 31 vmaxsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5d f4 vminsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5d 31 vminsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 59 f4 vmulsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 59 31 vmulsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 51 f4 vsqrtsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 51 31 vsqrtsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5c f4 vsubsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 5c 31 vsubsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 00 vcmpeqsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 00 vcmpeqsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 01 vcmpltsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 01 vcmpltsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 02 vcmplesd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 02 vcmplesd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 03 vcmpunordsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 03 vcmpunordsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 04 vcmpneqsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 04 vcmpneqsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 05 vcmpnltsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 05 vcmpnltsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 06 vcmpnlesd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 06 vcmpnlesd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 f4 07 vcmpordsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb c2 31 07 vcmpordsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 58 f4 vaddss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 58 31 vaddss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5a f4 vcvtss2sd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5a 31 vcvtss2sd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5e f4 vdivss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5e 31 vdivss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5f f4 vmaxss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5f 31 vmaxss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5d f4 vminss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5d 31 vminss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 59 f4 vmulss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 59 31 vmulss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 53 f4 vrcpss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 53 31 vrcpss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 52 f4 vrsqrtss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 52 31 vrsqrtss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 51 f4 vsqrtss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 51 31 vsqrtss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5c f4 vsubss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 5c 31 vsubss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 00 vcmpeqss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 00 vcmpeqss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 01 vcmpltss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 01 vcmpltss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 02 vcmpless %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 02 vcmpless \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 03 vcmpunordss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 03 vcmpunordss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 04 vcmpneqss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 04 vcmpneqss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 05 vcmpnltss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 05 vcmpnltss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 06 vcmpnless %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 06 vcmpnless \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 f4 07 vcmpordss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 07 vcmpordss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 +[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx +[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: c4 e1 fa 2d cc vcvtss2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2d 09 vcvtss2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2c cc vcvttss2si %xmm4,%rcx +[ ]*[a-f0-9]+: c4 e1 fa 2c 09 vcvttss2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 db 2a e1 vcvtsi2sd %ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 db 2a 21 vcvtsi2sdl \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 da 2a e1 vcvtsi2ss %ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 da 2a 21 vcvtsi2ssl \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 ca c2 f4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca c2 31 64 vcmpss \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 21 f4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 21 31 64 vinsertps \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0a f4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e3 49 0a 31 64 vroundss \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c5 d9 c4 e1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 c4 21 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 c4 e1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 c4 21 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 59 20 e1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 59 20 21 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: c4 e3 59 20 e1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c4 e3 59 20 21 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 +[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx +[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx +[ ]*[a-f0-9]+: c5 c8 12 f4 vmovhlps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 c8 16 f4 vmovlhps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: c5 d9 72 f4 64 vpslld \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 d9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx +#pass diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx.s b/gas/testsuite/gas/i386/x86-64-sse2avx.s new file mode 100644 index 0000000..689bb59 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sse2avx.s @@ -0,0 +1,683 @@ +# Check 64bit SSE to AVX instructions + + .allow_index_reg + .text +_start: +# Tests for op mem64 + ldmxcsr (%rcx) + stmxcsr (%rcx) + +# Tests for op xmm/mem128, xmm + cvtdq2ps %xmm4,%xmm6 + cvtdq2ps (%rcx),%xmm4 + cvtpd2dq %xmm4,%xmm6 + cvtpd2dq (%rcx),%xmm4 + cvtpd2ps %xmm4,%xmm6 + cvtpd2ps (%rcx),%xmm4 + cvtps2dq %xmm4,%xmm6 + cvtps2dq (%rcx),%xmm4 + cvttpd2dq %xmm4,%xmm6 + cvttpd2dq (%rcx),%xmm4 + cvttps2dq %xmm4,%xmm6 + cvttps2dq (%rcx),%xmm4 + movapd %xmm4,%xmm6 + movapd (%rcx),%xmm4 + movaps %xmm4,%xmm6 + movaps (%rcx),%xmm4 + movdqa %xmm4,%xmm6 + movdqa (%rcx),%xmm4 + movdqu %xmm4,%xmm6 + movdqu (%rcx),%xmm4 + movshdup %xmm4,%xmm6 + movshdup (%rcx),%xmm4 + movsldup %xmm4,%xmm6 + movsldup (%rcx),%xmm4 + movupd %xmm4,%xmm6 + movupd (%rcx),%xmm4 + movups %xmm4,%xmm6 + movups (%rcx),%xmm4 + pabsb %xmm4,%xmm6 + pabsb (%rcx),%xmm4 + pabsw %xmm4,%xmm6 + pabsw (%rcx),%xmm4 + pabsd %xmm4,%xmm6 + pabsd (%rcx),%xmm4 + phminposuw %xmm4,%xmm6 + phminposuw (%rcx),%xmm4 + ptest %xmm4,%xmm6 + ptest (%rcx),%xmm4 + rcpps %xmm4,%xmm6 + rcpps (%rcx),%xmm4 + rsqrtps %xmm4,%xmm6 + rsqrtps (%rcx),%xmm4 + sqrtpd %xmm4,%xmm6 + sqrtpd (%rcx),%xmm4 + sqrtps %xmm4,%xmm6 + sqrtps (%rcx),%xmm4 + +# Tests for op xmm, xmm/mem128 + movapd %xmm4,%xmm6 + movapd %xmm4,(%rcx) + movaps %xmm4,%xmm6 + movaps %xmm4,(%rcx) + movdqa %xmm4,%xmm6 + movdqa %xmm4,(%rcx) + movdqu %xmm4,%xmm6 + movdqu %xmm4,(%rcx) + movupd %xmm4,%xmm6 + movupd %xmm4,(%rcx) + movups %xmm4,%xmm6 + movups %xmm4,(%rcx) + +# Tests for op mem128, xmm + lddqu (%rcx),%xmm4 + movntdqa (%rcx),%xmm4 + +# Tests for op xmm, mem128 + movntdq %xmm4,(%rcx) + movntpd %xmm4,(%rcx) + movntps %xmm4,(%rcx) + +# Tests for op xmm/mem128, xmm[, xmm] + addpd %xmm4,%xmm6 + addpd (%rcx),%xmm6 + addps %xmm4,%xmm6 + addps (%rcx),%xmm6 + addsubpd %xmm4,%xmm6 + addsubpd (%rcx),%xmm6 + addsubps %xmm4,%xmm6 + addsubps (%rcx),%xmm6 + andnpd %xmm4,%xmm6 + andnpd (%rcx),%xmm6 + andnps %xmm4,%xmm6 + andnps (%rcx),%xmm6 + andpd %xmm4,%xmm6 + andpd (%rcx),%xmm6 + andps %xmm4,%xmm6 + andps (%rcx),%xmm6 + divpd %xmm4,%xmm6 + divpd (%rcx),%xmm6 + divps %xmm4,%xmm6 + divps (%rcx),%xmm6 + haddpd %xmm4,%xmm6 + haddpd (%rcx),%xmm6 + haddps %xmm4,%xmm6 + haddps (%rcx),%xmm6 + hsubpd %xmm4,%xmm6 + hsubpd (%rcx),%xmm6 + hsubps %xmm4,%xmm6 + hsubps (%rcx),%xmm6 + maxpd %xmm4,%xmm6 + maxpd (%rcx),%xmm6 + maxps %xmm4,%xmm6 + maxps (%rcx),%xmm6 + minpd %xmm4,%xmm6 + minpd (%rcx),%xmm6 + minps %xmm4,%xmm6 + minps (%rcx),%xmm6 + mulpd %xmm4,%xmm6 + mulpd (%rcx),%xmm6 + mulps %xmm4,%xmm6 + mulps (%rcx),%xmm6 + orpd %xmm4,%xmm6 + orpd (%rcx),%xmm6 + orps %xmm4,%xmm6 + orps (%rcx),%xmm6 + packsswb %xmm4,%xmm6 + packsswb (%rcx),%xmm6 + packssdw %xmm4,%xmm6 + packssdw (%rcx),%xmm6 + packuswb %xmm4,%xmm6 + packuswb (%rcx),%xmm6 + packusdw %xmm4,%xmm6 + packusdw (%rcx),%xmm6 + paddb %xmm4,%xmm6 + paddb (%rcx),%xmm6 + paddw %xmm4,%xmm6 + paddw (%rcx),%xmm6 + paddd %xmm4,%xmm6 + paddd (%rcx),%xmm6 + paddq %xmm4,%xmm6 + paddq (%rcx),%xmm6 + paddsb %xmm4,%xmm6 + paddsb (%rcx),%xmm6 + paddsw %xmm4,%xmm6 + paddsw (%rcx),%xmm6 + paddusb %xmm4,%xmm6 + paddusb (%rcx),%xmm6 + paddusw %xmm4,%xmm6 + paddusw (%rcx),%xmm6 + pand %xmm4,%xmm6 + pand (%rcx),%xmm6 + pandn %xmm4,%xmm6 + pandn (%rcx),%xmm6 + pavgb %xmm4,%xmm6 + pavgb (%rcx),%xmm6 + pavgw %xmm4,%xmm6 + pavgw (%rcx),%xmm6 + pcmpeqb %xmm4,%xmm6 + pcmpeqb (%rcx),%xmm6 + pcmpeqw %xmm4,%xmm6 + pcmpeqw (%rcx),%xmm6 + pcmpeqd %xmm4,%xmm6 + pcmpeqd (%rcx),%xmm6 + pcmpeqq %xmm4,%xmm6 + pcmpeqq (%rcx),%xmm6 + pcmpgtb %xmm4,%xmm6 + pcmpgtb (%rcx),%xmm6 + pcmpgtw %xmm4,%xmm6 + pcmpgtw (%rcx),%xmm6 + pcmpgtd %xmm4,%xmm6 + pcmpgtd (%rcx),%xmm6 + pcmpgtq %xmm4,%xmm6 + pcmpgtq (%rcx),%xmm6 + phaddw %xmm4,%xmm6 + phaddw (%rcx),%xmm6 + phaddd %xmm4,%xmm6 + phaddd (%rcx),%xmm6 + phaddsw %xmm4,%xmm6 + phaddsw (%rcx),%xmm6 + phsubw %xmm4,%xmm6 + phsubw (%rcx),%xmm6 + phsubd %xmm4,%xmm6 + phsubd (%rcx),%xmm6 + phsubsw %xmm4,%xmm6 + phsubsw (%rcx),%xmm6 + pmaddwd %xmm4,%xmm6 + pmaddwd (%rcx),%xmm6 + pmaddubsw %xmm4,%xmm6 + pmaddubsw (%rcx),%xmm6 + pmaxsb %xmm4,%xmm6 + pmaxsb (%rcx),%xmm6 + pmaxsw %xmm4,%xmm6 + pmaxsw (%rcx),%xmm6 + pmaxsd %xmm4,%xmm6 + pmaxsd (%rcx),%xmm6 + pmaxub %xmm4,%xmm6 + pmaxub (%rcx),%xmm6 + pmaxuw %xmm4,%xmm6 + pmaxuw (%rcx),%xmm6 + pmaxud %xmm4,%xmm6 + pmaxud (%rcx),%xmm6 + pminsb %xmm4,%xmm6 + pminsb (%rcx),%xmm6 + pminsw %xmm4,%xmm6 + pminsw (%rcx),%xmm6 + pminsd %xmm4,%xmm6 + pminsd (%rcx),%xmm6 + pminub %xmm4,%xmm6 + pminub (%rcx),%xmm6 + pminuw %xmm4,%xmm6 + pminuw (%rcx),%xmm6 + pminud %xmm4,%xmm6 + pminud (%rcx),%xmm6 + pmulhuw %xmm4,%xmm6 + pmulhuw (%rcx),%xmm6 + pmulhrsw %xmm4,%xmm6 + pmulhrsw (%rcx),%xmm6 + pmulhw %xmm4,%xmm6 + pmulhw (%rcx),%xmm6 + pmullw %xmm4,%xmm6 + pmullw (%rcx),%xmm6 + pmulld %xmm4,%xmm6 + pmulld (%rcx),%xmm6 + pmuludq %xmm4,%xmm6 + pmuludq (%rcx),%xmm6 + pmuldq %xmm4,%xmm6 + pmuldq (%rcx),%xmm6 + por %xmm4,%xmm6 + por (%rcx),%xmm6 + psadbw %xmm4,%xmm6 + psadbw (%rcx),%xmm6 + pshufb %xmm4,%xmm6 + pshufb (%rcx),%xmm6 + psignb %xmm4,%xmm6 + psignb (%rcx),%xmm6 + psignw %xmm4,%xmm6 + psignw (%rcx),%xmm6 + psignd %xmm4,%xmm6 + psignd (%rcx),%xmm6 + psllw %xmm4,%xmm6 + psllw (%rcx),%xmm6 + pslld %xmm4,%xmm6 + pslld (%rcx),%xmm6 + psllq %xmm4,%xmm6 + psllq (%rcx),%xmm6 + psraw %xmm4,%xmm6 + psraw (%rcx),%xmm6 + psrad %xmm4,%xmm6 + psrad (%rcx),%xmm6 + psrlw %xmm4,%xmm6 + psrlw (%rcx),%xmm6 + psrld %xmm4,%xmm6 + psrld (%rcx),%xmm6 + psrlq %xmm4,%xmm6 + psrlq (%rcx),%xmm6 + psubb %xmm4,%xmm6 + psubb (%rcx),%xmm6 + psubw %xmm4,%xmm6 + psubw (%rcx),%xmm6 + psubd %xmm4,%xmm6 + psubd (%rcx),%xmm6 + psubq %xmm4,%xmm6 + psubq (%rcx),%xmm6 + psubsb %xmm4,%xmm6 + psubsb (%rcx),%xmm6 + psubsw %xmm4,%xmm6 + psubsw (%rcx),%xmm6 + psubusb %xmm4,%xmm6 + psubusb (%rcx),%xmm6 + psubusw %xmm4,%xmm6 + psubusw (%rcx),%xmm6 + punpckhbw %xmm4,%xmm6 + punpckhbw (%rcx),%xmm6 + punpckhwd %xmm4,%xmm6 + punpckhwd (%rcx),%xmm6 + punpckhdq %xmm4,%xmm6 + punpckhdq (%rcx),%xmm6 + punpckhqdq %xmm4,%xmm6 + punpckhqdq (%rcx),%xmm6 + punpcklbw %xmm4,%xmm6 + punpcklbw (%rcx),%xmm6 + punpcklwd %xmm4,%xmm6 + punpcklwd (%rcx),%xmm6 + punpckldq %xmm4,%xmm6 + punpckldq (%rcx),%xmm6 + punpcklqdq %xmm4,%xmm6 + punpcklqdq (%rcx),%xmm6 + pxor %xmm4,%xmm6 + pxor (%rcx),%xmm6 + subpd %xmm4,%xmm6 + subpd (%rcx),%xmm6 + subps %xmm4,%xmm6 + subps (%rcx),%xmm6 + unpckhpd %xmm4,%xmm6 + unpckhpd (%rcx),%xmm6 + unpckhps %xmm4,%xmm6 + unpckhps (%rcx),%xmm6 + unpcklpd %xmm4,%xmm6 + unpcklpd (%rcx),%xmm6 + unpcklps %xmm4,%xmm6 + unpcklps (%rcx),%xmm6 + xorpd %xmm4,%xmm6 + xorpd (%rcx),%xmm6 + xorps %xmm4,%xmm6 + xorps (%rcx),%xmm6 + cmpeqpd %xmm4,%xmm6 + cmpeqpd (%rcx),%xmm6 + cmpeqps %xmm4,%xmm6 + cmpeqps (%rcx),%xmm6 + cmpltpd %xmm4,%xmm6 + cmpltpd (%rcx),%xmm6 + cmpltps %xmm4,%xmm6 + cmpltps (%rcx),%xmm6 + cmplepd %xmm4,%xmm6 + cmplepd (%rcx),%xmm6 + cmpleps %xmm4,%xmm6 + cmpleps (%rcx),%xmm6 + cmpunordpd %xmm4,%xmm6 + cmpunordpd (%rcx),%xmm6 + cmpunordps %xmm4,%xmm6 + cmpunordps (%rcx),%xmm6 + cmpneqpd %xmm4,%xmm6 + cmpneqpd (%rcx),%xmm6 + cmpneqps %xmm4,%xmm6 + cmpneqps (%rcx),%xmm6 + cmpnltpd %xmm4,%xmm6 + cmpnltpd (%rcx),%xmm6 + cmpnltps %xmm4,%xmm6 + cmpnltps (%rcx),%xmm6 + cmpnlepd %xmm4,%xmm6 + cmpnlepd (%rcx),%xmm6 + cmpnleps %xmm4,%xmm6 + cmpnleps (%rcx),%xmm6 + cmpordpd %xmm4,%xmm6 + cmpordpd (%rcx),%xmm6 + cmpordps %xmm4,%xmm6 + cmpordps (%rcx),%xmm6 + +# Tests for op imm8, xmm/mem128, xmm + pcmpestri $100,%xmm4,%xmm6 + pcmpestri $100,(%rcx),%xmm6 + pcmpestrm $100,%xmm4,%xmm6 + pcmpestrm $100,(%rcx),%xmm6 + pcmpistri $100,%xmm4,%xmm6 + pcmpistri $100,(%rcx),%xmm6 + pcmpistrm $100,%xmm4,%xmm6 + pcmpistrm $100,(%rcx),%xmm6 + pshufd $100,%xmm4,%xmm6 + pshufd $100,(%rcx),%xmm6 + pshufhw $100,%xmm4,%xmm6 + pshufhw $100,(%rcx),%xmm6 + pshuflw $100,%xmm4,%xmm6 + pshuflw $100,(%rcx),%xmm6 + roundpd $100,%xmm4,%xmm6 + roundpd $100,(%rcx),%xmm6 + roundps $100,%xmm4,%xmm6 + roundps $100,(%rcx),%xmm6 + +# Tests for op imm8, xmm/mem128, xmm[, xmm] + blendpd $100,%xmm4,%xmm6 + blendpd $100,(%rcx),%xmm6 + blendps $100,%xmm4,%xmm6 + blendps $100,(%rcx),%xmm6 + cmppd $100,%xmm4,%xmm6 + cmppd $100,(%rcx),%xmm6 + cmpps $100,%xmm4,%xmm6 + cmpps $100,(%rcx),%xmm6 + dppd $100,%xmm4,%xmm6 + dppd $100,(%rcx),%xmm6 + dpps $100,%xmm4,%xmm6 + dpps $100,(%rcx),%xmm6 + mpsadbw $100,%xmm4,%xmm6 + mpsadbw $100,(%rcx),%xmm6 + palignr $100,%xmm4,%xmm6 + palignr $100,(%rcx),%xmm6 + pblendw $100,%xmm4,%xmm6 + pblendw $100,(%rcx),%xmm6 + shufpd $100,%xmm4,%xmm6 + shufpd $100,(%rcx),%xmm6 + shufps $100,%xmm4,%xmm6 + shufps $100,(%rcx),%xmm6 + +# Tests for op xmm0, xmm/mem128, xmm[, xmm] + blendvpd %xmm0,%xmm4,%xmm6 + blendvpd %xmm0,(%rcx),%xmm6 + blendvpd %xmm4,%xmm6 + blendvpd (%rcx),%xmm6 + blendvps %xmm0,%xmm4,%xmm6 + blendvps %xmm0,(%rcx),%xmm6 + blendvps %xmm4,%xmm6 + blendvps (%rcx),%xmm6 + pblendvb %xmm0,%xmm4,%xmm6 + pblendvb %xmm0,(%rcx),%xmm6 + pblendvb %xmm4,%xmm6 + pblendvb (%rcx),%xmm6 + +# Tests for op xmm/mem64, xmm + comisd %xmm4,%xmm6 + comisd (%rcx),%xmm4 + cvtdq2pd %xmm4,%xmm6 + cvtdq2pd (%rcx),%xmm4 + cvtps2pd %xmm4,%xmm6 + cvtps2pd (%rcx),%xmm4 + movddup %xmm4,%xmm6 + movddup (%rcx),%xmm4 + pmovsxbw %xmm4,%xmm6 + pmovsxbw (%rcx),%xmm4 + pmovsxwd %xmm4,%xmm6 + pmovsxwd (%rcx),%xmm4 + pmovsxdq %xmm4,%xmm6 + pmovsxdq (%rcx),%xmm4 + pmovzxbw %xmm4,%xmm6 + pmovzxbw (%rcx),%xmm4 + pmovzxwd %xmm4,%xmm6 + pmovzxwd (%rcx),%xmm4 + pmovzxdq %xmm4,%xmm6 + pmovzxdq (%rcx),%xmm4 + ucomisd %xmm4,%xmm6 + ucomisd (%rcx),%xmm4 + +# Tests for op mem64, xmm + movsd (%rcx),%xmm4 + +# Tests for op xmm, mem64 + movlpd %xmm4,(%rcx) + movlps %xmm4,(%rcx) + movhpd %xmm4,(%rcx) + movhps %xmm4,(%rcx) + movsd %xmm4,(%rcx) + +# Tests for op xmm, regq/mem64 +# Tests for op regq/mem64, xmm + movq %xmm4,%rcx + movq %rcx,%xmm4 + movq %xmm4,(%rcx) + movq (%rcx),%xmm4 + +# Tests for op xmm/mem64, regl + cvtsd2si %xmm4,%ecx + cvtsd2si (%rcx),%ecx + cvttsd2si %xmm4,%ecx + cvttsd2si (%rcx),%ecx + +# Tests for op xmm/mem64, regq + cvtsd2si %xmm4,%rcx + cvtsd2si (%rcx),%rcx + cvttsd2si %xmm4,%rcx + cvttsd2si (%rcx),%rcx + +# Tests for op regq/mem64, xmm[, xmm] + cvtsi2sdq %rcx,%xmm4 + cvtsi2sdq (%rcx),%xmm4 + cvtsi2ssq %rcx,%xmm4 + cvtsi2ssq (%rcx),%xmm4 + +# Tests for op imm8, regq/mem64, xmm[, xmm] + pinsrq $100,%rcx,%xmm4 + pinsrq $100,(%rcx),%xmm4 + +# Testsf for op imm8, xmm, regq/mem64 + pextrq $100,%xmm4,%rcx + pextrq $100,%xmm4,(%rcx) + +# Tests for op mem64, xmm[, xmm] + movlpd (%rcx),%xmm4 + movlps (%rcx),%xmm4 + movhpd (%rcx),%xmm4 + movhps (%rcx),%xmm4 + +# Tests for op imm8, xmm/mem64, xmm[, xmm] + cmpsd $100,%xmm4,%xmm6 + cmpsd $100,(%rcx),%xmm6 + roundsd $100,%xmm4,%xmm6 + roundsd $100,(%rcx),%xmm6 + +# Tests for op xmm/mem64, xmm[, xmm] + addsd %xmm4,%xmm6 + addsd (%rcx),%xmm6 + cvtsd2ss %xmm4,%xmm6 + cvtsd2ss (%rcx),%xmm6 + divsd %xmm4,%xmm6 + divsd (%rcx),%xmm6 + maxsd %xmm4,%xmm6 + maxsd (%rcx),%xmm6 + minsd %xmm4,%xmm6 + minsd (%rcx),%xmm6 + mulsd %xmm4,%xmm6 + mulsd (%rcx),%xmm6 + sqrtsd %xmm4,%xmm6 + sqrtsd (%rcx),%xmm6 + subsd %xmm4,%xmm6 + subsd (%rcx),%xmm6 + cmpeqsd %xmm4,%xmm6 + cmpeqsd (%rcx),%xmm6 + cmpltsd %xmm4,%xmm6 + cmpltsd (%rcx),%xmm6 + cmplesd %xmm4,%xmm6 + cmplesd (%rcx),%xmm6 + cmpunordsd %xmm4,%xmm6 + cmpunordsd (%rcx),%xmm6 + cmpneqsd %xmm4,%xmm6 + cmpneqsd (%rcx),%xmm6 + cmpnltsd %xmm4,%xmm6 + cmpnltsd (%rcx),%xmm6 + cmpnlesd %xmm4,%xmm6 + cmpnlesd (%rcx),%xmm6 + cmpordsd %xmm4,%xmm6 + cmpordsd (%rcx),%xmm6 + +# Tests for op xmm/mem32, xmm[, xmm] + addss %xmm4,%xmm6 + addss (%rcx),%xmm6 + cvtss2sd %xmm4,%xmm6 + cvtss2sd (%rcx),%xmm6 + divss %xmm4,%xmm6 + divss (%rcx),%xmm6 + maxss %xmm4,%xmm6 + maxss (%rcx),%xmm6 + minss %xmm4,%xmm6 + minss (%rcx),%xmm6 + mulss %xmm4,%xmm6 + mulss (%rcx),%xmm6 + rcpss %xmm4,%xmm6 + rcpss (%rcx),%xmm6 + rsqrtss %xmm4,%xmm6 + rsqrtss (%rcx),%xmm6 + sqrtss %xmm4,%xmm6 + sqrtss (%rcx),%xmm6 + subss %xmm4,%xmm6 + subss (%rcx),%xmm6 + cmpeqss %xmm4,%xmm6 + cmpeqss (%rcx),%xmm6 + cmpltss %xmm4,%xmm6 + cmpltss (%rcx),%xmm6 + cmpless %xmm4,%xmm6 + cmpless (%rcx),%xmm6 + cmpunordss %xmm4,%xmm6 + cmpunordss (%rcx),%xmm6 + cmpneqss %xmm4,%xmm6 + cmpneqss (%rcx),%xmm6 + cmpnltss %xmm4,%xmm6 + cmpnltss (%rcx),%xmm6 + cmpnless %xmm4,%xmm6 + cmpnless (%rcx),%xmm6 + cmpordss %xmm4,%xmm6 + cmpordss (%rcx),%xmm6 + +# Tests for op xmm/mem32, xmm + comiss %xmm4,%xmm6 + comiss (%rcx),%xmm4 + pmovsxbd %xmm4,%xmm6 + pmovsxbd (%rcx),%xmm4 + pmovsxwq %xmm4,%xmm6 + pmovsxwq (%rcx),%xmm4 + pmovzxbd %xmm4,%xmm6 + pmovzxbd (%rcx),%xmm4 + pmovzxwq %xmm4,%xmm6 + pmovzxwq (%rcx),%xmm4 + ucomiss %xmm4,%xmm6 + ucomiss (%rcx),%xmm4 + +# Tests for op mem32, xmm + movss (%rcx),%xmm4 + +# Tests for op xmm, mem32 + movss %xmm4,(%rcx) + +# Tests for op xmm, regl/mem32 +# Tests for op regl/mem32, xmm + movd %xmm4,%ecx + movd %xmm4,(%rcx) + movd %ecx,%xmm4 + movd (%rcx),%xmm4 + +# Tests for op xmm/mem32, regl + cvtss2si %xmm4,%ecx + cvtss2si (%rcx),%ecx + cvttss2si %xmm4,%ecx + cvttss2si (%rcx),%ecx + +# Tests for op xmm/mem32, regq + cvtss2si %xmm4,%rcx + cvtss2si (%rcx),%rcx + cvttss2si %xmm4,%rcx + cvttss2si (%rcx),%rcx + +# Tests for op xmm, regq + movmskpd %xmm4,%rcx + movmskps %xmm4,%rcx + pmovmskb %xmm4,%rcx + +# Tests for op imm8, xmm, regq/mem32 + extractps $100,%xmm4,%rcx + extractps $100,%xmm4,(%rcx) +# Tests for op imm8, xmm, regl/mem32 + pextrd $100,%xmm4,%ecx + pextrd $100,%xmm4,(%rcx) + extractps $100,%xmm4,%ecx + extractps $100,%xmm4,(%rcx) + +# Tests for op regl/mem32, xmm[, xmm] + cvtsi2sd %ecx,%xmm4 + cvtsi2sd (%rcx),%xmm4 + cvtsi2ss %ecx,%xmm4 + cvtsi2ss (%rcx),%xmm4 + +# Tests for op imm8, xmm/mem32, xmm[, xmm] + cmpss $100,%xmm4,%xmm6 + cmpss $100,(%rcx),%xmm6 + insertps $100,%xmm4,%xmm6 + insertps $100,(%rcx),%xmm6 + roundss $100,%xmm4,%xmm6 + roundss $100,(%rcx),%xmm6 + +# Tests for op xmm/m16, xmm + pmovsxbq %xmm4,%xmm6 + pmovsxbq (%rcx),%xmm4 + pmovzxbq %xmm4,%xmm6 + pmovzxbq (%rcx),%xmm4 + +# Tests for op imm8, xmm, regl/mem16 + pextrw $100,%xmm4,%ecx + pextrw $100,%xmm4,(%rcx) + +# Tests for op imm8, xmm, regq/mem16 + pextrw $100,%xmm4,%rcx + pextrw $100,%xmm4,(%rcx) + +# Tests for op imm8, regl/mem16, xmm[, xmm] + pinsrw $100,%ecx,%xmm4 + pinsrw $100,(%rcx),%xmm4 + + + pinsrw $100,%rcx,%xmm4 + pinsrw $100,(%rcx),%xmm4 + +# Tests for op imm8, xmm, regl/mem8 + pextrb $100,%xmm4,%ecx + pextrb $100,%xmm4,(%rcx) + +# Tests for op imm8, regl/mem8, xmm[, xmm] + pinsrb $100,%ecx,%xmm4 + pinsrb $100,(%rcx),%xmm4 + +# Tests for op imm8, xmm, regq + pextrw $100,%xmm4,%rcx +# Tests for op imm8, xmm, regq/mem8 + pextrb $100,%xmm4,%rcx + pextrb $100,%xmm4,(%rcx) + +# Tests for op imm8, regl/mem8, xmm[, xmm] + pinsrb $100,%ecx,%xmm4 + pinsrb $100,(%rcx),%xmm4 + +# Tests for op xmm, xmm + maskmovdqu %xmm4,%xmm6 + movq %xmm4,%xmm6 + +# Tests for op xmm, regl + movmskpd %xmm4,%ecx + movmskps %xmm4,%ecx + pmovmskb %xmm4,%ecx +# Tests for op xmm, xmm[, xmm] + movhlps %xmm4,%xmm6 + movlhps %xmm4,%xmm6 + movsd %xmm4,%xmm6 + movss %xmm4,%xmm6 + +# Tests for op imm8, xmm[, xmm] + pslld $100,%xmm4 + pslldq $100,%xmm4 + psllq $100,%xmm4 + psllw $100,%xmm4 + psrad $100,%xmm4 + psraw $100,%xmm4 + psrld $100,%xmm4 + psrldq $100,%xmm4 + psrlq $100,%xmm4 + psrlw $100,%xmm4 + +# Tests for op imm8, xmm, regl + pextrw $100,%xmm4,%ecx + diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 919f205..86b03c7 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2008-04-03 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (MAX_OPERANDS): Set to 5. + (MAX_MNEM_SIZE): Changed to 20. + 2008-03-09 Paul Brook <paul@codesourcery.com> * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. diff --git a/include/opcode/i386.h b/include/opcode/i386.h index 4fe769a..f59eeea 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -100,7 +100,7 @@ #define REX_B 1 /* max operands per insn */ -#define MAX_OPERANDS 4 +#define MAX_OPERANDS 5 /* max immediates per insn (lcall, ljmp, insertq, extrq) */ #define MAX_IMMEDIATE_OPERANDS 2 @@ -109,7 +109,7 @@ #define MAX_MEMORY_OPERANDS 2 /* max size of insn mnemonics. */ -#define MAX_MNEM_SIZE 16 +#define MAX_MNEM_SIZE 20 /* max size of register name in insn mnemonics. */ #define MAX_REG_NAME_SIZE 8 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index fdbaedb..0c1be77 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,152 @@ +2008-04-03 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (OP_E_register): New. + (OP_E_memory): Likewise. + (OP_VEX): Likewise. + (OP_EX_Vex): Likewise. + (OP_EX_VexW): Likewise. + (OP_XMM_Vex): Likewise. + (OP_XMM_VexW): Likewise. + (OP_REG_VexI4): Likewise. + (PCLMUL_Fixup): Likewise. + (VEXI4_Fixup): Likewise. + (VZERO_Fixup): Likewise. + (VCMP_Fixup): Likewise. + (VPERMIL2_Fixup): Likewise. + (rex_original): Likewise. + (rex_ignored): Likewise. + (Mxmm): Likewise. + (XMM): Likewise. + (EXxmm): Likewise. + (EXxmmq): Likewise. + (EXymmq): Likewise. + (Vex): Likewise. + (Vex128): Likewise. + (Vex256): Likewise. + (VexI4): Likewise. + (EXdVex): Likewise. + (EXqVex): Likewise. + (EXVexW): Likewise. + (EXdVexW): Likewise. + (EXqVexW): Likewise. + (XMVex): Likewise. + (XMVexW): Likewise. + (XMVexI4): Likewise. + (PCLMUL): Likewise. + (VZERO): Likewise. + (VCMP): Likewise. + (VPERMIL2): Likewise. + (xmm_mode): Likewise. + (xmmq_mode): Likewise. + (ymmq_mode): Likewise. + (vex_mode): Likewise. + (vex128_mode): Likewise. + (vex256_mode): Likewise. + (USE_VEX_C4_TABLE): Likewise. + (USE_VEX_C5_TABLE): Likewise. + (USE_VEX_LEN_TABLE): Likewise. + (VEX_C4_TABLE): Likewise. + (VEX_C5_TABLE): Likewise. + (VEX_LEN_TABLE): Likewise. + (REG_VEX_XX): Likewise. + (MOD_VEX_XXX): Likewise. + (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. + (PREFIX_0F3A44): Likewise. + (PREFIX_0F3ADF): Likewise. + (PREFIX_VEX_XXX): Likewise. + (VEX_OF): Likewise. + (VEX_OF38): Likewise. + (VEX_OF3A): Likewise. + (VEX_LEN_XXX): Likewise. + (vex): Likewise. + (need_vex): Likewise. + (need_vex_reg): Likewise. + (vex_i4_done): Likewise. + (vex_table): Likewise. + (vex_len_table): Likewise. + (OP_REG_VexI4): Likewise. + (vex_cmp_op): Likewise. + (pclmul_op): Likewise. + (vpermil2_op): Likewise. + (m_mode): Updated. + (es_reg): Likewise. + (PREFIX_0F38F0): Likewise. + (PREFIX_0F3A60): Likewise. + (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. + (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF + and PREFIX_VEX_XXX entries. + (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. + (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and + PREFIX_0F3ADF. + (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. + Add MOD_VEX_XXX entries. + (ckprefix): Initialize rex_original and rex_ignored. Store the + REX byte in rex_original. + (get_valid_dis386): Handle the implicit prefix in VEX prefix + bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. + (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before + calling get_valid_dis386. Use rex_original and rex_ignored when + printing out REX. + (putop): Handle "XY". + (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and + ymmq_mode. + (OP_E_extended): Updated to use OP_E_register and + OP_E_memory. + (OP_XMM): Handle VEX. + (OP_EX): Likewise. + (XMM_Fixup): Likewise. + (CMP_Fixup): Use ARRAY_SIZE. + + * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, + CPU_FMA_FLAGS and CPU_AVX_FLAGS. + (operand_type_init): Add OPERAND_TYPE_REGYMM and + OPERAND_TYPE_VEX_IMM4. + (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. + (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, + VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, + VexImmExt and SSE2AVX. + (operand_types): Add RegYMM, Ymmword and Vex_Imm4. + + * i386-opc.h (CpuAVX): New. + (CpuAES): Likewise. + (CpuCLMUL): Likewise. + (CpuFMA): Likewise. + (Vex): Likewise. + (Vex256): Likewise. + (VexNDS): Likewise. + (VexNDD): Likewise. + (VexW0): Likewise. + (VexW1): Likewise. + (Vex0F): Likewise. + (Vex0F38): Likewise. + (Vex0F3A): Likewise. + (Vex3Sources): Likewise. + (VexImmExt): Likewise. + (SSE2AVX): Likewise. + (RegYMM): Likewise. + (Ymmword): Likewise. + (Vex_Imm4): Likewise. + (Implicit1stXmm0): Likewise. + (CpuXsave): Updated. + (CpuLM): Likewise. + (ByteOkIntel): Likewise. + (OldGcc): Likewise. + (Control): Likewise. + (Unspecified): Likewise. + (OTMax): Likewise. + (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. + (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, + vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, + vex3sources, veximmext and sse2avx. + (i386_operand_type): Add regymm, ymmword and vex_imm4. + + * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. + + * i386-reg.tbl: Add AVX registers, ymm0..ymm15. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com> From Robin Getz <robin.getz@analog.com> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index cb6a171..164b457 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -53,6 +53,8 @@ static void oappend (const char *); static void append_seg (void); static void OP_indirE (int, int); static void print_operand_value (char *, int, bfd_vma); +static void OP_E_register (int, int); +static void OP_E_memory (int, int, int); static void OP_E_extended (int, int, int); static void print_displacement (char *, bfd_vma); static void OP_E (int, int); @@ -89,6 +91,17 @@ static void OP_MXC (int,int); static void OP_MS (int, int); static void OP_XS (int, int); static void OP_M (int, int); +static void OP_VEX (int, int); +static void OP_EX_Vex (int, int); +static void OP_EX_VexW (int, int); +static void OP_XMM_Vex (int, int); +static void OP_XMM_VexW (int, int); +static void OP_REG_VexI4 (int, int); +static void PCLMUL_Fixup (int, int); +static void VEXI4_Fixup (int, int); +static void VZERO_Fixup (int, int); +static void VCMP_Fixup (int, int); +static void VPERMIL2_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); @@ -132,6 +145,11 @@ static int prefixes; static int rex; /* Bits of REX we've already used. */ static int rex_used; +/* Original REX prefix. */ +static int rex_original; +/* REX bits in original REX prefix ignored. It may not be the same + as rex_original since some bits may not be ignored. */ +static int rex_ignored; /* Mark parts used in the REX prefix. When we are testing for empty prefix (for 8bit register REX extension), just mask it out. Otherwise test for REX bit is excuse for existence of REX @@ -237,6 +255,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ #define Mq { OP_M, q_mode } #define Mx { OP_M, x_mode } +#define Mxmm { OP_M, xmm_mode } #define Gb { OP_G, b_mode } #define Gv { OP_G, v_mode } #define Gd { OP_G, d_mode } @@ -329,6 +348,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define MX { OP_MMX, 0 } #define XM { OP_XMM, 0 } +#define XMM { OP_XMM, xmm_mode } #define EM { OP_EM, v_mode } #define EMd { OP_EM, d_mode } #define EMx { OP_EM, x_mode } @@ -336,6 +356,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EXd { OP_EX, d_mode } #define EXq { OP_EX, q_mode } #define EXx { OP_EX, x_mode } +#define EXxmm { OP_EX, xmm_mode } +#define EXxmmq { OP_EX, xmmq_mode } +#define EXymmq { OP_EX, ymmq_mode } #define MS { OP_MS, v_mode } #define XS { OP_XS, v_mode } #define EMCq { OP_EMC, q_mode } @@ -344,6 +367,23 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define CMP { CMP_Fixup, 0 } #define XMM0 { XMM_Fixup, 0 } +#define Vex { OP_VEX, vex_mode } +#define Vex128 { OP_VEX, vex128_mode } +#define Vex256 { OP_VEX, vex256_mode } +#define VexI4 { VEXI4_Fixup, 0} +#define EXdVex { OP_EX_Vex, d_mode } +#define EXqVex { OP_EX_Vex, q_mode } +#define EXVexW { OP_EX_VexW, x_mode } +#define EXdVexW { OP_EX_VexW, d_mode } +#define EXqVexW { OP_EX_VexW, q_mode } +#define XMVex { OP_XMM_Vex, 0 } +#define XMVexW { OP_XMM_VexW, 0 } +#define XMVexI4 { OP_REG_VexI4, x_mode } +#define PCLMUL { PCLMUL_Fixup, 0 } +#define VZERO { VZERO_Fixup, 0 } +#define VCMP { VCMP_Fixup, 0 } +#define VPERMIL2 { VPERMIL2_Fixup, 0 } + /* Used handle "rep" prefix for string instructions. */ #define Xbr { REP_Fixup, eSI_reg } #define Xvr { REP_Fixup, eSI_reg } @@ -374,10 +414,16 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define q_mode (d_mode + 1) /* ten-byte operand */ #define t_mode (q_mode + 1) -/* 16-byte XMM operand */ +/* 16-byte XMM or 32-byte YMM operand */ #define x_mode (t_mode + 1) +/* 16-byte XMM operand */ +#define xmm_mode (x_mode + 1) +/* 16-byte XMM or quad word operand */ +#define xmmq_mode (xmm_mode + 1) +/* 32-byte YMM or quad word operand */ +#define ymmq_mode (xmmq_mode + 1) /* d_mode in 32bit, q_mode in 64bit mode. */ -#define m_mode (x_mode + 1) +#define m_mode (ymmq_mode + 1) /* pair of v_mode operands */ #define a_mode (m_mode + 1) #define cond_jump_mode (a_mode + 1) @@ -399,8 +445,14 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define dqb_mode (o_mode + 1) /* registers like dq_mode, memory like d_mode. */ #define dqd_mode (dqb_mode + 1) - -#define es_reg (dqd_mode + 1) +/* normal vex mode */ +#define vex_mode (dqd_mode + 1) +/* 128bit vex mode */ +#define vex128_mode (vex_mode + 1) +/* 256bit vex mode */ +#define vex256_mode (vex128_mode + 1) + +#define es_reg (vex256_mode + 1) #define cs_reg (es_reg + 1) #define ss_reg (cs_reg + 1) #define ds_reg (ss_reg + 1) @@ -465,6 +517,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define USE_PREFIX_TABLE (USE_RM_TABLE + 1) #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1) #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1) +#define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1) +#define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1) +#define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1) #define FLOAT NULL, { { NULL, FLOATCODE } } @@ -475,6 +530,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) +#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) +#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) +#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) #define REG_80 0 #define REG_81 (REG_80 + 1) @@ -504,6 +562,10 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define REG_0FAE (REG_0FA7 + 1) #define REG_0FBA (REG_0FAE + 1) #define REG_0FC7 (REG_0FBA + 1) +#define REG_VEX_71 (REG_0FC7 + 1) +#define REG_VEX_72 (REG_VEX_71 + 1) +#define REG_VEX_73 (REG_VEX_72 + 1) +#define REG_VEX_AE (REG_VEX_73 + 1) #define MOD_8D 0 #define MOD_0F01_REG_0 (MOD_8D + 1) @@ -560,6 +622,35 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1) #define MOD_C4_32BIT (MOD_62_32BIT + 1) #define MOD_C5_32BIT (MOD_C4_32BIT + 1) +#define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1) +#define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1) +#define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1) +#define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1) +#define MOD_VEX_2B (MOD_VEX_17 + 1) +#define MOD_VEX_51 (MOD_VEX_2B + 1) +#define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1) +#define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1) +#define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1) +#define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1) +#define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1) +#define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1) +#define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1) +#define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1) +#define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1) +#define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1) +#define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1) +#define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1) +#define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1) +#define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1) +#define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1) +#define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1) +#define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1) +#define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1) +#define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1) +#define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1) +#define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1) +#define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1) +#define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1) #define RM_0F01_REG_0 0 #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1) @@ -649,7 +740,12 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define PREFIX_0F383F (PREFIX_0F383E + 1) #define PREFIX_0F3840 (PREFIX_0F383F + 1) #define PREFIX_0F3841 (PREFIX_0F3840 + 1) -#define PREFIX_0F38F0 (PREFIX_0F3841 + 1) +#define PREFIX_0F38DB (PREFIX_0F3841 + 1) +#define PREFIX_0F38DC (PREFIX_0F38DB + 1) +#define PREFIX_0F38DD (PREFIX_0F38DC + 1) +#define PREFIX_0F38DE (PREFIX_0F38DD + 1) +#define PREFIX_0F38DF (PREFIX_0F38DE + 1) +#define PREFIX_0F38F0 (PREFIX_0F38DF + 1) #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1) #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1) #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1) @@ -668,10 +764,223 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1) #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1) #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1) -#define PREFIX_0F3A60 (PREFIX_0F3A42 + 1) +#define PREFIX_0F3A44 (PREFIX_0F3A42 + 1) +#define PREFIX_0F3A60 (PREFIX_0F3A44 + 1) #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1) #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1) #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1) +#define PREFIX_0F3ADF (PREFIX_0F3A63 + 1) +#define PREFIX_VEX_10 (PREFIX_0F3ADF + 1) +#define PREFIX_VEX_11 (PREFIX_VEX_10 + 1) +#define PREFIX_VEX_12 (PREFIX_VEX_11 + 1) +#define PREFIX_VEX_16 (PREFIX_VEX_12 + 1) +#define PREFIX_VEX_2A (PREFIX_VEX_16 + 1) +#define PREFIX_VEX_2C (PREFIX_VEX_2A + 1) +#define PREFIX_VEX_2D (PREFIX_VEX_2C + 1) +#define PREFIX_VEX_2E (PREFIX_VEX_2D + 1) +#define PREFIX_VEX_2F (PREFIX_VEX_2E + 1) +#define PREFIX_VEX_51 (PREFIX_VEX_2F + 1) +#define PREFIX_VEX_52 (PREFIX_VEX_51 + 1) +#define PREFIX_VEX_53 (PREFIX_VEX_52 + 1) +#define PREFIX_VEX_58 (PREFIX_VEX_53 + 1) +#define PREFIX_VEX_59 (PREFIX_VEX_58 + 1) +#define PREFIX_VEX_5A (PREFIX_VEX_59 + 1) +#define PREFIX_VEX_5B (PREFIX_VEX_5A + 1) +#define PREFIX_VEX_5C (PREFIX_VEX_5B + 1) +#define PREFIX_VEX_5D (PREFIX_VEX_5C + 1) +#define PREFIX_VEX_5E (PREFIX_VEX_5D + 1) +#define PREFIX_VEX_5F (PREFIX_VEX_5E + 1) +#define PREFIX_VEX_60 (PREFIX_VEX_5F + 1) +#define PREFIX_VEX_61 (PREFIX_VEX_60 + 1) +#define PREFIX_VEX_62 (PREFIX_VEX_61 + 1) +#define PREFIX_VEX_63 (PREFIX_VEX_62 + 1) +#define PREFIX_VEX_64 (PREFIX_VEX_63 + 1) +#define PREFIX_VEX_65 (PREFIX_VEX_64 + 1) +#define PREFIX_VEX_66 (PREFIX_VEX_65 + 1) +#define PREFIX_VEX_67 (PREFIX_VEX_66 + 1) +#define PREFIX_VEX_68 (PREFIX_VEX_67 + 1) +#define PREFIX_VEX_69 (PREFIX_VEX_68 + 1) +#define PREFIX_VEX_6A (PREFIX_VEX_69 + 1) +#define PREFIX_VEX_6B (PREFIX_VEX_6A + 1) +#define PREFIX_VEX_6C (PREFIX_VEX_6B + 1) +#define PREFIX_VEX_6D (PREFIX_VEX_6C + 1) +#define PREFIX_VEX_6E (PREFIX_VEX_6D + 1) +#define PREFIX_VEX_6F (PREFIX_VEX_6E + 1) +#define PREFIX_VEX_70 (PREFIX_VEX_6F + 1) +#define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1) +#define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1) +#define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1) +#define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1) +#define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1) +#define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1) +#define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1) +#define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1) +#define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1) +#define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1) +#define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1) +#define PREFIX_VEX_75 (PREFIX_VEX_74 + 1) +#define PREFIX_VEX_76 (PREFIX_VEX_75 + 1) +#define PREFIX_VEX_77 (PREFIX_VEX_76 + 1) +#define PREFIX_VEX_7C (PREFIX_VEX_77 + 1) +#define PREFIX_VEX_7D (PREFIX_VEX_7C + 1) +#define PREFIX_VEX_7E (PREFIX_VEX_7D + 1) +#define PREFIX_VEX_7F (PREFIX_VEX_7E + 1) +#define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1) +#define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1) +#define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1) +#define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1) +#define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1) +#define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1) +#define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1) +#define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1) +#define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1) +#define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1) +#define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1) +#define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1) +#define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1) +#define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1) +#define PREFIX_VEX_DB (PREFIX_VEX_DA + 1) +#define PREFIX_VEX_DC (PREFIX_VEX_DB + 1) +#define PREFIX_VEX_DD (PREFIX_VEX_DC + 1) +#define PREFIX_VEX_DE (PREFIX_VEX_DD + 1) +#define PREFIX_VEX_DF (PREFIX_VEX_DE + 1) +#define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1) +#define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1) +#define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1) +#define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1) +#define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1) +#define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1) +#define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1) +#define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1) +#define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1) +#define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1) +#define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1) +#define PREFIX_VEX_EB (PREFIX_VEX_EA + 1) +#define PREFIX_VEX_EC (PREFIX_VEX_EB + 1) +#define PREFIX_VEX_ED (PREFIX_VEX_EC + 1) +#define PREFIX_VEX_EE (PREFIX_VEX_ED + 1) +#define PREFIX_VEX_EF (PREFIX_VEX_EE + 1) +#define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1) +#define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1) +#define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1) +#define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1) +#define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1) +#define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1) +#define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1) +#define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1) +#define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1) +#define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1) +#define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1) +#define PREFIX_VEX_FB (PREFIX_VEX_FA + 1) +#define PREFIX_VEX_FC (PREFIX_VEX_FB + 1) +#define PREFIX_VEX_FD (PREFIX_VEX_FC + 1) +#define PREFIX_VEX_FE (PREFIX_VEX_FD + 1) +#define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1) +#define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1) +#define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1) +#define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1) +#define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1) +#define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1) +#define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1) +#define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1) +#define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1) +#define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1) +#define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1) +#define PREFIX_VEX_380B (PREFIX_VEX_380A + 1) +#define PREFIX_VEX_380C (PREFIX_VEX_380B + 1) +#define PREFIX_VEX_380D (PREFIX_VEX_380C + 1) +#define PREFIX_VEX_380E (PREFIX_VEX_380D + 1) +#define PREFIX_VEX_380F (PREFIX_VEX_380E + 1) +#define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1) +#define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1) +#define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1) +#define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1) +#define PREFIX_VEX_381C (PREFIX_VEX_381A + 1) +#define PREFIX_VEX_381D (PREFIX_VEX_381C + 1) +#define PREFIX_VEX_381E (PREFIX_VEX_381D + 1) +#define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1) +#define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1) +#define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1) +#define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1) +#define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1) +#define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1) +#define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1) +#define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1) +#define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1) +#define PREFIX_VEX_382B (PREFIX_VEX_382A + 1) +#define PREFIX_VEX_382C (PREFIX_VEX_382B + 1) +#define PREFIX_VEX_382D (PREFIX_VEX_382C + 1) +#define PREFIX_VEX_382E (PREFIX_VEX_382D + 1) +#define PREFIX_VEX_382F (PREFIX_VEX_382E + 1) +#define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1) +#define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1) +#define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1) +#define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1) +#define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1) +#define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1) +#define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1) +#define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1) +#define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1) +#define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1) +#define PREFIX_VEX_383B (PREFIX_VEX_383A + 1) +#define PREFIX_VEX_383C (PREFIX_VEX_383B + 1) +#define PREFIX_VEX_383D (PREFIX_VEX_383C + 1) +#define PREFIX_VEX_383E (PREFIX_VEX_383D + 1) +#define PREFIX_VEX_383F (PREFIX_VEX_383E + 1) +#define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1) +#define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1) +#define PREFIX_VEX_3A04 (PREFIX_VEX_3841 + 1) +#define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1) +#define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1) +#define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1) +#define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1) +#define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1) +#define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1) +#define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1) +#define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1) +#define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1) +#define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1) +#define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1) +#define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1) +#define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1) +#define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1) +#define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1) +#define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1) +#define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1) +#define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1) +#define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1) +#define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1) +#define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1) +#define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1) +#define PREFIX_VEX_3A48 (PREFIX_VEX_3A42 + 1) +#define PREFIX_VEX_3A49 (PREFIX_VEX_3A48 + 1) +#define PREFIX_VEX_3A4A (PREFIX_VEX_3A49 + 1) +#define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1) +#define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1) +#define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1) +#define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1) +#define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1) +#define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1) +#define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1) +#define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1) +#define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1) +#define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1) +#define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1) +#define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1) +#define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1) +#define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1) +#define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1) +#define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1) +#define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1) +#define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1) +#define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1) +#define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1) +#define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1) +#define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1) +#define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1) +#define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1) +#define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1) +#define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1) #define X86_64_06 0 #define X86_64_07 (X86_64_06 + 1) @@ -709,6 +1018,208 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1) #define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1) +#define VEX_0F 0 +#define VEX_0F38 (VEX_0F + 1) +#define VEX_0F3A (VEX_0F38 + 1) + +#define VEX_LEN_10_P_1 0 +#define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1) +#define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1) +#define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1) +#define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1) +#define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1) +#define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1) +#define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1) +#define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1) +#define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1) +#define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1) +#define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1) +#define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1) +#define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1) +#define VEX_LEN_2B_M_0 (VEX_LEN_2A_P_3 + 1) +#define VEX_LEN_2C_P_1 (VEX_LEN_2B_M_0 + 1) +#define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1) +#define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1) +#define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1) +#define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1) +#define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1) +#define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1) +#define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1) +#define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1) +#define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1) +#define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1) +#define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1) +#define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1) +#define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1) +#define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1) +#define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1) +#define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1) +#define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1) +#define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1) +#define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1) +#define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1) +#define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1) +#define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1) +#define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1) +#define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1) +#define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1) +#define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1) +#define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1) +#define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1) +#define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1) +#define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1) +#define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1) +#define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1) +#define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1) +#define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1) +#define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1) +#define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1) +#define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1) +#define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1) +#define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1) +#define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1) +#define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1) +#define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1) +#define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1) +#define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1) +#define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1) +#define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1) +#define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1) +#define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1) +#define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1) +#define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1) +#define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1) +#define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1) +#define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1) +#define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1) +#define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1) +#define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1) +#define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1) +#define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1) +#define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1) +#define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1) +#define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1) +#define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1) +#define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1) +#define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1) +#define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1) +#define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1) +#define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1) +#define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1) +#define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1) +#define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1) +#define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1) +#define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1) +#define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1) +#define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1) +#define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1) +#define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1) +#define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1) +#define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1) +#define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1) +#define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1) +#define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1) +#define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1) +#define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1) +#define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1) +#define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1) +#define VEX_LEN_E7_P_2_M_0 (VEX_LEN_E5_P_2 + 1) +#define VEX_LEN_E8_P_2 (VEX_LEN_E7_P_2_M_0 + 1) +#define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1) +#define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1) +#define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1) +#define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1) +#define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1) +#define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1) +#define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1) +#define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1) +#define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1) +#define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1) +#define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1) +#define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1) +#define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1) +#define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1) +#define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1) +#define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1) +#define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1) +#define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1) +#define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1) +#define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1) +#define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1) +#define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1) +#define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1) +#define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1) +#define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1) +#define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1) +#define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1) +#define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1) +#define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1) +#define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1) +#define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1) +#define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1) +#define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1) +#define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1) +#define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1) +#define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1) +#define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1) +#define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1) +#define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1) +#define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1) +#define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1) +#define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1) +#define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1) +#define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1) +#define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1) +#define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1) +#define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1) +#define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1) +#define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1) +#define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1) +#define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1) +#define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1) +#define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1) +#define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1) +#define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1) +#define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1) +#define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1) +#define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1) +#define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1) +#define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1) +#define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1) +#define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1) +#define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1) +#define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1) +#define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1) +#define VEX_LEN_3A06_P_2 (VEX_LEN_3841_P_2 + 1) +#define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1) +#define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1) +#define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1) +#define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1) +#define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1) +#define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1) +#define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1) +#define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1) +#define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1) +#define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1) +#define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1) +#define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1) +#define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1) +#define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1) +#define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1) +#define VEX_LEN_3A4C_P_2 (VEX_LEN_3A42_P_2 + 1) +#define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1) +#define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1) +#define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1) +#define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1) +#define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1) +#define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1) +#define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1) +#define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1) +#define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1) +#define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1) +#define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1) +#define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1) + typedef void (*op_rtn) (int bytemode, int sizeflag); struct dis386 { @@ -757,6 +1268,8 @@ struct dis386 { '%' => add 1 upper case letter to the macro. 2 upper case letter macros: + "XY" => print 'x' or 'y' if no register operands or suffix_always + is true. 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand or suffix_always is true @@ -1414,6 +1927,17 @@ static struct } modrm; static unsigned char need_modrm; +static struct + { + int register_specifier; + int length; + int prefix; + int w; + } +vex; +static unsigned char need_vex; +static unsigned char need_vex_reg; +static unsigned char vex_i4_done; /* If we are accessing mod/rm/reg without need_modrm set, then the values are stale. Hitting this abort likely indicates that you @@ -1795,6 +2319,50 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0FC7_REG_6) }, { MOD_TABLE (MOD_0FC7_REG_7) }, }, + /* REG_VEX_71 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_71_REG_2) }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_71_REG_4) }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_71_REG_6) }, + { "(bad)", { XX } }, + }, + /* REG_VEX_72 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_72_REG_2) }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_72_REG_4) }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_72_REG_6) }, + { "(bad)", { XX } }, + }, + /* REG_VEX_73 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_73_REG_2) }, + { MOD_TABLE (MOD_VEX_73_REG_3) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_73_REG_6) }, + { MOD_TABLE (MOD_VEX_73_REG_7) }, + }, + /* REG_VEX_AE */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_AE_REG_2) }, + { MOD_TABLE (MOD_VEX_AE_REG_3) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, }; static const struct dis386 prefix_table[][4] = { @@ -2430,6 +2998,46 @@ static const struct dis386 prefix_table[][4] = { { "(bad)", { XX } }, }, + /* PREFIX_0F38DB */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "aesimc", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_0F38DC */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "aesenc", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_0F38DD */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "aesenclast", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_0F38DE */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "aesdec", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_0F38DF */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "aesdeclast", { XM, EXx } }, + { "(bad)", { XX } }, + }, + /* PREFIX_0F38F0 */ { { "(bad)", { XX } }, @@ -2582,6 +3190,14 @@ static const struct dis386 prefix_table[][4] = { { "(bad)", { XX } }, }, + /* PREFIX_0F3A44 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pclmulqdq", { XM, EXx, PCLMUL } }, + { "(bad)", { XX } }, + }, + /* PREFIX_0F3A60 */ { { "(bad)", { XX } }, @@ -2613,6 +3229,1702 @@ static const struct dis386 prefix_table[][4] = { { "pcmpistri", { XM, EXx, Ib } }, { "(bad)", { XX } }, }, + + /* PREFIX_0F3ADF */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "aeskeygenassist", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_10 */ + { + { "vmovups", { XM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_10_P_1) }, + { "vmovupd", { XM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_10_P_3) }, + }, + + /* PREFIX_VEX_11 */ + { + { "vmovups", { EXx, XM } }, + { VEX_LEN_TABLE (VEX_LEN_11_P_1) }, + { "vmovupd", { EXx, XM } }, + { VEX_LEN_TABLE (VEX_LEN_11_P_3) }, + }, + + /* PREFIX_VEX_12 */ + { + { MOD_TABLE (MOD_VEX_12_PREFIX_0) }, + { "vmovsldup", { XM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_12_P_2) }, + { "vmovddup", { XM, EXymmq } }, + }, + + /* PREFIX_VEX_16 */ + { + { MOD_TABLE (MOD_VEX_16_PREFIX_0) }, + { "vmovshdup", { XM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_16_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_2A */ + { + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_2A_P_1) }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_2A_P_3) }, + }, + + /* PREFIX_VEX_2C */ + { + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_2C_P_1) }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_2C_P_3) }, + }, + + /* PREFIX_VEX_2D */ + { + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_2D_P_1) }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_2D_P_3) }, + }, + + /* PREFIX_VEX_2E */ + { + { VEX_LEN_TABLE (VEX_LEN_2E_P_0) }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_2E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_2F */ + { + { VEX_LEN_TABLE (VEX_LEN_2F_P_0) }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_2F_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_51 */ + { + { "vsqrtps", { XM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_51_P_1) }, + { "vsqrtpd", { XM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_51_P_3) }, + }, + + /* PREFIX_VEX_52 */ + { + { "vrsqrtps", { XM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_52_P_1) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_53 */ + { + { "vrcpps", { XM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_53_P_1) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_58 */ + { + { "vaddps", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_58_P_1) }, + { "vaddpd", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_58_P_3) }, + }, + + /* PREFIX_VEX_59 */ + { + { "vmulps", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_59_P_1) }, + { "vmulpd", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_59_P_3) }, + }, + + /* PREFIX_VEX_5A */ + { + { "vcvtps2pd", { XM, EXxmmq } }, + { VEX_LEN_TABLE (VEX_LEN_5A_P_1) }, + { "vcvtpd2ps%XY", { XMM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5A_P_3) }, + }, + + /* PREFIX_VEX_5B */ + { + { "vcvtdq2ps", { XM, EXx } }, + { "vcvttps2dq", { XM, EXx } }, + { "vcvtps2dq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_5C */ + { + { "vsubps", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5C_P_1) }, + { "vsubpd", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5C_P_3) }, + }, + + /* PREFIX_VEX_5D */ + { + { "vminps", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5D_P_1) }, + { "vminpd", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5D_P_3) }, + }, + + /* PREFIX_VEX_5E */ + { + { "vdivps", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5E_P_1) }, + { "vdivpd", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5E_P_3) }, + }, + + /* PREFIX_VEX_5F */ + { + { "vmaxps", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5F_P_1) }, + { "vmaxpd", { XM, Vex, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_5F_P_3) }, + }, + + /* PREFIX_VEX_60 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_60_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_61 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_61_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_62 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_62_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_63 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_63_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_64 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_64_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_65 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_65_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_66 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_66_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_67 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_67_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_68 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_68_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_69 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_69_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_6A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_6A_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_6B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_6B_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_6C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_6C_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_6D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_6D_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_6E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_6E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_6F */ + { + { "(bad)", { XX } }, + { "vmovdqu", { XM, EXx } }, + { "vmovdqa", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_70 */ + { + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_70_P_1) }, + { VEX_LEN_TABLE (VEX_LEN_70_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_70_P_3) }, + }, + + /* PREFIX_VEX_71_REG_2 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_71_REG_4 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_71_REG_6 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_72_REG_2 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_72_REG_4 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_72_REG_6 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_73_REG_2 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_73_REG_3 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_73_REG_6 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_73_REG_7 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_74 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_74_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_75 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_75_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_76 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_76_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_77 */ + { + { "", { VZERO } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_7C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vhaddpd", { XM, Vex, EXx } }, + { "vhaddps", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_7D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vhsubpd", { XM, Vex, EXx } }, + { "vhsubps", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_7E */ + { + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_7E_P_1) }, + { VEX_LEN_TABLE (VEX_LEN_7E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_7F */ + { + { "(bad)", { XX } }, + { "vmovdqu", { EXx, XM } }, + { "vmovdqa", { EXx, XM } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_C2 */ + { + { "vcmpps", { XM, Vex, EXx, VCMP } }, + { VEX_LEN_TABLE (VEX_LEN_C2_P_1) }, + { "vcmppd", { XM, Vex, EXx, VCMP } }, + { VEX_LEN_TABLE (VEX_LEN_C2_P_3) }, + }, + + /* PREFIX_VEX_C4 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_C4_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_C5 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_C5_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D0 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vaddsubpd", { XM, Vex, EXx } }, + { "vaddsubps", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_D1 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D1_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D2 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D2_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D3 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D3_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D4 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D4_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D5 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D5_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D6 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D6_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D7 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_D7_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D8 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D8_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_D9 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D9_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_DA */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_DA_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_DB */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_DB_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_DC */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_DC_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_DD */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_DD_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_DE */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_DE_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_DF */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_DF_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E0 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_E0_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E1 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_E1_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E2 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_E2_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E3 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_E3_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E4 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_E4_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E5 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_E5_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E6 */ + { + { "(bad)", { XX } }, + { "vcvtdq2pd", { XM, EXxmmq } }, + { "vcvttpd2dq%XY", { XMM, EXx } }, + { "vcvtpd2dq%XY", { XMM, EXx } }, + }, + + /* PREFIX_VEX_E7 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_E7_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E8 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_E8_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_E9 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_E9_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_EA */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_EA_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_EB */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_EB_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_EC */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_EC_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_ED */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_ED_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_EE */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_EE_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_EF */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_EF_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F0 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_F0_PREFIX_3) }, + }, + + /* PREFIX_VEX_F1 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F1_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F2 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F2_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F3 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F3_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F4 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F4_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F5 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F5_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F6 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F6_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F7 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F7_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F8 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F8_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_F9 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_F9_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_FA */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_FA_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_FB */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_FB_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_FC */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_FC_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_FD */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_FD_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_FE */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_FE_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3800 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3800_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3801 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3801_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3802 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3802_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3803 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3803_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3804 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3804_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3805 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3805_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3806 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3806_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3807 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3807_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3808 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3808_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3809 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3809_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_380A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_380A_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_380B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_380B_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_380C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vpermilps", { XM, Vex, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_380D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vpermilpd", { XM, Vex, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_380E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vtestps", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_380F */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vtestpd", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3817 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vptest", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3818 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_3818_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3819 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_3819_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_381A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_381A_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_381C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_381C_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_381D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_381D_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_381E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_381E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3820 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3820_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3821 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3821_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3822 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3822_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3823 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3823_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3824 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3824_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3825 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3825_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3828 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3828_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3829 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3829_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_382A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_382A_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_382B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_382B_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_382C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_382C_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_382D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_382D_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_382E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_382E_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_382F */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { MOD_TABLE (MOD_VEX_382F_PREFIX_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3830 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3830_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3831 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3831_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3832 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3832_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3833 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3833_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3834 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3834_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3835 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3835_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3837 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3837_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3838 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3838_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3839 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3839_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_383A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_383A_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_383B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_383B_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_383C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_383C_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_383D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_383D_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_383E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_383E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_383F */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_383F_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3840 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3840_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3841 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3841_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A04 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vpermilps", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A05 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vpermilpd", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A06 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A08 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vroundps", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A09 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vroundpd", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vblendps", { XM, Vex, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vblendpd", { XM, Vex, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0F */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A14 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A15 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A16 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A17 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A18 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A19 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A20 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A21 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A22 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A40 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vdpps", { XM, Vex, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A41 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A42 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A48 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vpermil2ps", { XMVexW, Vex, EXVexW, EXVexW, VPERMIL2 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A49 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vpermil2pd", { XMVexW, Vex, EXVexW, EXVexW, VPERMIL2 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A4A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A4B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A4C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A5C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A5D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A5E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A5F */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A60 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A61 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A62 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A63 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A68 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A69 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A6A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A6B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A6C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A6D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A6E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A6F */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A78 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A79 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A7A */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A7B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A7C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A7D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A7E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A7F */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) }, + { "(bad)", { XX } }, + }, }; static const struct dis386 x86_64_table[][2] = { @@ -2727,13 +5039,13 @@ static const struct dis386 x86_64_table[][2] = { /* X86_64_C4 */ { { MOD_TABLE (MOD_C4_32BIT) }, - { "(bad)", { XX } }, + { VEX_C4_TABLE (VEX_0F) }, }, /* X86_64_C5 */ { { MOD_TABLE (MOD_C5_32BIT) }, - { "(bad)", { XX } }, + { VEX_C5_TABLE (VEX_0F) }, }, /* X86_64_CE */ @@ -3617,11 +5929,11 @@ static const struct dis386 three_byte_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_0F38DB) }, + { PREFIX_TABLE (PREFIX_0F38DC) }, + { PREFIX_TABLE (PREFIX_0F38DD) }, + { PREFIX_TABLE (PREFIX_0F38DE) }, + { PREFIX_TABLE (PREFIX_0F38DF) }, /* e0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -3738,7 +6050,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F3A41) }, { PREFIX_TABLE (PREFIX_0F3A42) }, { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_0F3A44) }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -3912,7 +6224,7 @@ static const struct dis386 three_byte_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_0F3ADF) }, /* e0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -4531,7 +6843,2067 @@ static const struct dis386 three_byte_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - } + }, +}; + +static const struct dis386 vex_table[][256] = { + /* VEX_0F */ + { + /* 00 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 08 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 10 */ + { PREFIX_TABLE (PREFIX_VEX_10) }, + { PREFIX_TABLE (PREFIX_VEX_11) }, + { PREFIX_TABLE (PREFIX_VEX_12) }, + { MOD_TABLE (MOD_VEX_13) }, + { "vunpcklpX", { XM, Vex, EXx } }, + { "vunpckhpX", { XM, Vex, EXx } }, + { PREFIX_TABLE (PREFIX_VEX_16) }, + { MOD_TABLE (MOD_VEX_17) }, + /* 18 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 20 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 28 */ + { "vmovapX", { XM, EXx } }, + { "vmovapX", { EXx, XM } }, + { PREFIX_TABLE (PREFIX_VEX_2A) }, + { MOD_TABLE (MOD_VEX_2B) }, + { PREFIX_TABLE (PREFIX_VEX_2C) }, + { PREFIX_TABLE (PREFIX_VEX_2D) }, + { PREFIX_TABLE (PREFIX_VEX_2E) }, + { PREFIX_TABLE (PREFIX_VEX_2F) }, + /* 30 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 38 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 40 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 48 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 50 */ + { MOD_TABLE (MOD_VEX_51) }, + { PREFIX_TABLE (PREFIX_VEX_51) }, + { PREFIX_TABLE (PREFIX_VEX_52) }, + { PREFIX_TABLE (PREFIX_VEX_53) }, + { "vandpX", { XM, Vex, EXx } }, + { "vandnpX", { XM, Vex, EXx } }, + { "vorpX", { XM, Vex, EXx } }, + { "vxorpX", { XM, Vex, EXx } }, + /* 58 */ + { PREFIX_TABLE (PREFIX_VEX_58) }, + { PREFIX_TABLE (PREFIX_VEX_59) }, + { PREFIX_TABLE (PREFIX_VEX_5A) }, + { PREFIX_TABLE (PREFIX_VEX_5B) }, + { PREFIX_TABLE (PREFIX_VEX_5C) }, + { PREFIX_TABLE (PREFIX_VEX_5D) }, + { PREFIX_TABLE (PREFIX_VEX_5E) }, + { PREFIX_TABLE (PREFIX_VEX_5F) }, + /* 60 */ + { PREFIX_TABLE (PREFIX_VEX_60) }, + { PREFIX_TABLE (PREFIX_VEX_61) }, + { PREFIX_TABLE (PREFIX_VEX_62) }, + { PREFIX_TABLE (PREFIX_VEX_63) }, + { PREFIX_TABLE (PREFIX_VEX_64) }, + { PREFIX_TABLE (PREFIX_VEX_65) }, + { PREFIX_TABLE (PREFIX_VEX_66) }, + { PREFIX_TABLE (PREFIX_VEX_67) }, + /* 68 */ + { PREFIX_TABLE (PREFIX_VEX_68) }, + { PREFIX_TABLE (PREFIX_VEX_69) }, + { PREFIX_TABLE (PREFIX_VEX_6A) }, + { PREFIX_TABLE (PREFIX_VEX_6B) }, + { PREFIX_TABLE (PREFIX_VEX_6C) }, + { PREFIX_TABLE (PREFIX_VEX_6D) }, + { PREFIX_TABLE (PREFIX_VEX_6E) }, + { PREFIX_TABLE (PREFIX_VEX_6F) }, + /* 70 */ + { PREFIX_TABLE (PREFIX_VEX_70) }, + { REG_TABLE (REG_VEX_71) }, + { REG_TABLE (REG_VEX_72) }, + { REG_TABLE (REG_VEX_73) }, + { PREFIX_TABLE (PREFIX_VEX_74) }, + { PREFIX_TABLE (PREFIX_VEX_75) }, + { PREFIX_TABLE (PREFIX_VEX_76) }, + { PREFIX_TABLE (PREFIX_VEX_77) }, + /* 78 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_7C) }, + { PREFIX_TABLE (PREFIX_VEX_7D) }, + { PREFIX_TABLE (PREFIX_VEX_7E) }, + { PREFIX_TABLE (PREFIX_VEX_7F) }, + /* 80 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 88 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 90 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 98 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { REG_TABLE (REG_VEX_AE) }, + { "(bad)", { XX } }, + /* b0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_C2) }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_C4) }, + { PREFIX_TABLE (PREFIX_VEX_C5) }, + { "vshufpX", { XM, Vex, EXx, Ib } }, + { "(bad)", { XX } }, + /* c8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d0 */ + { PREFIX_TABLE (PREFIX_VEX_D0) }, + { PREFIX_TABLE (PREFIX_VEX_D1) }, + { PREFIX_TABLE (PREFIX_VEX_D2) }, + { PREFIX_TABLE (PREFIX_VEX_D3) }, + { PREFIX_TABLE (PREFIX_VEX_D4) }, + { PREFIX_TABLE (PREFIX_VEX_D5) }, + { PREFIX_TABLE (PREFIX_VEX_D6) }, + { PREFIX_TABLE (PREFIX_VEX_D7) }, + /* d8 */ + { PREFIX_TABLE (PREFIX_VEX_D8) }, + { PREFIX_TABLE (PREFIX_VEX_D9) }, + { PREFIX_TABLE (PREFIX_VEX_DA) }, + { PREFIX_TABLE (PREFIX_VEX_DB) }, + { PREFIX_TABLE (PREFIX_VEX_DC) }, + { PREFIX_TABLE (PREFIX_VEX_DD) }, + { PREFIX_TABLE (PREFIX_VEX_DE) }, + { PREFIX_TABLE (PREFIX_VEX_DF) }, + /* e0 */ + { PREFIX_TABLE (PREFIX_VEX_E0) }, + { PREFIX_TABLE (PREFIX_VEX_E1) }, + { PREFIX_TABLE (PREFIX_VEX_E2) }, + { PREFIX_TABLE (PREFIX_VEX_E3) }, + { PREFIX_TABLE (PREFIX_VEX_E4) }, + { PREFIX_TABLE (PREFIX_VEX_E5) }, + { PREFIX_TABLE (PREFIX_VEX_E6) }, + { PREFIX_TABLE (PREFIX_VEX_E7) }, + /* e8 */ + { PREFIX_TABLE (PREFIX_VEX_E8) }, + { PREFIX_TABLE (PREFIX_VEX_E9) }, + { PREFIX_TABLE (PREFIX_VEX_EA) }, + { PREFIX_TABLE (PREFIX_VEX_EB) }, + { PREFIX_TABLE (PREFIX_VEX_EC) }, + { PREFIX_TABLE (PREFIX_VEX_ED) }, + { PREFIX_TABLE (PREFIX_VEX_EE) }, + { PREFIX_TABLE (PREFIX_VEX_EF) }, + /* f0 */ + { PREFIX_TABLE (PREFIX_VEX_F0) }, + { PREFIX_TABLE (PREFIX_VEX_F1) }, + { PREFIX_TABLE (PREFIX_VEX_F2) }, + { PREFIX_TABLE (PREFIX_VEX_F3) }, + { PREFIX_TABLE (PREFIX_VEX_F4) }, + { PREFIX_TABLE (PREFIX_VEX_F5) }, + { PREFIX_TABLE (PREFIX_VEX_F6) }, + { PREFIX_TABLE (PREFIX_VEX_F7) }, + /* f8 */ + { PREFIX_TABLE (PREFIX_VEX_F8) }, + { PREFIX_TABLE (PREFIX_VEX_F9) }, + { PREFIX_TABLE (PREFIX_VEX_FA) }, + { PREFIX_TABLE (PREFIX_VEX_FB) }, + { PREFIX_TABLE (PREFIX_VEX_FC) }, + { PREFIX_TABLE (PREFIX_VEX_FD) }, + { PREFIX_TABLE (PREFIX_VEX_FE) }, + { "(bad)", { XX } }, + }, + /* VEX_0F38 */ + { + /* 00 */ + { PREFIX_TABLE (PREFIX_VEX_3800) }, + { PREFIX_TABLE (PREFIX_VEX_3801) }, + { PREFIX_TABLE (PREFIX_VEX_3802) }, + { PREFIX_TABLE (PREFIX_VEX_3803) }, + { PREFIX_TABLE (PREFIX_VEX_3804) }, + { PREFIX_TABLE (PREFIX_VEX_3805) }, + { PREFIX_TABLE (PREFIX_VEX_3806) }, + { PREFIX_TABLE (PREFIX_VEX_3807) }, + /* 08 */ + { PREFIX_TABLE (PREFIX_VEX_3808) }, + { PREFIX_TABLE (PREFIX_VEX_3809) }, + { PREFIX_TABLE (PREFIX_VEX_380A) }, + { PREFIX_TABLE (PREFIX_VEX_380B) }, + { PREFIX_TABLE (PREFIX_VEX_380C) }, + { PREFIX_TABLE (PREFIX_VEX_380D) }, + { PREFIX_TABLE (PREFIX_VEX_380E) }, + { PREFIX_TABLE (PREFIX_VEX_380F) }, + /* 10 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_3817) }, + /* 18 */ + { PREFIX_TABLE (PREFIX_VEX_3818) }, + { PREFIX_TABLE (PREFIX_VEX_3819) }, + { PREFIX_TABLE (PREFIX_VEX_381A) }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_381C) }, + { PREFIX_TABLE (PREFIX_VEX_381D) }, + { PREFIX_TABLE (PREFIX_VEX_381E) }, + { "(bad)", { XX } }, + /* 20 */ + { PREFIX_TABLE (PREFIX_VEX_3820) }, + { PREFIX_TABLE (PREFIX_VEX_3821) }, + { PREFIX_TABLE (PREFIX_VEX_3822) }, + { PREFIX_TABLE (PREFIX_VEX_3823) }, + { PREFIX_TABLE (PREFIX_VEX_3824) }, + { PREFIX_TABLE (PREFIX_VEX_3825) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 28 */ + { PREFIX_TABLE (PREFIX_VEX_3828) }, + { PREFIX_TABLE (PREFIX_VEX_3829) }, + { PREFIX_TABLE (PREFIX_VEX_382A) }, + { PREFIX_TABLE (PREFIX_VEX_382B) }, + { PREFIX_TABLE (PREFIX_VEX_382C) }, + { PREFIX_TABLE (PREFIX_VEX_382D) }, + { PREFIX_TABLE (PREFIX_VEX_382E) }, + { PREFIX_TABLE (PREFIX_VEX_382F) }, + /* 30 */ + { PREFIX_TABLE (PREFIX_VEX_3830) }, + { PREFIX_TABLE (PREFIX_VEX_3831) }, + { PREFIX_TABLE (PREFIX_VEX_3832) }, + { PREFIX_TABLE (PREFIX_VEX_3833) }, + { PREFIX_TABLE (PREFIX_VEX_3834) }, + { PREFIX_TABLE (PREFIX_VEX_3835) }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_3837) }, + /* 38 */ + { PREFIX_TABLE (PREFIX_VEX_3838) }, + { PREFIX_TABLE (PREFIX_VEX_3839) }, + { PREFIX_TABLE (PREFIX_VEX_383A) }, + { PREFIX_TABLE (PREFIX_VEX_383B) }, + { PREFIX_TABLE (PREFIX_VEX_383C) }, + { PREFIX_TABLE (PREFIX_VEX_383D) }, + { PREFIX_TABLE (PREFIX_VEX_383E) }, + { PREFIX_TABLE (PREFIX_VEX_383F) }, + /* 40 */ + { PREFIX_TABLE (PREFIX_VEX_3840) }, + { PREFIX_TABLE (PREFIX_VEX_3841) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 48 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 50 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 58 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 60 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 68 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 70 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 78 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 80 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 88 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 90 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 98 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* f0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* f8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, + /* VEX_0F3A */ + { + /* 00 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_3A04) }, + { PREFIX_TABLE (PREFIX_VEX_3A05) }, + { PREFIX_TABLE (PREFIX_VEX_3A06) }, + { "(bad)", { XX } }, + /* 08 */ + { PREFIX_TABLE (PREFIX_VEX_3A08) }, + { PREFIX_TABLE (PREFIX_VEX_3A09) }, + { PREFIX_TABLE (PREFIX_VEX_3A0A) }, + { PREFIX_TABLE (PREFIX_VEX_3A0B) }, + { PREFIX_TABLE (PREFIX_VEX_3A0C) }, + { PREFIX_TABLE (PREFIX_VEX_3A0D) }, + { PREFIX_TABLE (PREFIX_VEX_3A0E) }, + { PREFIX_TABLE (PREFIX_VEX_3A0F) }, + /* 10 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_3A14) }, + { PREFIX_TABLE (PREFIX_VEX_3A15) }, + { PREFIX_TABLE (PREFIX_VEX_3A16) }, + { PREFIX_TABLE (PREFIX_VEX_3A17) }, + /* 18 */ + { PREFIX_TABLE (PREFIX_VEX_3A18) }, + { PREFIX_TABLE (PREFIX_VEX_3A19) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 20 */ + { PREFIX_TABLE (PREFIX_VEX_3A20) }, + { PREFIX_TABLE (PREFIX_VEX_3A21) }, + { PREFIX_TABLE (PREFIX_VEX_3A22) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 28 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 30 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 38 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 40 */ + { PREFIX_TABLE (PREFIX_VEX_3A40) }, + { PREFIX_TABLE (PREFIX_VEX_3A41) }, + { PREFIX_TABLE (PREFIX_VEX_3A42) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 48 */ + { PREFIX_TABLE (PREFIX_VEX_3A48) }, + { PREFIX_TABLE (PREFIX_VEX_3A49) }, + { PREFIX_TABLE (PREFIX_VEX_3A4A) }, + { PREFIX_TABLE (PREFIX_VEX_3A4B) }, + { PREFIX_TABLE (PREFIX_VEX_3A4C) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 50 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 58 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_3A5C) }, + { PREFIX_TABLE (PREFIX_VEX_3A5D) }, + { PREFIX_TABLE (PREFIX_VEX_3A5E) }, + { PREFIX_TABLE (PREFIX_VEX_3A5F) }, + /* 60 */ + { PREFIX_TABLE (PREFIX_VEX_3A60) }, + { PREFIX_TABLE (PREFIX_VEX_3A61) }, + { PREFIX_TABLE (PREFIX_VEX_3A62) }, + { PREFIX_TABLE (PREFIX_VEX_3A63) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 68 */ + { PREFIX_TABLE (PREFIX_VEX_3A68) }, + { PREFIX_TABLE (PREFIX_VEX_3A69) }, + { PREFIX_TABLE (PREFIX_VEX_3A6A) }, + { PREFIX_TABLE (PREFIX_VEX_3A6B) }, + { PREFIX_TABLE (PREFIX_VEX_3A6C) }, + { PREFIX_TABLE (PREFIX_VEX_3A6D) }, + { PREFIX_TABLE (PREFIX_VEX_3A6E) }, + { PREFIX_TABLE (PREFIX_VEX_3A6F) }, + /* 70 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 78 */ + { PREFIX_TABLE (PREFIX_VEX_3A78) }, + { PREFIX_TABLE (PREFIX_VEX_3A79) }, + { PREFIX_TABLE (PREFIX_VEX_3A7A) }, + { PREFIX_TABLE (PREFIX_VEX_3A7B) }, + { PREFIX_TABLE (PREFIX_VEX_3A7C) }, + { PREFIX_TABLE (PREFIX_VEX_3A7D) }, + { PREFIX_TABLE (PREFIX_VEX_3A7E) }, + { PREFIX_TABLE (PREFIX_VEX_3A7F) }, + /* 80 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 88 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 90 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 98 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* f0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* f8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, +}; + +static const struct dis386 vex_len_table[][2] = { + /* VEX_LEN_10_P_1 */ + { + { "vmovss", { XMVex, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_10_P_3 */ + { + { "vmovsd", { XMVex, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_11_P_1 */ + { + { "vmovss", { EXdVex, Vex128, XM } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_11_P_3 */ + { + { "vmovsd", { EXqVex, Vex128, XM } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_12_P_0_M_0 */ + { + { "vmovlps", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_12_P_0_M_1 */ + { + { "vmovhlps", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_12_P_2 */ + { + { "vmovlpd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_13_M_0 */ + { + { "vmovlpX", { EXq, XM } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_16_P_0_M_0 */ + { + { "vmovhps", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_16_P_0_M_1 */ + { + { "vmovlhps", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_16_P_2 */ + { + { "vmovhpd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_17_M_0 */ + { + { "vmovhpX", { EXq, XM } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2A_P_1 */ + { + { "vcvtsi2ss%LQ", { XM, Vex128, Ev } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2A_P_3 */ + { + { "vcvtsi2sd%LQ", { XM, Vex128, Ev } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2B_M_0 */ + { + { "vmovntpX", { Mx, XM } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2C_P_1 */ + { + { "vcvttss2siY", { Gv, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2C_P_3 */ + { + { "vcvttsd2siY", { Gv, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2D_P_1 */ + { + { "vcvtss2siY", { Gv, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2D_P_3 */ + { + { "vcvtsd2siY", { Gv, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2E_P_0 */ + { + { "vucomiss", { XM, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2E_P_2 */ + { + { "vucomisd", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2F_P_0 */ + { + { "vcomiss", { XM, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_2F_P_2 */ + { + { "vcomisd", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_51_P_1 */ + { + { "vsqrtss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_51_P_3 */ + { + { "vsqrtsd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_52_P_1 */ + { + { "vrsqrtss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_53_P_1 */ + { + { "vrcpss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_58_P_1 */ + { + { "vaddss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_58_P_3 */ + { + { "vaddsd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_59_P_1 */ + { + { "vmulss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_59_P_3 */ + { + { "vmulsd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5A_P_1 */ + { + { "vcvtss2sd", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5A_P_3 */ + { + { "vcvtsd2ss", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5C_P_1 */ + { + { "vsubss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5C_P_3 */ + { + { "vsubsd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5D_P_1 */ + { + { "vminss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5D_P_3 */ + { + { "vminsd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5E_P_1 */ + { + { "vdivss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5E_P_3 */ + { + { "vdivsd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5F_P_1 */ + { + { "vmaxss", { XM, Vex128, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_5F_P_3 */ + { + { "vmaxsd", { XM, Vex128, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_60_P_2 */ + { + { "vpunpcklbw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_61_P_2 */ + { + { "vpunpcklwd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_62_P_2 */ + { + { "vpunpckldq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_63_P_2 */ + { + { "vpacksswb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_64_P_2 */ + { + { "vpcmpgtb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_65_P_2 */ + { + { "vpcmpgtw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_66_P_2 */ + { + { "vpcmpgtd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_67_P_2 */ + { + { "vpackuswb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_68_P_2 */ + { + { "vpunpckhbw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_69_P_2 */ + { + { "vpunpckhwd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_6A_P_2 */ + { + { "vpunpckhdq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_6B_P_2 */ + { + { "vpackssdw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_6C_P_2 */ + { + { "vpunpcklqdq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_6D_P_2 */ + { + { "vpunpckhqdq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_6E_P_2 */ + { + { "vmovK", { XM, Edq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_70_P_1 */ + { + { "vpshufhw", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_70_P_2 */ + { + { "vpshufd", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_70_P_3 */ + { + { "vpshuflw", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_71_R_2_P_2 */ + { + { "vpsrlw", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_71_R_4_P_2 */ + { + { "vpsraw", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_71_R_6_P_2 */ + { + { "vpsllw", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_72_R_2_P_2 */ + { + { "vpsrld", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_72_R_4_P_2 */ + { + { "vpsrad", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_72_R_6_P_2 */ + { + { "vpslld", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_73_R_2_P_2 */ + { + { "vpsrlq", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_73_R_3_P_2 */ + { + { "vpsrldq", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_73_R_6_P_2 */ + { + { "vpsllq", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_73_R_7_P_2 */ + { + { "vpslldq", { Vex128, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_74_P_2 */ + { + { "vpcmpeqb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_75_P_2 */ + { + { "vpcmpeqw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_76_P_2 */ + { + { "vpcmpeqd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_7E_P_1 */ + { + { "vmovq", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_7E_P_2 */ + { + { "vmovK", { Edq, XM } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_AE_R_2_M0 */ + { + { "vldmxcsr", { Md } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_AE_R_3_M0 */ + { + { "vstmxcsr", { Md } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_C2_P_1 */ + { + { "vcmpss", { XM, Vex128, EXd, VCMP } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_C2_P_3 */ + { + { "vcmpsd", { XM, Vex128, EXq, VCMP } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_C4_P_2 */ + { + { "vpinsrw", { XM, Vex128, Edqw, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_C5_P_2 */ + { + { "vpextrw", { Gdq, XS, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D1_P_2 */ + { + { "vpsrlw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D2_P_2 */ + { + { "vpsrld", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D3_P_2 */ + { + { "vpsrlq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D4_P_2 */ + { + { "vpaddq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D5_P_2 */ + { + { "vpmullw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D6_P_2 */ + { + { "vmovq", { EXq, XM } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D7_P_2_M_1 */ + { + { "vpmovmskb", { Gdq, XS } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D8_P_2 */ + { + { "vpsubusb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_D9_P_2 */ + { + { "vpsubusw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_DA_P_2 */ + { + { "vpminub", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_DB_P_2 */ + { + { "vpand", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_DC_P_2 */ + { + { "vpaddusb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_DD_P_2 */ + { + { "vpaddusw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_DE_P_2 */ + { + { "vpmaxub", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_DF_P_2 */ + { + { "vpandn", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E0_P_2 */ + { + { "vpavgb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E1_P_2 */ + { + { "vpsraw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E2_P_2 */ + { + { "vpsrad", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E3_P_2 */ + { + { "vpavgw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E4_P_2 */ + { + { "vpmulhuw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E5_P_2 */ + { + { "vpmulhw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E7_P_2_M_0 */ + { + { "vmovntdq", { Mx, XM } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E8_P_2 */ + { + { "vpsubsb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_E9_P_2 */ + { + { "vpsubsw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_EA_P_2 */ + { + { "vpminsw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_EB_P_2 */ + { + { "vpor", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_EC_P_2 */ + { + { "vpaddsb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_ED_P_2 */ + { + { "vpaddsw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_EE_P_2 */ + { + { "vpmaxsw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_EF_P_2 */ + { + { "vpxor", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F1_P_2 */ + { + { "vpsllw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F2_P_2 */ + { + { "vpslld", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F3_P_2 */ + { + { "vpsllq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F4_P_2 */ + { + { "vpmuludq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F5_P_2 */ + { + { "vpmaddwd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F6_P_2 */ + { + { "vpsadbw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F7_P_2 */ + { + { "vmaskmovdqu", { XM, XS } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F8_P_2 */ + { + { "vpsubb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_F9_P_2 */ + { + { "vpsubw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_FA_P_2 */ + { + { "vpsubd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_FB_P_2 */ + { + { "vpsubq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_FC_P_2 */ + { + { "vpaddb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_FD_P_2 */ + { + { "vpaddw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_FE_P_2 */ + { + { "vpaddd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3800_P_2 */ + { + { "vpshufb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3801_P_2 */ + { + { "vphaddw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3802_P_2 */ + { + { "vphaddd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3803_P_2 */ + { + { "vphaddsw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3804_P_2 */ + { + { "vpmaddubsw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3805_P_2 */ + { + { "vphsubw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3806_P_2 */ + { + { "vphsubd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3807_P_2 */ + { + { "vphsubsw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3808_P_2 */ + { + { "vpsignb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3809_P_2 */ + { + { "vpsignw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_380A_P_2 */ + { + { "vpsignd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_380B_P_2 */ + { + { "vpmulhrsw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3819_P_2_M_0 */ + { + { "(bad)", { XX } }, + { "vbroadcastsd", { XM, Mq } }, + }, + + /* VEX_LEN_381A_P_2_M_0 */ + { + { "(bad)", { XX } }, + { "vbroadcastf128", { XM, Mxmm } }, + }, + + /* VEX_LEN_381C_P_2 */ + { + { "vpabsb", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_381D_P_2 */ + { + { "vpabsw", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_381E_P_2 */ + { + { "vpabsd", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3820_P_2 */ + { + { "vpmovsxbw", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3821_P_2 */ + { + { "vpmovsxbd", { XM, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3822_P_2 */ + { + { "vpmovsxbq", { XM, EXw } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3823_P_2 */ + { + { "vpmovsxwd", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3824_P_2 */ + { + { "vpmovsxwq", { XM, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3825_P_2 */ + { + { "vpmovsxdq", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3828_P_2 */ + { + { "vpmuldq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3829_P_2 */ + { + { "vpcmpeqq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_382A_P_2_M_0 */ + { + { "vmovntdqa", { XM, Mx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_382B_P_2 */ + { + { "vpackusdw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3830_P_2 */ + { + { "vpmovzxbw", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3831_P_2 */ + { + { "vpmovzxbd", { XM, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3832_P_2 */ + { + { "vpmovzxbq", { XM, EXw } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3833_P_2 */ + { + { "vpmovzxwd", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3834_P_2 */ + { + { "vpmovzxwq", { XM, EXd } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3835_P_2 */ + { + { "vpmovzxdq", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3837_P_2 */ + { + { "vpcmpgtq", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3838_P_2 */ + { + { "vpminsb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3839_P_2 */ + { + { "vpminsd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_383A_P_2 */ + { + { "vpminuw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_383B_P_2 */ + { + { "vpminud", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_383C_P_2 */ + { + { "vpmaxsb", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_383D_P_2 */ + { + { "vpmaxsd", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_383E_P_2 */ + { + { "vpmaxuw", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_383F_P_2 */ + { + { "vpmaxud", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3840_P_2 */ + { + { "vpmulld", { XM, Vex128, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3841_P_2 */ + { + { "vphminposuw", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A06_P_2 */ + { + { "(bad)", { XX } }, + { "vperm2f128", { XM, Vex256, EXx, Ib } }, + }, + + /* VEX_LEN_3A0A_P_2 */ + { + { "vroundss", { XM, Vex128, EXd, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A0B_P_2 */ + { + { "vroundsd", { XM, Vex128, EXq, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A0E_P_2 */ + { + { "vpblendw", { XM, Vex128, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A0F_P_2 */ + { + { "vpalignr", { XM, Vex128, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A14_P_2 */ + { + { "vpextrb", { Edqb, XM, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A15_P_2 */ + { + { "vpextrw", { Edqw, XM, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A16_P_2 */ + { + { "vpextrK", { Edq, XM, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A17_P_2 */ + { + { "vextractps", { Edqd, XM, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A18_P_2 */ + { + { "(bad)", { XX } }, + { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, + }, + + /* VEX_LEN_3A19_P_2 */ + { + { "(bad)", { XX } }, + { "vextractf128", { EXxmm, XM, Ib } }, + }, + + /* VEX_LEN_3A20_P_2 */ + { + { "vpinsrb", { XM, Vex128, Edqb, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A21_P_2 */ + { + { "vinsertps", { XM, Vex128, EXd, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A22_P_2 */ + { + { "vpinsrK", { XM, Vex128, Edq, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A41_P_2 */ + { + { "vdppd", { XM, Vex128, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A42_P_2 */ + { + { "vmpsadbw", { XM, Vex128, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A4C_P_2 */ + { + { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A60_P_2 */ + { + { "vpcmpestrm", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A61_P_2 */ + { + { "vpcmpestri", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A62_P_2 */ + { + { "vpcmpistrm", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A63_P_2 */ + { + { "vpcmpistri", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A6A_P_2 */ + { + { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A6B_P_2 */ + { + { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A6E_P_2 */ + { + { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A6F_P_2 */ + { + { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A7A_P_2 */ + { + { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A7B_P_2 */ + { + { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A7E_P_2 */ + { + { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + { "(bad)", { XX } }, + }, + + /* VEX_LEN_3A7F_P_2 */ + { + { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + { "(bad)", { XX } }, + }, }; static const struct dis386 mod_table[][2] = { @@ -4742,7 +9114,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FAE_REG_6 */ - { "(bad)", { XX } }, + { "xsaveopt", { M } }, { RM_TABLE (RM_0FAE_REG_6) }, }, { @@ -4803,11 +9175,156 @@ static const struct dis386 mod_table[][2] = { { /* MOD_C4_32BIT */ { "lesS", { Gv, Mp } }, - { "(bad)", { XX } }, + { VEX_C4_TABLE (VEX_0F) }, }, { /* MOD_C5_32BIT */ { "ldsS", { Gv, Mp } }, + { VEX_C5_TABLE (VEX_0F) }, + }, + { + /* MOD_VEX_12_PREFIX_0 */ + { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) }, + { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) }, + }, + { + /* MOD_VEX_13 */ + { VEX_LEN_TABLE (VEX_LEN_13_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_16_PREFIX_0 */ + { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) }, + { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) }, + }, + { + /* MOD_VEX_17 */ + { VEX_LEN_TABLE (VEX_LEN_17_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_2B */ + { VEX_LEN_TABLE (VEX_LEN_2B_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_51 */ + { "(bad)", { XX } }, + { "vmovmskpX", { Gdq, XS } }, + }, + { + /* MOD_VEX_71_REG_2 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_71_REG_2) }, + }, + { + /* MOD_VEX_71_REG_4 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_71_REG_4) }, + }, + { + /* MOD_VEX_71_REG_6 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_71_REG_6) }, + }, + { + /* MOD_VEX_72_REG_2 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_72_REG_2) }, + }, + { + /* MOD_VEX_72_REG_4 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_72_REG_4) }, + }, + { + /* MOD_VEX_72_REG_6 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_72_REG_6) }, + }, + { + /* MOD_VEX_73_REG_2 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_73_REG_2) }, + }, + { + /* MOD_VEX_73_REG_3 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_73_REG_3) }, + }, + { + /* MOD_VEX_73_REG_6 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_73_REG_6) }, + }, + { + /* MOD_VEX_73_REG_7 */ + { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_73_REG_7) }, + }, + { + /* MOD_VEX_AE_REG_2 */ + { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_AE_REG_3 */ + { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_D7_PREFIX_2 */ + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) }, + }, + { + /* MOD_VEX_E7_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_F0_PREFIX_3 */ + { "vlddqu", { XM, M } }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_3818_PREFIX_2 */ + { "vbroadcastss", { XM, Md } }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_3819_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_381A_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_382A_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_382C_PREFIX_2 */ + { "vmaskmovps", { XM, Vex, Mx } }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_382D_PREFIX_2 */ + { "vmaskmovpd", { XM, Vex, Mx } }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_382E_PREFIX_2 */ + { "vmaskmovps", { Mx, Vex, XM } }, + { "(bad)", { XX } }, + }, + { + /* MOD_VEX_382F_PREFIX_2 */ + { "vmaskmovpd", { Mx, Vex, XM } }, { "(bad)", { XX } }, }, }; @@ -4910,6 +9427,8 @@ ckprefix (void) { int newrex; rex = 0; + rex_original = 0; + rex_ignored = 0; prefixes = 0; used_prefixes = 0; rex_used = 0; @@ -4996,6 +9515,7 @@ ckprefix (void) return; } rex = newrex; + rex_original = rex; codep++; } } @@ -5157,7 +9677,7 @@ with the -M switch (multiple options should be separated by commas):\n")); static const struct dis386 * get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) { - int index; + int index, vex_table_index; if (dp->name != NULL) return dp; @@ -5178,30 +9698,55 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) break; case USE_PREFIX_TABLE: - index = 0; - used_prefixes |= (prefixes & PREFIX_REPZ); - if (prefixes & PREFIX_REPZ) + if (need_vex) { - index = 1; - repz_prefix = NULL; + /* The prefix in VEX is implicit. */ + switch (vex.prefix) + { + case 0: + index = 0; + break; + case REPE_PREFIX_OPCODE: + index = 1; + break; + case DATA_PREFIX_OPCODE: + index = 2; + break; + case REPNE_PREFIX_OPCODE: + index = 3; + break; + default: + abort (); + break; + } } - else + else { - /* We should check PREFIX_REPNZ and PREFIX_REPZ before - PREFIX_DATA. */ - used_prefixes |= (prefixes & PREFIX_REPNZ); - if (prefixes & PREFIX_REPNZ) + index = 0; + used_prefixes |= (prefixes & PREFIX_REPZ); + if (prefixes & PREFIX_REPZ) { - index = 3; - repnz_prefix = NULL; + index = 1; + repz_prefix = NULL; } else { - used_prefixes |= (prefixes & PREFIX_DATA); - if (prefixes & PREFIX_DATA) + /* We should check PREFIX_REPNZ and PREFIX_REPZ before + PREFIX_DATA. */ + used_prefixes |= (prefixes & PREFIX_REPNZ); + if (prefixes & PREFIX_REPNZ) + { + index = 3; + repnz_prefix = NULL; + } + else { - index = 2; - data_prefix = NULL; + used_prefixes |= (prefixes & PREFIX_DATA); + if (prefixes & PREFIX_DATA) + { + index = 2; + data_prefix = NULL; + } } } } @@ -5222,6 +9767,128 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) modrm.rm = *codep & 7; break; + case USE_VEX_LEN_TABLE: + if (!need_vex) + abort (); + + switch (vex.length) + { + case 128: + index = 0; + break; + case 256: + index = 1; + break; + default: + abort (); + break; + } + + dp = &vex_len_table[dp->op[1].bytemode][index]; + break; + + case USE_VEX_C4_TABLE: + FETCH_DATA (info, codep + 3); + /* All bits in the REX prefix are ignored. */ + rex_ignored = rex; + rex = ~(*codep >> 5) & 0x7; + switch ((*codep & 0x1f)) + { + default: + BadOp (); + case 0x1: + vex_table_index = 0; + break; + case 0x2: + vex_table_index = 1; + break; + case 0x3: + vex_table_index = 2; + break; + } + codep++; + vex.w = *codep & 0x80; + if (vex.w && address_mode == mode_64bit) + rex |= REX_W; + + vex.register_specifier = (~(*codep >> 3)) & 0xf; + if (address_mode != mode_64bit + && vex.register_specifier > 0x7) + BadOp (); + + vex.length = (*codep & 0x4) ? 256 : 128; + switch ((*codep & 0x3)) + { + case 0: + vex.prefix = 0; + break; + case 1: + vex.prefix = DATA_PREFIX_OPCODE; + break; + case 2: + vex.prefix = REPE_PREFIX_OPCODE; + break; + case 3: + vex.prefix = REPNE_PREFIX_OPCODE; + break; + } + need_vex = 1; + need_vex_reg = 1; + codep++; + index = *codep++; + dp = &vex_table[vex_table_index][index]; + /* There is no MODRM byte for VEX [82|77]. */ + if (index != 0x77 && index != 0x82) + { + FETCH_DATA (info, codep + 1); + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; + } + break; + + case USE_VEX_C5_TABLE: + FETCH_DATA (info, codep + 2); + /* All bits in the REX prefix are ignored. */ + rex_ignored = rex; + rex = (*codep & 0x80) ? 0 : REX_R; + + vex.register_specifier = (~(*codep >> 3)) & 0xf; + if (address_mode != mode_64bit + && vex.register_specifier > 0x7) + BadOp (); + + vex.length = (*codep & 0x4) ? 256 : 128; + switch ((*codep & 0x3)) + { + case 0: + vex.prefix = 0; + break; + case 1: + vex.prefix = DATA_PREFIX_OPCODE; + break; + case 2: + vex.prefix = REPE_PREFIX_OPCODE; + break; + case 3: + vex.prefix = REPNE_PREFIX_OPCODE; + break; + } + need_vex = 1; + need_vex_reg = 1; + codep++; + index = *codep++; + dp = &vex_table[dp->op[1].bytemode][index]; + /* There is no MODRM byte for VEX [82|77]. */ + if (index != 0x77 && index != 0x82) + { + FETCH_DATA (info, codep + 1); + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; + } + break; + default: oappend (INTERNAL_DISASSEMBLER_ERROR); return NULL; @@ -5515,6 +10182,9 @@ print_insn (bfd_vma pc, disassemble_info *info) } else { + need_vex = 0; + need_vex_reg = 0; + vex_i4_done = 0; dp = get_valid_dis386 (dp, info); if (dp != NULL && putop (dp->name, sizeflag) == 0) { @@ -5542,10 +10212,10 @@ print_insn (bfd_vma pc, disassemble_info *info) (*info->fprintf_func) (info->stream, "%s", name); return 1; } - if (rex & ~rex_used) + if ((rex_original & ~rex_used) || rex_ignored) { const char *name; - name = prefix_name (rex | 0x40, priv.orig_sizeflag); + name = prefix_name (rex_original, priv.orig_sizeflag); if (name == NULL) name = INTERNAL_DISASSEMBLER_ERROR; (*info->fprintf_func) (info->stream, "%s ", name); @@ -6316,19 +10986,59 @@ case_Q: } break; case 'X': - if (prefixes & PREFIX_DATA) + if (l != 0 || len != 1) + { + SAVE_LAST (*p); + break; + } + if (need_vex && vex.prefix) + { + if (vex.prefix == DATA_PREFIX_OPCODE) + *obufp++ = 'd'; + else + *obufp++ = 's'; + } + else if (prefixes & PREFIX_DATA) *obufp++ = 'd'; else *obufp++ = 's'; used_prefixes |= (prefixes & PREFIX_DATA); break; case 'Y': - if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) - break; - if (rex & REX_W) + if (l == 0 && len == 1) { - USED_REX (REX_W); - *obufp++ = 'q'; + if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) + break; + if (rex & REX_W) + { + USED_REX (REX_W); + *obufp++ = 'q'; + } + break; + } + else + { + if (l != 1 || len != 2 || last[0] != 'X') + { + SAVE_LAST (*p); + break; + } + if (!need_vex) + abort (); + if (intel_syntax + || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) + break; + switch (vex.length) + { + case 128: + *obufp++ = 'x'; + break; + case 256: + *obufp++ = 'y'; + break; + default: + abort (); + } } break; /* implicit operand size 'l' for i386 or 'q' for x86-64 */ @@ -6577,8 +11287,58 @@ intel_operand_size (int bytemode, int sizeflag) oappend ("TBYTE PTR "); break; case x_mode: + if (need_vex) + { + switch (vex.length) + { + case 128: + oappend ("XMMWORD PTR "); + break; + case 256: + oappend ("YMMWORD PTR "); + break; + default: + abort (); + } + } + else + oappend ("XMMWORD PTR "); + break; + case xmm_mode: oappend ("XMMWORD PTR "); break; + case xmmq_mode: + if (!need_vex) + abort (); + + switch (vex.length) + { + case 128: + oappend ("QWORD PTR "); + break; + case 256: + oappend ("XMMWORD PTR "); + break; + default: + abort (); + } + break; + case ymmq_mode: + if (!need_vex) + abort (); + + switch (vex.length) + { + case 128: + oappend ("QWORD PTR "); + break; + case 256: + oappend ("YMMWORD PTR "); + break; + default: + abort (); + } + break; case o_mode: oappend ("OWORD PTR "); break; @@ -6588,78 +11348,76 @@ intel_operand_size (int bytemode, int sizeflag) } static void -OP_E_extended (int bytemode, int sizeflag, int has_drex) +OP_E_register (int bytemode, int sizeflag) { - bfd_vma disp; - int add = 0; - int riprel = 0; - USED_REX (REX_B); - if (rex & REX_B) - add += 8; + int reg = modrm.rm; + const char **names; - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; + USED_REX (REX_B); + if ((rex & REX_B)) + reg += 8; - if (modrm.mod == 3) + switch (bytemode) { - switch (bytemode) + case b_mode: + USED_REX (0); + if (rex) + names = names8rex; + else + names = names8; + break; + case w_mode: + names = names16; + break; + case d_mode: + names = names32; + break; + case q_mode: + names = names64; + break; + case m_mode: + names = address_mode == mode_64bit ? names64 : names32; + break; + case stack_v_mode: + if (address_mode == mode_64bit && (sizeflag & DFLAG)) { - case b_mode: - USED_REX (0); - if (rex) - oappend (names8rex[modrm.rm + add]); - else - oappend (names8[modrm.rm + add]); - break; - case w_mode: - oappend (names16[modrm.rm + add]); - break; - case d_mode: - oappend (names32[modrm.rm + add]); - break; - case q_mode: - oappend (names64[modrm.rm + add]); - break; - case m_mode: - if (address_mode == mode_64bit) - oappend (names64[modrm.rm + add]); - else - oappend (names32[modrm.rm + add]); - break; - case stack_v_mode: - if (address_mode == mode_64bit && (sizeflag & DFLAG)) - { - oappend (names64[modrm.rm + add]); - used_prefixes |= (prefixes & PREFIX_DATA); - break; - } - bytemode = v_mode; - /* FALLTHRU */ - case v_mode: - case dq_mode: - case dqb_mode: - case dqd_mode: - case dqw_mode: - USED_REX (REX_W); - if (rex & REX_W) - oappend (names64[modrm.rm + add]); - else if ((sizeflag & DFLAG) || bytemode != v_mode) - oappend (names32[modrm.rm + add]); - else - oappend (names16[modrm.rm + add]); + names = names64; used_prefixes |= (prefixes & PREFIX_DATA); break; - case 0: - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; } + bytemode = v_mode; + /* FALLTHRU */ + case v_mode: + case dq_mode: + case dqb_mode: + case dqd_mode: + case dqw_mode: + USED_REX (REX_W); + if (rex & REX_W) + names = names64; + else if ((sizeflag & DFLAG) || bytemode != v_mode) + names = names32; + else + names = names16; + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case 0: + return; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); return; } + oappend (names[reg]); +} + +static void +OP_E_memory (int bytemode, int sizeflag, int has_drex) +{ + bfd_vma disp = 0; + int add = (rex & REX_B) ? 8 : 0; + int riprel = 0; - disp = 0; + USED_REX (REX_B); if (intel_syntax) intel_operand_size (bytemode, sizeflag); append_seg (); @@ -6913,6 +11671,19 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex) } static void +OP_E_extended (int bytemode, int sizeflag, int has_drex) +{ + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + if (modrm.mod == 3) + OP_E_register (bytemode, sizeflag); + else + OP_E_memory (bytemode, sizeflag, has_drex); +} + +static void OP_E (int bytemode, int sizeflag) { OP_E_extended (bytemode, sizeflag, 0); @@ -7604,7 +12375,7 @@ OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) } static void -OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { int add; USED_REX (REX_R); @@ -7612,7 +12383,22 @@ OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) add = 8; else add = 0; - sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); + if (need_vex && bytemode != xmm_mode) + { + switch (vex.length) + { + case 128: + sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); + break; + case 256: + sprintf (scratchbuf, "%%ymm%d", modrm.reg + add); + break; + default: + abort (); + } + } + else + sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); oappend (scratchbuf + intel_syntax); } @@ -7703,7 +12489,24 @@ OP_EX (int bytemode, int sizeflag) /* Skip mod/rm byte. */ MODRM_CHECK; codep++; - sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); + if (need_vex + && bytemode != xmm_mode + && bytemode != xmmq_mode) + { + switch (vex.length) + { + case 128: + sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); + break; + case 256: + sprintf (scratchbuf, "%%ymm%d", modrm.rm + add); + break; + default: + abort (); + } + } + else + sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); oappend (scratchbuf + intel_syntax); } @@ -7879,7 +12682,7 @@ CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) FETCH_DATA (the_info, codep + 1); cmp_type = *codep++ & 0xff; - if (cmp_type < 8) + if (cmp_type < ARRAY_SIZE (simd_cmp_op)) { char suffix [3]; char *p = obuf + strlen (obuf) - 2; @@ -8000,7 +12803,22 @@ CMPXCHG8B_Fixup (int bytemode, int sizeflag) static void XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) { - sprintf (scratchbuf, "%%xmm%d", reg); + if (need_vex) + { + switch (vex.length) + { + case 128: + sprintf (scratchbuf, "%%xmm%d", reg); + break; + case 256: + sprintf (scratchbuf, "%%ymm%d", reg); + break; + default: + abort (); + } + } + else + sprintf (scratchbuf, "%%xmm%d", reg); oappend (scratchbuf + intel_syntax); } @@ -8410,3 +13228,393 @@ OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED, codep++; } } + +/* Display the destination register operand for instructions with + VEX. */ + +static void +OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) +{ + if (!need_vex) + abort (); + + if (!need_vex_reg) + return; + + switch (vex.length) + { + case 128: + switch (bytemode) + { + case vex_mode: + case vex128_mode: + break; + default: + abort (); + return; + } + + sprintf (scratchbuf, "%%xmm%d", vex.register_specifier); + break; + case 256: + switch (bytemode) + { + case vex_mode: + case vex256_mode: + break; + default: + abort (); + return; + } + + sprintf (scratchbuf, "%%ymm%d", vex.register_specifier); + break; + default: + abort (); + break; + } + oappend (scratchbuf + intel_syntax); +} + +static void +OP_EX_VexW (int bytemode, int sizeflag) +{ + int reg = -1; + static unsigned char vex_i4; + + if (!vex_i4_done) + { + int bytes_before_imm = 0; + + /* Skip mod/rm byte once. We will be called twice. */ + MODRM_CHECK; + codep++; + + if (modrm.mod != 3) + { + /* There are SIB/displacement bytes. */ + if ((sizeflag & AFLAG) || address_mode == mode_64bit) + { + /* 32/64 bit address mode */ + int base = modrm.rm; + + /* Check SIB byte. */ + if (base == 4) + { + FETCH_DATA (the_info, codep + 1); + base = *codep & 7; + bytes_before_imm++; + } + + switch (modrm.mod) + { + case 0: + /* When modrm.rm == 5 or modrm.rm == 4 and base in + SIB == 5, there is a 4 byte displacement. */ + if (base != 5) + /* No displacement. */ + break; + case 2: + /* 4 byte displacement. */ + bytes_before_imm += 4; + break; + case 1: + /* 1 byte displacement. */ + bytes_before_imm++; + break; + } + } + else + { /* 16 bit address mode */ + switch (modrm.mod) + { + case 0: + /* When modrm.rm == 6, there is a 2 byte + displacement. */ + if (modrm.rm != 6) + /* No displacement. */ + break; + case 2: + /* 2 byte displacement. */ + bytes_before_imm += 2; + break; + case 1: + /* 1 byte displacement. */ + bytes_before_imm++; + break; + } + } + } + + FETCH_DATA (the_info, codep + bytes_before_imm + 1); + vex_i4 = codep [bytes_before_imm]; + vex_i4_done = 1; + if (vex.w) + reg = vex_i4 >> 4; + } + else + { + if (!vex.w) + reg = vex_i4 >> 4; + } + + if (reg == -1 && modrm.mod != 3) + { + OP_E_memory (bytemode, sizeflag, 0); + return; + } + else + { + if (reg == -1) + { + reg = modrm.rm; + USED_REX (REX_B); + if (rex & REX_B) + reg += 8; + } + else if (reg > 7 && address_mode != mode_64bit) + BadOp (); + } + + switch (vex.length) + { + case 128: + sprintf (scratchbuf, "%%xmm%d", reg); + break; + case 256: + sprintf (scratchbuf, "%%ymm%d", reg); + break; + default: + abort (); + } + oappend (scratchbuf + intel_syntax); +} + +static void +VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + /* Skip the immediate byte and check for invalid bits. */ + FETCH_DATA (the_info, codep + 1); + if (*codep++ & 0xf) + BadOp (); +} + +static void +OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) +{ + int reg; + FETCH_DATA (the_info, codep + 1); + reg = *codep++; + + if (bytemode != x_mode) + abort (); + + if (reg & 0xf) + BadOp (); + + reg >>= 4; + switch (vex.length) + { + case 128: + sprintf (scratchbuf, "%%xmm%d", reg); + break; + case 256: + sprintf (scratchbuf, "%%ymm%d", reg); + break; + default: + abort (); + } + oappend (scratchbuf + intel_syntax); +} + +static void +OP_XMM_VexW (int bytemode, int sizeflag) +{ + /* Turn off the REX.W bit since it is used for swapping operands + now. */ + rex &= ~REX_W; + OP_XMM (bytemode, sizeflag); +} + +static void +OP_EX_Vex (int bytemode, int sizeflag) +{ + if (modrm.mod != 3) + { + if (vex.register_specifier != 0) + BadOp (); + need_vex_reg = 0; + } + OP_EX (bytemode, sizeflag); +} + +static void +OP_XMM_Vex (int bytemode, int sizeflag) +{ + if (modrm.mod != 3) + { + if (vex.register_specifier != 0) + BadOp (); + need_vex_reg = 0; + } + OP_XMM (bytemode, sizeflag); +} + +static void +VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + switch (vex.length) + { + case 128: + strcpy (obuf, "vzeroupper"); + break; + case 256: + strcpy (obuf, "vzeroall"); + break; + default: + abort (); + } +} + +static const char *vex_cmp_op[] = { + "eq", + "lt", + "le", + "unord", + "neq", + "nlt", + "nle", + "ord", + "eq_uq", + "nge", + "ngt", + "false", + "neq_oq", + "ge", + "gt", + "true", + "eq_os", + "lt_oq", + "le_oq", + "unord_s", + "neq_us", + "nlt_uq", + "nle_uq", + "ord_s", + "eq_us", + "nge_uq", + "ngt_uq", + "false_os", + "neq_os", + "ge_oq", + "gt_oq", + "true_us" +}; + +static void +VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int cmp_type; + + FETCH_DATA (the_info, codep + 1); + cmp_type = *codep++ & 0xff; + if (cmp_type < ARRAY_SIZE (vex_cmp_op)) + { + char suffix [3]; + char *p = obuf + strlen (obuf) - 2; + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = '\0'; + sprintf (p, "%s%s", vex_cmp_op[cmp_type], suffix); + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, cmp_type); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; + } +} + +static const char *pclmul_op[] = { + "lql", + "hql", + "lqh", + "hqh" +}; + +static void +PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int pclmul_type; + + FETCH_DATA (the_info, codep + 1); + pclmul_type = *codep++ & 0xff; + switch (pclmul_type) + { + case 0x10: + pclmul_type = 2; + break; + case 0x11: + pclmul_type = 3; + break; + default: + break; + } + if (pclmul_type < ARRAY_SIZE (pclmul_op)) + { + char suffix [4]; + char *p = obuf + strlen (obuf) - 3; + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = p[2]; + suffix[3] = '\0'; + sprintf (p, "%s%s", pclmul_op[pclmul_type], suffix); + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, pclmul_type); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; + } +} + +static const char *vpermil2_op[] = { + "td", + "td", + "mo", + "mz" +}; + +static void +VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int vpermil2_type; + + FETCH_DATA (the_info, codep + 1); + vpermil2_type = *codep++ & 0xf; + if (vpermil2_type < ARRAY_SIZE (vpermil2_op)) + { + char suffix [4]; + char *p = obuf + strlen (obuf) - 3; + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = p[2]; + suffix[3] = '\0'; + sprintf (p, "%s%s", vpermil2_op[vpermil2_type], suffix); + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, vpermil2_type); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; + } +} diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index f7e9369..b225e06 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -102,6 +102,12 @@ static initializer cpu_flag_init [] = "CpuSMX" }, { "CPU_XSAVE_FLAGS", "CpuXsave" }, + { "CPU_AES_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" }, + { "CPU_CLMUL_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuCLMUL" }, + { "CPU_FMA_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" }, { "CPU_3DNOW_FLAGS", "CpuMMX|Cpu3dnow" }, { "CPU_3DNOWA_FLAGS", @@ -116,6 +122,8 @@ static initializer cpu_flag_init [] = "CpuABM" }, { "CPU_SSE5_FLAGS", "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5"}, + { "CPU_AVX_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX" }, }; static initializer operand_type_init [] = @@ -182,6 +190,8 @@ static initializer operand_type_init [] = "RegMMX" }, { "OPERAND_TYPE_REGXMM", "RegXMM" }, + { "OPERAND_TYPE_REGYMM", + "RegYMM" }, { "OPERAND_TYPE_ESSEG", "EsSeg" }, { "OPERAND_TYPE_ACC32", @@ -210,6 +220,8 @@ static initializer operand_type_init [] = "Imm32|Imm32S|Imm64|Disp32" }, { "OPERAND_TYPE_IMM32_32S_64_DISP32_64", "Imm32|Imm32S|Imm64|Disp32|Disp64" }, + { "OPERAND_TYPE_VEX_IMM4", + "VEX_Imm4" }, }; typedef struct bitfield @@ -239,6 +251,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuSSSE3), BITFIELD (CpuSSE4_1), BITFIELD (CpuSSE4_2), + BITFIELD (CpuAVX), BITFIELD (CpuSSE4a), BITFIELD (CpuSSE5), BITFIELD (Cpu3dnow), @@ -248,8 +261,11 @@ static bitfield cpu_flags[] = BITFIELD (CpuVMX), BITFIELD (CpuSMX), BITFIELD (CpuABM), - BITFIELD (CpuLM), BITFIELD (CpuXsave), + BITFIELD (CpuAES), + BITFIELD (CpuCLMUL), + BITFIELD (CpuFMA), + BITFIELD (CpuLM), BITFIELD (Cpu64), BITFIELD (CpuNo64), #ifdef CpuUnused @@ -285,6 +301,7 @@ static bitfield opcode_modifiers[] = BITFIELD (IsString), BITFIELD (RegKludge), BITFIELD (FirstXmm0), + BITFIELD (Implicit1stXmm0), BITFIELD (ByteOkIntel), BITFIELD (ToDword), BITFIELD (ToQword), @@ -297,6 +314,18 @@ static bitfield opcode_modifiers[] = BITFIELD (Drex), BITFIELD (Drexv), BITFIELD (Drexc), + BITFIELD (Vex), + BITFIELD (Vex256), + BITFIELD (VexNDD), + BITFIELD (VexNDS), + BITFIELD (VexW0), + BITFIELD (VexW1), + BITFIELD (Vex0F), + BITFIELD (Vex0F38), + BITFIELD (Vex0F3A), + BITFIELD (Vex3Sources), + BITFIELD (VexImmExt), + BITFIELD (SSE2AVX), BITFIELD (OldGcc), BITFIELD (ATTMnemonic), BITFIELD (ATTSyntax), @@ -312,6 +341,7 @@ static bitfield operand_types[] = BITFIELD (FloatReg), BITFIELD (RegMMX), BITFIELD (RegXMM), + BITFIELD (RegYMM), BITFIELD (Imm8), BITFIELD (Imm8S), BITFIELD (Imm16), @@ -345,8 +375,10 @@ static bitfield operand_types[] = BITFIELD (Qword), BITFIELD (Tbyte), BITFIELD (Xmmword), + BITFIELD (Ymmword), BITFIELD (Unspecified), BITFIELD (Anysize), + BITFIELD (Vex_Imm4), #ifdef OTUnused BITFIELD (OTUnused), #endif diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index 0c924e3..11a88aa 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -20,378 +20,404 @@ #define CPU_UNKNOWN_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ - 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } } + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } } #define CPU_GENERIC32_FLAGS \ { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_GENERIC64_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } #define CPU_NONE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_I186_FLAGS \ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_I286_FLAGS \ { { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_I386_FLAGS \ { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_I486_FLAGS \ { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_I586_FLAGS \ { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_I686_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_P2_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_P3_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_P4_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_NOCONA_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } #define CPU_CORE_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_CORE2_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } #define CPU_K6_FLAGS \ { { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_K6_2_FLAGS \ { { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_ATHLON_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_K8_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } #define CPU_AMDFAM10_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \ - 1, 1, 0, 0, 0, 0, 1, 0, 0, 0 } } + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } #define CPU_MMX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SSE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SSE2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SSE3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SSSE3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SSE4_1_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SSE4_2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ - 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } } + 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_VMX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SMX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_XSAVE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_AES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ + 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } } + +#define CPU_CLMUL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ + 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } + +#define CPU_FMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ + 0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0 } } #define CPU_3DNOW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_3DNOWA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_PADLOCK_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SVME_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SSE4A_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_ABM_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } } + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } #define CPU_SSE5_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \ - 1, 1, 0, 0, 1, 0, 0, 0, 0, 0 } } + 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_AVX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ + 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_NONE \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_REG8 \ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_REG16 \ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_REG32 \ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_REG64 \ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM1 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM8 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM8S \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM16 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM32 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM32S \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM64 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_BASEINDEX \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_DISP8 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_DISP16 \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_DISP32 \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_DISP32S \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_DISP64 \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_INOUTPORTREG \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_SHIFTCOUNT \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_CONTROL \ - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_TEST \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_DEBUG \ { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_FLOATREG \ { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_FLOATACC \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_SREG2 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_SREG3 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_ACC \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_JUMPABSOLUTE \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_REGMMX \ { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_REGXMM \ { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REGYMM \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_ESSEG \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_ACC32 \ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_ACC64 \ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_INOUTPORTREG \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_REG16_INOUTPORTREG \ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_DISP16_32 \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_ANYDISP \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ - 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM16_32 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM16_32S \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM16_32_32S \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM32_32S_DISP32 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM64_DISP64 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM32_32S_64_DISP32 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \ - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \ - 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0 } } + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ + 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_VEX_IMM4 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 0 } } diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index d66f02b..4ea2ec4 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -80,10 +80,18 @@ #define CpuSSE4_2 (CpuSSE4_1 + 1) /* SSE5 support required */ #define CpuSSE5 (CpuSSE4_2 + 1) +/* AVX support required */ +#define CpuAVX (CpuSSE5 + 1) /* Xsave/xrstor New Instuctions support required */ -#define CpuXsave (CpuSSE5 + 1) +#define CpuXsave (CpuAVX + 1) +/* AES support required */ +#define CpuAES (CpuXsave + 1) +/* CLMUL support required */ +#define CpuCLMUL (CpuAES + 1) +/* FMA support required */ +#define CpuFMA (CpuCLMUL + 1) /* 64bit support available, used by -march= in assembler. */ -#define CpuLM (CpuXsave + 1) +#define CpuLM (CpuFMA + 1) /* 64bit support required */ #define Cpu64 (CpuLM + 1) /* Not supported in the 64bit mode */ @@ -131,7 +139,11 @@ typedef union i386_cpu_flags unsigned int cpusse4_1:1; unsigned int cpusse4_2:1; unsigned int cpusse5:1; + unsigned int cpuavx:1; unsigned int cpuxsave:1; + unsigned int cpuaes:1; + unsigned int cpuclmul:1; + unsigned int cpufma:1; unsigned int cpulm:1; unsigned int cpu64:1; unsigned int cpuno64:1; @@ -198,8 +210,10 @@ typedef union i386_cpu_flags #define RegKludge (IsString + 1) /* The first operand must be xmm0 */ #define FirstXmm0 (RegKludge + 1) +/* An implicit xmm0 as the first operand */ +#define Implicit1stXmm0 (FirstXmm0 + 1) /* BYTE is OK in Intel syntax. */ -#define ByteOkIntel (FirstXmm0 + 1) +#define ByteOkIntel (Implicit1stXmm0 + 1) /* Convert to DWORD */ #define ToDword (ByteOkIntel + 1) /* Convert to QWORD */ @@ -221,8 +235,34 @@ typedef union i386_cpu_flags #define Drexv (Drex + 1) /* special DREX for comparisons */ #define Drexc (Drexv + 1) +/* insn has VEX prefix. */ +#define Vex (Drexc + 1) +/* insn has 256bit VEX prefix. */ +#define Vex256 (Vex + 1) +/* insn has VEX NDS. Register-only source is encoded in Vex + prefix. */ +#define VexNDS (Vex256 + 1) +/* insn has VEX NDD. Register destination is encoded in Vex + prefix. */ +#define VexNDD (VexNDS + 1) +/* insn has VEX W0. */ +#define VexW0 (VexNDD + 1) +/* insn has VEX W1. */ +#define VexW1 (VexW0 + 1) +/* insn has VEX 0x0F opcode prefix. */ +#define Vex0F (VexW1 + 1) +/* insn has VEX 0x0F38 opcode prefix. */ +#define Vex0F38 (Vex0F + 1) +/* insn has VEX 0x0F3A opcode prefix. */ +#define Vex0F3A (Vex0F38 + 1) +/* insn has VEX prefix with 3 soures. */ +#define Vex3Sources (Vex0F3A + 1) +/* instruction has VEX 8 bit imm */ +#define VexImmExt (Vex3Sources + 1) +/* SSE to AVX support required */ +#define SSE2AVX (VexImmExt + 1) /* Compatible with old (<= 2.8.1) versions of gcc */ -#define OldGcc (Drexc + 1) +#define OldGcc (SSE2AVX + 1) /* AT&T mnemonic. */ #define ATTMnemonic (OldGcc + 1) /* AT&T syntax. */ @@ -260,6 +300,7 @@ typedef struct i386_opcode_modifier unsigned int isstring:1; unsigned int regkludge:1; unsigned int firstxmm0:1; + unsigned int implicit1stxmm0:1; unsigned int byteokintel:1; unsigned int todword:1; unsigned int toqword:1; @@ -272,6 +313,18 @@ typedef struct i386_opcode_modifier unsigned int drex:1; unsigned int drexv:1; unsigned int drexc:1; + unsigned int vex:1; + unsigned int vex256:1; + unsigned int vexnds:1; + unsigned int vexndd:1; + unsigned int vexw0:1; + unsigned int vexw1:1; + unsigned int vex0f:1; + unsigned int vex0f38:1; + unsigned int vex0f3a:1; + unsigned int vex3sources:1; + unsigned int veximmext:1; + unsigned int sse2avx:1; unsigned int oldgcc:1; unsigned int attmnemonic:1; unsigned int attsyntax:1; @@ -294,8 +347,10 @@ typedef struct i386_opcode_modifier #define RegMMX (FloatReg + 1) /* SSE register */ #define RegXMM (RegMMX + 1) +/* AVX registers */ +#define RegYMM (RegXMM + 1) /* Control register */ -#define Control (RegXMM + 1) +#define Control (RegYMM + 1) /* Debug register */ #define Debug (Control + 1) /* Test register */ @@ -371,13 +426,18 @@ typedef struct i386_opcode_modifier #define Tbyte (Qword + 1) /* XMMWORD memory. */ #define Xmmword (Tbyte + 1) +/* YMMWORD memory. */ +#define Ymmword (Xmmword + 1) /* Unspecified memory size. */ -#define Unspecified (Xmmword + 1) +#define Unspecified (Ymmword + 1) /* Any memory size. */ #define Anysize (Unspecified + 1) +/* VEX 4 bit immediate */ +#define Vex_Imm4 (Anysize + 1) + /* The last bitfield in i386_operand_type. */ -#define OTMax Anysize +#define OTMax Vex_Imm4 #define OTNumOfUints \ (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) @@ -399,6 +459,7 @@ typedef union i386_operand_type unsigned int floatreg:1; unsigned int regmmx:1; unsigned int regxmm:1; + unsigned int regymm:1; unsigned int control:1; unsigned int debug:1; unsigned int test:1; @@ -432,8 +493,10 @@ typedef union i386_operand_type unsigned int qword:1; unsigned int tbyte:1; unsigned int xmmword:1; + unsigned int ymmword:1; unsigned int unspecified:1; unsigned int anysize:1; + unsigned int vex_imm4:1; #ifdef OTUnused unsigned int unused:(OTNumOfBits - OTUnused); #endif diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index cfb31f1..dc71cf3 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -912,30 +912,37 @@ emms, 0, 0xf77, None, 2, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's // spec). AMD's spec, having been in existence for much longer, failed to // recognize that and specified movd for 32- and 64-bit operations. -movd, 2, 0xf6e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } -movd, 2, 0xf6e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX } -movd, 2, 0xf7e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Disp32S } -movd, 2, 0xf7e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegMMX, Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S|Disp32S } +movd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +movd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { RegXMM, Qword|Reg64|BaseIndex|Disp8|Disp32|Disp32S } movd, 2, 0x660f6e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Disp32S, RegXMM } movd, 2, 0x660f6e, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S|Disp32S, RegXMM } movd, 2, 0x660f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Disp32S } movd, 2, 0x660f7e, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S|Disp32S } +movd, 2, 0xf6e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +movd, 2, 0xf6e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX } +movd, 2, 0xf7e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Disp32S } +movd, 2, 0xf7e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegMMX, Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S|Disp32S } // In the 64bit mode the short form mov immediate is redefined to have -// 64bit displacement value. -movq, 2, 0xf6f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } -movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegMMX, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } -movq, 2, 0xf30f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX } -movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S } -movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } -movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S } -// We put the 64bit displacement first and we only mark constants -// larger than 32bit as Disp64. +// 64bit displacement value. We put the 64bit displacement first and +// we only mark constants larger than 32bit as Disp64. movq, 2, 0xa0, None, 1, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp64|Unspecified|Qword, Acc|Qword } movq, 2, 0x88, None, 1, Cpu64, D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S } movq, 2, 0xc6, 0x0, 1, Cpu64, W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm32S, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } movq, 2, 0xb0, None, 1, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm64, Reg64 } +movq, 2, 0xf37e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +movq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +movq, 2, 0xf30f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S } +movq, 2, 0xf6f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegMMX, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } +movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX } +movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S } // The segment register moves accept Reg64 so that a segment register // can be copied to a 64 bit register, and vice versa. movq, 2, 0x8c, None, 1, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2|SReg3, Reg64|RegMem } @@ -944,327 +951,543 @@ movq, 2, 0x8e, None, 1, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q // are 32bit. In the 64bit mode they are 64bit. movq, 2, 0xf20, None, 2, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Control, Reg64|RegMem } movq, 2, 0xf21, None, 2, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Debug, Reg64|RegMem } -// Real MMX instructions. -packssdw, 2, 0xf6b, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +// Real MMX/SSE instructions. +packssdw, 2, 0x666b, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } packssdw, 2, 0x660f6b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -packsswb, 2, 0xf63, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packssdw, 2, 0xf6b, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packsswb, 2, 0x6663, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } packsswb, 2, 0x660f63, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -packuswb, 2, 0xf67, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packsswb, 2, 0xf63, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packuswb, 2, 0x6667, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } packuswb, 2, 0x660f67, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -paddb, 2, 0xffc, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packuswb, 2, 0xf67, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddb, 2, 0x66fc, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } paddb, 2, 0x660ffc, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -paddw, 2, 0xffd, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddb, 2, 0xffc, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddw, 2, 0x66fd, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } paddw, 2, 0x660ffd, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -paddd, 2, 0xffe, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddw, 2, 0xffd, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddd, 2, 0x66fe, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } paddd, 2, 0x660ffe, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -paddq, 2, 0xfd4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddd, 2, 0xffe, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddq, 2, 0x66d4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } paddq, 2, 0x660fd4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -paddsb, 2, 0xfec, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddq, 2, 0xfd4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddsb, 2, 0x66ec, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } paddsb, 2, 0x660fec, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -paddsw, 2, 0xfed, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddsb, 2, 0xfec, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddsw, 2, 0x66ed, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } paddsw, 2, 0x660fed, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -paddusb, 2, 0xfdc, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddsw, 2, 0xfed, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddusb, 2, 0x66dc, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } paddusb, 2, 0x660fdc, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -paddusw, 2, 0xfdd, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddusb, 2, 0xfdc, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddusw, 2, 0x66dd, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } paddusw, 2, 0x660fdd, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pand, 2, 0xfdb, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddusw, 2, 0xfdd, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pand, 2, 0x66db, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pand, 2, 0x660fdb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pandn, 2, 0xfdf, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pand, 2, 0xfdb, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pandn, 2, 0x66df, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pandn, 2, 0x660fdf, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pcmpeqb, 2, 0xf74, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pandn, 2, 0xfdf, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqb, 2, 0x6674, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpeqb, 2, 0x660f74, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pcmpeqw, 2, 0xf75, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqb, 2, 0xf74, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqw, 2, 0x6675, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpeqw, 2, 0x660f75, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pcmpeqd, 2, 0xf76, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqw, 2, 0xf75, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqd, 2, 0x6676, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpeqd, 2, 0x660f76, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pcmpgtb, 2, 0xf64, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqd, 2, 0xf76, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtb, 2, 0x6664, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpgtb, 2, 0x660f64, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pcmpgtw, 2, 0xf65, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtb, 2, 0xf64, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtw, 2, 0x6665, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpgtw, 2, 0x660f65, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pcmpgtd, 2, 0xf66, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtw, 2, 0xf65, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtd, 2, 0x6666, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpgtd, 2, 0x660f66, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pmaddwd, 2, 0xff5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtd, 2, 0xf66, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaddwd, 2, 0x66f5, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmaddwd, 2, 0x660ff5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pmulhw, 2, 0xfe5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaddwd, 2, 0xff5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhw, 2, 0x66e5, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmulhw, 2, 0x660fe5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pmullw, 2, 0xfd5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhw, 2, 0xfe5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmullw, 2, 0x66d5, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmullw, 2, 0x660fd5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -por, 2, 0xfeb, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmullw, 2, 0xfd5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +por, 2, 0x66eb, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } por, 2, 0x660feb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psllw, 2, 0xff1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +por, 2, 0xfeb, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psllw, 2, 0x6671, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psllw, 2, 0x66f1, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllw, 2, 0x660f71, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } psllw, 2, 0x660ff1, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psllw, 2, 0xf71, 0x6, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } -psllw, 2, 0x660f71, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } -pslld, 2, 0xff2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psllw, 2, 0xff1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pslld, 2, 0x6672, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +pslld, 2, 0x66f2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pslld, 2, 0x660f72, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } pslld, 2, 0x660ff2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pslld, 2, 0xf72, 0x6, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } -pslld, 2, 0x660f72, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } -psllq, 2, 0xff3, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pslld, 2, 0xff2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psllq, 2, 0x6673, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psllq, 2, 0x66f3, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllq, 2, 0x660f73, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } psllq, 2, 0x660ff3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psllq, 2, 0xf73, 0x6, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } -psllq, 2, 0x660f73, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } -psraw, 2, 0xfe1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psllq, 2, 0xff3, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psraw, 2, 0x6671, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psraw, 2, 0x66e1, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psraw, 2, 0x660f71, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } psraw, 2, 0x660fe1, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psraw, 2, 0xf71, 0x4, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } -psraw, 2, 0x660f71, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } -psrad, 2, 0xfe2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psraw, 2, 0xfe1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrad, 2, 0x6672, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrad, 2, 0x66e2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrad, 2, 0x660f72, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } psrad, 2, 0x660fe2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psrad, 2, 0xf72, 0x4, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } -psrad, 2, 0x660f72, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } -psrlw, 2, 0xfd1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrad, 2, 0xfe2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrlw, 2, 0x6671, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrlw, 2, 0x66d1, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrlw, 2, 0x660f71, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } psrlw, 2, 0x660fd1, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psrlw, 2, 0xf71, 0x2, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } -psrlw, 2, 0x660f71, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } -psrld, 2, 0xfd2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrlw, 2, 0xfd1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrld, 2, 0x6672, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrld, 2, 0x66d2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrld, 2, 0x660f72, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } psrld, 2, 0x660fd2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psrld, 2, 0xf72, 0x2, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } -psrld, 2, 0x660f72, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } -psrlq, 2, 0xfd3, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrld, 2, 0xfd2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrlq, 2, 0x6673, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrlq, 2, 0x66d3, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrlq, 2, 0x660f73, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } psrlq, 2, 0x660fd3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psrlq, 2, 0xf73, 0x2, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } -psrlq, 2, 0x660f73, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } -psubb, 2, 0xff8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrlq, 2, 0xfd3, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubb, 2, 0x66f8, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psubb, 2, 0x660ff8, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psubw, 2, 0xff9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubb, 2, 0xff8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubw, 2, 0x66f9, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psubw, 2, 0x660ff9, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psubd, 2, 0xffa, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubw, 2, 0xff9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubd, 2, 0x66fa, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psubd, 2, 0x660ffa, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psubq, 2, 0xffb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubd, 2, 0xffa, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubq, 2, 0x66fb, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psubq, 2, 0x660ffb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psubsb, 2, 0xfe8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubq, 2, 0xffb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubsb, 2, 0x66e8, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psubsb, 2, 0x660fe8, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psubsw, 2, 0xfe9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubsb, 2, 0xfe8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubsw, 2, 0x66e9, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psubsw, 2, 0x660fe9, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psubusb, 2, 0xfd8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubsw, 2, 0xfe9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubusb, 2, 0x66d8, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psubusb, 2, 0x660fd8, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psubusw, 2, 0xfd9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubusb, 2, 0xfd8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubusw, 2, 0x66d9, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psubusw, 2, 0x660fd9, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -punpckhbw, 2, 0xf68, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubusw, 2, 0xfd9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhbw, 2, 0x6668, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } punpckhbw, 2, 0x660f68, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -punpckhwd, 2, 0xf69, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhbw, 2, 0xf68, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhwd, 2, 0x6669, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } punpckhwd, 2, 0x660f69, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -punpckhdq, 2, 0xf6a, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhwd, 2, 0xf69, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhdq, 2, 0x666a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } punpckhdq, 2, 0x660f6a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -punpcklbw, 2, 0xf60, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhdq, 2, 0xf6a, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpcklbw, 2, 0x6660, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } punpcklbw, 2, 0x660f60, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -punpcklwd, 2, 0xf61, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpcklbw, 2, 0xf60, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpcklwd, 2, 0x6661, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } punpcklwd, 2, 0x660f61, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -punpckldq, 2, 0xf62, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpcklwd, 2, 0xf61, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckldq, 2, 0x6662, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } punpckldq, 2, 0x660f62, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pxor, 2, 0xfef, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckldq, 2, 0xf62, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pxor, 2, 0x66ef, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pxor, 2, 0x660fef, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pxor, 2, 0xfef, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } // SSE instructions. +addps, 2, 0x58, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addps, 2, 0xf58, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addss, 2, 0xf358, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addss, 2, 0xf30f58, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andnps, 2, 0x55, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } andnps, 2, 0xf55, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andps, 2, 0x54, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } andps, 2, 0xf54, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqps, 2, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpeqps, 2, 0xfc2, 0x0, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqss, 2, 0xf3c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpeqss, 2, 0xf30fc2, 0x0, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpleps, 2, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpleps, 2, 0xfc2, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpless, 2, 0xf3c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpless, 2, 0xf30fc2, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltps, 2, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpltps, 2, 0xfc2, 0x1, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltss, 2, 0xf3c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpltss, 2, 0xf30fc2, 0x1, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqps, 2, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpneqps, 2, 0xfc2, 0x4, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqss, 2, 0xf3c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpneqss, 2, 0xf30fc2, 0x4, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnleps, 2, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpnleps, 2, 0xfc2, 0x6, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnless, 2, 0xf3c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpnless, 2, 0xf30fc2, 0x6, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltps, 2, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpnltps, 2, 0xfc2, 0x5, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltss, 2, 0xf3c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpnltss, 2, 0xf30fc2, 0x5, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordps, 2, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpordps, 2, 0xfc2, 0x7, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordss, 2, 0xf3c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpordss, 2, 0xf30fc2, 0x7, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordps, 2, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpunordps, 2, 0xfc2, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordss, 2, 0xf3c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpunordss, 2, 0xf30fc2, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpps, 3, 0xc2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpps, 3, 0xfc2, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpss, 3, 0xf3c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpss, 3, 0xf30fc2, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +comiss, 2, 0x2f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } comiss, 2, 0xf2f, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtpi2ps, 2, 0xf2a, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } cvtps2pi, 2, 0xf2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvtsi2ss, 2, 0xf32a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } cvtss2si, 2, 0xf30f2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } cvttps2pi, 2, 0xf2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvttss2si, 2, 0xf32c, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } cvttss2si, 2, 0xf30f2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +divps, 2, 0x5e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } divps, 2, 0xf5e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divss, 2, 0xf35e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } divss, 2, 0xf30f5e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } ldmxcsr, 1, 0xfae, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } maskmovq, 2, 0xff7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, RegMMX } +maxps, 2, 0x5f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } maxps, 2, 0xf5f, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxss, 2, 0xf35f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } maxss, 2, 0xf30f5f, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minps, 2, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } minps, 2, 0xf5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minss, 2, 0xf35d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } minss, 2, 0xf30f5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movaps, 2, 0xf28, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movaps, 2, 0xf29, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movhlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } movhlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +movhps, 2, 0x16, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movhps, 2, 0x17, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } movhps, 2, 0xf16, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } movhps, 2, 0xf17, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movlhps, 2, 0x16, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } movlhps, 2, 0xf16, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +movlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } movlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } movlps, 2, 0xf13, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 } movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +movntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } movntps, 2, 0xf2b, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } movntq, 2, 0xfe7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } movntdq, 2, 0x660fe7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } movss, 2, 0xf30f10, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movss, 2, 0xf30f11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movups, 2, 0x10, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movups, 2, 0xf10, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movups, 2, 0xf11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +mulps, 2, 0x59, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mulps, 2, 0xf59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulss, 2, 0xf359, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mulss, 2, 0xf30f59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +orps, 2, 0x56, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } orps, 2, 0xf56, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pavgb, 2, 0xfe0, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pavgb, 2, 0x66e0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pavgb, 2, 0x660fe0, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pavgw, 2, 0xfe3, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pavgw, 2, 0x66e3, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pavgw, 2, 0x660fe3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pextrw, 3, 0xfc5, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } +pextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 } +pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } pextrw, 3, 0x660fc5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } - -// Streaming SIMD extensions 4.1 Instructions. pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } - -pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +pextrw, 3, 0xfc5, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } +pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } -pmaxsw, 2, 0xfee, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +pmaxsw, 2, 0x66ee, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmaxsw, 2, 0x660fee, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pmaxub, 2, 0xfde, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaxsw, 2, 0xfee, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaxub, 2, 0x66de, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmaxub, 2, 0x660fde, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pminsw, 2, 0xfea, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaxub, 2, 0xfde, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pminsw, 2, 0x66ea, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pminsw, 2, 0x660fea, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pminub, 2, 0xfda, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pminsw, 2, 0xfea, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pminub, 2, 0x66da, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pminub, 2, 0x660fda, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pmovmskb, 2, 0xfd7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegMMX, Reg32|Reg64 } +pminub, 2, 0xfda, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 } pmovmskb, 2, 0x660fd7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } -pmulhuw, 2, 0xfe4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmovmskb, 2, 0xfd7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegMMX, Reg32|Reg64 } +pmulhuw, 2, 0x66e4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmulhuw, 2, 0x660fe4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhuw, 2, 0xfe4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } prefetchnta, 1, 0xf18, 0x0, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } prefetcht0, 1, 0xf18, 0x1, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } prefetcht1, 1, 0xf18, 0x2, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } prefetcht2, 1, 0xf18, 0x3, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } psadbw, 2, 0xff6, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psadbw, 2, 0x66f6, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psadbw, 2, 0x660ff6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pshufw, 3, 0xf70, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +rcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } rcpps, 2, 0xf53, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rcpss, 2, 0xf353, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } rcpss, 2, 0xf30f53, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } rsqrtps, 2, 0xf52, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rsqrtss, 2, 0xf352, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } rsqrtss, 2, 0xf30f52, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } sfence, 0, 0xfae, 0xf8, 2, CpuSSE|Cpu3dnowA, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +shufps, 3, 0xc6, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } shufps, 3, 0xfc6, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } sqrtps, 2, 0xf51, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtss, 2, 0xf351, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } sqrtss, 2, 0xf30f51, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +stmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } stmxcsr, 1, 0xfae, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +subps, 2, 0x5c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } subps, 2, 0xf5c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subss, 2, 0xf35c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } subss, 2, 0xf30f5c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ucomiss, 2, 0x2e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ucomiss, 2, 0xf2e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpckhps, 2, 0x15, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } unpckhps, 2, 0xf15, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpcklps, 2, 0x14, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } unpcklps, 2, 0xf14, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +xorps, 2, 0x57, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } xorps, 2, 0xf57, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } // SSE2 instructions. +addpd, 2, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addpd, 2, 0x660f58, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsd, 2, 0xf258, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addsd, 2, 0xf20f58, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andnpd, 2, 0x6655, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } andnpd, 2, 0x660f55, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andpd, 2, 0x6654, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } andpd, 2, 0x660f54, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqpd, 2, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpeqpd, 2, 0x660fc2, 0x0, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqsd, 2, 0xf2c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpeqsd, 2, 0xf20fc2, 0x0, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmplepd, 2, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmplepd, 2, 0x660fc2, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmplesd, 2, 0xf2c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmplesd, 2, 0xf20fc2, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltpd, 2, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpltpd, 2, 0x660fc2, 0x1, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltsd, 2, 0xf2c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpltsd, 2, 0xf20fc2, 0x1, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqpd, 2, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpneqpd, 2, 0x660fc2, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqsd, 2, 0xf2c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpneqsd, 2, 0xf20fc2, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnlepd, 2, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpnlepd, 2, 0x660fc2, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnlesd, 2, 0xf2c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpnlesd, 2, 0xf20fc2, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltpd, 2, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpnltpd, 2, 0x660fc2, 0x5, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltsd, 2, 0xf2c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpnltsd, 2, 0xf20fc2, 0x5, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordpd, 2, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpordpd, 2, 0x660fc2, 0x7, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordsd, 2, 0xf2c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpordsd, 2, 0xf20fc2, 0x7, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordpd, 2, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpunordpd, 2, 0x660fc2, 0x3, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordsd, 2, 0xf2c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpunordsd, 2, 0xf20fc2, 0x3, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmppd, 3, 0x66c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmppd, 3, 0x660fc2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } // Intel mode string compare. cmpsd, 0, 0xa7, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 } cmpsd, 2, 0xa7, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +cmpsd, 3, 0xf2c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpsd, 3, 0xf20fc2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +comisd, 2, 0x662f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } comisd, 2, 0x660f2f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtpi2pd, 2, 0x660f2a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } +cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +divpd, 2, 0x665e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } divpd, 2, 0x660f5e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divsd, 2, 0xf25e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } divsd, 2, 0xf20f5e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxpd, 2, 0x665f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } maxpd, 2, 0x660f5f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxsd, 2, 0xf25f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } maxsd, 2, 0xf20f5f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minpd, 2, 0x665d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } minpd, 2, 0x660f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minsd, 2, 0xf25d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } minsd, 2, 0xf20f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movapd, 2, 0x660f28, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movapd, 2, 0x660f29, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movhpd, 2, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } movhpd, 2, 0x660f16, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } movhpd, 2, 0x660f17, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movlpd, 2, 0x6612, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } movlpd, 2, 0x660f12, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } movlpd, 2, 0x660f13, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 } movmskpd, 2, 0x660f50, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +movntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } movntpd, 2, 0x660f2b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } // Intel mode string move. movsd, 0, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 } movsd, 2, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } movsd, 2, 0xf20f10, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movupd, 2, 0x6610, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movupd, 2, 0x660f10, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movupd, 2, 0x660f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +mulpd, 2, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mulpd, 2, 0x660f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulsd, 2, 0xf259, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mulsd, 2, 0xf20f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +orpd, 2, 0x6656, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } orpd, 2, 0x660f56, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +shufpd, 3, 0x66c6, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } shufpd, 3, 0x660fc6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } sqrtpd, 2, 0x660f51, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtsd, 2, 0xf251, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } sqrtsd, 2, 0xf20f51, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subpd, 2, 0x665c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } subpd, 2, 0x660f5c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subsd, 2, 0xf25c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } subsd, 2, 0xf20f5c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ucomisd, 2, 0x662e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ucomisd, 2, 0x660f2e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpckhpd, 2, 0x6615, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } unpckhpd, 2, 0x660f15, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpcklpd, 2, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } unpcklpd, 2, 0x660f14, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +xorpd, 2, 0x6657, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } xorpd, 2, 0x660f57, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtdq2pd, 2, 0xf30fe6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtpd2dq, 2, 0xf20fe6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtdq2ps, 2, 0xf5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtpd2pi, 2, 0x660f2d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtpd2ps, 2, 0x660f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtps2pd, 2, 0xf5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtps2dq, 2, 0x660f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtsd2si, 2, 0xf22d, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } cvtsd2si, 2, 0xf20f2d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvtsd2ss, 2, 0xf25a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtsd2ss, 2, 0xf20f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtss2sd, 2, 0xf35a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvtss2sd, 2, 0xf30f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvttpd2pi, 2, 0x660f2c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvttsd2si, 2, 0xf22c, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } cvttsd2si, 2, 0xf20f2c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvttpd2dq, 2, 0x660fe6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cvttps2dq, 2, 0xf30f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } maskmovdqu, 2, 0x660ff7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +movdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdqa, 2, 0x660f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqa, 2, 0x660f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegMMX } movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, RegXMM } -pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0x660ff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pshufd, 3, 0x6670, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pshufd, 3, 0x660f70, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufhw, 3, 0xf370, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pshufhw, 3, 0xf30f70, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshuflw, 3, 0xf270, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pshuflw, 3, 0xf20f70, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pslldq, 2, 0x6673, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } pslldq, 2, 0x660f73, 0x7, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psrldq, 2, 0x6673, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } psrldq, 2, 0x660f73, 0x3, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +punpckhqdq, 2, 0x666d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } punpckhqdq, 2, 0x660f6d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklqdq, 2, 0x666c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } punpcklqdq, 2, 0x660f6c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } // SSE3 instructions. +addsubpd, 2, 0x66d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addsubpd, 2, 0x660fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsubps, 2, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addsubps, 2, 0xf20fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } cmpxchg16b, 1, 0xfc7, 0x1, 2, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Oword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } fisttp, 1, 0xdf, 0x1, 1, CpuSSE3, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } fisttp, 1, 0xdd, 0x1, 1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } fisttpll, 1, 0xdd, 0x1, 1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +haddpd, 2, 0x667c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } haddpd, 2, 0x660f7c, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +haddps, 2, 0xf27c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } haddps, 2, 0xf20f7c, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +hsubpd, 2, 0x667d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } hsubpd, 2, 0x660f7d, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +hsubps, 2, 0xf27d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } hsubps, 2, 0xf20f7d, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +lddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } lddqu, 2, 0xf20ff0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } monitor, 0, 0xf01, 0xc8, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } // monitor is very special. CX and DX are always 64bits with zero upper @@ -1275,8 +1498,11 @@ monitor, 0, 0xf01, 0xc8, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0, { Reg16|Reg32, Reg32, Reg32 } // Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg64, Reg64 } +movddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movddup, 2, 0xf20f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movshdup, 2, 0xf30f16, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movsldup, 2, 0xf30f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mwait, 0, 0xf01, 0xc9, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } // mwait is very special. AX and CX are always 64bits with zero upper @@ -1307,99 +1533,171 @@ getsec, 0, 0xf37, None, 2, CpuSMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld // SSSE3 instructions. -phaddw, 2, 0xf3801, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddw, 2, 0x6601, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } phaddw, 2, 0x660f3801, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -phaddd, 2, 0xf3802, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddw, 2, 0xf3801, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddd, 2, 0x6602, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } phaddd, 2, 0x660f3802, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -phaddsw, 2, 0xf3803, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddd, 2, 0xf3802, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddsw, 2, 0x6603, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } phaddsw, 2, 0x660f3803, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -phsubw, 2, 0xf3805, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddsw, 2, 0xf3803, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubw, 2, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } phsubw, 2, 0x660f3805, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -phsubd, 2, 0xf3806, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubw, 2, 0xf3805, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubd, 2, 0x6606, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } phsubd, 2, 0x660f3806, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -phsubsw, 2, 0xf3807, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubd, 2, 0xf3806, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubsw, 2, 0x6607, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } phsubsw, 2, 0x660f3807, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pmaddubsw, 2, 0xf3804, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubsw, 2, 0xf3807, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaddubsw, 2, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmaddubsw, 2, 0x660f3804, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pmulhrsw, 2, 0xf380b, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaddubsw, 2, 0xf3804, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhrsw, 2, 0x660b, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmulhrsw, 2, 0x660f380b, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pshufb, 2, 0xf3800, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhrsw, 2, 0xf380b, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pshufb, 2, 0x6600, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pshufb, 2, 0x660f3800, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psignb, 2, 0xf3808, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pshufb, 2, 0xf3800, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignb, 2, 0x6608, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psignb, 2, 0x660f3808, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psignw, 2, 0xf3809, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignb, 2, 0xf3808, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignw, 2, 0x6609, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psignw, 2, 0x660f3809, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -psignd, 2, 0xf380a, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignw, 2, 0xf3809, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignd, 2, 0x660a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } psignd, 2, 0x660f380a, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -palignr, 3, 0xf3a0f, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignd, 2, 0xf380a, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +palignr, 3, 0x660f, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } palignr, 3, 0x660f3a0f, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pabsb, 2, 0xf381c, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +palignr, 3, 0xf3a0f, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsb, 2, 0x661c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pabsb, 2, 0x660f381c, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pabsw, 2, 0xf381d, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsb, 2, 0xf381c, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsw, 2, 0x661d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pabsw, 2, 0x660f381d, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pabsd, 2, 0xf381e, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsw, 2, 0xf381d, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsd, 2, 0x661e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pabsd, 2, 0x660f381e, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsd, 2, 0xf381e, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } // SSE4.1 instructions. +blendpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } blendpd, 3, 0x660f3a0d, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } blendps, 3, 0x660f3a0c, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvpd, 3, 0x664b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvpd, 2, 0x664b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } blendvpd, 3, 0x660f3815, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } blendvpd, 2, 0x660f3815, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvps, 3, 0x664a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvps, 2, 0x664a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } blendvps, 3, 0x660f3814, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } blendvps, 2, 0x660f3814, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +dppd, 3, 0x6641, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } dppd, 3, 0x660f3a41, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +dpps, 3, 0x6640, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } dpps, 3, 0x660f3a40, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +extractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +insertps, 3, 0x6621, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } insertps, 3, 0x660f3a21, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } movntdqa, 2, 0x660f382a, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +mpsadbw, 3, 0x6642, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mpsadbw, 3, 0x660f3a42, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packusdw, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } packusdw, 2, 0x660f382b, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendvb, 3, 0x664c, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendvb, 2, 0x664c, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pblendvb, 3, 0x660f3810, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pblendvb, 2, 0x660f3810, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendw, 3, 0x660e, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pblendw, 3, 0x660f3a0e, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqq, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpeqq, 2, 0x660f3829, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } pextrd, 3, 0x660f3a16, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F3A|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } pextrq, 3, 0x660f3a16, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +phminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } phminposuw, 2, 0x660f3841, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrd, 3, 0x6622, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } pinsrd, 3, 0x660f3a22, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrq, 3, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F3A|Size64|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } pinsrq, 3, 0x660f3a22, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +pmaxsb, 2, 0x663c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmaxsb, 2, 0x660f383c, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxsd, 2, 0x663d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmaxsd, 2, 0x660f383d, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxud, 2, 0x663f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmaxud, 2, 0x660f383f, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxuw, 2, 0x663e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmaxuw, 2, 0x660f383e, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsb, 2, 0x6638, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pminsb, 2, 0x660f3838, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsd, 2, 0x6639, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pminsd, 2, 0x660f3839, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminud, 2, 0x663b, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pminud, 2, 0x660f383b, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminuw, 2, 0x663a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pminuw, 2, 0x660f383a, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovsxbw, 2, 0x660f3820, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbd, 2, 0x6621, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovsxbd, 2, 0x660f3821, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbq, 2, 0x6622, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovsxbq, 2, 0x660f3822, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxwd, 2, 0x6623, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovsxwd, 2, 0x660f3823, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxwq, 2, 0x6624, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovsxwq, 2, 0x660f3824, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxdq, 2, 0x6625, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovsxdq, 2, 0x660f3825, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbw, 2, 0x6630, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovzxbw, 2, 0x660f3830, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbd, 2, 0x6631, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovzxbd, 2, 0x660f3831, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbq, 2, 0x6632, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovzxbq, 2, 0x660f3832, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovzxwd, 2, 0x660f3833, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxwq, 2, 0x6634, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovzxwq, 2, 0x660f3834, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxdq, 2, 0x6635, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmovzxdq, 2, 0x660f3835, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmuldq, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuldq, 2, 0x660f3828, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulld, 2, 0x6640, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmulld, 2, 0x660f3840, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ptest, 2, 0x660f3817, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } roundpd, 3, 0x660f3a09, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } roundps, 3, 0x660f3a08, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundsd, 3, 0x660b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } roundsd, 3, 0x660f3a0b, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundss, 3, 0x660a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } roundss, 3, 0x660f3a0a, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } // SSE4.2 instructions. +pcmpgtq, 2, 0x6637, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpgtq, 2, 0x660f3837, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpestri, 3, 0x6661, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpestri, 3, 0x660f3a61, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpestrm, 3, 0x6660, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpestrm, 3, 0x660f3a60, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpistri, 3, 0x660f3a63, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pcmpistrm, 3, 0x660f3a62, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } // We put non-8bit version before 8bit so that crc32 with memory operand // defaults to non-8bit. @@ -1415,6 +1713,702 @@ xrstor, 1, 0xfae, 0x5, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldS xgetbv, 0, 0xf01, 0xd0, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } xsetbv, 0, 0xf01, 0xd1, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +// AES instructions. + +aesdec, 2, 0x660f38de, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesdeclast, 2, 0x660f38df, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesenc, 2, 0x660f38dc, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesenclast, 2, 0x660f38dd, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesimc, 2, 0x660f38db, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aeskeygenassist, 3, 0x660f3adf, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// CLMUL + +pclmulqdq, 3, 0x660f3a44, None, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// AVX instructions. + +// We add Imm8 to Vex_Imm4. We use Imm8 to indicate that the operand +// is an immediate. We will check if its value will fit 4 bits. + +vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vaddsd, 3, 0xf258, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddss, 3, 0xf358, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddsubpd, 3, 0x66d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddsubpd, 3, 0x66d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vaddsubps, 3, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddsubps, 3, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vandnpd, 3, 0x6655, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vandnpd, 3, 0x6655, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vandnps, 3, 0x55, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vandnps, 3, 0x55, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vandps, 3, 0x54, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vandps, 3, 0x54, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vblendpd, 4, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vblendpd, 4, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vblendps, 4, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vblendps, 4, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vblendvpd, 4, 0x664b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vblendvpd, 4, 0x664b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|Vex3Sources|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|Vex3Sources|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vbroadcastf128, 2, 0x661a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM } +vbroadcastsd, 2, 0x6619, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM } +vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM } +vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_ossd, 3, 0xf2c2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_osss, 3, 0xf3c2, 0x10, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeqsd, 3, 0xf2c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeqss, 3, 0xf3c2, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_uqsd, 3, 0xf2c2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uqss, 3, 0xf3c2, 0x8, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_ussd, 3, 0xf2c2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_usss, 3, 0xf3c2, 0x18, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpfalse_ossd, 3, 0xf2c2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalse_osss, 3, 0xf3c2, 0x1b, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpfalsesd, 3, 0xf2c2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalsess, 3, 0xf3c2, 0xb, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpge_oqsd, 3, 0xf2c2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpge_oqss, 3, 0xf3c2, 0x1d, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgepd, 3, 0x66c2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgepd, 3, 0x66c2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgeps, 3, 0xc2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgeps, 3, 0xc2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgesd, 3, 0xf2c2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgess, 3, 0xf3c2, 0xd, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgt_oqpd, 3, 0x66c2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgt_oqpd, 3, 0x66c2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgt_oqps, 3, 0xc2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgt_oqps, 3, 0xc2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgt_oqsd, 3, 0xf2c2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgt_oqss, 3, 0xf3c2, 0x1e, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgtpd, 3, 0x66c2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgtpd, 3, 0x66c2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgtps, 3, 0xc2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgtps, 3, 0xc2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgtsd, 3, 0xf2c2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgtss, 3, 0xf3c2, 0xe, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmple_oqpd, 3, 0x66c2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmple_oqpd, 3, 0x66c2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmple_oqps, 3, 0xc2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmple_oqps, 3, 0xc2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmple_oqsd, 3, 0xf2c2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmple_oqss, 3, 0xf3c2, 0x12, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplepd, 3, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplepd, 3, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpleps, 3, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpleps, 3, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmplesd, 3, 0xf2c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpless, 3, 0xf3c2, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplt_oqpd, 3, 0x66c2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplt_oqpd, 3, 0x66c2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmplt_oqps, 3, 0xc2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplt_oqps, 3, 0xc2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmplt_oqsd, 3, 0xf2c2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplt_oqss, 3, 0xf3c2, 0x11, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpltsd, 3, 0xf2c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpltss, 3, 0xf3c2, 0x1, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_oqsd, 3, 0xf2c2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_oqss, 3, 0xf3c2, 0xc, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_ossd, 3, 0xf2c2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_osss, 3, 0xf3c2, 0x1c, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneqsd, 3, 0xf2c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneqss, 3, 0xf3c2, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_ussd, 3, 0xf2c2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_usss, 3, 0xf3c2, 0x14, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngesd, 3, 0xf2c2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngess, 3, 0xf3c2, 0x9, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnge_uqpd, 3, 0x66c2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnge_uqpd, 3, 0x66c2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnge_uqps, 3, 0xc2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnge_uqps, 3, 0xc2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnge_uqsd, 3, 0xf2c2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnge_uqss, 3, 0xf3c2, 0x19, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngtpd, 3, 0x66c2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngtpd, 3, 0x66c2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngtps, 3, 0xc2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngtps, 3, 0xc2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngtsd, 3, 0xf2c2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngtss, 3, 0xf3c2, 0xa, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngt_uqpd, 3, 0x66c2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngt_uqpd, 3, 0x66c2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngt_uqps, 3, 0xc2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngt_uqps, 3, 0xc2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngt_uqsd, 3, 0xf2c2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngt_uqss, 3, 0xf3c2, 0x1a, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlepd, 3, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlepd, 3, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnleps, 3, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnleps, 3, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnlesd, 3, 0xf2c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnless, 3, 0xf3c2, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnle_uqpd, 3, 0x66c2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnle_uqpd, 3, 0x66c2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnle_uqps, 3, 0xc2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnle_uqps, 3, 0xc2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnle_uqsd, 3, 0xf2c2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnle_uqss, 3, 0xf3c2, 0x16, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnltpd, 3, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnltpd, 3, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnltps, 3, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnltps, 3, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnltsd, 3, 0xf2c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnltss, 3, 0xf3c2, 0x5, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnlt_uqsd, 3, 0xf2c2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlt_uqss, 3, 0xf3c2, 0x15, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpordsd, 3, 0xf2c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpordss, 3, 0xf3c2, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_ssd, 3, 0xf2c2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_sss, 3, 0xf3c2, 0x17, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpsd, 4, 0xf2c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpss, 4, 0xf3c2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmptruesd, 3, 0xf2c2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptruess, 3, 0xf3c2, 0xf, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmptrue_ussd, 3, 0xf2c2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrue_usss, 3, 0xf3c2, 0x1f, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpunordsd, 3, 0xf2c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpunordss, 3, 0xf3c2, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_ssd, 3, 0xf2c2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_sss, 3, 0xf3c2, 0x13, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcomisd, 2, 0x662f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcomiss, 2, 0x2f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM } +vcvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM } +vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvtpd2dqx, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtpd2dqy, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM } +vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM } +vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvtpd2psx, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtpd2psy, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM } +vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM } +vcvtsd2si, 2, 0xf22d, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +vcvtsd2ss, 3, 0xf25a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcvtsi2sd, 3, 0xf22a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vcvtsi2ss, 3, 0xf32a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vcvtss2sd, 3, 0xf35a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Intelsyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM } +vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Intelsyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvttpd2dqx, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvttpd2dqy, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM } +vcvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vcvttsd2si, 2, 0xf22c, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +vcvttss2si, 2, 0xf32c, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +vdivpd, 3, 0x665e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdivpd, 3, 0x665e, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vdivps, 3, 0x5e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdivps, 3, 0x5e, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vdivsd, 3, 0xf25e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdivss, 3, 0xf35e, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdppd, 4, 0x6641, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vextractf128, 3, 0x6619, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vextractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vhsubpd, 3, 0x667d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vhsubpd, 3, 0x667d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vhsubps, 3, 0xf27d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vhsubps, 3, 0xf27d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vinsertf128, 4, 0x6618, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM, RegYMM } +vinsertps, 4, 0x6621, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vlddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vlddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM } +vldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +vmaskmovpd, 3, 0x662f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovpd, 3, 0x662f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovpd, 3, 0x662d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmaskmovpd, 3, 0x662d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM } +vmaskmovps, 3, 0x662e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovps, 3, 0x662e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovps, 3, 0x662c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmaskmovps, 3, 0x662c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM } +vmaxpd, 3, 0x665f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmaxpd, 3, 0x665f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vmaxps, 3, 0x5f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmaxps, 3, 0x5f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vmaxsd, 3, 0xf25f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmaxss, 3, 0xf35f, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vminpd, 3, 0x665d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vminpd, 3, 0x665d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vminsd, 3, 0xf25d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vminss, 3, 0xf35d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmovapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovhlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovhpd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmovhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovhps, 3, 0x16, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmovhps, 2, 0x17, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovlhps, 3, 0x16, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovlpd, 3, 0x6612, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmovlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmovlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 } +vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 } +vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovq, 2, 0xf37e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +vmovq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +vmovsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vmovsd, 3, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vmovss, 3, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovupd, 2, 0x6610, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovupd, 2, 0x6610, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovups, 2, 0x10, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovups, 2, 0x10, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vmulsd, 3, 0xf259, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmulss, 3, 0xf359, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vorps, 3, 0x56, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vorps, 3, 0x56, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpabsb, 2, 0x661c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpabsd, 2, 0x661e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpabsw, 2, 0x661d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpackssdw, 3, 0x666b, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpacksswb, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpackusdw, 3, 0x662b, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpackuswb, 3, 0x6667, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddsb, 3, 0x66ec, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddsw, 3, 0x66ed, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddb, 3, 0x66fc, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddd, 3, 0x66fe, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddq, 3, 0x66d4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddw, 3, 0x66fd, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddusb, 3, 0x66dc, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddusw, 3, 0x66dd, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpalignr, 4, 0x660f, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpand, 3, 0x66db, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpandn, 3, 0x66df, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpavgb, 3, 0x66e0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpavgw, 3, 0x66e3, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpblendvb, 4, 0x664c, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpblendw, 4, 0x660e, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpeqb, 3, 0x6674, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpeqd, 3, 0x6676, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpeqq, 3, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpeqw, 3, 0x6675, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpestri, 3, 0x6661, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpcmpestrm, 3, 0x6660, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpcmpgtb, 3, 0x6664, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpgtd, 3, 0x6666, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpgtq, 3, 0x6637, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpgtw, 3, 0x6665, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vperm2f128, 4, 0x6606, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F3A|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +vpextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } +vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vphaddd, 3, 0x6602, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphaddsw, 3, 0x6603, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphaddw, 3, 0x6601, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vphsubd, 3, 0x6606, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphsubsw, 3, 0x6607, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphsubw, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpinsrd, 4, 0x6622, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpinsrq, 4, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F3A|Size64|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM, RegXMM } +vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpmaddubsw, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaddwd, 3, 0x66f5, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxsb, 3, 0x663c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxsd, 3, 0x663d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxsw, 3, 0x66ee, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxub, 3, 0x66de, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxud, 3, 0x663f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxuw, 3, 0x663e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminsb, 3, 0x6638, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminsd, 3, 0x6639, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminsw, 3, 0x66ea, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminub, 3, 0x66da, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminud, 3, 0x663b, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminuw, 3, 0x663a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +vpmovsxbd, 2, 0x6621, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxbq, 2, 0x6622, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxdq, 2, 0x6625, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxwd, 2, 0x6623, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxwq, 2, 0x6624, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxbd, 2, 0x6631, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxbq, 2, 0x6632, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxbw, 2, 0x6630, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxdq, 2, 0x6635, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxwq, 2, 0x6634, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmuldq, 3, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmulhrsw, 3, 0x660b, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmulhuw, 3, 0x66e4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmulhw, 3, 0x66e5, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmulld, 3, 0x6640, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmullw, 3, 0x66d5, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmuludq, 3, 0x66f4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpor, 3, 0x66eb, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsadbw, 3, 0x66f6, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpshufb, 3, 0x6600, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpshufd, 3, 0x6670, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpshufhw, 3, 0xf370, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpshuflw, 3, 0xf270, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpsignb, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsignd, 3, 0x660a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsignw, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpslld, 3, 0x6672, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpslld, 3, 0x66f2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpslldq, 3, 0x6673, 0x7, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsllq, 3, 0x6673, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsllq, 3, 0x66f3, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsllw, 3, 0x6671, 0x6, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsllw, 3, 0x66f1, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsrad, 3, 0x6672, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrad, 3, 0x66e2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsraw, 3, 0x6671, 0x4, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsraw, 3, 0x66e1, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsrld, 3, 0x6672, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrld, 3, 0x66d2, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsrldq, 3, 0x6673, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrlq, 3, 0x6673, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrlq, 3, 0x66d3, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsrlw, 3, 0x6671, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDD|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrlw, 3, 0x66d1, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubb, 3, 0x66f8, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubd, 3, 0x66fa, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubq, 3, 0x66fb, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubsb, 3, 0x66e8, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubsw, 3, 0x66e9, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubusb, 3, 0x66d8, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubusw, 3, 0x66d9, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubw, 3, 0x66f9, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vpunpckhbw, 3, 0x6668, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpckhdq, 3, 0x666a, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpckhqdq, 3, 0x666d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpckhwd, 3, 0x6669, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpcklbw, 3, 0x6660, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpckldq, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpcklqdq, 3, 0x666c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpcklwd, 3, 0x6661, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpxor, 3, 0x66ef, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vrcpss, 3, 0xf353, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vroundsd, 4, 0x660b, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vroundss, 4, 0x660a, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vrsqrtss, 3, 0xf352, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vshufpd, 4, 0x66c6, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vshufpd, 4, 0x66c6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vshufps, 4, 0xc6, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vshufps, 4, 0xc6, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vsqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vsqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vsqrtsd, 3, 0xf251, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vsqrtss, 3, 0xf351, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vstmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vsubpd, 3, 0x665c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vsubpd, 3, 0x665c, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vsubps, 3, 0x5c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vsubps, 3, 0x5c, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vsubsd, 3, 0xf25c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vsubss, 3, 0xf35c, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vtestpd, 2, 0x660f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vtestpd, 2, 0x660f, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vtestps, 2, 0x660e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vtestps, 2, 0x660e, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vucomisd, 2, 0x662e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vucomiss, 2, 0x2e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vunpckhpd, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vunpckhpd, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vunpckhps, 3, 0x15, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vunpckhps, 3, 0x15, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vunpcklpd, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vunpcklpd, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vunpcklps, 3, 0x14, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vunpcklps, 3, 0x14, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vzeroall, 0, 0x77, None, 1, CpuAVX, Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +vzeroupper, 0, 0x77, None, 1, CpuAVX, Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + + + + + +// FMA instructions + +vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsd, 4, 0x666b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsd, 4, 0x666b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddss, 4, 0x666a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddss, 4, 0x666a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubsd, 4, 0x666f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubsd, 4, 0x666f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubss, 4, 0x666e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubss, 4, 0x666e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmaddsd, 4, 0x667b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddsd, 4, 0x667b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmaddss, 4, 0x667a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddss, 4, 0x667a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsubsd, 4, 0x667f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubsd, 4, 0x667f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsubss, 4, 0x667e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubss, 4, 0x667e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } + // AMD 3DNow! instructions. prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 6aa89fc..c88a9e0 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -188,6 +188,23 @@ xmm12, RegXMM, RegRex, 4, Dw2Inval, 29 xmm13, RegXMM, RegRex, 5, Dw2Inval, 30 xmm14, RegXMM, RegRex, 6, Dw2Inval, 31 xmm15, RegXMM, RegRex, 7, Dw2Inval, 32 +// AVX registers. +ymm0, RegYMM, 0, 0, 53, 70 +ymm1, RegYMM, 0, 1, 54, 71 +ymm2, RegYMM, 0, 2, 55, 72 +ymm3, RegYMM, 0, 3, 56, 73 +ymm4, RegYMM, 0, 4, 57, 74 +ymm5, RegYMM, 0, 5, 58, 75 +ymm6, RegYMM, 0, 6, 59, 76 +ymm7, RegYMM, 0, 7, 60, 77 +ymm8, RegYMM, RegRex, 0, Dw2Inval, 78 +ymm9, RegYMM, RegRex, 1, Dw2Inval, 79 +ymm10, RegYMM, RegRex, 2, Dw2Inval, 80 +ymm11, RegYMM, RegRex, 3, Dw2Inval, 81 +ymm12, RegYMM, RegRex, 4, Dw2Inval, 82 +ymm13, RegYMM, RegRex, 5, Dw2Inval, 83 +ymm14, RegYMM, RegRex, 6, Dw2Inval, 84 +ymm15, RegYMM, RegRex, 7, Dw2Inval, 85 // No type will make these registers rejected for all purposes except // for addressing. This saves creating one extra type for RIP/EIP. rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16 diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 3ca4bed..9523785 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -24,16966 +24,30838 @@ const template i386_optab[] = { { "mov", 2, 0xa0, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, - 1, 0, 0 } }, + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } } } }, { "mov", 2, 0xa0, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, - 1, 0, 0 } }, + 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, { "mov", 2, 0x88, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, - { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, - 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, - 1, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } } } }, { "mov", 2, 0xb0, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } } } }, { "mov", 2, 0xc6, 0x0, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, - { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, - 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, - 1, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } } } }, { "mov", 2, 0xb0, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } } } }, { "mov", 2, 0x8c, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, { "mov", 2, 0x8c, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, - 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 1, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } } } }, { "mov", 2, 0x8c, None, 1, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 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1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } } } }, + { "vmovq", 2, 0xf37e, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 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1, 0, 0 } }, + { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vmovq", 2, 0x667e, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0 } }, + { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 1, 0, 0, 0, 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0, 0, 0 } }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } } } }, { "xcryptcbc", 0, 0xf30fa7, 0xd0, 2, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } } } }, { "xcryptctr", 0, 0xf30fa7, 0xd8, 2, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } } } }, { "xcryptcfb", 0, 0xf30fa7, 0xe0, 2, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } } } }, { "xcryptofb", 0, 0xf30fa7, 0xe8, 2, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } } } }, { "xstore", 0, 0xfa7, 0xc0, 2, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } }, + 0, 0, 0, 0, 0, 0 } } } }, { NULL, 0, 0, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } } } } + 0, 0, 0, 0, 0, 0 } } } } }; /* i386 register table. */ @@ -16992,948 +30864,1028 @@ const reg_entry i386_regtab[] = { { "st", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 11, 33 } }, { "al", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { Dw2Inval, Dw2Inval } }, { "cl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { Dw2Inval, Dw2Inval } }, { "dl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { Dw2Inval, Dw2Inval } }, { "bl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { Dw2Inval, Dw2Inval } }, { "ah", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { Dw2Inval, Dw2Inval } }, { "ch", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { Dw2Inval, Dw2Inval } }, { "dh", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { Dw2Inval, Dw2Inval } }, { "bh", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { Dw2Inval, Dw2Inval } }, { "axl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex64, 0, { Dw2Inval, Dw2Inval } }, { "cxl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex64, 1, { Dw2Inval, Dw2Inval } }, { "dxl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex64, 2, { Dw2Inval, Dw2Inval } }, { "bxl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex64, 3, { Dw2Inval, Dw2Inval } }, { "spl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex64, 4, { Dw2Inval, Dw2Inval } }, { "bpl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex64, 5, { Dw2Inval, Dw2Inval } }, { "sil", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex64, 6, { Dw2Inval, Dw2Inval } }, { "dil", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex64, 7, { Dw2Inval, Dw2Inval } }, { "r8b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex|RegRex64, 0, { Dw2Inval, Dw2Inval } }, { "r9b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex|RegRex64, 1, { Dw2Inval, Dw2Inval } }, { "r10b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex|RegRex64, 2, { Dw2Inval, Dw2Inval } }, { "r11b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex|RegRex64, 3, { Dw2Inval, Dw2Inval } }, { "r12b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex|RegRex64, 4, { Dw2Inval, Dw2Inval } }, { "r13b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex|RegRex64, 5, { Dw2Inval, Dw2Inval } }, { "r14b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex|RegRex64, 6, { Dw2Inval, Dw2Inval } }, { "r15b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex|RegRex64, 7, { Dw2Inval, Dw2Inval } }, { "ax", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { Dw2Inval, Dw2Inval } }, { "cx", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { Dw2Inval, Dw2Inval } }, { "dx", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { Dw2Inval, Dw2Inval } }, { "bx", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { Dw2Inval, Dw2Inval } }, { "sp", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { Dw2Inval, Dw2Inval } }, { "bp", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { Dw2Inval, Dw2Inval } }, { "si", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { Dw2Inval, Dw2Inval } }, { "di", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { Dw2Inval, Dw2Inval } }, { "r8w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 0, { Dw2Inval, Dw2Inval } }, { "r9w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 1, { Dw2Inval, Dw2Inval } }, { "r10w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 2, { Dw2Inval, Dw2Inval } }, { "r11w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 3, { Dw2Inval, Dw2Inval } }, { "r12w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 4, { Dw2Inval, Dw2Inval } }, { "r13w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 5, { Dw2Inval, Dw2Inval } }, { "r14w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 6, { Dw2Inval, Dw2Inval } }, { "r15w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 7, { Dw2Inval, Dw2Inval } }, { "eax", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 0, Dw2Inval } }, { "ecx", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { 1, Dw2Inval } }, { "edx", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { 2, Dw2Inval } }, { "ebx", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { 3, Dw2Inval } }, { "esp", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { 4, Dw2Inval } }, { "ebp", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { 5, Dw2Inval } }, { "esi", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { 6, Dw2Inval } }, { "edi", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { 7, Dw2Inval } }, { "r8d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 0, { Dw2Inval, Dw2Inval } }, { "r9d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 1, { Dw2Inval, Dw2Inval } }, { "r10d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 2, { Dw2Inval, Dw2Inval } }, { "r11d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 3, { Dw2Inval, Dw2Inval } }, { "r12d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 4, { Dw2Inval, Dw2Inval } }, { "r13d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 5, { Dw2Inval, Dw2Inval } }, { "r14d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 6, { Dw2Inval, Dw2Inval } }, { "r15d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 7, { Dw2Inval, Dw2Inval } }, { "rax", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { Dw2Inval, 0 } }, { "rcx", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { Dw2Inval, 2 } }, { "rdx", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { Dw2Inval, 1 } }, { "rbx", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { Dw2Inval, 3 } }, { "rsp", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { Dw2Inval, 7 } }, { "rbp", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { Dw2Inval, 6 } }, { "rsi", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { Dw2Inval, 4 } }, { "rdi", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { Dw2Inval, 5 } }, { "r8", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 0, { Dw2Inval, 8 } }, { "r9", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 1, { Dw2Inval, 9 } }, { "r10", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 2, { Dw2Inval, 10 } }, { "r11", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 3, { Dw2Inval, 11 } }, { "r12", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 4, { Dw2Inval, 12 } }, { "r13", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 5, { Dw2Inval, 13 } }, { "r14", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 6, { Dw2Inval, 14 } }, { "r15", { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex, 7, { Dw2Inval, 15 } }, { "es", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 40, 50 } }, { "cs", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 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Dw2Inval } }, { "cr2", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { Dw2Inval, Dw2Inval } }, { "cr3", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { Dw2Inval, Dw2Inval } }, { "cr4", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { Dw2Inval, Dw2Inval } }, { "cr5", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { Dw2Inval, Dw2Inval } }, { "cr6", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { Dw2Inval, Dw2Inval } }, { "cr7", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { Dw2Inval, Dw2Inval } }, { "cr8", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 0, { Dw2Inval, Dw2Inval } }, { "cr9", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 1, { Dw2Inval, Dw2Inval } }, { "cr10", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 2, { Dw2Inval, Dw2Inval } }, { "cr11", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 3, { Dw2Inval, Dw2Inval } }, { "cr12", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 4, { Dw2Inval, Dw2Inval } }, { "cr13", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 5, { Dw2Inval, Dw2Inval } }, { "cr14", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 6, { Dw2Inval, Dw2Inval } }, { "cr15", - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 7, { Dw2Inval, Dw2Inval } }, { "db0", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { Dw2Inval, Dw2Inval } }, { "db1", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { Dw2Inval, Dw2Inval } }, { "db2", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { Dw2Inval, Dw2Inval } }, { "db3", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { Dw2Inval, Dw2Inval } }, { "db4", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { Dw2Inval, Dw2Inval } }, { "db5", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { Dw2Inval, Dw2Inval } }, { "db6", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { Dw2Inval, Dw2Inval } }, { "db7", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { Dw2Inval, Dw2Inval } }, { "db8", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 0, { Dw2Inval, Dw2Inval } }, { "db9", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 1, { Dw2Inval, Dw2Inval } }, { "db10", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 2, { Dw2Inval, Dw2Inval } }, { "db11", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 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0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { Dw2Inval, Dw2Inval } }, { "dr3", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { Dw2Inval, Dw2Inval } }, { "dr4", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { Dw2Inval, Dw2Inval } }, { "dr5", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { Dw2Inval, Dw2Inval } }, { "dr6", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { Dw2Inval, Dw2Inval } }, { "dr7", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { Dw2Inval, Dw2Inval } }, { "dr8", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 0, { Dw2Inval, Dw2Inval } }, { "dr9", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 1, { Dw2Inval, Dw2Inval } }, { "dr10", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 2, { Dw2Inval, Dw2Inval } }, { "dr11", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 3, { Dw2Inval, Dw2Inval } }, { "dr12", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 4, { Dw2Inval, Dw2Inval } }, { "dr13", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 5, { Dw2Inval, Dw2Inval } }, { "dr14", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 6, { Dw2Inval, Dw2Inval } }, { "dr15", - { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 7, { Dw2Inval, Dw2Inval } }, { "tr0", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { Dw2Inval, Dw2Inval } }, { "tr1", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { Dw2Inval, Dw2Inval } }, { "tr2", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { Dw2Inval, Dw2Inval } }, { "tr3", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { Dw2Inval, Dw2Inval } }, { "tr4", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { Dw2Inval, Dw2Inval } }, { "tr5", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { Dw2Inval, Dw2Inval } }, { "tr6", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { Dw2Inval, Dw2Inval } }, { "tr7", - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { Dw2Inval, Dw2Inval } }, { "mm0", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 29, 41 } }, { "mm1", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { 30, 42 } }, { "mm2", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { 31, 43 } }, { "mm3", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { 32, 44 } }, { "mm4", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { 33, 45 } }, { "mm5", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { 34, 46 } }, { "mm6", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { 35, 47 } }, { "mm7", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { 36, 48 } }, { "xmm0", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 21, 17 } }, { "xmm1", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { 22, 18 } }, { "xmm2", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { 23, 19 } }, { "xmm3", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { 24, 20 } }, { "xmm4", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { 25, 21 } }, { "xmm5", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { 26, 22 } }, { "xmm6", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { 27, 23 } }, { "xmm7", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { 28, 24 } }, { "xmm8", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 0, { Dw2Inval, 25 } }, { "xmm9", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 1, { Dw2Inval, 26 } }, { "xmm10", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 2, { Dw2Inval, 27 } }, { "xmm11", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 3, { Dw2Inval, 28 } }, { "xmm12", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 4, { Dw2Inval, 29 } }, { "xmm13", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 5, { Dw2Inval, 30 } }, { "xmm14", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 6, { Dw2Inval, 31 } }, { "xmm15", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, RegRex, 7, { Dw2Inval, 32 } }, + { "ymm0", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 53, 70 } }, + { "ymm1", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { 54, 71 } }, + { "ymm2", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { 55, 72 } }, + { "ymm3", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { 56, 73 } }, + { "ymm4", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { 57, 74 } }, + { "ymm5", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { 58, 75 } }, + { "ymm6", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { 59, 76 } }, + { "ymm7", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { 60, 77 } }, + { "ymm8", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, 78 } }, + { "ymm9", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, 79 } }, + { "ymm10", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, 80 } }, + { "ymm11", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, 81 } }, + { "ymm12", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, 82 } }, + { "ymm13", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, 83 } }, + { "ymm14", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, 84 } }, + { "ymm15", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, 85 } }, { "rip", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex64, RegRip, { Dw2Inval, 16 } }, { "eip", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, RegRex64, RegEip, { 8, Dw2Inval } }, { "eiz", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, RegEiz, { Dw2Inval, Dw2Inval } }, { "riz", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, RegRiz, { Dw2Inval, Dw2Inval } }, { "st(0)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 11, 33 } }, { "st(1)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { 12, 34 } }, { "st(2)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { 13, 35 } }, { "st(3)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { 14, 36 } }, { "st(4)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { 15, 37 } }, { "st(5)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { 16, 38 } }, { "st(6)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { 17, 39 } }, { "st(7)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { 18, 40 } }, { "eflags", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 9, 49 } }, { "rflags", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { Dw2Inval, 49 } }, { "fs.base", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { Dw2Inval, 58 } }, { "gs.base", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { Dw2Inval, 59 } }, { "tr", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 48, 62 } }, { "ldtr", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 49, 63 } }, { "st0", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 11, 33 } }, { "st1", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 1, { 12, 34 } }, { "st2", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 2, { 13, 35 } }, { "st3", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 3, { 14, 36 } }, { "st4", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 4, { 15, 37 } }, { "st5", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 5, { 16, 38 } }, { "st6", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 6, { 17, 39 } }, { "st7", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 7, { 18, 40 } }, { "fcw", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 37, 65 } }, { "fsw", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 38, 66 } }, { "mxcsr", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 } }, + 0, 0, 0, 0, 0, 0 } }, 0, 0, { 39, 64 } }, }; |