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authorMaciej W. Rozycki <macro@linux-mips.org>2012-05-18 23:12:31 +0000
committerMaciej W. Rozycki <macro@linux-mips.org>2012-05-18 23:12:31 +0000
commit02b67415e097cee626b6abf06346e5696ea8d334 (patch)
treef7bb4ddd4a8ae6c5da08b994f0a2b6ed602068cd
parent220cf8092f48bfb2f9a32ae344acb34a27a6cb03 (diff)
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* gdb.texinfo (Architecture-Specific Protocol Details): Define
nodes for subsections. Add @acronym mark-ups and adjust formatting.
-rw-r--r--gdb/doc/ChangeLog6
-rw-r--r--gdb/doc/gdb.texinfo32
2 files changed, 30 insertions, 8 deletions
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index a30b0a8..43ed045 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,9 @@
+2011-05-18 Eli Zaretskii <eliz@gnu.org>
+
+ * gdb.texinfo (Architecture-Specific Protocol Details): Define
+ nodes for subsections. Add @acronym mark-ups and adjust
+ formatting.
+
2012-05-18 Jan Kratochvil <jan.kratochvil@redhat.com>
Rename $ddir to $datadir.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 1c16eee..3515da7 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -36867,9 +36867,21 @@ This section describes how the remote protocol is applied to specific
target architectures. Also see @ref{Standard Target Features}, for
details of XML target descriptions for each architecture.
-@subsection ARM
+@menu
+* ARM-Specific Protocol Details::
+* MIPS-Specific Protocol Details::
+@end menu
+
+@node ARM-Specific Protocol Details
+@subsection @acronym{ARM}-specific Protocol Details
+
+@menu
+* ARM Breakpoint Kinds::
+@end menu
-@subsubsection Breakpoint Kinds
+@node ARM Breakpoint Kinds
+@subsubsection @acronym{ARM} Breakpoint Kinds
+@cindex breakpoint kinds, @acronym{ARM}
These breakpoint kinds are defined for the @samp{Z0} and @samp{Z1} packets.
@@ -36882,31 +36894,35 @@ These breakpoint kinds are defined for the @samp{Z0} and @samp{Z1} packets.
32-bit Thumb mode (Thumb-2) breakpoint.
@item 4
-32-bit ARM mode breakpoint.
+32-bit @acronym{ARM} mode breakpoint.
@end table
-@subsection MIPS
+@node MIPS-Specific Protocol Details
+@subsection @acronym{MIPS}-specific Protocol Details
+
+@menu
+* MIPS Register packet Format::
+@end menu
-@subsubsection Register Packet Format
+@node MIPS Register packet Format
+@subsubsection @acronym{MIPS} Register Packet Format
The following @code{g}/@code{G} packets have previously been defined.
In the below, some thirty-two bit registers are transferred as
sixty-four bits. Those registers should be zero/sign extended (which?)
to fill the space allocated. Register bytes are transferred in target
byte order. The two nibbles within a register byte are transferred
-most-significant - least-significant.
+most-significant -- least-significant.
@table @r
@item MIPS32
-
All registers are transferred as thirty-two bit quantities in the order:
32 general-purpose; sr; lo; hi; bad; cause; pc; 32 floating-point
registers; fsr; fir; fp.
@item MIPS64
-
All registers are transferred as sixty-four bit quantities (including
thirty-two bit registers such as @code{sr}). The ordering is the same
as @code{MIPS32}.