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| author | Jeff Law <law@redhat.com> | 1997-10-21 16:07:53 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1997-10-21 16:07:53 +0000 |
| commit | f4ab2b2fdcb88957359714806ea1838ab335b145 (patch) | |
| tree | 3a6752828f9e63766a5eb599189bf8325af2a066 | |
| parent | 92ad193bb04841ab7c0bc16ab9e8379f9d0f48cc (diff) | |
| download | gdb-f4ab2b2fdcb88957359714806ea1838ab335b145.zip gdb-f4ab2b2fdcb88957359714806ea1838ab335b145.tar.gz gdb-f4ab2b2fdcb88957359714806ea1838ab335b145.tar.bz2 | |
* simops.c: Correctly handle register restores for "ret" and "retf"
instructions.
pr13306 related stuff.
| -rw-r--r-- | sim/mn10300/ChangeLog | 13 | ||||
| -rw-r--r-- | sim/mn10300/simops.c | 124 |
2 files changed, 71 insertions, 66 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index fe92b59..9717037 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,16 @@ +Tue Oct 21 10:12:03 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Correctly handle register restores for "ret" and "retf" + instructions. + +Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c index c0243c2..3d82952 100644 --- a/sim/mn10300/simops.c +++ b/sim/mn10300/simops.c @@ -2709,60 +2709,57 @@ void OP_FCFF0000 (insn, extension) void OP_DF0000 (insn, extension) unsigned long insn, extension; { - unsigned int sp; + unsigned int sp, offset; unsigned long mask; State.regs[REG_SP] += insn & 0xff; sp = State.regs[REG_SP]; + offset = -4; mask = (insn & 0xff00) >> 8; - if (mask & 0x8) + if (mask & 0x80) { - sp += 4; - State.regs[REG_LAR] = load_word (sp); - sp += 4; - State.regs[REG_LIR] = load_word (sp); - sp += 4; - State.regs[REG_MDR] = load_word (sp); - sp += 4; - State.regs[REG_A0 + 1] = load_word (sp); - sp += 4; - State.regs[REG_A0] = load_word (sp); - sp += 4; - State.regs[REG_D0 + 1] = load_word (sp); - sp += 4; - State.regs[REG_D0] = load_word (sp); - sp += 4; + State.regs[REG_D0 + 2] = load_word (sp + offset); + offset -= 4; } - if (mask & 0x10) + if (mask & 0x40) { - State.regs[REG_A0 + 3] = load_word (sp); - sp += 4; + State.regs[REG_D0 + 3] = load_word (sp + offset); + offset -= 4; } if (mask & 0x20) { - State.regs[REG_A0 + 2] = load_word (sp); - sp += 4; + State.regs[REG_A0 + 2] = load_word (sp + offset); + offset -= 4; } - if (mask & 0x40) + if (mask & 0x10) { - State.regs[REG_D0 + 3] = load_word (sp); - sp += 4; + State.regs[REG_A0 + 3] = load_word (sp + offset); + offset -= 4; } - if (mask & 0x80) + if (mask & 0x8) { - State.regs[REG_D0 + 2] = load_word (sp); - sp += 4; + State.regs[REG_D0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_D0 + 1] = load_word (sp + offset); + offset -= 4; + State.regs[REG_A0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_A0 + 1] = load_word (sp + offset); + offset -= 4; + State.regs[REG_MDR] = load_word (sp + offset); + offset -= 4; + State.regs[REG_LIR] = load_word (sp + offset); + offset -= 4; + State.regs[REG_LAR] = load_word (sp + offset); + offset -= 4; } - /* And make sure to update the stack pointer. */ - State.regs[REG_SP] = sp; - /* Restore the PC value. */ State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8) | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24)); @@ -2773,62 +2770,57 @@ void OP_DF0000 (insn, extension) void OP_DE0000 (insn, extension) unsigned long insn, extension; { - unsigned int sp; + unsigned int sp, offset; unsigned long mask; - sp = State.regs[REG_SP] + (insn & 0xff); - State.regs[REG_SP] = sp; - State.regs[REG_PC] = State.regs[REG_MDR] - 3; - + State.regs[REG_SP] += (insn & 0xff); sp = State.regs[REG_SP]; + State.regs[REG_PC] = State.regs[REG_MDR] - 3; + offset = -4; mask = (insn & 0xff00) >> 8; - if (mask & 0x8) + if (mask & 0x80) { - sp += 4; - State.regs[REG_LAR] = load_word (sp); - sp += 4; - State.regs[REG_LIR] = load_word (sp); - sp += 4; - State.regs[REG_MDR] = load_word (sp); - sp += 4; - State.regs[REG_A0 + 1] = load_word (sp); - sp += 4; - State.regs[REG_A0] = load_word (sp); - sp += 4; - State.regs[REG_D0 + 1] = load_word (sp); - sp += 4; - State.regs[REG_D0] = load_word (sp); - sp += 4; + State.regs[REG_D0 + 2] = load_word (sp + offset); + offset -= 4; } - if (mask & 0x10) + if (mask & 0x40) { - State.regs[REG_A0 + 3] = load_word (sp); - sp += 4; + State.regs[REG_D0 + 3] = load_word (sp + offset); + offset -= 4; } if (mask & 0x20) { - State.regs[REG_A0 + 2] = load_word (sp); - sp += 4; + State.regs[REG_A0 + 2] = load_word (sp + offset); + offset -= 4; } - if (mask & 0x40) + if (mask & 0x10) { - State.regs[REG_D0 + 3] = load_word (sp); - sp += 4; + State.regs[REG_A0 + 3] = load_word (sp + offset); + offset -= 4; } - if (mask & 0x80) + if (mask & 0x8) { - State.regs[REG_D0 + 2] = load_word (sp); - sp += 4; + State.regs[REG_D0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_D0 + 1] = load_word (sp + offset); + offset -= 4; + State.regs[REG_A0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_A0 + 1] = load_word (sp + offset); + offset -= 4; + State.regs[REG_MDR] = load_word (sp + offset); + offset -= 4; + State.regs[REG_LIR] = load_word (sp + offset); + offset -= 4; + State.regs[REG_LAR] = load_word (sp + offset); + offset -= 4; } - - /* And make sure to update the stack pointer. */ - State.regs[REG_SP] = sp; } /* rets */ |