x86-64: Also optimize "clr reg64"

"clr reg" is an alias of "xor reg, reg".  We can encode "clr reg64" as
"xor reg32, reg32".

gas/

	* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
	as "xor reg32, reg32".
	* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
	* testsuite/gas/i386/x86-64-optimize-1.d: Updated.

opcodes/

	* i386-opc.tbl: Add Optimize to clr.
	* i386-tbl.h: Regenerated.

7 files changed, 30 insertions, 9 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d9ea1a4..7c37f13 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 
+	* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
+	as "xor reg32, reg32".
+	* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
+	* testsuite/gas/i386/x86-64-optimize-1.d: Updated.
+
+2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* NEWS: Mention -mold-gcc removal.
 	* config/tc-i386.c (i386_error): Remove old_gcc_only.
 	(old_gcc): Removed.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 53ac4b4..1c64d08 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3801,7 +3801,8 @@ optimize_encoding (void)
 	}
     }
   else if (flag_code == CODE_64BIT
-	   && ((i.reg_operands == 1
+	   && ((i.types[1].bitfield.qword
+		&& i.reg_operands == 1
 		&& i.imm_operands == 1
 		&& i.op[0].imms->X_op == O_constant
 		&& ((i.tm.base_opcode == 0xb0
@@ -3816,12 +3817,16 @@ optimize_encoding (void)
 			    || ((i.tm.base_opcode == 0xf6
 				 || i.tm.base_opcode == 0xc6)
 				&& i.tm.extension_opcode == 0x0)))))
-	       || (i.reg_operands == 2
-		   && i.op[0].regs == i.op[1].regs
-		   && ((i.tm.base_opcode == 0x30
-			|| i.tm.base_opcode == 0x28)
-		       && i.tm.extension_opcode == None)))
-	   && i.types[1].bitfield.qword)
+	       || (i.types[0].bitfield.qword
+		   && ((i.reg_operands == 2
+			&& i.op[0].regs == i.op[1].regs
+			&& ((i.tm.base_opcode == 0x30
+			     || i.tm.base_opcode == 0x28)
+			    && i.tm.extension_opcode == None))
+		       || (i.reg_operands == 1
+			   && i.operands == 1
+			   && i.tm.base_opcode == 0x30
+			   && i.tm.extension_opcode == None)))))
     {
       /* Optimize: -O:
 	   andq $imm31, %r64   -> andl $imm31, %r32
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-1.d b/gas/testsuite/gas/i386/x86-64-optimize-1.d
index 506d586..f7fd1be 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-1.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-1.d
@@ -50,4 +50,6 @@ Disassembly of section .text:
  +[a-f0-9]+:	b8 ff 03 00 00       	mov    \$0x3ff,%eax
  +[a-f0-9]+:	48 b8 00 00 00 00 01 00 00 00 	movabs \$0x100000000,%rax
  +[a-f0-9]+:	48 b8 00 00 00 00 01 00 00 00 	movabs \$0x100000000,%rax
+ +[a-f0-9]+:	31 c0                	xor    %eax,%eax
+ +[a-f0-9]+:	45 31 f6             	xor    %r14d,%r14d
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-1.s b/gas/testsuite/gas/i386/x86-64-optimize-1.s
index 2c6dc6d..15d8cb0 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-1.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-1.s
@@ -45,3 +45,5 @@ _start:
 	movq	$1023,%rax
 	mov	$0x100000000,%rax
 	movq	$0x100000000,%rax
+	clrq	%rax
+	clrq	%r14
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 55f8a14..333dd43 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 
+	* i386-opc.tbl: Add Optimize to clr.
+	* i386-tbl.h: Regenerated.
+
+2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* i386-gen.c (opcode_modifiers): Remove OldGcc.
 	* i386-opc.h (OldGcc): Removed.
 	(i386_opcode_modifier): Remove oldgcc.
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index a3080be..8286379 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -205,7 +205,7 @@ xor, 2, 0x34, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byt
 xor, 2, 0x80, 0x6, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 
 // clr with 1 operand is really xor with 2 operands.
-clr, 1, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge, { Reg8|Reg16|Reg32|Reg64 }
+clr, 1, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 }
 
 adc, 2, 0x10, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 adc, 2, 0x83, 0x2, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 433f257..06b8b96 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -2115,7 +2115,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
       0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,