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authorJim Wilson <jimw@sifive.com>2018-03-06 12:01:04 -0800
committerJim Wilson <jimw@sifive.com>2018-03-06 12:01:50 -0800
commit770aa8a3d3da978a35520af5f205ab2d8a5371a0 (patch)
treecad4f7d1d9c153222489e313462a400e06e4b0d7
parent9add17f218409f357d5ed8b831c777ac93f41ec4 (diff)
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RISC-V: Disallow output format changes.
PR 22920 * emultempl/riscvelf.em (riscv_create_output_section_statements): New. (LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS): New. * testsuite/ld-elf/pr21884.d (#notarget): Add riscv*-*-*. * testsuite/ld-unique/pr21529.d (#notarget): Likewise. * testsuite/ld-srec/srec.exp (run_srec_test): For riscv*-*-* target, call setup_xfail.
-rw-r--r--ld/ChangeLog10
-rw-r--r--ld/emultempl/riscvelf.em20
-rw-r--r--ld/testsuite/ld-elf/pr21884.d2
-rw-r--r--ld/testsuite/ld-srec/srec.exp6
-rw-r--r--ld/testsuite/ld-unique/pr21529.d2
5 files changed, 38 insertions, 2 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog
index c796125..218df5c 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,13 @@
+2018-03-06 Jim Wilson <jimw@sifive.com>
+
+ PR 22920
+ * emultempl/riscvelf.em (riscv_create_output_section_statements): New.
+ (LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS): New.
+ * testsuite/ld-elf/pr21884.d (#notarget): Add riscv*-*-*.
+ * testsuite/ld-unique/pr21529.d (#notarget): Likewise.
+ * testsuite/ld-srec/srec.exp (run_srec_test): For riscv*-*-* target,
+ call setup_xfail.
+
2018-03-03 James Cowgill <james.cowgill@mips.com>
Maciej W. Rozycki <macro@mips.com>
diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em
index a284c63..eaaf4c5 100644
--- a/ld/emultempl/riscvelf.em
+++ b/ld/emultempl/riscvelf.em
@@ -62,7 +62,27 @@ gld${EMULATION_NAME}_after_allocation (void)
gld${EMULATION_NAME}_map_segments (need_layout);
}
+/* This is a convenient point to tell BFD about target specific flags.
+ After the output has been created, but before inputs are read. */
+
+static void
+riscv_create_output_section_statements (void)
+{
+ /* See PR 22920 for an example of why this is necessary. */
+ if (strstr (bfd_get_target (link_info.output_bfd), "riscv") == NULL)
+ {
+ /* The RISC-V backend needs special fields in the output hash structure.
+ These will only be created if the output format is a RISC-V format,
+ hence we do not support linking and changing output formats at the
+ same time. Use a link followed by objcopy to change output formats. */
+ einfo (_("%F%P: error: cannot change output format"
+ " whilst linking %s binaries\n"), "RISC-V");
+ return;
+ }
+}
+
EOF
LDEMUL_BEFORE_ALLOCATION=riscv_elf_before_allocation
LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
+LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=riscv_create_output_section_statements
diff --git a/ld/testsuite/ld-elf/pr21884.d b/ld/testsuite/ld-elf/pr21884.d
index 2645a87..e7eae56 100644
--- a/ld/testsuite/ld-elf/pr21884.d
+++ b/ld/testsuite/ld-elf/pr21884.d
@@ -2,7 +2,7 @@
#source: pr21884b.s
#ld: -T pr21884.t
#objdump: -b binary -s
-#notarget: aarch64*-*-* arm*-*-* avr-*-* hppa-*-* ia64-*-* m68hc1*-*-* nds32*-*-* score-*-* v850-*-*
+#notarget: aarch64*-*-* arm*-*-* avr-*-* hppa-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-*
# Skip targets which can't change output format to binary.
.*: file format binary
diff --git a/ld/testsuite/ld-srec/srec.exp b/ld/testsuite/ld-srec/srec.exp
index fb6162f..7cda271 100644
--- a/ld/testsuite/ld-srec/srec.exp
+++ b/ld/testsuite/ld-srec/srec.exp
@@ -282,6 +282,12 @@ proc run_srec_test { test objs } {
setup_xfail "msp430*-*-*"
}
+ # The RISC-V target does not correctly process
+ # relocs when output format is not ELF.
+ if [istarget riscv*-*-*] {
+ setup_xfail "riscv*-*-*"
+ }
+
# SH64 targets cannot convert format in the linker
# using the -oformat command line switch.
if [istarget sh64*-*-elf] {
diff --git a/ld/testsuite/ld-unique/pr21529.d b/ld/testsuite/ld-unique/pr21529.d
index 655a9ef..11d47b8 100644
--- a/ld/testsuite/ld-unique/pr21529.d
+++ b/ld/testsuite/ld-unique/pr21529.d
@@ -1,6 +1,6 @@
#ld: --oformat binary -T pr21529.ld -e main
#objdump: -s -b binary
-#notarget: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* score-*-* v850-*-*
+#notarget: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-*
# Skip targets which can't change output format to binary.
#pass