x86: also correctly support TEST opcode aliases

Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.

9 files changed, 38 insertions, 2 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5340f8b..c40140f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2017-02-24  Jan Beulich  <jbeulich@suse.com>
+
+	* testsuite/gas/i386/opcode.s: Add alternative TEST forms.
+	* testsuite/gas/i386/x86-64-opcode.s: Likewise.
+	* testsuite/gas/i386/opcode.d: Adjust accordingly.
+	* testsuite/gas/i386/opcode-intel.d: Likewise.
+	* testsuite/gas/i386/x86-64-opcode.d: Likewise.
+	* testsuite/gas/i386/ilp32/x86-64-opcode.d: Likewise.
+
 2017-02-24  Sheldon Lobo  <sheldon.lobo@oracle.com>
 
 	Test cases for the architecture level aware SPARC ASI work.
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d b/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
index 5515f9f..53893b3 100644
--- a/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
@@ -302,4 +302,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 07                	sysret 
 [ 	]*[a-f0-9]+:	0f 01 f8             	swapgs 
 [ 	]*[a-f0-9]+:	66 68 22 22          	pushw  \$0x2222
+[ 	]*[a-f0-9]+:	f6 c9 01             	test   \$(0x)?0*1,%cl
+[ 	]*[a-f0-9]+:	66 f7 c9 02 00       	test   \$(0x)?0*2,%cx
+[ 	]*[a-f0-9]+:	f7 c9 04 00 00 00    	test   \$(0x)?0*4,%ecx
+[ 	]*[a-f0-9]+:	48 f7 c9 08 00 00 00 	test   \$(0x)?0*8,%rcx
 #pass
diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d
index e924bf9..404758c 100644
--- a/gas/testsuite/gas/i386/opcode-intel.d
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -601,4 +601,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	82 f3 01             	xor    bl,0x1
  +[a-f0-9]+:	82 fb 01             	cmp    bl,0x1
  +[a-f0-9]+:	62 f3 7d 08 15 e8 ab 	vpextrw eax,xmm5,0xab
+ +[a-f0-9]+:	f6 c9 01             	test   cl,(0x)?0*1
+ +[a-f0-9]+:	66 f7 c9 02 00       	test   cx,(0x)?0*2
+ +[a-f0-9]+:	f7 c9 04 00 00 00    	test   ecx,(0x)?0*4
 #pass
diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index dd89828..c7dc410 100644
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -600,4 +600,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	82 f3 01             	xor    \$0x1,%bl
  +[a-f0-9]+:	82 fb 01             	cmp    \$0x1,%bl
  +[a-f0-9]+:	62 f3 7d 08 15 e8 ab 	vpextrw \$0xab,%xmm5,%eax
+ +[a-f0-9]+:	f6 c9 01             	test   \$(0x)?0*1,%cl
+ +[a-f0-9]+:	66 f7 c9 02 00       	test   \$(0x)?0*2,%cx
+ +[a-f0-9]+:	f7 c9 04 00 00 00    	test   \$(0x)?0*4,%ecx
 #pass
diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index 101085a..64357b5 100644
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -600,3 +600,7 @@ foo:
 	.byte 0x82, 0xfb, 0x01
 
 	.byte 0x62, 0xf3, 0x7d, 0x08, 0x15, 0xe8, 0xab
+
+	.byte 0xf6, 0xc9, 0x01
+	.byte 0x66, 0xf7, 0xc9, 0x02, 0x00
+	.byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index d29c2ab..a6087e0 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -301,4 +301,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 07                	sysret 
 [ 	]*[a-f0-9]+:	0f 01 f8             	swapgs 
 [ 	]*[a-f0-9]+:	66 68 22 22          	pushw  \$0x2222
+[ 	]*[a-f0-9]+:	f6 c9 01             	test   \$(0x)?0*1,%cl
+[ 	]*[a-f0-9]+:	66 f7 c9 02 00       	test   \$(0x)?0*2,%cx
+[ 	]*[a-f0-9]+:	f7 c9 04 00 00 00    	test   \$(0x)?0*4,%ecx
+[ 	]*[a-f0-9]+:	48 f7 c9 08 00 00 00 	test   \$(0x)?0*8,%rcx
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index f271da5..ffc8b94 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -427,3 +427,8 @@
         swapgs		              #  --  --	 -- --	 0F 01 f8
 
 	pushw $0x2222
+
+	.byte 0xf6, 0xc9, 0x01
+	.byte 0x66, 0xf7, 0xc9, 0x02, 0x00
+	.byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00
+	.byte 0x48, 0xf7, 0xc9, 0x08, 0x00, 0x00, 0x00
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 61d35a1..2bbe8b8 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-02-24  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
+
 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 
 	Add support for associating SPARC ASIs with an architecture level.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 108f0e3..2b61d4a 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3511,7 +3511,7 @@ static const struct dis386 reg_table[][8] = {
   /* REG_F6 */
   {
     { "testA",	{ Eb, Ib }, 0 },
-    { Bad_Opcode },
+    { "testA",	{ Eb, Ib }, 0 },
     { "notA",	{ Ebh1 }, 0 },
     { "negA",	{ Ebh1 }, 0 },
     { "mulA",	{ Eb }, 0 },	/* Don't print the implicit %al register,  */
@@ -3522,7 +3522,7 @@ static const struct dis386 reg_table[][8] = {
   /* REG_F7 */
   {
     { "testQ",	{ Ev, Iv }, 0 },
-    { Bad_Opcode },
+    { "testQ",	{ Ev, Iv }, 0 },
     { "notQ",	{ Evh1 }, 0 },
     { "negQ",	{ Evh1 }, 0 },
     { "mulQ",	{ Ev }, 0 },	/* Don't print the implicit register.  */