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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2017-11-07 20:24:21 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2017-11-07 20:24:21 +0000 |
| commit | 52eab766df54915f8d3d71475235868285c4ca82 (patch) | |
| tree | c3f32bdcb1fe484c7a19846f1ede53a9e4ef53b9 | |
| parent | 016f5a3777ab6ce33616917be7795a7501f29dd7 (diff) | |
| download | gdb-52eab766df54915f8d3d71475235868285c4ca82.zip gdb-52eab766df54915f8d3d71475235868285c4ca82.tar.gz gdb-52eab766df54915f8d3d71475235868285c4ca82.tar.bz2 | |
opcodes/arc: Fix incorrect insn_class for some nps insns
A small number of NPS400 instruction incorrectly used NONE as an
insn_class_t, which would trigger a build warning. Fixed by changing to
MISC.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/arc-nps400-tbl.h | 8 |
2 files changed, 8 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7107ee6..70f146f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com> + + * arc-nps400-tbl.h: Change incorrect use of NONE to MISC. + 2017-11-07 Alan Modra <amodra@gmail.com> * opintl.h: Formatting, comment fixes. diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index a40ee75..15ef692 100644 --- a/opcodes/arc-nps400-tbl.h +++ b/opcodes/arc-nps400-tbl.h @@ -980,13 +980,13 @@ ASRI_LIKE (0x4, C_NPS_GIC) /* Atomic Operations. */ /* exc<.di><.f> a,a,[xa:b] */ -{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, +{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, /* exc<.di><.f> a,a,[sd:b] */ -{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, +{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, /* exc<.di><.f> a,a,[xd:b] */ -{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, +{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, /* exc<.di><.f> a,a,[b] */ -{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, +{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }}, |