diff options
author | Chris Demetriou <cgd@google.com> | 2002-03-05 22:24:24 +0000 |
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committer | Chris Demetriou <cgd@google.com> | 2002-03-05 22:24:24 +0000 |
commit | 86b77b471b497fe282bffc264d459a34f5f29822 (patch) | |
tree | 14d95790e50775b10894fcd13da3fd02346a6a6e | |
parent | b43df9952bf5c1f9884c928f71f57607d20ba3c4 (diff) | |
download | gdb-86b77b471b497fe282bffc264d459a34f5f29822.zip gdb-86b77b471b497fe282bffc264d459a34f5f29822.tar.gz gdb-86b77b471b497fe282bffc264d459a34f5f29822.tar.bz2 |
2002-03-05 Chris Demetriou <cgd@broadcom.com>
* mips.igen: Fix formatting of all SignalException calls.
-rw-r--r-- | sim/mips/ChangeLog | 4 | ||||
-rw-r--r-- | sim/mips/mips.igen | 38 |
2 files changed, 23 insertions, 19 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 7d3eb9b..c6075ea 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,7 @@ +2002-03-05 Chris Demetriou <cgd@broadcom.com> + + * mips.igen: Fix formatting of all SignalException calls. + 2002-02-05 Chris Demetriou <cgd@broadcom.com> * sim-main.h (SIGNEXTEND): Remove. diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index da55b8c..9b20a6b 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -825,14 +825,14 @@ PC = cia - 4; /* reference the branch instruction */ else PC = cia; - SignalException(BreakPoint, instruction_0); + SignalException (BreakPoint, instruction_0); } else { /* If we get this far, we're not an instruction reserved by the sim. Raise the exception. */ - SignalException(BreakPoint, instruction_0); + SignalException (BreakPoint, instruction_0); } } @@ -2746,7 +2746,7 @@ *vr5000: *r3900: { - SignalException(SystemCall, instruction_0); + SignalException (SystemCall, instruction_0); } @@ -2760,7 +2760,7 @@ *vr5000: { if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2774,7 +2774,7 @@ *vr5000: { if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2788,7 +2788,7 @@ *vr5000: { if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2802,7 +2802,7 @@ *vr5000: { if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2816,7 +2816,7 @@ *vr5000: { if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2830,7 +2830,7 @@ *vr5000: { if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2844,7 +2844,7 @@ *vr5000: { if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2858,7 +2858,7 @@ *vr5000: { if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2872,7 +2872,7 @@ *vr5000: { if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2886,7 +2886,7 @@ *vr5000: { if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2900,7 +2900,7 @@ *vr5000: { if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -2914,7 +2914,7 @@ *vr5000: { if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -3380,7 +3380,7 @@ check_fpu (SD_); { if ((fmt == fmt_double) | 0) - SignalException(ReservedInstruction,instruction_0); + SignalException (ReservedInstruction, instruction_0); else StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double)); } @@ -3400,7 +3400,7 @@ check_fpu (SD_); { if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) - SignalException(ReservedInstruction,instruction_0); + SignalException (ReservedInstruction, instruction_0); else StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long)); } @@ -3425,7 +3425,7 @@ check_fpu (SD_); { if ((fmt == fmt_single) | 0) - SignalException(ReservedInstruction,instruction_0); + SignalException (ReservedInstruction, instruction_0); else StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single)); } @@ -3447,7 +3447,7 @@ check_fpu (SD_); { if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) - SignalException(ReservedInstruction,instruction_0); + SignalException (ReservedInstruction, instruction_0); else StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word)); } |