diff options
| author | Claudiu Zissulescu <claziss@synopsys.com> | 2017-02-06 11:26:13 +0100 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2017-02-06 11:26:13 +0100 |
| commit | 6ec7c1ae19e9e1bf2edad5125941a2fd5fdfde0b (patch) | |
| tree | 2618ac0c1711a72e5ad9151057af06ad140e9cd0 | |
| parent | 20b477a75c00de06a92b9577fd74416699d2c37f (diff) | |
| download | gdb-6ec7c1ae19e9e1bf2edad5125941a2fd5fdfde0b.zip gdb-6ec7c1ae19e9e1bf2edad5125941a2fd5fdfde0b.tar.gz gdb-6ec7c1ae19e9e1bf2edad5125941a2fd5fdfde0b.tar.bz2 | |
[ARC] Provide an interface to decode ARC instructions.
gas/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (parse_opcode_flags): Ignore implicit flags.
include/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
Anton Kolesov <anton.kolesov@synopsys.com>
* opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0,
BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes.
(flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT
flag classes.
opcode/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
Anton Kolesov <anton.kolesov@synopsys.com>
* arc-dis.c (arc_disassemble_info): New structure.
(init_arc_disasm_info): New function.
(find_format_from_table): Ignore implicit flags.
(find_format): Update dissassembler private data.
(print_flags): Likewise.
(print_insn_arc): Likewise.
(arc_opcode_to_insn_type): Consider the new added instruction
classes.
(arcAnalyzeInstr): Remove.
(arc_insn_decode): New function.
* arc-dis.h (arc_ldst_writeback_mode): New enum.
(arc_ldst_data_size): Likewise.
(arc_condition_code): Likewise.
(arc_operand_kind): Likewise.
(arc_insn_kind): New struct.
(arc_instruction): Likewise.
(arc_insn_decode): Declare function.
(ARC_Debugger_OperandType): Deleted.
(Flow): Likewise.
(NullifyMode): Likewise.
(allOperandsSize): Likewise.
(arcDisState): Likewise.
(arcAnalyzeInstr): Likewise.
* arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced
insn_class_t enums.
* arc-opc.c (F_SIZED): New define.
(C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise.
(C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise.
(C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise.
(arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags.
* opcodes/arc-tbl.h: Update instructions to include new
F_CLASS_IMPLICIT flags.
(bbit0, lp): Change class.
(bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
| -rw-r--r-- | gas/config/tc-arc.c | 4 | ||||
| -rw-r--r-- | include/opcode/arc.h | 24 | ||||
| -rw-r--r-- | opcodes/arc-dis.c | 211 | ||||
| -rw-r--r-- | opcodes/arc-dis.h | 196 | ||||
| -rw-r--r-- | opcodes/arc-opc.c | 57 | ||||
| -rw-r--r-- | opcodes/arc-tbl.h | 508 |
6 files changed, 636 insertions, 364 deletions
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index ec0fb68..9a3b26b 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -1671,6 +1671,10 @@ parse_opcode_flags (const struct arc_opcode *opcode, int cl_matches = 0; struct arc_flags *pflag = NULL; + /* Check if opcode has implicit flag classes. */ + if (cl_flags->flag_class & F_CLASS_IMPLICIT) + continue; + /* Check for extension conditional codes. */ if (ext_condcode.arc_ext_condcode && cl_flags->flag_class & F_CLASS_EXTEND) diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 859bb9f..f263fff 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -42,27 +42,40 @@ typedef enum ACL, ARITH, AUXREG, + BBIT0, + BBIT1, + BI, + BIH, BITOP, BITSTREAM, BMU, BRANCH, + BRCC, CONTROL, DIVREM, DPI, DSP, + EI, + ENTER, FLOAT, INVALID, + JLI, JUMP, KERNEL, + LEAVE, LOAD, LOGICAL, + LOOP, MEMORY, MOVE, MPY, NET, PROTOCOL_DECODE, PMU, + POP, + PUSH, STORE, + SUB, XY } insn_class_t; @@ -111,7 +124,16 @@ typedef enum F_CLASS_EXTEND = (1 << 2), /* Condition code flag. */ - F_CLASS_COND = (1 << 3) + F_CLASS_COND = (1 << 3), + + /* Write back mode. */ + F_CLASS_WB = (1 << 4), + + /* Data size. */ + F_CLASS_ZZ = (1 << 5), + + /* Implicit flag. */ + F_CLASS_IMPLICIT = (1 << 6) } flag_class_t; /* The opcode table is an array of struct arc_opcode. */ diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index 53ba5f5..3afd253 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -51,6 +51,33 @@ struct arc_operand_iterator const unsigned char *opidx; }; +/* A private data used by ARC decoder. */ +struct arc_disassemble_info +{ + /* The current disassembled arc opcode. */ + const struct arc_opcode *opcode; + + /* Instruction length w/o limm field. */ + unsigned insn_len; + + /* TRUE if we have limm. */ + bfd_boolean limm_p; + + /* LIMM value, if exists. */ + unsigned limm; + + /* Condition code, if exists. */ + unsigned condition_code; + + /* Writeback mode. */ + unsigned writeback_mode; + + /* Number of operands. */ + unsigned operands_count; + + struct arc_insn_operand operands[MAX_INSN_ARGS]; +}; + /* Globals variables. */ static const char * const regnames[64] = @@ -108,6 +135,20 @@ static linkclass decodelist = NULL; /* Functions implementation. */ +/* Initialize private data. */ +static bfd_boolean +init_arc_disasm_info (struct disassemble_info *info) +{ + struct arc_disassemble_info *arc_infop + = calloc (sizeof (*arc_infop), 1); + + if (arc_infop == NULL) + return FALSE; + + info->private_data = arc_infop; + return TRUE; +} + /* Add a new element to the decode list. */ static void @@ -280,6 +321,10 @@ find_format_from_table (struct disassemble_info *info, continue; } + /* Check for the implicit flags. */ + if (cl_flags->flag_class & F_CLASS_IMPLICIT) + continue; + for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { const struct arc_flag_operand *flg_operand = @@ -367,6 +412,7 @@ find_format (bfd_vma memaddr, bfd_boolean needs_limm; const extInstruction_t *einsn, *i; unsigned limm = 0; + struct arc_disassemble_info *arc_infop = info->private_data; /* First, try the extension instructions. */ if (*insn_len == 4) @@ -422,6 +468,12 @@ An error occured while generating the extension instruction operations"); } *opcode_result = opcode; + + /* Update private data. */ + arc_infop->opcode = opcode; + arc_infop->limm = (needs_limm) ? limm : 0; + arc_infop->limm_p = needs_limm; + return TRUE; } @@ -432,6 +484,7 @@ print_flags (const struct arc_opcode *opcode, { const unsigned char *flgidx; unsigned int value; + struct arc_disassemble_info *arc_infop = info->private_data; /* Now extract and print the flags. */ for (flgidx = opcode->flags; *flgidx; flgidx++) @@ -459,6 +512,18 @@ print_flags (const struct arc_opcode *opcode, const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx]; + /* Implicit flags are only used for the insn decoder. */ + if (cl_flags->flag_class & F_CLASS_IMPLICIT) + { + if (cl_flags->flag_class & F_CLASS_COND) + arc_infop->condition_code = flg_operand->code; + else if (cl_flags->flag_class & F_CLASS_WB) + arc_infop->writeback_mode = flg_operand->code; + else if (cl_flags->flag_class & F_CLASS_ZZ) + info->data_size = flg_operand->code; + continue; + } + if (!flg_operand->favail) continue; @@ -496,8 +561,13 @@ print_flags (const struct arc_opcode *opcode, info->insn_type = dis_condjsr; else if (info->insn_type == dis_branch) info->insn_type = dis_condbranch; + arc_infop->condition_code = flg_operand->code; } + /* Check for the write back modes. */ + if (cl_flags->flag_class & F_CLASS_WB) + arc_infop->writeback_mode = flg_operand->code; + (*info->fprintf_func) (info->stream, "%s", flg_operand->name); } } @@ -733,7 +803,15 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode) switch (opcode->insn_class) { case BRANCH: + case BBIT0: + case BBIT1: + case BI: + case BIH: + case BRCC: + case EI: + case JLI: case JUMP: + case LOOP: if (!strncmp (opcode->name, "bl", 2) || !strncmp (opcode->name, "jl", 2)) { @@ -753,8 +831,14 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode) case LOAD: case STORE: case MEMORY: + case ENTER: + case PUSH: + case POP: insn_type = dis_dref; break; + case LEAVE: + insn_type = dis_branch; + break; default: insn_type = dis_nonbranch; break; @@ -783,6 +867,7 @@ print_insn_arc (bfd_vma memaddr, int value; struct arc_operand_iterator iter; Elf_Internal_Ehdr *header = NULL; + struct arc_disassemble_info *arc_infop; if (info->disassembler_options) { @@ -792,6 +877,9 @@ print_insn_arc (bfd_vma memaddr, info->disassembler_options = NULL; } + if (info->private_data == NULL && !init_arc_disasm_info (info)) + return -1; + memset (&iter, 0, sizeof (iter)); highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0); lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1); @@ -813,7 +901,7 @@ print_insn_arc (bfd_vma memaddr, default: isa_mask = ARC_OPCODE_ARCv2EM; /* TODO: Perhaps remove defitinion of header since it is only used at - this location. */ + this location. */ if (header != NULL && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS) { @@ -899,6 +987,8 @@ print_insn_arc (bfd_vma memaddr, insn_len = arc_insn_length (buffer[highbyte], buffer[lowbyte], info); pr_debug ("instruction length = %d bytes\n", insn_len); + arc_infop = info->private_data; + arc_infop->insn_len = insn_len; switch (insn_len) { @@ -957,7 +1047,7 @@ print_insn_arc (bfd_vma memaddr, /* Set some defaults for the insn info. */ info->insn_info_valid = 1; info->branch_delay_insns = 0; - info->data_size = 0; + info->data_size = 4; info->insn_type = dis_nonbranch; info->target = 0; info->target2 = 0; @@ -1016,6 +1106,7 @@ print_insn_arc (bfd_vma memaddr, need_comma = FALSE; open_braket = FALSE; + arc_infop->operands_count = 0; /* Now extract and print the operands. */ operand = NULL; @@ -1034,14 +1125,14 @@ print_insn_arc (bfd_vma memaddr, if ((operand->flags & ARC_OPERAND_IGNORE) && (operand->flags & ARC_OPERAND_IR) - && value == -1) + && value == -1) continue; if (operand->flags & ARC_OPERAND_COLON) - { - (*info->fprintf_func) (info->stream, ":"); - continue; - } + { + (*info->fprintf_func) (info->stream, ":"); + continue; + } if (need_comma) (*info->fprintf_func) (info->stream, ","); @@ -1106,12 +1197,12 @@ print_insn_arc (bfd_vma memaddr, (*info->fprintf_func) (info->stream, "%d", value); } else if (operand->flags & ARC_OPERAND_ADDRTYPE) - { - const char *addrtype = get_addrtype (value); - (*info->fprintf_func) (info->stream, "%s", addrtype); - /* A colon follow an address type. */ - need_comma = FALSE; - } + { + const char *addrtype = get_addrtype (value); + (*info->fprintf_func) (info->stream, "%s", addrtype); + /* A colon follow an address type. */ + need_comma = FALSE; + } else { if (operand->flags & ARC_OPERAND_TRUNCATE @@ -1129,6 +1220,24 @@ print_insn_arc (bfd_vma memaddr, (*info->fprintf_func) (info->stream, "%#x", value); } } + + if (operand->flags & ARC_OPERAND_LIMM) + { + arc_infop->operands[arc_infop->operands_count].kind + = ARC_OPERAND_KIND_LIMM; + /* It is not important to have exactly the LIMM indicator + here. */ + arc_infop->operands[arc_infop->operands_count].value = 63; + } + else + { + arc_infop->operands[arc_infop->operands_count].value = value; + arc_infop->operands[arc_infop->operands_count].kind + = (operand->flags & ARC_OPERAND_IR + ? ARC_OPERAND_KIND_REG + : ARC_OPERAND_KIND_SHIMM); + } + arc_infop->operands_count ++; } return insn_len; @@ -1152,30 +1261,6 @@ arc_get_disassembler (bfd *abfd) return print_insn_arc; } -/* Disassemble ARC instructions. Used by debugger. */ - -struct arcDisState -arcAnalyzeInstr (bfd_vma memaddr, - struct disassemble_info *info) -{ - struct arcDisState ret; - memset (&ret, 0, sizeof (struct arcDisState)); - - ret.instructionLen = print_insn_arc (memaddr, info); - -#if 0 - ret.words[0] = insn[0]; - ret.words[1] = insn[1]; - ret._this = &ret; - ret.coreRegName = _coreRegName; - ret.auxRegName = _auxRegName; - ret.condCodeName = _condCodeName; - ret.instName = _instName; -#endif - - return ret; -} - void print_arc_disassembler_options (FILE *stream) { @@ -1199,6 +1284,58 @@ with -M switch (multiple options should be separated by commas):\n")); fpud Recognize double precision FPU instructions.\n")); } +void arc_insn_decode (bfd_vma addr, + struct disassemble_info *info, + disassembler_ftype disasm_func, + struct arc_instruction *insn) +{ + const struct arc_opcode *opcode; + struct arc_disassemble_info *arc_infop; + + /* Ensure that insn would be in the reset state. */ + memset (insn, 0, sizeof (struct arc_instruction)); + + /* There was an error when disassembling, for example memory read error. */ + if (disasm_func (addr, info) < 0) + { + insn->valid = FALSE; + return; + } + + assert (info->private_data != NULL); + arc_infop = info->private_data; + + insn->length = arc_infop->insn_len;; + insn->address = addr; + + /* Quick exit if memory at this address is not an instruction. */ + if (info->insn_type == dis_noninsn) + { + insn->valid = FALSE; + return; + } + + insn->valid = TRUE; + + opcode = (const struct arc_opcode *) arc_infop->opcode; + insn->insn_class = opcode->insn_class; + insn->limm_value = arc_infop->limm; + insn->limm_p = arc_infop->limm_p; + + insn->is_control_flow = (info->insn_type == dis_branch + || info->insn_type == dis_condbranch + || info->insn_type == dis_jsr + || info->insn_type == dis_condjsr); + + insn->has_delay_slot = info->branch_delay_insns; + insn->writeback_mode + = (enum arc_ldst_writeback_mode) arc_infop->writeback_mode; + insn->data_size_mode = info->data_size; + insn->condition_code = arc_infop->condition_code; + memcpy (insn->operands, arc_infop->operands, + sizeof (struct arc_insn_operand) * MAX_INSN_ARGS); + insn->operands_count = arc_infop->operands_count; +} /* Local variables: eval: (c-set-style "gnu") diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h index a981e53..ff9bd00 100644 --- a/opcodes/arc-dis.h +++ b/opcodes/arc-dis.h @@ -26,86 +26,148 @@ extern "C" { #endif -enum ARC_Debugger_OperandType +enum arc_ldst_writeback_mode { - ARC_UNDEFINED, - ARC_LIMM, - ARC_SHIMM, - ARC_REGISTER, - ARCOMPACT_REGISTER /* Valid only for the - registers allowed in - 16 bit mode. */ + ARC_WRITEBACK_NO = 0, + ARC_WRITEBACK_AW = 1, + ARC_WRITEBACK_A = ARC_WRITEBACK_AW, + ARC_WRITEBACK_AB = 2, + ARC_WRITEBACK_AS = 3, }; -enum Flow + +enum arc_ldst_data_size { - noflow, - direct_jump, - direct_call, - indirect_jump, - indirect_call, - invalid_instr + ARC_SCALING_NONE = 4, + ARC_SCALING_B = 1, + ARC_SCALING_H = 2, + ARC_SCALING_D = 8, }; -enum NullifyMode + +enum arc_condition_code { - BR_exec_when_no_jump, - BR_exec_always, - BR_exec_when_jump + ARC_CC_AL = 0x0, + ARC_CC_RA = ARC_CC_AL, + ARC_CC_EQ = 0x1, + ARC_CC_Z = ARC_CC_EQ, + ARC_CC_NE = 0x2, + ARC_CC_NZ = ARC_CC_NE, + ARC_CC_PL = 0x3, + ARC_CC_P = ARC_CC_PL, + ARC_CC_MI = 0x4, + ARC_CC_N = ARC_CC_MI, + ARC_CC_CS = 0x5, + ARC_CC_C = ARC_CC_CS, + ARC_CC_LO = ARC_CC_CS, + ARC_CC_CC = 0x6, + ARC_CC_NC = ARC_CC_CC, + ARC_CC_HS = ARC_CC_CC, + ARC_CC_VS = 0x7, + ARC_CC_V = ARC_CC_VS, + ARC_CC_VC = 0x8, + ARC_CC_NV = ARC_CC_VC, + ARC_CC_GT = 0x9, + ARC_CC_GE = 0xA, + ARC_CC_LT = 0xB, + ARC_CC_LE = 0xC, + ARC_CC_HI = 0xD, + ARC_CC_LS = 0xE, + ARC_CC_PNZ = 0xF, + ARC_CC_UNDEF0 = 0x10, + ARC_CC_UNDEF1 = 0x11, + ARC_CC_UNDEF2 = 0x12, + ARC_CC_UNDEF3 = 0x13, + ARC_CC_UNDEF4 = 0x14, + ARC_CC_UNDEF5 = 0x15, + ARC_CC_UNDEF6 = 0x16, + ARC_CC_UNDEF7 = 0x17, + ARC_CC_UNDEF8 = 0x18, + ARC_CC_UNDEF9 = 0x19, + ARC_CC_UNDEFA = 0x1A, + ARC_CC_UNDEFB = 0x1B, + ARC_CC_UNDEFC = 0x1C, + ARC_CC_UNDEFD = 0x1D, + ARC_CC_UNDEFE = 0x1E, + ARC_CC_UNDEFF = 0x1F }; -enum { allOperandsSize = 256 }; +enum arc_operand_kind +{ + ARC_OPERAND_KIND_UNKNOWN = 0, + ARC_OPERAND_KIND_REG, + ARC_OPERAND_KIND_SHIMM, + ARC_OPERAND_KIND_LIMM +}; -struct arcDisState +struct arc_insn_operand { - void *_this; - int instructionLen; - void (*err)(void*, const char*); - const char *(*coreRegName)(void*, int); - const char *(*auxRegName)(void*, int); - const char *(*condCodeName)(void*, int); - const char *(*instName)(void*, int, int, int*); - - unsigned char* instruction; - unsigned index; - const char *comm[6]; /* Instr name, cond, NOP, 3 operands. */ - - union - { - unsigned int registerNum; - unsigned int shortimm; - unsigned int longimm; - } source_operand; - enum ARC_Debugger_OperandType sourceType; - - int opWidth; - int targets[4]; - /* START ARC LOCAL. */ - unsigned int addresses[4]; - /* END ARC LOCAL. */ - /* Set as a side-effect of calling the disassembler. - Used only by the debugger. */ - enum Flow flow; - int register_for_indirect_jump; - int ea_reg1, ea_reg2, _offset; - int _cond, _opcode; - unsigned long words[2]; - char *commentBuffer; - char instrBuffer[40]; - char operandBuffer[allOperandsSize]; - char _ea_present; - char _addrWriteBack; /* Address writeback. */ - char _mem_load; - char _load_len; - enum NullifyMode nullifyMode; - unsigned char commNum; - unsigned char isBranch; - unsigned char tcnt; - unsigned char acnt; + /* Operand value as encoded in instruction. */ + unsigned long value; + + enum arc_operand_kind kind; +}; + +/* Container for information about instruction. Provides a higher + level access to data that is contained in struct arc_opcode. */ + +struct arc_instruction +{ + /* Address of this instruction. */ + bfd_vma address; + + /* Whether this is a valid instruction. */ + bfd_boolean valid; + + insn_class_t insn_class; + + /* Length (without LIMM). */ + unsigned length; + + /* Is there a LIMM in this instruction? */ + int limm_p; + + /* Long immediate value. */ + unsigned limm_value; + + /* Is it a branch/jump instruction? */ + int is_control_flow; + + /* Whether this instruction has a delay slot. */ + int has_delay_slot; + + /* Value of condition code field. */ + enum arc_condition_code condition_code; + + /* Load/store writeback mode. */ + enum arc_ldst_writeback_mode writeback_mode; + + /* Load/store data size. */ + enum arc_ldst_data_size data_size_mode; + + /* Amount of operands in instruction. Note that amount of operands + reported by opcodes disassembler can be different from the one + encoded in the instruction. Notable case is "ld a,[b,offset]", + when offset == 0. In this case opcodes disassembler presents + this instruction as "ld a,[b]", hence there are *two* operands, + not three. OPERANDS_COUNT and OPERANDS contain only those + explicit operands, hence it is up to invoker to handle the case + described above based on instruction opcodes. Another notable + thing is that in opcodes disassembler representation square + brackets (`[' and `]') are so called fake-operands - they are in + the list of operands, but do not have any value of they own. + Those "operands" are not present in this array. */ + struct arc_insn_operand operands[MAX_INSN_ARGS]; + + unsigned int operands_count; }; -struct arcDisState -arcAnalyzeInstr (bfd_vma memaddr, struct disassemble_info *); +/* Fill INSN with data about instruction at specified ADDR. */ + +void arc_insn_decode (bfd_vma addr, + struct disassemble_info *di, + disassembler_ftype func, + struct arc_instruction *insn); #ifdef __cplusplus } diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index b89a873..295d92f 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -1290,9 +1290,11 @@ const struct arc_flag_operand arc_flag_operands[] = { "h", 2, 2, 7, 1 }, #define F_H17 (F_H7 + 1) { "h", 2, 2, 17, 1 }, +#define F_SIZED (F_H17 + 1) + { "dd", 8, 0, 0, 0 }, /* Fake. */ /* Fake Flags. */ -#define F_NE (F_H17 + 1) +#define F_NE (F_SIZED + 1) { "ne", 0, 0, 0, 1 }, /* ARC NPS400 Support: See comment near head of file. */ @@ -1398,7 +1400,52 @@ const struct arc_flag_class arc_flag_classes[] = #define C_EMPTY 0 { F_CLASS_NONE, { F_NULL } }, -#define C_CC (C_EMPTY + 1) +#define C_CC_EQ (C_EMPTY + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} }, + +#define C_CC_GE (C_CC_EQ + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} }, + +#define C_CC_GT (C_CC_GE + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} }, + +#define C_CC_HI (C_CC_GT + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} }, + +#define C_CC_HS (C_CC_HI + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} }, + +#define C_CC_LE (C_CC_HS + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} }, + +#define C_CC_LO (C_CC_LE + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} }, + +#define C_CC_LS (C_CC_LO + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} }, + +#define C_CC_LT (C_CC_LS + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} }, + +#define C_CC_NE (C_CC_LT + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} }, + +#define C_AA_AB (C_CC_NE + 1) + {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} }, + +#define C_AA_AW (C_AA_AB + 1) + {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} }, + +#define C_ZZ_D (C_AA_AW + 1) + {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} }, + +#define C_ZZ_H (C_ZZ_D + 1) + {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} }, + +#define C_ZZ_B (C_ZZ_H + 1) + {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} }, + +#define C_CC (C_ZZ_B + 1) { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, @@ -1409,13 +1456,13 @@ const struct arc_flag_class arc_flag_classes[] = #define C_AA_ADDR3 (C_CC + 1) #define C_AA27 (C_CC + 1) - { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, + { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, #define C_AA_ADDR9 (C_AA_ADDR3 + 1) #define C_AA21 (C_AA_ADDR3 + 1) - { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, + { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, #define C_AA_ADDR22 (C_AA_ADDR9 + 1) #define C_AA8 (C_AA_ADDR9 + 1) - { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, + { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, #define C_F (C_AA_ADDR22 + 1) { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } }, diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h index 809f303..c7d5c34 100644 --- a/opcodes/arc-tbl.h +++ b/opcodes/arc-tbl.h @@ -1397,76 +1397,76 @@ { "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D }}, /* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */ -{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, +{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, /* bbit0<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y110. */ -{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, +{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, /* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110. */ -{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, +{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, /* bbit0<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y110. */ -{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, +{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, /* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110001110. */ -{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, +{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, /* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC001110. */ -{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, +{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, /* bbit0<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y110. */ -{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, +{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, /* bbit0<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y110. */ -{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, +{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, /* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu011110. */ -{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, +{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, /* bbit0<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y110. */ -{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, +{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, /* bbit0 limm,limm,s9 00001110sssssss1S111111110001110. */ -{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }}, +{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }}, /* bbit0<.T> limm,limm,s9 00001110sssssss1S11111111000Y110. */ -{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, +{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, /* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111. */ -{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, +{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, /* bbit1<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y111. */ -{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, +{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, /* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111. */ -{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, +{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, /* bbit1<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y111. */ -{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, +{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, /* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110001111. */ -{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, +{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, /* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC001111. */ -{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, +{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, /* bbit1<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y111. */ -{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, +{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, /* bbit1<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y111. */ -{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, +{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, /* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu011111. */ -{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, +{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, /* bbit1<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y111. */ -{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, +{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, /* bbit1 limm,limm,s9 00001110sssssss1S111111110001111. */ -{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }}, +{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }}, /* bbit1<.T> limm,limm,s9 00001110sssssss1S11111111000Y111. */ -{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, +{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, /* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA. */ { "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, @@ -1532,25 +1532,25 @@ { "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, /* beq_s s10 1111001sssssssss. */ -{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { 0 }}, +{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_EQ }}, /* bge_s s7 1111011001ssssss. */ -{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }}, +{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_GE }}, /* bgt_s s7 1111011000ssssss. */ -{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }}, +{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_GT }}, /* bhi_s s7 1111011100ssssss. */ -{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }}, +{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HI }}, /* bhs_s s7 1111011101ssssss. */ -{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }}, +{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HS }}, /* bi c 00100RRR001001000RRRCCCCCCRRRRRR. */ -{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }}, +{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BI, CD1, { BRAKET, RC, BRAKETdup }, { 0 }}, /* bi limm 00100RRR001001000RRR111110RRRRRR. */ -{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }}, +{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BI, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }}, /* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA. */ { "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, @@ -1616,10 +1616,10 @@ { "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, /* bih c 00100RRR001001010RRRCCCCCCRRRRRR. */ -{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }}, +{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BIH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }}, /* bih limm 00100RRR001001010RRR111110RRRRRR. */ -{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }}, +{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BIH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }}, /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A32_5 }, { C_D }}, @@ -1628,16 +1628,16 @@ { "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A32_5 }, { C_CC, C_D }}, /* ble_s s7 1111011011ssssss. */ -{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }}, +{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LE }}, /* blo_s s7 1111011110ssssss. */ -{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }}, +{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LO }}, /* bls_s s7 1111011111ssssss. */ -{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }}, +{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LS }}, /* blt_s s7 1111011010ssssss. */ -{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }}, +{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LT }}, /* bl_s s13 11111sssssssssss. */ { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A32_5_S }, { 0 }}, @@ -1766,217 +1766,217 @@ { "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, /* bne_s s10 1111010sssssssss. */ -{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { 0 }}, +{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_NE }}, /* breq<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000. */ -{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, +{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_EQ }}, /* breq<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y000. */ -{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, +{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_EQ }}, /* breq<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000. */ -{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, +{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_EQ }}, /* breq<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y000. */ -{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, +{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_EQ }}, /* breq b,limm,s9 00001bbbsssssss1SBBB111110000000. */ -{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, +{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_EQ }}, /* breq limm,c,s9 00001110sssssss1S111CCCCCC000000. */ -{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, +{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_EQ }}, /* breq<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y000. */ -{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, +{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_EQ }}, /* breq<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y000. */ -{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, +{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_EQ }}, /* breq limm,u6,s9 00001110sssssss1S111uuuuuu010000. */ -{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, +{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_EQ }}, /* breq<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y000. */ -{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, +{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_EQ }}, /* breq<.T> limm,limm,s9 00001110sssssss1S11111111000Y000. */ -{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, +{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_EQ }}, /* breq_s b,0,s8 11101bbb0sssssss. */ -{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }}, +{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { C_CC_EQ }}, /* brge<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011. */ -{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, +{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_GE }}, /* brge<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y011. */ -{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_GE }}, /* brge<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011. */ -{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, +{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_GE }}, /* brge<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y011. */ -{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_GE }}, /* brge b,limm,s9 00001bbbsssssss1SBBB111110000011. */ -{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, +{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_GE }}, /* brge limm,c,s9 00001110sssssss1S111CCCCCC000011. */ -{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, +{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_GE }}, /* brge<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y011. */ -{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, +{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_GE }}, /* brge<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y011. */ -{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, +{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_GE }}, /* brge limm,u6,s9 00001110sssssss1S111uuuuuu010011. */ -{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, +{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_GE }}, /* brge<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y011. */ -{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, +{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_GE }}, /* brge<.T> limm,limm,s9 00001110sssssss1S11111111000Y011. */ -{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, +{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_GE }}, /* brhs<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101. */ -{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, +{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_HS }}, /* brhs<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y101. */ -{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_HS }}, /* brhs<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101. */ -{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, +{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_HS }}, /* brhs<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y101. */ -{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_HS }}, /* brhs b,limm,s9 00001bbbsssssss1SBBB111110000101. */ -{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, +{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_HS }}, /* brhs limm,c,s9 00001110sssssss1S111CCCCCC000101. */ -{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, +{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_HS }}, /* brhs<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y101. */ -{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, +{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_HS }}, /* brhs<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y101. */ -{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, +{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_HS }}, /* brhs limm,u6,s9 00001110sssssss1S111uuuuuu010101. */ -{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, +{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_HS }}, /* brhs<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y101. */ -{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, +{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_HS }}, /* brhs<.T> limm,limm,s9 00001110sssssss1S11111111000Y101. */ -{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, +{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_HS }}, /* brk 00100101011011110000000000111111. */ -{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, +{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { C_CC_HS }}, /* brk_s 0111111111111111. */ { "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, /* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */ -{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, +{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LO }}, /* brlo<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y100. */ -{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_LO }}, /* brlo<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100. */ -{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, +{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LO }}, /* brlo<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y100. */ -{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_LO }}, /* brlo b,limm,s9 00001bbbsssssss1SBBB111110000100. */ -{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, +{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LO }}, /* brlo limm,c,s9 00001110sssssss1S111CCCCCC000100. */ -{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, +{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LO }}, /* brlo<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y100. */ -{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, +{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_LO }}, /* brlo<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y100. */ -{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, +{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_LO }}, /* brlo limm,u6,s9 00001110sssssss1S111uuuuuu010100. */ -{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, +{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LO }}, /* brlo<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y100. */ -{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, +{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_LO }}, /* brlo<.T> limm,limm,s9 00001110sssssss1S11111111000Y100. */ -{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, +{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_LO }}, /* brlt<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010. */ -{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, +{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LT }}, /* brlt<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y010. */ -{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_LT }}, /* brlt<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010. */ -{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, +{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LT }}, /* brlt<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y010. */ -{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_LT }}, /* brlt b,limm,s9 00001bbbsssssss1SBBB111110000010. */ -{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, +{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LT }}, /* brlt limm,c,s9 00001110sssssss1S111CCCCCC000010. */ -{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, +{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LT }}, /* brlt<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y010. */ -{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, +{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_LT }}, /* brlt<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y010. */ -{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, +{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_LT }}, /* brlt limm,u6,s9 00001110sssssss1S111uuuuuu010010. */ -{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, +{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LT }}, /* brlt<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y010. */ -{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, +{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_LT }}, /* brlt<.T> limm,limm,s9 00001110sssssss1S11111111000Y010. */ -{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, +{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_LT }}, /* brne<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001. */ -{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }}, +{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_NE }}, /* brne<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y001. */ -{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_NE }}, /* brne<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN10001. */ -{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, +{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_NE }}, /* brne<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y001. */ -{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, +{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_NE }}, /* brne b,limm,s9 00001bbbsssssss1SBBB111110000001. */ -{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, +{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_NE }}, /* brne limm,c,s9 00001110sssssss1S111CCCCCC000001. */ -{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, +{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_NE }}, /* brne<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y001. */ -{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, +{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_NE }}, /* brne<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y001. */ -{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, +{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_NE }}, /* brne limm,u6,s9 00001110sssssss1S111uuuuuu010001. */ -{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, +{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_NE }}, /* brne<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y001. */ -{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, +{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_NE }}, /* brne<.T> limm,limm,s9 00001110sssssss1S11111111000Y001. */ -{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, +{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_NE }}, /* brne_s b,0,s8 11101bbb1sssssss. */ -{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }}, +{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { C_CC_NE }}, /* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA. */ { "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, @@ -6188,11 +6188,11 @@ { "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, /* ei_s u10 010111uuuuuuuuuu. */ -{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD2, { UIMM10_6_S }, { 0 }}, +{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, EI, CD2, { UIMM10_6_S }, { 0 }}, /* enter_s u6 110000UU111uuuu0. */ -{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }}, -{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD1, { UIMM6_11_S }, { 0 }}, +{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }}, +{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { UIMM6_11_S }, { 0 }}, /* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */ { "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }}, @@ -7875,10 +7875,10 @@ { "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }}, /* jeq_s BLINK 0111110011100000. */ -{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, +{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_EQ }}, /* jeq_s BLINK 0111110011100000. */ -{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, +{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_EQ }}, /* jl c 00100RRR001000100RRRCCCCCCRRRRRR. */ { "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }}, @@ -7953,7 +7953,7 @@ { "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }}, /* jli_s u10 010110uuuuuuuuuu. */ -{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD1, { UIMM10_6_S }, { 0 }}, +{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JLI, CD1, { UIMM10_6_S }, { 0 }}, /* jl_s b 01111bbb01000000. */ { "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }}, @@ -7968,10 +7968,10 @@ { "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }}, /* jne_s BLINK 0111110111100000. */ -{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, +{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_NE }}, /* jne_s BLINK 0111110111100000. */ -{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, +{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_NE }}, /* j_s b 01111bbb00000000. */ { "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }}, @@ -8073,70 +8073,70 @@ { "ld", 0x26307FBE, 0xFF387FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, LIMMdup, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, /* ldb_s a,b,c 01100bbbccc01aaa. */ -{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }}, +{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_B }}, /* ldb_s c,b,u5 10001bbbcccuuuuu. */ -{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }}, +{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B }}, /* ldb_s b,SP,u7 11000bbb001uuuuu. */ -{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, +{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }}, /* ldb_s R0,GP,s9 1100101sssssssss. */ -{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { 0 }}, +{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { C_ZZ_B }}, /* ldd<.di><.aa> a,b 00010bbb000000000BBBDaa110AAAAAA. */ -{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }}, +{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, /* ldd<.di><.aa> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA. */ -{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }}, +{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, /* ldd<.di><.aa> 0,b 00010bbb000000000BBBDaa110111110. */ -{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }}, +{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, /* ldd<.di><.aa> 0,b,c 00100bbbaa110110DBBBCCCCCC111110. */ -{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }}, +{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, /* ldd<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA. */ -{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }}, +{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, /* ldd<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa110111110. */ -{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }}, +{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, /* ldd<.di> a,limm 00010110000000000111DRR110AAAAAA. */ -{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20 }}, +{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_ZZ_D }}, /* ldd<.di><.aa> a,b,limm 00100bbbaa110110DBBB111110AAAAAA. */ -{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }}, +{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, /* ldd<.di> a,limm,c 00100110RR110110D111CCCCCCAAAAAA. */ -{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16 }}, +{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_ZZ_D }}, /* ldd<.di> 0,limm 00010110000000000111DRR110111110. */ -{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI20 }}, +{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_ZZ_D }}, /* ldd<.di><.aa> 0,b,limm 00100bbbaa110110DBBB111110111110. */ -{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }}, +{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, /* ldd<.di> 0,limm,c 00100110RR110110D111CCCCCC111110. */ -{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16 }}, +{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_ZZ_D }}, /* ldd<.di><.aa> a,limm,s9 00010110ssssssssS111Daa110AAAAAA. */ -{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }}, +{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, /* ldd<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa110111110. */ -{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }}, +{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, /* ldh_s a,b,c 01100bbbccc10aaa. */ -{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }}, +{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H }}, /* ldh_s c,b,u6 10010bbbcccuuuuu. */ -{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }}, +{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }}, /* ldh_s.X c,b,u6 10011bbbcccuuuuu. */ -{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }}, +{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD, C_ZZ_H }}, /* ldh_s R0,GP,s10 1100110sssssssss. */ -{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { 0 }}, +{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { C_ZZ_H }}, /* ldi b,c 00100bbb00100110RBBBCCCCCCRRRRRR. */ { "ldi", 0x20260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }}, @@ -8184,16 +8184,16 @@ { "ldm", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, UIMM6_A16_21, LIMM }, { 0 }}, /* ldw_s a,b,c 01100bbbccc10aaa. */ -{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }}, +{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H }}, /* ldw_s c,b,u6 10010bbbcccuuuuu. */ -{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }}, +{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }}, /* ldw_s.X c,b,u6 10011bbbcccuuuuu. */ -{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }}, +{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD, C_ZZ_H }}, /* ldw_s R0,GP,s10 1100110sssssssss. */ -{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { 0 }}, +{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { C_ZZ_H }}, /* ld_s a,b,c 01100bbbccc00aaa. */ { "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }}, @@ -8229,8 +8229,8 @@ { "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { R1_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }}, /* leave_s u7 11000UUU110uuuu0. */ -{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }}, -{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD1, { UIMM7_11_S }, { 0 }}, +{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }}, +{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { UIMM7_11_S }, { 0 }}, /* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */ { "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }}, @@ -8269,22 +8269,22 @@ { "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }}, /* lp s13 00100RRR101010000RRRssssssSSSSSS. */ -{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { SIMM13_A16_20 }, { 0 }}, +{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { SIMM13_A16_20 }, { 0 }}, /* lp s13 00100RRR10101000RRRRssssssSSSSSS. */ -{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A16_20 }, { 0 }}, +{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { SIMM13_A16_20 }, { 0 }}, /* lp<cc> u7 00100RRR111010000RRRuuuuuu1QQQQQ. */ -{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { UIMM7_A16_20 }, { C_CC }}, +{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { UIMM7_A16_20 }, { C_CC }}, /* lp u7 00100RRR011010000RRRuuuuuuRRRRRR. */ -{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, BRANCH, NONE, { UIMM7_A16_20 }, { 0 }}, +{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, LOOP, NONE, { UIMM7_A16_20 }, { 0 }}, /* lp<cc> u7 00100RRR11101000RRRRuuuuuu1QQQQQ. */ -{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { UIMM7_A16_20 }, { C_CC }}, +{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { UIMM7_A16_20 }, { C_CC }}, /* lp u7 00100RRR01101000RRRRuuuuuuRRRRRR. */ -{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { UIMM7_A16_20 }, { 0 }}, +{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { UIMM7_A16_20 }, { 0 }}, /* lr b,c 00100bbb001010100BBBCCCCCCRRRRRR. */ { "lr", 0x202A0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }}, @@ -10201,10 +10201,10 @@ { "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { ZA_S, LIMM_S }, { 0 }}, /* mov_s.ne b,h 01110bbbhhh111HH. */ -{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB_S, RH_S }, { C_NE }}, +{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB_S, RH_S }, { C_NE, C_CC_NE }}, /* mov_s.ne b,limm 01110bbb11011111. */ -{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB_S, LIMM_S }, { C_NE }}, +{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB_S, LIMM_S }, { C_NE, C_CC_NE }}, /* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA. */ { "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }}, @@ -12889,10 +12889,10 @@ { "pkqb", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, /* pop_s b 11000bbb11000001. */ -{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S }, { 0 }}, +{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, NONE, { RB_S }, { C_AA_AB }}, /* pop_s BLINK 11000RRR11010001. */ -{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }}, +{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, NONE, { BLINK_S }, { C_AA_AB }}, /* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110. */ { "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }}, @@ -12991,10 +12991,10 @@ { "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }}, /* push_s b 11000bbb11100001. */ -{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S }, { 0 }}, +{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, NONE, { RB_S }, { C_AA_AW }}, /* push_s blink 11000RRR11110001. */ -{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }}, +{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, NONE, { BLINK_S }, { C_AA_AW }}, /* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */ { "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }}, @@ -14641,40 +14641,40 @@ { "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, /* stb_s c,b,u5 10101bbbcccuuuuu. */ -{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }}, +{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B }}, /* stb_s b,SP,u7 11000bbb011uuuuu. */ -{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, +{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }}, /* std<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaa110. */ -{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }}, +{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, /* std<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaa111. */ -{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }}, +{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, /* std<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110. */ -{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, +{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, /* std<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111. */ -{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, +{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, /* std<.di> c,limm 00011110000000000111CCCCCCDRR110. */ -{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26 }}, +{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_ZZ_D }}, /* std<.di> w6,limm 00011110000000000111wwwwwwDRR111. */ -{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26 }}, +{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_ZZ_D }}, /* std<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110Daa110. */ -{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, +{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, /* std<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111. */ -{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, +{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, /* std<.di><.aa> limm,limm,s9 00011110ssssssssS111111110Daa110. */ -{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, +{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, /* sth_s c,b,u6 10110bbbcccuuuuu. */ -{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }}, +{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }}, /* stm a,u6,b 00101bbb01001101RBBBRuuuuuAAAAAA. */ { "stm", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, STORE, NONE, { RA, UIMM6_A16_21, RB }, { 0 }}, @@ -14689,7 +14689,7 @@ { "stm", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, STORE, NONE, { ZA, UIMM6_A16_21, LIMM }, { 0 }}, /* stw_s c,b,u6 10110bbbcccuuuuu. */ -{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }}, +{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }}, /* st_s b,SP,u7 11000bbb010uuuuu. */ { "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, @@ -14701,244 +14701,244 @@ { "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, CD2, { R0_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }}, /* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA. */ -{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, +{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, RC }, { C_F }}, /* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110. */ -{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, +{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, RC }, { C_F }}, /* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ. */ -{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, +{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ -{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, +{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }}, /* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110. */ -{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, +{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, /* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ. */ -{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, +{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, /* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS. */ -{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, +{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, /* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA. */ -{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, +{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, RC }, { C_F }}, /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ -{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, +{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, LIMM }, { C_F }}, /* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110. */ -{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, +{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F }}, /* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110. */ -{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, +{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, LIMM }, { C_F }}, /* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ. */ -{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, +{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, /* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ. */ -{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, +{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, /* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA. */ -{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, +{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, /* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110. */ -{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, +{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, /* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ. */ -{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, +{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, /* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS. */ -{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, +{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, /* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA. */ -{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, +{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }}, /* sub<.f> 0,limm,limm 0010011000000010F111111110111110. */ -{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, +{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, /* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ. */ -{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, +{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, /* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA. */ -{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, +{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, RC }, { C_F }}, /* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110. */ -{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, +{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, RC }, { C_F }}, /* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ. */ -{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, +{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, /* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA. */ -{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, +{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }}, /* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110. */ -{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, +{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, /* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ. */ -{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, +{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, /* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS. */ -{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, +{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, /* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA. */ -{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, +{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, RC }, { C_F }}, /* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA. */ -{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, +{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, LIMM }, { C_F }}, /* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110. */ -{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, +{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F }}, /* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110. */ -{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, +{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, LIMM }, { C_F }}, /* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ. */ -{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, +{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, /* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ. */ -{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, +{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, /* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA. */ -{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, +{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, /* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110. */ -{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, +{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, /* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ. */ -{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, +{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, /* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS. */ -{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, +{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, /* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA. */ -{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, +{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }}, /* sub1<.f> 0,limm,limm 0010011000010111F111111110111110. */ -{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, +{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, /* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ. */ -{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, +{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, /* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA. */ -{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, +{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, RC }, { C_F }}, /* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110. */ -{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, +{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, RC }, { C_F }}, /* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ. */ -{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, +{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, /* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA. */ -{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, +{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }}, /* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110. */ -{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, +{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, /* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ. */ -{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, +{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, /* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS. */ -{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, +{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, /* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA. */ -{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, +{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, RC }, { C_F }}, /* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA. */ -{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, +{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, LIMM }, { C_F }}, /* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110. */ -{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, +{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F }}, /* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110. */ -{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, +{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, LIMM }, { C_F }}, /* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ. */ -{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, +{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, /* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ. */ -{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, +{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, /* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA. */ -{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, +{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, /* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110. */ -{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, +{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, /* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ. */ -{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, +{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, /* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS. */ -{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, +{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, /* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA. */ -{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, +{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }}, /* sub2<.f> 0,limm,limm 0010011000011000F111111110111110. */ -{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, +{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, /* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ. */ -{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, +{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, /* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA. */ -{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, +{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, RC }, { C_F }}, /* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110. */ -{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, +{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, RC }, { C_F }}, /* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ. */ -{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, +{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, /* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA. */ -{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, +{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }}, /* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110. */ -{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, +{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, /* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ. */ -{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, +{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, /* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS. */ -{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, +{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, /* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA. */ -{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, +{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, RC }, { C_F }}, /* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA. */ -{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, +{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, LIMM }, { C_F }}, /* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110. */ -{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, +{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F }}, /* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110. */ -{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, +{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, LIMM }, { C_F }}, /* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ. */ -{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, +{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, /* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ. */ -{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, +{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, /* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA. */ -{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, +{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, /* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110. */ -{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, +{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, /* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ. */ -{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, +{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, /* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS. */ -{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, +{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, /* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA. */ -{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, +{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }}, /* sub3<.f> 0,limm,limm 0010011000011001F111111110111110. */ -{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, +{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, /* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ. */ -{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, +{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, /* subs<.f> a,b,c 00101bbb00000111FBBBCCCCCCAAAAAA. */ { "subs", 0x28070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }}, @@ -15064,22 +15064,22 @@ { "subsdw", 0x2EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, /* sub_s b,b,c 01111bbbccc00010. */ -{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, +{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, /* sub_s a,b,c 01001bbbccc10aaa. */ -{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { RA_S, RB_S, RC_S }, { 0 }}, +{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, CD2, { RA_S, RB_S, RC_S }, { 0 }}, /* sub_s c,b,u3 01101bbbccc01uuu. */ -{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }}, +{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }}, /* sub_s b,b,u5 10111bbb011uuuuu. */ -{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, +{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, /* sub_s SP,SP,u7 11000001101uuuuu. */ -{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }}, +{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }}, /* sub_s.ne b,b,b 01111bbb11000000. */ -{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE }}, +{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE, C_CC_NE }}, /* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000. */ { "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }}, |