diff options
author | Gavin Romig-Koch <gavin@redhat.com> | 1999-11-01 19:29:55 +0000 |
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committer | Gavin Romig-Koch <gavin@redhat.com> | 1999-11-01 19:29:55 +0000 |
commit | 2bd7f1f332946c3baeef11111d1dfb1994ce9942 (patch) | |
tree | 4a2d3dec575bdd40004c21aeb955f15b5747646c | |
parent | c58c5ee7b57bdfbc8305a7676bb7791ba4e12248 (diff) | |
download | gdb-2bd7f1f332946c3baeef11111d1dfb1994ce9942.zip gdb-2bd7f1f332946c3baeef11111d1dfb1994ce9942.tar.gz gdb-2bd7f1f332946c3baeef11111d1dfb1994ce9942.tar.bz2 |
For include/opcode:
* mips.h (OPCODE_IS_MEMBER): New.
For gas:
* config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER.
(mips_ip): Use OPCODE_IS_MEMBER.
For opcodes:
* mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
-rw-r--r-- | gas/ChangeLog | 5 | ||||
-rw-r--r-- | gas/config/tc-mips.c | 65 | ||||
-rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
-rw-r--r-- | include/opcode/mips.h | 18 | ||||
-rw-r--r-- | opcodes/ChangeLog | 4 | ||||
-rw-r--r-- | opcodes/mips-dis.c | 24 |
6 files changed, 42 insertions, 78 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index bd67830..d3aa148 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> + + * config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER. + (mips_ip): Use OPCODE_IS_MEMBER. + Wed Oct 27 16:50:44 1999 Don Lindsay <dlindsay@cygnus.com> * config/tc-arm.c (reg_required_here): Improve comments. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index f98a332..d2fdca7 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2424,7 +2424,6 @@ macro_build (place, counter, ep, name, fmt, va_alist) struct mips_cl_insn insn; bfd_reloc_code_real_type r; va_list args; - int insn_isa; #ifdef USE_STDARG va_start (args, fmt); @@ -2458,31 +2457,9 @@ macro_build (place, counter, ep, name, fmt, va_alist) /* Search until we get a match for NAME. */ while (1) { - insn_isa = 0; - - if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) - insn_isa = 1; - else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) - insn_isa = 2; - else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) - insn_isa = 3; - else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) - insn_isa = 4; - if (strcmp (fmt, insn.insn_mo->args) == 0 && insn.insn_mo->pinfo != INSN_MACRO - && ((insn_isa != 0 - && insn_isa <= mips_opts.isa) - || (mips_cpu == 4650 - && (insn.insn_mo->membership & INSN_4650) != 0) - || (mips_cpu == 4010 - && (insn.insn_mo->membership & INSN_4010) != 0) - || ((mips_cpu == 4100 - || mips_cpu == 4111 - ) - && (insn.insn_mo->membership & INSN_4100) != 0) - || (mips_cpu == 3900 - && (insn.insn_mo->membership & INSN_3900) != 0)) + && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_cpu) && (mips_cpu != 4650 || (insn.insn_mo->pinfo & FP_D) == 0)) break; @@ -7028,37 +7005,15 @@ mips_ip (str, ip) argsStart = s; for (;;) { - int insn_isa; boolean ok; assert (strcmp (insn->name, str) == 0); - insn_isa = 0; - if ((insn->membership & INSN_ISA) == INSN_ISA1) - insn_isa = 1; - else if ((insn->membership & INSN_ISA) == INSN_ISA2) - insn_isa = 2; - else if ((insn->membership & INSN_ISA) == INSN_ISA3) - insn_isa = 3; - else if ((insn->membership & INSN_ISA) == INSN_ISA4) - insn_isa = 4; - - if (insn_isa != 0 - && insn_isa <= mips_opts.isa) - ok = true; - else if (insn->pinfo == INSN_MACRO) - ok = false; - else if ((mips_cpu == 4650 && (insn->membership & INSN_4650) != 0) - || (mips_cpu == 4010 && (insn->membership & INSN_4010) != 0) - || ((mips_cpu == 4100 - || mips_cpu == 4111 - ) - && (insn->membership & INSN_4100) != 0) - || (mips_cpu == 3900 && (insn->membership & INSN_3900) != 0)) + if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_cpu)) ok = true; - else + else ok = false; - + if (insn->pinfo != INSN_MACRO) { if (mips_cpu == 4650 && (insn->pinfo & FP_D) != 0) @@ -7073,18 +7028,16 @@ mips_ip (str, ip) ++insn; continue; } - - if (insn_isa == 0 - || insn_isa <= mips_opts.isa) - insn_error = _("opcode not supported on this processor"); else { static char buf[100]; - - sprintf (buf, _("opcode requires -mips%d or greater"), insn_isa); + sprintf (buf, + _("opcode not supported on this processor: %d (MIPS%d)"), + mips_cpu, mips_opts.isa); + insn_error = buf; + return; } - return; } ip->insn_mo = insn; diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 63d2e83..ebf79dd 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): New. + 1999-10-29 Nick Clifton <nickc@cygnus.com> * d30v.h (SHORT_AR): Define. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index f0a8c7e..07e0fd7 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -319,6 +319,24 @@ struct mips_opcode /* Toshiba R3900 instruction. */ #define INSN_3900 0x00000080 +/* Test for membership in an ISA including chip specific ISAs. + INSN is pointer to an element of the opcode table; ISA is the + specified ISA to test against; and CPU is the CPU specific ISA + to test, or zero if no CPU specific ISA test is desired. */ + +#define OPCODE_IS_MEMBER(insn,isa,cpu) \ + ((((insn)->membership & INSN_ISA) != 0 \ + && ((insn)->membership & INSN_ISA) <= isa) \ + || (cpu == 4650 \ + && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == 4010 \ + && ((insn)->membership & INSN_4010) != 0) \ + || ((cpu == 4100 \ + || cpu == 4111 \ + ) \ + && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == 3900 \ + && ((insn)->membership & INSN_3900) != 0)) /* This is a list of macro expanded instructions. * diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b8c8822..0ac1cf1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> + + * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER. + 1999-10-29 Nick Clifton <nickc@cygnus.com> * d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 1e3577c..a1bd62e 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -387,28 +387,8 @@ _print_insn_mips (memaddr, word, info) if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match) { register const char *d; - int insn_isa; - - if ((op->membership & INSN_ISA) == INSN_ISA1) - insn_isa = 1; - else if ((op->membership & INSN_ISA) == INSN_ISA2) - insn_isa = 2; - else if ((op->membership & INSN_ISA) == INSN_ISA3) - insn_isa = 3; - else if ((op->membership & INSN_ISA) == INSN_ISA4) - insn_isa = 4; - else - insn_isa = 15; - - if (insn_isa > mips_isa - && (target_processor == 4650 - && op->membership & INSN_4650) == 0 - && (target_processor == 4010 - && op->membership & INSN_4010) == 0 - && (target_processor == 4100 - && op->membership & INSN_4100) == 0 - && (target_processor == 3900 - && op->membership & INSN_3900) == 0) + + if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor)) continue; (*info->fprintf_func) (info->stream, "%s", op->name); |