MIPS/opcodes: Mark descriptive SYNC mnemonics as aliases

Following the way how descriptive SYNC mnemonics have been defined in
the architecture[1][2] mark them as aliases, so that the generic SYNC
instruction can be alternatively disassembled along with its immediate
operand, as noted in the documents referred.

References:

[1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
    Revision 5.04, December 11, 2013, Table 4.7 "Encodings of the
    Bits[10:6] of the SYNC instruction; the SType Field", p. 305

[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
    Revision 5.04, January 15, 2014, Table 5.28 "Encodings of the
    Bits[10:6] of the SYNC instruction; the SType Field", p. 481

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
	"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
	"sync_rmb" and "sync_wmb" as aliases.
	* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
	"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.

	gas/
	* testsuite/gas/mips/mips32r2-sync-1.d: New test.
	* testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

7 files changed, 88 insertions, 14 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index be2a658..63ca633 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* testsuite/gas/mips/mips32r2-sync-1.d: New test.
+	* testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test.
+	* testsuite/gas/mips/mips.exp: Run the new tests.
+
 2017-05-10  Maciej W. Rozycki  <macro@imgtec.com>
 
 	* testsuite/gas/mips/isa-override-2.d: New test.
diff --git a/gas/testsuite/gas/mips/micromips@mips32r2-sync-1.d b/gas/testsuite/gas/mips/micromips@mips32r2-sync-1.d
new file mode 100644
index 0000000..e68a492
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@mips32r2-sync-1.d
@@ -0,0 +1,29 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M no-aliases
+#name: MIPS32r2 sync instructions
+#as: -32
+#source: mips32r2-sync.s
+
+# Check MIPS32r2 sync instructions assembly and disassembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0000 6b7c 	sync
+[0-9a-f]+ <[^>]*> 0002 6b7c 	sync	0x2
+[0-9a-f]+ <[^>]*> 0004 6b7c 	sync	0x4
+[0-9a-f]+ <[^>]*> 0008 6b7c 	sync	0x8
+[0-9a-f]+ <[^>]*> 0010 6b7c 	sync	0x10
+[0-9a-f]+ <[^>]*> 0011 6b7c 	sync	0x11
+[0-9a-f]+ <[^>]*> 0012 6b7c 	sync	0x12
+[0-9a-f]+ <[^>]*> 0013 6b7c 	sync	0x13
+[0-9a-f]+ <[^>]*> 0018 6b7c 	sync	0x18
+[0-9a-f]+ <[^>]*> 0000 6b7c 	sync
+[0-9a-f]+ <[^>]*> 0002 6b7c 	sync	0x2
+[0-9a-f]+ <[^>]*> 0004 6b7c 	sync	0x4
+[0-9a-f]+ <[^>]*> 0008 6b7c 	sync	0x8
+[0-9a-f]+ <[^>]*> 0010 6b7c 	sync	0x10
+[0-9a-f]+ <[^>]*> 0011 6b7c 	sync	0x11
+[0-9a-f]+ <[^>]*> 0012 6b7c 	sync	0x12
+[0-9a-f]+ <[^>]*> 0013 6b7c 	sync	0x13
+[0-9a-f]+ <[^>]*> 0018 6b7c 	sync	0x18
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 9574d22..e1fcce6 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1403,6 +1403,8 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "mips32-sync"
     run_dump_test_arches "mips32r2-sync" \
 					[mips_arch_list_matching mips32r2]
+    run_dump_test_arches "mips32r2-sync-1" \
+					[mips_arch_list_matching mips32r2]
     run_dump_test_arches "alnv_ps-swap" [mips_arch_list_matching fpisa5 \
 						!mips32r6]
     run_dump_test_arches "cache" [lsort -dictionary -unique [concat \
diff --git a/gas/testsuite/gas/mips/mips32r2-sync-1.d b/gas/testsuite/gas/mips/mips32r2-sync-1.d
new file mode 100644
index 0000000..69c5c27
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32r2-sync-1.d
@@ -0,0 +1,29 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M no-aliases
+#name: MIPS32r2 sync instructions 1
+#as: -32
+#source: mips32r2-sync.s
+
+# Check MIPS32r2 sync instructions assembly and disassembly
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0000000f 	sync
+[0-9a-f]+ <[^>]*> 0000008f 	sync	0x2
+[0-9a-f]+ <[^>]*> 0000010f 	sync	0x4
+[0-9a-f]+ <[^>]*> 0000020f 	sync	0x8
+[0-9a-f]+ <[^>]*> 0000040f 	sync	0x10
+[0-9a-f]+ <[^>]*> 0000044f 	sync	0x11
+[0-9a-f]+ <[^>]*> 0000048f 	sync	0x12
+[0-9a-f]+ <[^>]*> 000004cf 	sync	0x13
+[0-9a-f]+ <[^>]*> 0000060f 	sync	0x18
+[0-9a-f]+ <[^>]*> 0000000f 	sync
+[0-9a-f]+ <[^>]*> 0000008f 	sync	0x2
+[0-9a-f]+ <[^>]*> 0000010f 	sync	0x4
+[0-9a-f]+ <[^>]*> 0000020f 	sync	0x8
+[0-9a-f]+ <[^>]*> 0000040f 	sync	0x10
+[0-9a-f]+ <[^>]*> 0000044f 	sync	0x11
+[0-9a-f]+ <[^>]*> 0000048f 	sync	0x12
+[0-9a-f]+ <[^>]*> 000004cf 	sync	0x13
+[0-9a-f]+ <[^>]*> 0000060f 	sync	0x18
+	\.\.\.
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 542316a..770b65d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
+	"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
+	"sync_rmb" and "sync_wmb" as aliases.
+	* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
+	"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
+
 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* arc-dis.c (parse_option): Update quarkse_em option..
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index d47e1e2..dcd235f 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -1064,11 +1064,11 @@ const struct mips_opcode micromips_opcodes[] =
 {"invalidate",		"t,~(b)",	0x60009000, 0xfc00f000,	RD_1|RD_3|SM,		0,		I1,		0,	0 }, /* same */
 {"invalidate",		"t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"swxc1",		"D,t(b)",	0x54000088, 0xfc0007ff,	RD_1|RD_2|RD_3|SM|FP_S,	0,		I1,		0,	0 },
-{"sync_acquire",	"",		0x00116b7c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
-{"sync_mb",		"",		0x00106b7c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
-{"sync_release",	"",		0x00126b7c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
-{"sync_rmb",		"",		0x00136b7c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
-{"sync_wmb",		"",		0x00046b7c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
+{"sync_acquire",	"",		0x00116b7c, 0xffffffff,	NODS,			INSN2_ALIAS,	I1,		0,	0 },
+{"sync_mb",		"",		0x00106b7c, 0xffffffff,	NODS,			INSN2_ALIAS,	I1,		0,	0 },
+{"sync_release",	"",		0x00126b7c, 0xffffffff,	NODS,			INSN2_ALIAS,	I1,		0,	0 },
+{"sync_rmb",		"",		0x00136b7c, 0xffffffff,	NODS,			INSN2_ALIAS,	I1,		0,	0 },
+{"sync_wmb",		"",		0x00046b7c, 0xffffffff,	NODS,			INSN2_ALIAS,	I1,		0,	0 },
 {"sync",		"",		0x00006b7c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
 {"sync",		"1",		0x00006b7c, 0xffe0ffff,	NODS,			0,		I1,		0,	0 },
 {"synci",		"o(b)",		0x42000000, 0xffe00000,	RD_2|SM,		0,		I1,		0,	0 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 5cb8e73..e47d1fd 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1962,15 +1962,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"invalidate",		"t,o(b)",	0xb8000000, 0xfc000000,	RD_1|RD_3,		0,		I2,		0,	I37 }, /* same */
 {"invalidate",		"t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I2,		0,	I37 }, /* as swr */
 {"swxc1",		"S,t(b)",	0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S,	0,		I4_33,		0,	I37 },
-{"synciobdma",		"",		0x0000008f, 0xffffffff,	NODS,			0,		IOCT,		0,	0 },
-{"syncs",		"",		0x0000018f, 0xffffffff,	NODS,			0,		IOCT,		0,	0 },
-{"syncw",		"",		0x0000010f, 0xffffffff,	NODS,			0,		IOCT,		0,	0 },
-{"syncws",		"",		0x0000014f, 0xffffffff,	NODS,			0,		IOCT,		0,	0 },
-{"sync_acquire",	"",		0x0000044f, 0xffffffff,	NODS,			0,		I33,		0,	0 },
-{"sync_mb",		"",		0x0000040f, 0xffffffff,	NODS,			0,		I33,		0,	0 },
-{"sync_release",	"",		0x0000048f, 0xffffffff,	NODS,			0,		I33,		0,	0 },
-{"sync_rmb",		"",		0x000004cf, 0xffffffff,	NODS,			0,		I33,		0,	0 },
-{"sync_wmb",		"",		0x0000010f, 0xffffffff,	NODS,			0,		I33,		0,	0 },
+{"synciobdma",		"",		0x0000008f, 0xffffffff,	NODS,			INSN2_ALIAS,	IOCT,		0,	0 },
+{"syncs",		"",		0x0000018f, 0xffffffff,	NODS,			INSN2_ALIAS,	IOCT,		0,	0 },
+{"syncw",		"",		0x0000010f, 0xffffffff,	NODS,			INSN2_ALIAS,	IOCT,		0,	0 },
+{"syncws",		"",		0x0000014f, 0xffffffff,	NODS,			INSN2_ALIAS,	IOCT,		0,	0 },
+{"sync_acquire",	"",		0x0000044f, 0xffffffff,	NODS,			INSN2_ALIAS,	I33,		0,	0 },
+{"sync_mb",		"",		0x0000040f, 0xffffffff,	NODS,			INSN2_ALIAS,	I33,		0,	0 },
+{"sync_release",	"",		0x0000048f, 0xffffffff,	NODS,			INSN2_ALIAS,	I33,		0,	0 },
+{"sync_rmb",		"",		0x000004cf, 0xffffffff,	NODS,			INSN2_ALIAS,	I33,		0,	0 },
+{"sync_wmb",		"",		0x0000010f, 0xffffffff,	NODS,			INSN2_ALIAS,	I33,		0,	0 },
 {"sync",		"",		0x0000000f, 0xffffffff,	NODS,			0,		I2|G1,		0,	0 },
 {"sync",		"1",		0x0000000f, 0xfffff83f,	NODS,			0,		I32,		0,	0 },
 {"sync.p",		"",		0x0000040f, 0xffffffff,	NODS,			0,		I2,		0,	0 },