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authorJeff Law <law@redhat.com>2000-02-26 01:48:35 +0000
committerJeff Law <law@redhat.com>2000-02-26 01:48:35 +0000
commit28d33191ee02313e3877af7fcd6c061f9f9ae7c8 (patch)
treefab7701c2ef9d02e157cb55d3a989728c882b66d
parent36e89602d2543e9dce32189126c14c31a4853c24 (diff)
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* doc/c-mips.texi (MIPS Opts): Fix typo in last patch.
-rw-r--r--gas/ChangeLog4
-rw-r--r--gas/doc/c-mips.texi2
2 files changed, 5 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index feb81f8..1bb6e38 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2000-02-26 Andreas Jaeger <aj@suse.de>
+
+ * doc/c-mips.texi (MIPS Opts): Fix typo in last patch.
+
2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au>
* config/tc-i386.c (md_assemble): Don't swap intersegment jmp and
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 6234b0c..26940de 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -71,7 +71,7 @@ assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
Assume that 32-bit general purpose registers are available. This
affects synthetic instructions such as @code{move}, which will assemble
to a 32-bit or a 64-bit instruction depending on this flag. On some
-MIPS variants there is be a 32-bit mode flag; when this flag is set,
+MIPS variants there is a 32-bit mode flag; when this flag is set,
64-bit instructions generate a trap. Also, some 32-bit OSes only save
the 32-bit registers on a context switch, so it is essential never to
use the 64-bit registers.