[MIPS] Add Loongson 3A2000/3A3000 proccessor support.

bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs464e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS464E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs464e to
	bfd_mach_mips_gs464 extension.

binutils/
	* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs464e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
	(mips_cpu_info_table): Add gs464e descriptors.
	* doc/as.texi (march table): Add gs464e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
	* opcode/mips.h (CPU_XXX): New CPU_GS464E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs464e and gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464e descriptors.

21 files changed, 86 insertions, 1 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 16ebfdd..70957e1 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,18 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* archures.c (bfd_architecture): New machine
+	bfd_mach_mips_gs464e.
+	* bfd-in2.h (bfd_architecture): Likewise.
+	* cpu-mips.c (enum I_xxx): Likewise.
+	(arch_info_struct): Likewise.
+	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
+	E_MIPS_MACH_GS464E.
+	(mips_set_isa_flags): Likewise.
+	(mips_mach_extensions): Map bfd_mach_mips_gs464e to
+	bfd_mach_mips_gs464 extension.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* archures.c (bfd_architecture): Rename
 	bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464.
 	* bfd-in2.h (bfd_architecture): Likewise.
diff --git a/bfd/archures.c b/bfd/archures.c
index f247eaa..2fd9bda 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -176,6 +176,7 @@ DESCRIPTION
 .#define bfd_mach_mips_loongson_2e	3001
 .#define bfd_mach_mips_loongson_2f	3002
 .#define bfd_mach_mips_gs464		3003
+.#define bfd_mach_mips_gs464e		3004
 .#define bfd_mach_mips_sb1		12310201 {* octal 'SB', 01.  *}
 .#define bfd_mach_mips_octeon		6501
 .#define bfd_mach_mips_octeonp		6601
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index dc8e514..6819416 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2070,6 +2070,7 @@ enum bfd_architecture
 #define bfd_mach_mips_loongson_2e      3001
 #define bfd_mach_mips_loongson_2f      3002
 #define bfd_mach_mips_gs464            3003
+#define bfd_mach_mips_gs464e           3004
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01.  */
 #define bfd_mach_mips_octeon           6501
 #define bfd_mach_mips_octeonp          6601
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index f578d95..2617c79 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -99,6 +99,7 @@ enum
   I_loongson_2e,
   I_loongson_2f,
   I_gs464,
+  I_gs464e,
   I_mipsocteon,
   I_mipsocteonp,
   I_mipsocteon2,
@@ -151,6 +152,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e",	  FALSE, NN(I_loongson_2e)),
   N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",	  FALSE, NN(I_loongson_2f)),
   N (64, 64, bfd_mach_mips_gs464, "mips:gs464",	  FALSE, NN(I_gs464)),
+  N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e",	  FALSE, NN(I_gs464e)),
   N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, NN(I_mipsocteon)),
   N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+",  FALSE, NN(I_mipsocteonp)),
   N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2",  FALSE, NN(I_mipsocteon2)),
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index f880fa3..25c2d9c 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -6790,6 +6790,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_GS464:
       return bfd_mach_mips_gs464;
 
+    case E_MIPS_MACH_GS464E:
+      return bfd_mach_mips_gs464e;
+
     case E_MIPS_MACH_OCTEON3:
       return bfd_mach_mips_octeon3;
 
@@ -11988,6 +11991,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464;
       break;
 
+    case bfd_mach_mips_gs464e:
+      val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
+      break;
+
     case bfd_mach_mips_octeon:
     case bfd_mach_mips_octeonp:
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
@@ -13993,6 +14000,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
   { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
   { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
   { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+  { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
   { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
 
   /* MIPS64 extensions.  */
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index a8eff4d..ed5760e 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,10 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
+	* readelf.c (get_machine_flags): Handle gs464e.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* NEWS: Mention Loongson 3A1000 proccessor support.
 	* readelf.c (get_machine_flags): Rename loongson-3a to gs464.
 	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.
diff --git a/binutils/NEWS b/binutils/NEWS
index a5fd811..775436d 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,10 @@
 -*- text -*-
 
+* The MIPS port now supports the Loongson 3A2000/3A3000 processor which
+  implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE,
+  Loongson-ext ASE and Loongson-ext2 ASE instructions. Add -march=gs464e
+  option for Loongson 3A2000/3A3000 processor.
+
 * The MIPS port now supports the Loongson 3A1000 processor, aka Loongson3a,
   which implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE
   and Loongson-ext ASE instructions. Add -march=gs464 option for Loongson
diff --git a/binutils/readelf.c b/binutils/readelf.c
index c5bfb7d..16f759e 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3405,6 +3405,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
   	    case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
   	    case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
 	    case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
+	    case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break;
 	    case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
 	    case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
 	    case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
diff --git a/elfcpp/ChangeLog b/elfcpp/ChangeLog
index 2d2a6e1..c744299 100644
--- a/elfcpp/ChangeLog
+++ b/elfcpp/ChangeLog
@@ -1,5 +1,9 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
 	E_MIPS_MACH_GS464.
 
diff --git a/elfcpp/mips.h b/elfcpp/mips.h
index b2def97..277300f 100644
--- a/elfcpp/mips.h
+++ b/elfcpp/mips.h
@@ -236,6 +236,7 @@ enum
   E_MIPS_MACH_LS2E = 0x00A00000,
   E_MIPS_MACH_LS2F = 0x00A10000,
   E_MIPS_MACH_GS464 = 0x00A20000,
+  E_MIPS_MACH_GS464E = 0x00A30000,
 };
 
 // MIPS architecture
diff --git a/gas/ChangeLog b/gas/ChangeLog
index f5e0bad..a9413fa 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
+	(mips_cpu_info_table): Add gs464e descriptors.
+	* doc/as.texi (march table): Add gs464e.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
 	CPU_LOONGSON_3A to CPU_GS464.
 	(mips_cpu_info_table): Add gs464 descriptors, Keep
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 0847875..9c0a1fd 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -422,7 +422,8 @@ static int mips_32bitmode = 0;
     || (ISA) == ISA_MIPS64R5		\
     || (ISA) == ISA_MIPS64R6		\
     || (CPU) == CPU_R5900)		\
-   && (CPU) != CPU_GS464)
+   && ((CPU) != CPU_GS464		\
+    || (CPU) != CPU_GS464E))
 
 /* Return true if ISA supports move to/from high part of a 64-bit
    floating-point register. */
@@ -19814,6 +19815,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
      ISA_MIPS64R2,	CPU_GS464 },
   { "gs464",          0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
      ISA_MIPS64R2,	CPU_GS464 },
+  { "gs464e",         0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+     | ASE_LOONGSON_EXT2,	ISA_MIPS64R2,	CPU_GS464E },
 
   /* Cavium Networks Octeon CPU core */
   { "octeon",	      0, 0,			ISA_MIPS64R2, CPU_OCTEON },
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 2152164..2682e36 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -438,6 +438,7 @@ p6600,
 loongson2e,
 loongson2f,
 gs464,
+gs464e,
 octeon,
 octeon+,
 octeon2,
diff --git a/gold/mips.cc b/gold/mips.cc
index bfe8c41..12aa7de 100644
--- a/gold/mips.cc
+++ b/gold/mips.cc
@@ -3983,6 +3983,7 @@ class Target_mips : public Sized_target<size, big_endian>
     mach_mips_loongson_2e     = 3001,
     mach_mips_loongson_2f     = 3002,
     mach_mips_gs464           = 3003,
+    mach_mips_gs464e          = 3004,
     mach_mips_sb1             = 12310201, // octal 'SB', 01
     mach_mips_octeon          = 6501,
     mach_mips_octeonp         = 6601,
@@ -4148,6 +4149,7 @@ class Target_mips : public Sized_target<size, big_endian>
     this->add_extension(mach_mips_octeon2, mach_mips_octeonp);
     this->add_extension(mach_mips_octeonp, mach_mips_octeon);
     this->add_extension(mach_mips_octeon, mach_mipsisa64r2);
+    this->add_extension(mach_mips_gs464e, mach_mips_gs464);
     this->add_extension(mach_mips_gs464, mach_mipsisa64r2);
 
     // MIPS64 extensions.
@@ -8861,6 +8863,9 @@ Target_mips<size, big_endian>::elf_mips_mach(elfcpp::Elf_Word flags)
     case elfcpp::E_MIPS_MACH_GS464:
       return mach_mips_gs464;
 
+    case elfcpp::E_MIPS_MACH_GS464E:
+      return mach_mips_gs464e;
+
     case elfcpp::E_MIPS_MACH_OCTEON3:
       return mach_mips_octeon3;
 
@@ -12526,6 +12531,8 @@ Target_mips<size, big_endian>::elf_mips_mach_name(elfcpp::Elf_Word e_flags)
       return "mips:loongson_2f";
     case elfcpp::E_MIPS_MACH_GS464:
       return "mips:gs464";
+    case elfcpp::E_MIPS_MACH_GS464E:
+      return "mips:gs464e";
     case elfcpp::E_MIPS_MACH_OCTEON:
       return "mips:octeon";
     case elfcpp::E_MIPS_MACH_OCTEON2:
diff --git a/include/ChangeLog b/include/ChangeLog
index 1a516ab..623c954 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,11 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+
+	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
+	* opcode/mips.h (CPU_XXX): New CPU_GS464E.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
 	E_MIPS_MACH_GS464.
 	(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index db24080..e27b6af 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -300,6 +300,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_LS2E        0x00A00000
 #define E_MIPS_MACH_LS2F        0x00A10000
 #define E_MIPS_MACH_GS464       0x00A20000
+#define E_MIPS_MACH_GS464E	0x00A30000
 
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 9424a92..4ad65c9 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1373,6 +1373,7 @@ static const unsigned int mips_isa_table[] = {
 #define CPU_LOONGSON_2E 3001
 #define CPU_LOONGSON_2F 3002
 #define CPU_GS464	3003
+#define CPU_GS464E	3004
 #define CPU_OCTEON	6501
 #define CPU_OCTEONP	6601
 #define CPU_OCTEON2	6502
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 74807f3..9d1e02f 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,5 +1,10 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
+	gs464e and gs464.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
 	to gs464.
 
diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
index 93cdbfe..dcd33ba 100644
--- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
+++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
@@ -315,3 +315,8 @@ good_combination { "-march=interaptiv-mr2 -32" "-march=m5100 -32" } \
 		 { mips32r2 interaptiv-mr2 } \
 		 MIPS32r5 "Imagination interAptiv MR2" \
 		 { "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
+
+good_combination { "-march=gs464 -32" "-march=gs464e -32" }	\
+		 { gs464e o32 }					\
+		 MIPS64r2 "None"				\
+		 { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a2c4b29..6f338f8 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 	loongson3a as an alias of gs464 for compatibility.
 	* mips-opc.c (mips_opcodes): Change Comments.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 66e867f..0f5799d 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -640,6 +640,11 @@ const struct mips_arch_choice mips_arch_choices[] =
     mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
     mips_hwr_names_numeric },
 
+  { "g464e",   1, bfd_mach_mips_gs464e, CPU_GS464E,
+    ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+    | ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
+    mips_hwr_names_numeric },
+
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
     ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
     mips_cp1_names_mips3264, mips_hwr_names_numeric },