Bunch of changes from Richard Earnshaw for generic bi-endian ARM aout targets.

Details in change logs.

21 files changed, 251 insertions, 15 deletions

diff --git a/ChangeLog b/ChangeLog
index f845a00..98d7d23 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,13 @@
+Thu May 18 18:08:49 1995  Ken Raeburn  <raeburn@kr-laptop.cygnus.com>
+
+	Changes for ARM based on patches from Richard Earnshaw:
+	* config.sub: Handle armeb and armel.
+	* configure.in: Omit arm linker only for riscix.
+
+Thu May 11 17:23:26 1995  Per Bothner  <bothner@kalessin.cygnus.com>
+
+	* config.guess:  Update from FSF.
+
 Tue May  9 15:52:05 1995  Michael Meissner  <meissner@cygnus.com>
 
 	* config.sub: Recognize powerpcle as the little endian varient of
diff --git a/bfd/.Sanitize b/bfd/.Sanitize
index 98129d3..8cdb2e5 100644
--- a/bfd/.Sanitize
+++ b/bfd/.Sanitize
@@ -48,6 +48,7 @@ TODO
 VERSION
 aix386-core.c
 aout-adobe.c
+aout-arm.c
 aout-encap.c
 aout-ns32k.c
 aout-target.h
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index dac03db..da62ecb 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,37 @@
+Thu May 18 04:24:01 1995  Ken Raeburn  <raeburn@kr-laptop.cygnus.com>
+
+	Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
+
+	* aoutx.h (aout_link_input_section_standard): If defined, call
+	MY_relocatable_reloc before doing a partial relocation.
+
+	* aout-arm.c: (WRITE_HEADERS): Delete.
+	(NAME): Define version to override default in aoutx.h
+	(MY(howto_table)): Reformat.  Alter some entries slightly.
+	(RELOC_ARM_BITS_NEG_{BIG,LITTLE}): Define.
+	(MY(reloc_howto), MY(put_reloc), MY(relocatable_reloc)): New functions.
+	(MY_reloc_howto, MY_put_reloc, MY_relocatable_reloc): Define.
+	(MY(fix_pcrel_26)): Renamed from aoutarm_fix_pcrel_26, return
+	bfd_reloc_ok not bfd_reloc_continue.
+	(MY(fix_pcrel_26_done)): Likewise.
+	(MY(bfd_reloc_type_lookup)): Renamed from aoutarm_reloc_type_lookup.
+	(MY_bfd_link_hash_table_create, MY_bfd_link_add_symbols,
+	MY_bfd_final_link): Delete.
+	(MY_swap_std_reloc_in, MY_swap_std_reloc_out, MY_get_section_contents):
+	Define.
+	(aoutx.h): Include it.
+	(MY(swap_std_reloc_{in,out})): New functions.
+	Use RELOC_ARM_BITS_NEG_{BIG,LITTLE} to extract negative reloc bit.
+	(aoutarm_squirt_out_relocs): Delete.
+ 
+	From: David Taylor (dtaylor@armltd.co.uk)
+	* config/arm[lb]-aout.mt: New files.
+	* aout-arm.c: New file.
+	* config.bfd: Handle arm{,e[lb]}-*-aout
+	* configure.in: Add vetor for aout_arm_{big,little}_vec.
+	* reloc.c: New relocation types for the ARM.
+	* targets.c (aout_arm_{big,little}_vec): declare.
+
 Tue May 16 10:29:51 1995  Jim Kingdon  <kingdon@deneb.cygnus.com>
 
 	* libbfd.c (bfd_stat): If bfd_cache_lookup returns an error,
diff --git a/configure.in b/configure.in
index 6c71fb7..302e3ea 100644
--- a/configure.in
+++ b/configure.in
@@ -362,7 +362,7 @@ case "${target}" in
     noconfigdirs="$noconfigdirs libg++ libstdc++ libio librx"
     ;;
 # end-sanitize-psion
-  arm-*-*)
+  arm-*-riscix*)
     noconfigdirs="$noconfigdirs ld"
     ;;
   h8300*-*-* | \
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7336fca..34bd170 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,105 @@
+Thu May 18 04:25:11 1995  Ken Raeburn  <raeburn@kr-laptop.cygnus.com>
+
+	Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
+
+	* config/tc-arm.c (CP_T_{Pre,UD,WB}): Define, bits in co-processor 
+	instructions.
+	([ls]fm_flags): Correct error in bitmasks.
+	(cp_address_required_here): Delete second parameter, FLAGS.  All 
+	callers changed.  Remove all dead code referring to FLAGS.  If 
+	address is just "[Reg]" then convert into a PRE-INCREMENT UP format.
+	(do_fp_ldmstm): Handle full-descending and empty-ascending stack 
+	formats explicitly.
+
+	* config/tc-arm.c (internalError): Define.
+	(ARM_{1,2,250,3,6,7,7DM,ANY,2UP,ALL,3UP,6UP,LONGMUL}): Define processor
+	variants.
+	(FPU_{CORE,FPA10,FPA11,NONE,ALL,MEMMULTI}): Define floating point
+	variants.
+	({CPU,FPU}_DEFAULT): Define.
+	(cpu_variant): New variable.
+	(asm_flg): Change more_flags to flag_bits.
+	Add prototypes for new functions.
+	(FLAG_{S,P,B,T,ED,FD,FA,EA,IB,IA,DB,DA,L}): Delete.
+	(s_flag[], ldst_flags[], byte_flag[], cmp_flags[], ldm_flags[],
+	 stm_flags[], lfm_flags[], sfm_flags[], round_flags[], except_flags[],
+	 cplong_flag[]): New variables.
+	(asm_opcode, insns[]): New format, add version support.
+	(arm_flg_hsh): Delete.
+	(do_mul, do_mla): Remove "Warning" from warning messages.
+	(do_arit): Simplify.
+	(do_swap): Make error message more appropriate.
+	(md_begin): Build hash tables starting at first entry in tables.
+	(md_number_to_chars): Cope with big/little-endian selection.
+	(md_chars_to_number): New function.
+	(md_apply_fix): Rewrite to make endian independent.
+	(tc_gen_reloc): Better error messages.
+	(md_assemble): Reject opcodes forbidden by the currently selected cpu
+	variant.  Rewrite handling code for instruction flags.
+	(md_shortopts): Add option "m:".
+	(md_parse_option): Get the desired cpu/fpu variant.
+
+	From: David Taylor (dtaylor@armltd.co.uk)
+	* configure.in (architecture variants): Check for "armeb" and "arm*",
+	set endianness accordingly.
+	* read.c (read_a_source_file): New hooks md_start_line_hook and
+	md_after_pass_hook.
+	* config/arm-{big,lit}.mt: New files
+	* config/tc-arm.h ({LITTLE,BIG}_ENDIAN, BYTE_ORDER): Define.
+	(TARGET_FORMAT): Select depending on endianness and emulation and 
+	object format.
+	(md_after_pass_hook, md_start_line_hook): Define.
+	* config/tc-arm.c: Include subsegs.h, symbols.h and listing.h.
+	(shift[]): Add uppper case equivalents.
+	(CP_T_[XY], TRANS_BIT): Define.
+	(conds[]): Delete initial NULL entry, add "lo" entry as synonym for 
+	"cc".
+	(LONGEST_FLAG, flags[]): Delete.
+	(arm_psr): New structure.
+	(psrs[]): New variable.
+	(PSR_ALL): Define.
+	(LONGEST_INST): Bump to 5.
+	(LITERAL_MASK, COND_MASK, OPCODE_MASK, DATA_OP_SHIFT): Define.
+	(OPCODE_{AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,TST,TEQ,CMP,CMN,ORR,MOV,BIC,
+	 MVN}): Define.
+	(insns[]): Add smull, umull, smlal, umlal, ldfm, stfm, msr and mrs
+	instructions.  Add nop and adr pseudo ops.
+	(reg_table): Add APCS register name variants.
+	(arm_psr_hsh): New hash table.
+	(md_pseudo_table): Add "ltorg", "pool", "extend", "ldouble" and 
+	"packed".
+	(MAX_LITERAL_POOL_SIZE): Define.
+	(struct literalS): New structure.
+	(literals, next_literal_pool_place, lit_pool_num, current_poolP): New
+	variables.
+	(add_to_lit_pool, symbol_locate, symbol_make_empty): New functions.
+	(validate_immediate): Return FAIL on failure.
+	(s_ltorg): New function.
+	(psr_required_here, psrf_required_here): New functions.
+	(cp_address_required_here): New parameter, flag, all callers changed.
+	If flag is non-zero, restrict the legal addressing modes.
+	(do_nop, do_mrs, do_msr, do_mull): New functions.
+	(negate_data_op): New function.
+	(data_op2): accept #x,y meaning x rotated right by y, but only when
+	suitable constants.  If immediate is not legal, try changing the
+	opcode.
+	(do_adr): New function.
+	(do_ldst): accept "ldr reg, =expr".  Put expr in the pool if it can't
+	be done as an immediate.
+	(do_fp_ldst): Use CP_T_[XY], not immediate values.
+	(do_fp_ldmstm): New function.
+	(arm_psr_parse): New function.
+	(output_inst): Use INSN_SIZE in call to md_number_to_chars.
+	(md_assemble): Add hack so that "Label instruction" causes alignment of
+	the label.
+	(arm_after_pass_hook, arm_start_line_hook, arm_frob_symbol): New 
+	functions.
+
+Wed May 17 05:25:16 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* config/tc-ppc.c (md_show_usage): Add \'s at end of lines in
+	strings for non-GCC compilers.
+
 Tue May 16 19:36:00 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 
 	* config/obj-ecoff.c (ecoff_pop_insert): New function.
diff --git a/gas/config/.Sanitize b/gas/config/.Sanitize
index 0406a2a..91be3b0 100644
--- a/gas/config/.Sanitize
+++ b/gas/config/.Sanitize
@@ -41,6 +41,8 @@ Things-to-keep:
 
 aout_gnu.h
 alpha-opcode.h
+arm-big.mt
+arm-lit.mt
 atof-ieee.c
 atof-tahoe.c
 atof-vax.c
diff --git a/gas/config/arm-big.mt b/gas/config/arm-big.mt
new file mode 100644
index 0000000..31e773a
--- /dev/null
+++ b/gas/config/arm-big.mt
@@ -0,0 +1 @@
+TDEFINES=-DTARGET_BYTES_BIG_ENDIAN
diff --git a/gas/config/arm-lit.mt b/gas/config/arm-lit.mt
new file mode 100644
index 0000000..9e240e8
--- /dev/null
+++ b/gas/config/arm-lit.mt
@@ -0,0 +1 @@
+TDEFINES=-DTARGET_BYTES_LITTLE_ENDIAN
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 64dbbc6..4c8a668 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)	
+
+	* arm/arm7dm.s: New file -- tests for ARM7DM instructions.
+	* arm/arm6.s: Correct bogus tests.
+	* arm/gas.exp (arm6.s): Is now a valid test.
+	(arm7dm.s): New test.
+	* arm/float.s: Add load/store multiple floating point instruction 
+	tests.
+
+Wed May  3 13:14:44 1995  Jeff Law  (law@snake.cs.utah.edu)
+
+	* gas/hppa/reloc/longcall.s: New test.
+	* gas/hppa/reloc/reloc.exp: Run it.
+
 Tue May  2 16:37:48 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 
 	* gas/mips/ld.d: Modified for gas delay-slot fixes.
diff --git a/gas/testsuite/gas/arm/.Sanitize b/gas/testsuite/gas/arm/.Sanitize
index 4594424..6fb3a4f 100644
--- a/gas/testsuite/gas/arm/.Sanitize
+++ b/gas/testsuite/gas/arm/.Sanitize
@@ -27,6 +27,7 @@ Things-to-keep:
 
 arm3.s
 arm6.s
+arm7dm.s
 copro.s
 float.s
 gas.exp
diff --git a/gas/testsuite/gas/arm/arm7dm.s b/gas/testsuite/gas/arm/arm7dm.s
new file mode 100644
index 0000000..7496c70
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm7dm.s
@@ -0,0 +1,12 @@
+.text
+.align 0
+	
+	smull	r0, r1, r2, r3
+	umull	r0, r1, r2, r3
+	smlal	r0, r1, r2, r3
+	umlal	r0, r1, r4, r3
+
+	smullne	r0, r1, r3, r4
+	smulls	r1, r0, r9, r11
+	umlaleqs r2, r9, r4, r9
+	smlalge r14, r10, r8, r14
diff --git a/gas/testsuite/gas/arm/gas.exp b/gas/testsuite/gas/arm/gas.exp
index 92f6adc..339c3e6 100644
--- a/gas/testsuite/gas/arm/gas.exp
+++ b/gas/testsuite/gas/arm/gas.exp
@@ -1,14 +1,14 @@
 #
 # Some ARM tests
 #
-if [istarget arm-*-riscix*] then {
+if [istarget arm-*-*] then {
     gas_test "inst.s" "" $stdoptlist "Basic instruction set"
 
     gas_test "arm3.s" "" $stdoptlist "Arm 3 instructions"
 
-    # These instructions aren't supported, and I'm told some are
-    # actually invalid.
-    gas_test_error "arm6.s" "" "Arm 6 instructions"
+    gas_test "arm6.s" "" $stdoptlist "Arm 6 instructions"
+
+    gas_test "arm7dm.s" "" $stdoptlist "Arm 7DM instructions"
 
     gas_test "copro.s" "" $stdoptlist "Co processor instructions"
 
diff --git a/ld/config/.Sanitize b/ld/config/.Sanitize
index d0e688c..a4fcf74 100644
--- a/ld/config/.Sanitize
+++ b/ld/config/.Sanitize
@@ -41,6 +41,8 @@ Things-to-keep:
 
 alpha.mt
 alphaosf.mh
+armb-aout.mt
+arml-aout.mt
 cf-h8300h.mt
 coff-a29k.mt
 coff-h8300.mt
diff --git a/ld/config/armb-aout.mt b/ld/config/armb-aout.mt
new file mode 100644
index 0000000..5a9985f
--- /dev/null
+++ b/ld/config/armb-aout.mt
@@ -0,0 +1 @@
+EMUL=armaoutb
diff --git a/ld/config/arml-aout.mt b/ld/config/arml-aout.mt
new file mode 100644
index 0000000..7e7d993
--- /dev/null
+++ b/ld/config/arml-aout.mt
@@ -0,0 +1 @@
+EMUL=armaoutl
diff --git a/ld/emulparams/.Sanitize b/ld/emulparams/.Sanitize
index 83e5a4f..570b70a 100644
--- a/ld/emulparams/.Sanitize
+++ b/ld/emulparams/.Sanitize
@@ -42,6 +42,8 @@ Things-to-keep:
 README
 a29k.sh
 alpha.sh
+armaoutb.sh
+armaoutl.sh
 coff_sparc.sh
 ebmon29k.sh
 elf32_sparc.sh
diff --git a/ld/emulparams/armaoutb.sh b/ld/emulparams/armaoutb.sh
new file mode 100644
index 0000000..76cd873
--- /dev/null
+++ b/ld/emulparams/armaoutb.sh
@@ -0,0 +1,7 @@
+SCRIPT_NAME=armaout
+OUTPUT_FORMAT="a.out-arm-big"
+HEADER_START_ADDR=0x8000
+TEXT_START_ADDR=0x8000
+NONPAGED_TEXT_START_ADDRESS=0x8000
+PAGE_SIZE=32768
+ARCH=arm
diff --git a/ld/emulparams/armaoutl.sh b/ld/emulparams/armaoutl.sh
new file mode 100644
index 0000000..bda8501
--- /dev/null
+++ b/ld/emulparams/armaoutl.sh
@@ -0,0 +1,7 @@
+SCRIPT_NAME=armaout
+OUTPUT_FORMAT="a.out-arm-little"
+HEADER_START_ADDR=0x8000
+TEXT_START_ADDR=0x8000
+NONPAGED_TEXT_START_ADDRESS=0x8000
+PAGE_SIZE=32768
+ARCH=arm
diff --git a/ld/scripttempl/.Sanitize b/ld/scripttempl/.Sanitize
index 46c2242..0e6008a 100644
--- a/ld/scripttempl/.Sanitize
+++ b/ld/scripttempl/.Sanitize
@@ -34,6 +34,7 @@ Things-to-keep:
 README
 a29k.sc
 alpha.sc
+armaout.sc
 aout.sc
 ebmon29k.sc
 elf.sc
diff --git a/ld/scripttempl/armaout.sc b/ld/scripttempl/armaout.sc
new file mode 100644
index 0000000..e9276a8
--- /dev/null
+++ b/ld/scripttempl/armaout.sc
@@ -0,0 +1,35 @@
+cat <<EOF
+OUTPUT_FORMAT("${OUTPUT_FORMAT}")
+OUTPUT_ARCH(${ARCH})
+
+${RELOCATING+${LIB_SEARCH_DIRS}}
+${STACKZERO+${RELOCATING+${STACKZERO}}}
+SECTIONS
+{
+  .text   ${RELOCATING+${TEXT_START_ADDR}} :
+  {
+    CREATE_OBJECT_SYMBOLS
+    ${RELOCATING+__stext_ = .;}
+    *(.text)
+    ${PAD_TEXT+${RELOCATING+. = ${DATA_ALIGNMENT};}}
+    ${RELOCATING+_etext = ${DATA_ALIGNMENT};}
+    ${RELOCATING+__etext = ${DATA_ALIGNMENT};}
+  }
+  .data ${RELOCATING+${DATA_ALIGNMENT}} :
+  {
+    ${RELOCATING+__sdata_ = .;}
+    *(.data)
+    ${CONSTRUCTING+CONSTRUCTORS}
+    ${RELOCATING+_edata  =  .;}
+    ${RELOCATING+__edata  =  .;}
+  }
+  .bss ${RELOCATING+ SIZEOF(.data) + ADDR (.data)} :
+  {
+   ${RELOCATING+ __bss_start = .};
+   *(.bss)
+   *(COMMON)
+   ${RELOCATING+_end = ALIGN(4) };
+   ${RELOCATING+__end = ALIGN(4) };
+  }
+}
+EOF
diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h
index 9b8d3be..9326a03 100644
--- a/opcodes/arm-opc.h
+++ b/opcodes/arm-opc.h
@@ -1,6 +1,6 @@
 /* Opcode table for the ARM.
 
-   Copyright 1994 Free Software Foundation, Inc.
+   Copyright 1994, 1995 Free Software Foundation, Inc.
    
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -28,7 +28,8 @@ struct arm_opcode {
    %<bitfield>d		print the bitfield in decimal
    %<bitfield>x		print the bitfield in hex
    %<bitfield>r		print as an ARM register
-   %<bitfield>f		print a floating point constant if >7 else an fp register
+   %<bitfield>f		print a floating point constant if >7 else a
+			floating point register
    %c			print condition code (always bits 28-31)
    %P			print floating point precision in arithmetic insn
    %Q			print floating point precision in ldf/stf insn
@@ -47,11 +48,16 @@ struct arm_opcode {
    %F			print the COUNT field of a LFM/SFM instruction.
 */
 
+/* Note: There is a partial ordering in this table - it must be searched from
+   the top to obtain a correct match. */
+
 static struct arm_opcode arm_opcodes[] = {
     /* ARM instructions */
     {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
     {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
     {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
+    {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
+    {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
     {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
     {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
     {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
@@ -72,8 +78,8 @@ static struct arm_opcode arm_opcodes[] = {
     {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
     {0x04000000, 0x0c100000, "str%c%22'b%t\t%12-15r, %a"},
     {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
-    {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%22`!, %m%22'^"},
-    {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%22`!, %m%22'^"},
+    {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
+    {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
     {0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
     {0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
 
@@ -119,10 +125,6 @@ static struct arm_opcode arm_opcodes[] = {
     {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
     {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
     {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
-    {0x0d000200, 0x0f900fff, "sfm%cfd\t%12-14f, %F, [%16-19r]%21'!"},
-    {0x0c900200, 0x0f900fff, "lfm%cfd\t%12-14f, %F, [%16-19r]%21'!"},
-    {0x0c800200, 0x0f900fff, "sfm%cea\t%12-14f, %F, [%16-19r]%21'!"},
-    {0x0d100200, 0x0f900fff, "lfm%cea\t%12-14f, %F, [%16-19r]%21'!"},
     {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
     {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 
@@ -130,8 +132,8 @@ static struct arm_opcode arm_opcodes[] = {
     {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
     {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
     {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
-    {0x0c000000, 0x0e100000, "stc%c%22`l\t%8-11d, cr%12-15d, %A"},
-    {0x0c100000, 0x0e100000, "ldc%c%22`l\t%8-11d, cr%12-15d, %A"},
+    {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
+    {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
     /* the rest */
     {0x00000000, 0x00000000, "undefined instruction %0-31x"},
     {0x00000000, 0x00000000, 0}