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authorJeff Law <law@redhat.com>1996-12-04 05:00:49 +0000
committerJeff Law <law@redhat.com>1996-12-04 05:00:49 +0000
commite4e13022939b13bc1ca90745a7b19a752e590f84 (patch)
tree721ae63cc340d4b5fb49c8ef29fe5d7168ebd44e
parentb61802e7cb86e29a2811d5b5f90478e735f1ca97 (diff)
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* simops.c: Treat both operands as signed values for
"div" instruction. Fixes another dozen c-torture execution failures.
-rw-r--r--sim/mn10300/ChangeLog11
-rw-r--r--sim/mn10300/simops.c4
2 files changed, 13 insertions, 2 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index 7695f4f..ce0dc91 100644
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,5 +1,16 @@
+Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Treat both operands as signed values for
+ "div" instruction.
+
+ * simops.c: Fix simulation of division instructions.
+ Fix typos/thinkos in several "cmp" and "sub" instructions.
+
Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
+ * simops.c: Fix carry bit handling in "sub" and "cmp"
+ instructions.
+
* simops.c: Fix "mov imm8,an" and "mov imm16,dn".
Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index 931da3a..6b4fde6 100644
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -1421,8 +1421,8 @@ void OP_F260 ()
temp = State.regs[REG_MDR];
temp <<= 32;
temp |= State.regs[REG_D0 + (insn & 0x3)];
- State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
- temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
+ State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
+ temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);