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authorJiong Wang <jiwang@sourceware.org>2013-02-20 07:45:14 +0000
committerJiong Wang <jiwang@sourceware.org>2013-02-20 07:45:14 +0000
commitb74ea3eb0155e3a04f92f99db4b0a8abf1561ffe (patch)
tree76c7e7707ba00f344001a5df1d89d731b82ec635
parent286cc68d2d0f4a0836c680c05dd0daf1aea5baa3 (diff)
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* MAINTAINERS (Write After Approval): Add myself to the list.
-rw-r--r--gdb/ChangeLog10
-rw-r--r--gdb/MAINTAINERS1
2 files changed, 8 insertions, 3 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index ddb1824..46c67f4 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2013-02-20 Jiong Wang <jiwang@tilera.com>
+
+ * MAINTAINERS (Write After Approval): Add myself to the list.
+
2013-02-19 Pedro Alves <palves@redhat.com>
Garbage collect 'struct monitor_ops'::load_routine.
@@ -43,11 +47,11 @@
2013-02-19 Jiong Wang <jiwang@tilera.com>
- * tilegx-tdep.c (tilegx_skip_prologue): Use skip_prologue_using_sal.
+ * tilegx-tdep.c (tilegx_skip_prologue): Use skip_prologue_using_sal.
2013-02-19 Jiong Wang <jiwang@tilera.com>
- * tilegx-tdep.c (INT_SWINT_1_SIGRETURN): New macro.
+ * tilegx-tdep.c (INT_SWINT_1_SIGRETURN): New macro.
(tilegx_write_pc): New function.
(tilegx_cannot_reference_register): Return zero if REGNO
is TILEGX_FAULTNUM_REGNUM.
@@ -61,7 +65,7 @@
2013-02-19 Jiong Wang <jiwang@tilera.com>
* tilegx-tdep.c (tilegx_push_dummy_call): args pushed on stack
- should be aligned to 64bit.
+ should be aligned to 64bit.
2013-02-19 Kai Tietz <ktietz@redhat.com>
diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS
index 0b32d02..53c5e7c 100644
--- a/gdb/MAINTAINERS
+++ b/gdb/MAINTAINERS
@@ -638,6 +638,7 @@ D Venkatasubramanian dvenkat@noida.hcltech.com
Corinna Vinschen vinschen@redhat.com
Sami Wagiaalla swagiaal@redhat.com
Keith Walker keith.walker@arm.com
+Jiong Wang jiwang@tilera.com
Kris Warkentin kewarken@qnx.com
Philippe Waroquiers philippe.waroquiers@skynet.be
Ulrich Weigand uweigand@de.ibm.com