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| author | Jan Beulich <jbeulich@novell.com> | 2012-07-25 11:34:49 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@novell.com> | 2012-07-25 11:34:49 +0000 |
| commit | 9e2934f7999c248f7e8452d0726541ce9ad9edce (patch) | |
| tree | 700322253adb563e2843c6ac19a42ae1c107215d | |
| parent | 8280f326858028ecb33ceffc33a8ddbbc250f02d (diff) | |
| download | gdb-9e2934f7999c248f7e8452d0726541ce9ad9edce.zip gdb-9e2934f7999c248f7e8452d0726541ce9ad9edce.tar.gz gdb-9e2934f7999c248f7e8452d0726541ce9ad9edce.tar.bz2 | |
MASM accepts ESP/RSP being specified second in a memory address
operand, by silently making it the base register despite not being
specified first.
Consequently, we also permit an xmm/ymm index to be specified first
(possibly alone), nevertheless putting it in as index register.
2012-07-24 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_simplify_register): Handle
xmm/ymm index register being specified first as well as esp/rsp
base register being specified last in a memory operand.
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-i386-intel.c | 16 |
2 files changed, 21 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 445e36d..2d62c41 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2012-07-24 Jan Beulich <jbeulich@suse.com> + * config/tc-i386-intel.c (i386_intel_simplify_register): Handle + xmm/ymm index register being specified first as well as esp/rsp + base register being specified last in a memory operand. + +2012-07-24 Jan Beulich <jbeulich@suse.com> + * config/tc-i386-intel.c (i386_intel_simplify_register): Replace literal 4 by corresponding ESP_REG_NUM. diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c index 919f27c..099cbfc 100644 --- a/gas/config/tc-i386-intel.c +++ b/gas/config/tc-i386-intel.c @@ -278,10 +278,24 @@ i386_intel_simplify_register (expressionS *e) } i.op[this_operand].regs = i386_regtab + reg_num; } + else if (!intel_state.index + && (i386_regtab[reg_num].reg_type.bitfield.regxmm + || i386_regtab[reg_num].reg_type.bitfield.regymm)) + intel_state.index = i386_regtab + reg_num; else if (!intel_state.base && !intel_state.in_scale) intel_state.base = i386_regtab + reg_num; else if (!intel_state.index) - intel_state.index = i386_regtab + reg_num; + { + if (intel_state.in_scale + || i386_regtab[reg_num].reg_type.bitfield.baseindex) + intel_state.index = i386_regtab + reg_num; + else + { + /* Convert base to index and make ESP/RSP the base. */ + intel_state.index = intel_state.base; + intel_state.base = i386_regtab + reg_num; + } + } else { /* esp is invalid as index */ |